KR20220076722A - Display device - Google Patents

Abstract

Embodiments of the present invention relate to a display device, and more particularly, thin manufacturing is possible by using a base voltage line as an antenna pattern, and by connecting an impedance matching circuit to a base voltage line pattern used as an antenna pattern, antenna resonance It relates to a display device with improved characteristics.

Description

display device {DISPLAY DEVICE}

Embodiments of the present invention relate to a display device having an antenna pattern.

As a display device for displaying an image using digital data, a liquid crystal display (LCD) device using liquid crystal and an organic light emitting display device using an organic light emitting diode (OLED) are representative.

Such a display device may be used not only as a TV but also as a laptop, smart phone, or vehicle display device. In this case, digital data may be transmitted or received through a wireless network such as Wi-Fi or Long Term Evolution (LTE).

Embodiments of the present invention use the base voltage line as an antenna pattern, thereby providing a display device capable of being thinly manufactured and having excellent antenna performance.

In addition, embodiments of the present invention may provide a display device having improved antenna resonance characteristics by connecting an impedance matching circuit to a base voltage line pattern used as an antenna pattern.

In addition, embodiments of the present invention may provide a display device capable of extending a control range of a resonant frequency by opening a partial section of an antenna pattern.

According to an embodiment of the present invention, there is provided a display panel in which a plurality of sub-pixels are arranged and a base voltage line pattern for applying a base voltage is disposed along the outside of a display area where an image is displayed; At least one data driving circuit including a source driving integrated circuit for supplying a data voltage to the display panel through a data line, and an impedance matching circuit connected to one or more base voltage lines extending at any point in a base voltage line pattern A display device may be provided.

According to an embodiment of the present invention, the data driving circuit includes a source-side circuit film having one side connected to a display panel and the other side connected to a source printed circuit board, and a source driving integrated circuit mounted on the source-side circuit film A display device may be provided.

According to an embodiment of the present invention, the base voltage line may be disposed on the source-side circuit film to provide a display device connected to the base voltage pad of the source printed circuit board.

According to an embodiment of the present invention, the impedance matching circuit may provide a display device including at least one impedance element among a resistor, a capacitor, and an inductor.

According to an embodiment of the present invention, the impedance matching circuit comprises: a first impedance element and a third impedance element connected in series between a base voltage pad and a base voltage line pattern; and a node between the first impedance element and the third impedance element; It is possible to provide a display device including a second impedance element connected between ground nodes.

According to an embodiment of the present invention, there may be provided a display device in which the first impedance element is a capacitor and the second impedance element and the third impedance element are resistors.

According to an embodiment of the present invention, a display device may be provided in which the first impedance element and the second impedance element are capacitors, and the third impedance element is a resistor.

According to an embodiment of the present invention, a display device in which the base voltage line pattern is formed in a closed loop shape surrounding the display area of the display panel may be provided.

According to an embodiment of the present invention, it is possible to provide a display device in which the base voltage line pattern includes an open area in which a partial section is opened outside the display area of the display panel.

According to an embodiment of the present invention, it is possible to provide a display device in which the open area is formed to correspond to a space between the data driving circuits.

According to an embodiment of the present invention, it is possible to provide a display device that further includes a connection circuit for connecting a ground voltage line positioned in an open area and an impedance matching circuit.

According to an embodiment of the present invention, the connection circuit may provide a display device including resistance elements each connected to a base voltage line.

According to embodiments of the present invention, by using a base voltage line as an antenna pattern, a display device capable of being thinly manufactured and having excellent antenna performance may be provided.

Also, according to embodiments of the present invention, by disposing an impedance matching circuit in an antenna pattern, it is possible to provide a display device having improved antenna resonance characteristics.

Also, according to embodiments of the present invention, it is possible to provide a display device capable of extending a control range of a resonant frequency by opening a partial section of an antenna pattern.

1 is a diagram schematically showing a display device according to embodiments of the present invention.
2 is an exemplary system diagram of a display apparatus according to embodiments of the present invention.
3 is a circuit structural diagram of subpixels arranged in a display device according to embodiments of the present invention.
4 is a diagram illustrating a structure in a case in which a base voltage pattern is used as an antenna pattern in a display device according to embodiments of the present invention.
5 is a diagram illustrating a structure in a case in which an impedance matching circuit is connected to a base voltage line pattern in a display device according to embodiments of the present invention.
6 is a diagram illustrating various examples of an impedance matching circuit in a display device according to embodiments of the present invention.
7 is a signal diagram illustrating a change in a wireless signal according to a configuration of an impedance element used in an impedance matching circuit in a display device according to embodiments of the present invention.
8 is a diagram illustrating a structure in which a partial region of a base voltage pattern is opened in a display device according to still another exemplary embodiment of the present invention.
9 is a diagram illustrating a structure when an impedance matching circuit is connected to a base voltage line pattern through a connection circuit in a display device according to embodiments of the present invention.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same reference numerals as much as possible even though they are indicated in different drawings. In addition, in describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description may be omitted. When "includes", "having", "consisting of", etc. mentioned in this specification are used, other parts may be added unless "only" is used. When a component is expressed in the singular, it may include a case in which the plural is included unless otherwise explicitly stated.

In addition, in describing the components of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only for distinguishing the elements from other elements, and the essence, order, order, or number of the elements are not limited by the terms.

In the description of the positional relationship of the components, when it is described that two or more components are "connected", "coupled" or "connected", two or more components are directly "connected", "coupled" or "connected" ", but it will be understood that two or more components and other components may be further "interposed" and "connected," "coupled," or "connected." Here, other components may be included in one or more of two or more components that are “connected”, “coupled” or “connected” to each other.

In the description of the temporal flow relationship related to the components, the operation method or the production method, for example, the temporal precedence relationship such as "after", "after", "after", "before", etc. Alternatively, when a flow precedence relationship is described, it may include a case where it is not continuous unless "immediately" or "directly" is used.

On the other hand, when numerical values or corresponding information (eg, level, etc.) for a component are mentioned, even if there is no separate explicit description, the numerical value or the corresponding information is based on various factors (eg, process factors, internal or external shock, Noise, etc.) may be interpreted as including an error range that may occur.

1 is a view showing a schematic configuration of a display device according to embodiments of the present invention.

Referring to FIG. 1 , in a display apparatus 100 according to an embodiment of the present invention, a display panel 110 in which a plurality of sub-pixels SP are arranged in a row, and a gate driving circuit for driving the display panel 110 . 120 and the data driving circuit 130 , and a timing controller 140 for controlling the gate driving circuit 120 and the data driving circuit 130 may be included.

The display panel 110 is based on the scan signal transmitted from the gate driving circuit 120 through the plurality of gate lines GL and the data voltage transmitted from the data driving circuit 130 through the plurality of data lines DL. display the image.

In the case of a liquid crystal display, the display panel 110 includes a liquid crystal layer formed between two substrates, and includes a twisted nematic (TN) mode, a vertical alignment (VA) mode, an in plane switching (IPS) mode, and a fringe field switching (FFS) mode. ) mode, etc., may be operated in any known mode. On the other hand, in the case of an organic light emitting display, the display panel 110 may be implemented using a top emission method, a bottom emission method, or a dual emission method.

In the display panel 110 , a plurality of pixels may be arranged in a matrix form, and each pixel is a sub-pixel SP of a different color, for example, a white sub-pixel, a red sub-pixel, a green sub-pixel, and a blue sub-pixel. , and each subpixel SP may be defined by a plurality of data lines DL and a plurality of gate lines GL.

One sub-pixel SP is a thin film transistor (TFT) formed in a region where one data line DL and one gate line GL intersect, and an organic light emitting diode (OLED) for charging a data voltage. It may include a light emitting device such as an emitting diode (OLED), a storage capacitor electrically connected to the light emitting device to maintain a voltage, and the like.

For example, when the display device 100 having a resolution of 2,160 X 3,840 includes four sub-pixels SP of white (W), red (R), green (G), and blue (B), 2,160 pixels A total of 3,840 X 4 = 15,360 data lines DL may be provided by 3,840 data lines DL connected to the gate line GL and the four subpixels WRGB, respectively, and these gate lines GL ) and the data line DL intersect each sub-pixel SP to be disposed.

The gate driving circuit 120 is controlled by the controller 140 , and by sequentially outputting scan signals to the plurality of gate lines GL disposed on the display panel 110 , driving timing for the plurality of subpixels SP is performed. to control

The scan signal supplied to the gate line GL swings between a gate low voltage and a gate high voltage higher than the threshold voltage of the transistor.

In the display device 100 having a resolution of 2,160 X 3,840, a case in which scan signals are sequentially output from the first gate line to the 2,160 gate line with respect to 2,160 gate lines GL is called 2,160 phase (2,160 phase) driving. can do. Alternatively, as in the case of sequentially outputting the scan signal from the first gate line to the fourth gate line and then sequentially outputting the scan signal from the fifth gate line to the eighth gate line, the four gate lines GL are A case in which scan signals are sequentially output as a unit is referred to as 4-phase driving. That is, a case in which scan signals are sequentially output for every N gate lines GL may be referred to as N-phase driving.

In this case, the gate driving circuit 120 may include one or more gate driving integrated circuits (GDICs). Depending on the driving method, the gate driving circuit 120 may be located on only one side of the display panel 110 or on both sides. may be located. Alternatively, the gate driving circuit 120 may be built in a bezel region of the display panel 110 to be implemented in the form of a gate in panel (GIP).

Meanwhile, the data driving circuit 130 receives digital image data DATA from the timing controller 140 and converts the received digital image data DATA into an analog data voltage. Then, the data voltage is output to each data line DL according to the timing at which the scan signal is applied through the gate line GL. Accordingly, each sub-pixel SP connected to the data line DL displays a light emitting signal having a brightness corresponding to the data voltage.

Similarly, the data driving circuit 130 may include one or more source driving integrated circuits (SDICs). It may be connected to a bonding pad of the display panel 110 by a glass) method or may be directly disposed on the display panel 110 . In some cases, each source driving integrated circuit SDIC may be integrated and disposed on the display panel 110 . In addition, each source driving integrated circuit SDIC may be implemented in a Chip On Film (COF) method. In this case, each source driving integrated circuit SDIC is mounted on a circuit film, and the display panel is passed through the circuit film. It may be electrically connected to the data line DL of 110 .

The timing controller 140 supplies various control signals to the gate driving circuit 120 and the data driving circuit 130 , and controls operations of the gate driving circuit 120 and the data driving circuit 130 . That is, the timing controller 140 controls the gate driving circuit 120 to output a scan signal according to the timing implemented in each frame, and on the other hand, the image data received from the outside is used by the data driving circuit 130 . It is converted into digital image data DATA according to the data signal format, and transmitted to the data driving circuit 130 .

In this case, the timing controller 140 receives various timing signals including a vertical synchronization signal, a horizontal synchronization signal, a data enable signal, and a clock signal from the outside (eg, a host system) together with the digital image data DATA. do. Accordingly, the timing controller 140 generates a gate control signal GCS and a data control signal DCS using various timing signals received from the outside, and uses the same for the gate driving circuit 120 and the data driving circuit 130 . ) to each.

For example, the timing controller 140 outputs various gate control signals GCS including a gate start pulse, a gate shift clock, and a gate output enable signal to control the gate driving circuit 120 . Here, the gate start pulse controls the timing at which one or more gate driving integrated circuits GDIC constituting the gate driving circuit 120 start operation. Also, the gate shift clock is a clock signal commonly input to one or more gate driving integrated circuits GDIC, and controls shift timing of the scan signal. The gate output enable signal also specifies timing information of one or more gate drive integrated circuits (GDICs).

In addition, the timing controller 140 outputs various data control signals DCS including a source start pulse, a source sampling clock, and a source output enable signal to control the data driving circuit 130 . Here, the source start pulse controls the timing at which one or more source driving integrated circuits SDIC constituting the data driving circuit 130 start data sampling. The source sampling clock is a clock signal that controls the timing of sampling data in the source driving integrated circuit (SDIC). The source output enable signal controls the output timing of the data driving circuit 130 .

The display device 100 supplies various voltages or currents to the display panel 110 , the gate driving circuit 120 , the data driving circuit 130 , or a power management integrated circuit for controlling various voltages or currents to be supplied. may include

Meanwhile, the subpixel SP is positioned at a point where the gate line GL and the data line DL intersect, and a light emitting device may be disposed in each subpixel SP. For example, the organic light emitting display device 100 includes a light emitting device such as a light emitting diode (LED) or an organic light emitting diode (OLED) in each sub-pixel SP, and a current flowing through the light emitting device according to a data voltage is applied. By controlling it, the image can be displayed.

Also, the display device 100 may be various types of devices such as a liquid crystal display device, an organic light emitting display device, a plasma display panel, and a quantum dot display.

2 is an exemplary system diagram of a display device according to embodiments of the present invention.

Referring to FIG. 2 , in the display apparatus 100 according to embodiments of the present invention, the source driving integrated circuit SDIC included in the data driving circuit 130 is a COF among various methods (TAB, COG, COF, etc.). (Chip On Film) is implemented, and the gate driving circuit 120 is implemented in a GIP (Gate In Panel) form among various methods (TAB, COG, COF, GIP, etc.).

Each of the plurality of source driving integrated circuits SDIC included in the data driving circuit 130 may be mounted on the source side circuit film SF, and one side of the source side circuit film SF is connected to the display panel 110 and the display panel 110 . may be electrically connected. Also, wires for electrically connecting the source driving integrated circuit SDIC and the display panel 110 may be disposed on the source side circuit film SF.

The display apparatus 100 includes at least one source printed circuit board (SPCB), control components, and various electric It may include a Control Printed Circuit Board (CPCB) for mounting the devices.

In this case, the other side of the source-side circuit film SF on which the source driving integrated circuit SDIC is mounted may be connected to the at least one source printed circuit board SPCB. That is, one side of the source side circuit film SF on which the source driving integrated circuit SDIC is mounted may be electrically connected to the display panel 110 and the other side may be electrically connected to the source printed circuit board SPCB.

The timing controller 140 and the power management integrated circuit (Power Management IC) 150 may be mounted on the control printed circuit board (CPCB). The timing controller 140 may control operations of the data driving circuit 130 and the gate driving circuit 120 . The power management integrated circuit 150 supplies various voltages or currents, including driving voltages, to the display panel 110 , the data driving circuit 130 , and the gate driving circuit 120 , or controls the supplied voltages or currents. can

The at least one source printed circuit board (SPCB) and the control printed circuit board (CPCB) may be circuitly connected through at least one connecting member, and the connecting member is, for example, a flexible printed circuit (FPC). , a flexible flat cable (FFC), and the like. In addition, at least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) may be integrated into one printed circuit board.

The display apparatus 100 may further include a set board 170 electrically connected to the control printed circuit board (CPCB). In this case, the set board 170 may be referred to as a power board. A main power management circuit 160 that manages the total power of the display apparatus 100 may exist in the set board 170 . The main power management circuit 160 may interwork with the power management integrated circuit 150 .

In the case of the display device 100 having the above configuration, the driving voltage is generated in the set board 170 and transmitted to the power management integrated circuit 150 in the control printed circuit board (CPCB). The power management integrated circuit 150 transmits a driving voltage required for the display driving period or the deterioration sensing period to the source printed circuit board SPCB through the flexible printed circuit (FPC) or the flexible flat cable (FFC). The driving voltage transmitted to the source printed circuit board SPCB is supplied to emit light or sense a specific sub-pixel SP in the display panel 110 through the source driving integrated circuit SDIC.

In this case, each sub-pixel SP arranged in the display panel 110 may include an organic light emitting diode (OLED), which is a light emitting element, and circuit elements such as a driving transistor for driving the organic light emitting diode (OLED).

The type and number of circuit elements constituting each sub-pixel SP may be variously determined according to a provided function and a design method.

3 is a circuit structure diagram of sub-pixels arranged in a display device according to embodiments of the present invention.

Referring to FIG. 3 , a subpixel SP disposed in the display device 100 according to embodiments of the present invention may include one or more transistors and capacitors, and an organic light emitting diode (OLED) is disposed as a light emitting device. can be

For example, the subpixel SP may include a driving transistor DRT, a switching transistor SWT, a sensing transistor SENT, a storage capacitor Cst, and an organic light emitting diode OLED.

The driving transistor DRT has a first node N1 , a second node N2 , and a third node N3 . The first node N1 of the driving transistor DRT may be a gate node to which the data voltage Vdata is applied through the data line DL when the switching transistor SWT is turned on. The second node N2 of the driving transistor DRT may be electrically connected to an anode electrode of the organic light emitting diode OLED, and may be a source node or a drain node. The third node N3 of the driving transistor DRT is electrically connected to the driving voltage line DVL to which the driving voltage VDD is applied, and may be a drain node or a source node.

Here, during the display driving period, the driving voltage VDD necessary for driving the display may be supplied to the driving voltage line DVL. For example, the driving voltage VDD necessary for driving the display may be 27V.

The switching transistor SWT is electrically connected between the first node N1 of the driving transistor DRT and the data line DL, and the gate line GL is connected to the gate node and supplied through the gate line GL. It operates according to the scan signal SCAN. Also, when the switching transistor SWT is turned on, the operation of the driving transistor DRT is controlled by transferring the data voltage Vdata supplied through the data line DL to the gate node of the driving transistor DRT. will do

The sensing transistor SENT is electrically connected between the second node N2 of the driving transistor DRT and the reference voltage line RVL, and the gate line GL is connected to the gate node through the gate line GL. It operates according to the supplied scan signal SCAN. When the sensing transistor SENT is turned on, the sensing reference voltage Vref supplied through the reference voltage line RVL is transferred to the second node N2 of the driving transistor DRT.

That is, by controlling the switching transistor SWT and the sensing transistor SENT, the voltage of the first node N1 and the voltage of the second node N2 of the driving transistor DRT is controlled, and thus the organic light emitting diode OLED ) so that the current to drive it can be supplied.

The switching transistor SWT and the sensing transistor SENT may be connected to the same single gate line GL or may be connected to different signal lines. Here, a structure in which the switching transistor SWT and the sensing transistor SENT are connected to the same one gate line GL is shown as an example, and in this case, the scan signal SCAN transmitted through one gate line GL Accordingly, the switching transistor SWT and the sensing transistor SENT can be simultaneously controlled and the aperture ratio of the subpixel SP can be improved.

Meanwhile, the transistor disposed in the sub-pixel SP may be formed of a p-type transistor as well as an n-type transistor. Here, the case of the n-type transistor is exemplified.

The storage capacitor Cst is electrically connected between the first node N1 and the second node N2 of the driving transistor DRT, and maintains the data voltage Vdata for one frame.

The storage capacitor Cst may be connected between the first node N1 and the third node N3 of the driving transistor DRT depending on the type of the driving transistor DRT. The anode electrode of the organic light emitting diode OLED may be electrically connected to the second node N2 of the driving transistor DRT, and the base voltage VSS may be applied to the cathode electrode of the organic light emitting diode OLED. can Here, the base voltage VSS may be a ground voltage or a voltage higher or lower than the ground voltage. Also, the base voltage VSS may vary according to a driving state. For example, the base voltage VSS of the display driving period and the base voltage VSS of the sensing driving period may be set differently from each other.

At this time, the base voltage line to which the base voltage VSS is supplied extends from the source printed circuit board SPCB to the display panel 110 through the data driving circuit 130 , and in the display panel 110 , the sub-pixel SP ) may have a loop-shaped pattern along the non-display area positioned outside the display area.

In the display device 100 of the present invention, by disposing an impedance matching circuit (IMC) between the base voltage line pattern positioned on the display panel 110 and the base voltage pad of the source printed circuit board (SPCB), the antenna It controls the resonance characteristics and allows the base voltage line pattern to be used as the antenna pattern.

The antenna pattern may have a structure overlapped in several layers with an insulating layer interposed therebetween.

Meanwhile, the antenna pattern may be formed inside a printed circuit board such as a source printed circuit board (SPCB). In this case, when a radio signal (RF signal) is received from the outside while displaying an image on the display panel 110 , , a radio signal may cause a malfunction in the data driving circuit 130, and interference between the data voltage Vdata and the radio signal flowing in through the antenna pattern may reduce the reception sensitivity of the radio signal or display performance. Problems can arise.

In order to solve this problem, the display apparatus 100 according to embodiments of the present invention uses a base voltage line pattern as an antenna pattern and at the same time an impedance matching circuit (IMC) between the base voltage pads of the source printed circuit board (SPCB). ) to control the antenna resonance characteristics.

4 is a diagram illustrating a structure in a case in which a base voltage pattern is used as an antenna pattern in a display device according to embodiments of the present invention.

Referring to FIG. 4 , in the display apparatus 100 according to the embodiments of the present invention, the display panel 110 does not display an image in the display area AA in which an image is displayed and in the periphery of the display area AA. The non-display area NA may be included.

In this case, the base voltage line pattern VSSL_P positioned on the display panel 110 may be arranged in a loop shape in the non-display area NA corresponding to the outer portion of the display area AA.

The base voltage line pattern VSSL_P disposed in the non-display area NA of the display panel 110 may be connected to the base voltage pad VSSP positioned on the source printed circuit board SPCB by the base voltage line VSSL. have.

In this case, one or a plurality of base voltage line pads VSSP supplying the base voltage VSS may be formed in the source printed circuit board SPCB. When a plurality of base voltage pads VSSP are formed, they may be arranged to correspond to the number of data driving circuits 130 including the source driving integrated circuits SDIC. Here, three base voltage pads VSSP are disposed on the source printed circuit board SPCB to correspond to the three data driving circuits 130, and three base voltage lines (VSSP) extending from the three base voltage pads VSSP. A case in which VSSL is electrically connected to the base voltage line pattern VSSL_P formed on the display panel 110 is illustrated as an example.

In addition, the base voltage line VSSL extending from the base voltage pad VSSP and connected to the base voltage line pattern VSSL_P of the display panel 110 drives data to reduce a time delay of the transferred base voltage VSS. It may be formed on the source side circuit film SF constituting the circuit 130 .

In the display apparatus 100 of the present invention, the base voltage line pattern VSSL_P connects the base voltage pad VSSP and the base voltage line pattern VSSL_P so that the base voltage line pattern VSSL_P can be used as an antenna pattern for transmitting and receiving radio signals. An impedance matching circuit IMC may be positioned on the line VSSL.

The impedance matching circuit (IMC) serves to control a resonance frequency characteristic of a radio signal transmitted or received through a base voltage line pattern (VSSL_P) used as an antenna pattern.

That is, by configuring the impedance matching circuit IMC to match the frequency characteristics of the wireless signal transmitted through the base voltage line pattern VSSL_P, it is possible to increase the transmission efficiency of the wireless signal and reduce power consumption.

The impedance matching circuit IMC may include at least one of a resistor R, a capacitor C, and an inductor L.

5 is a diagram illustrating a structure in which an impedance matching circuit is connected to a base voltage line pattern in a display device according to embodiments of the present invention, and FIG. 6 is a diagram illustrating various examples of the impedance matching circuit.

5 and 6 , in the display apparatus 100 according to embodiments of the present invention, the base voltage line VSSL connected to the base voltage line pattern VSSL_P used as the antenna pattern is an impedance matching circuit IMC ) through the base voltage pad (VSSP).

The impedance matching circuit (IMC) is a resistor (R), a capacitor (C), and an inductor (R) to control the resonant frequency characteristics of a radio signal transmitted or received through a base voltage line pattern (VSSL_P) used as an antenna pattern ( L) may include at least one or more impedance elements E1, E2, and E3.

For example, in the impedance matching circuit IMC, the first impedance element E1 and the third impedance element E3 are connected in series between the base voltage pad VSSP and the base voltage line pattern VSSL_P, and the first The second impedance element E2 may be connected between the node between the impedance element E1 and the third impedance element E3 and the ground node.

In this case, in the impedance matching circuit IMC, all three impedance elements E1, E2, E3 composed of the first impedance element E1 to the third impedance element E3 are used, or more impedance elements may be used. , may consist of one or two impedance elements.

In addition, the impedance elements E1 , E2 , and E3 may be selected from a resistor R, a capacitor C, and an inductor L, respectively. For example, all of the first impedance element E1 to the third impedance element E3 may be formed of a resistor, or may be formed of one resistor and two capacitors. That is, the number and type of impedance elements constituting the impedance matching circuit IMC may be variously changed.

Referring to FIG. 6 , the impedance matching (IMC) for controlling the resonance characteristic in the display apparatus 100 according to embodiments of the present invention includes at least one of a resistor (R), a capacitor (C), and an inductor (L). It may be formed of the above impedance elements.

For example, when the wireless signal received through the base voltage line pattern VSSL_P and the internal signal of the display apparatus 100 have the same phase and different magnitudes, the resistance R between the impedance of the wireless signal and the internal signal impedance ), since there is a difference in components, an impedance matching circuit (IMC) may be configured by connecting resistors R of a certain size in parallel (FIG. 6(a)) or in series (FIG. 6(b)).

On the other hand, when the radio signal and the internal signal have different phases and the same size, since there is a difference in frequency component between the impedance of the radio signal and the impedance of the internal signal, a capacitor (C) and an inductor (L) of a certain size are connected in parallel. The impedance matching circuit IMC may be configured by connecting ( FIGS. 6( c ) to 6 ( g ) ).

Of course, when the phase and magnitude of the radio signal received through the base voltage line pattern (VSSL_P) and the internal signal are all different, the impedance matching circuit ( IMC) can be configured.

7 is a signal diagram illustrating a change in a wireless signal according to the configuration of an impedance element used in an impedance matching circuit in a display device according to embodiments of the present invention.

Referring to FIG. 7 , in the display device 100 according to embodiments of the present invention, the base voltage pad VSSP of the source printed circuit board SPCB and the base voltage line pattern VSSL_P of the display panel 110 are connected. The impedance matching circuit IMC formed on the connecting base voltage line VSSL may be configured by connecting at least one impedance element among a resistor R, a capacitor C, and an inductor L in series or in parallel.

In this case, the impedance elements constituting the impedance matching circuit (IMC) may be arranged in various types and shapes. Resonance characteristics with the radio signal transmitted through the base voltage line pattern VSSL_P according to the number and arrangement of the impedance elements. This can be changed.

For example, the impedance matching circuit IMC is connected in series between the base voltage pad VSSP and the base voltage line pattern VSSL_P as shown in FIG. 5 , and the first impedance element E1 and the third impedance element E3 are connected in series. ), and may include a second impedance element E2 connected between a node between the first impedance element E1 and the third impedance element E3 and a ground node.

In this case, the first impedance element E1 may be constituted by a capacitor C, and the second impedance element E2 and the third impedance element E3 may be constituted by a resistor R (Case 1).

Alternatively, the first impedance element E1 and the second impedance element E2 may be constituted by a capacitor C, and the third impedance element E3 may be constituted by a resistor R (cases 2 to 5). . In this case, the second case (Case 2) to the fifth case (Case 5) represent a case in which the value of the second impedance element E2 is different while the value of the first impedance element E1 is the same.

As such, when the positions and configurations of the impedance elements constituting the impedance matching circuit IMC are different, the resonance frequencies of the radio signal transmitted through the base voltage line pattern VSSL_P and the internal signal may be changed.

In other words, by differently changing the configuration and arrangement of the first impedance element E1 to the third impedance element E3 , the resonant frequency of the display apparatus 100 can be controlled, and as a result, the By synchronizing the frequency of the radio signal with the resonant frequency, it is possible to increase the reception sensitivity of the radio signal and increase the efficiency of signal processing.

As described above, the display device 100 of the present invention uses the base voltage line pattern VSSL_P and the configuration of the first impedance elements E1 to E3 included in the impedance matching circuit IMC, It is possible to control the resonance characteristics of the display apparatus 100 in various ways.

Meanwhile, although the case in which the base voltage line pattern VSSL_P formed on the display panel 110 is formed in a closed loop has been described above, a partial region of the base voltage line pattern VSSL_P is opened and an open region is formed through the connection circuit. By connecting the IMC and the impedance matching circuit, the control range of the resonant frequency may be extended.

8 is a diagram illustrating a structure in which a partial region of a base voltage pattern is opened in a display device according to still another exemplary embodiment of the present invention.

Referring to FIG. 8 , in the display apparatus 100 according to still another embodiment of the present invention, the base voltage line pattern VSSL_P positioned on the display panel 110 has a ratio corresponding to the outside of the display area AA. The display area NA may be arranged in a loop shape.

The base voltage line pattern VSSL_P may be formed in a closed loop shape as illustrated in FIG. 5 , or may have an open loop shape in which some regions are formed.

In this case, when a partial region of the base voltage line pattern VSSL_P is opened, the open region is a space between the base voltage lines VSSL connected to the base voltage pad VSSP, that is, between adjacent base voltage lines VSSL. It may correspond to space.

In this case, the base voltage line pattern VSSL_P may be formed in a form in which a space between adjacent base voltage lines VSSL extending along the source side circuit film SF constituting the data driving circuit 130 is opened. .

At this time, the base voltage line VSSL extending from the open region of the base voltage line pattern VSSL_P may be directly connected to the impedance matching circuit IMC, but to be connected to the impedance matching circuit IMC through the connecting circuit CC. may be

Accordingly, at least one base voltage line VSSL formed in the open area in the base voltage line pattern VSSL_P disposed in the non-display area NA of the display panel 110 is connected to the connection circuit CC and the impedance matching circuit IMC. may be connected at the base voltage pad VSSP of the source printed circuit board SPCB through

In this case, one or a plurality of base voltage line pads VSSP supplying the base voltage VSS may be formed in the source printed circuit board SPCB. When a plurality of base voltage pads VSSP are formed, they may be arranged to correspond to the number of data driving circuits 130 including the source driving integrated circuits SDIC. Here, one base voltage pad VSSP is connected to two base voltage lines VSSL through the open area of the base voltage line pad VSSL_P, and the other base voltage pad VSSP is one base voltage line. A case of being electrically connected to the base voltage line pattern VSSL_P of the closed region through (VSSL) is illustrated as an example.

At this time, the base voltage line VSSL extending from the base voltage pad VSSP and connected to the base voltage line pattern VSSL_P in the open region or the closed region uses data to reduce the time delay of the transferred base voltage VSS. It may be formed on the source side circuit film SF constituting the driving circuit 130 .

The impedance matching circuit (IMC) serves to control the resonant frequency characteristic of a radio signal transmitted or received through the base voltage line pattern (VSSL_P) used as the antenna pattern, and the connection circuit (CC) serves to control the base voltage line pattern (VSSL_P). It serves to connect the base voltage line VSSL extending from the open region of VSSL_P to the impedance matching circuit IMC.

As described above, by configuring the impedance matching circuit IMC to match the frequency characteristics of the wireless signal transmitted through the base voltage line pattern VSSL_P, it is possible to increase the transmission efficiency of the wireless signal and reduce power consumption. The impedance matching circuit IMC may include at least one of a resistor R, a capacitor C, and an inductor L.

The connection circuit CC allows two base voltage lines VSSL extending from the open region of the base voltage line pattern VSSL_P to be connected to the impedance matching circuit IMC.

9 is a diagram illustrating a structure when an impedance matching circuit is connected to a base voltage line pattern through a connection circuit in a display device according to embodiments of the present invention.

Referring to FIG. 9 , in the display apparatus 100 according to embodiments of the present invention, a part of a base voltage line pattern VSSL_P used as an antenna pattern is partially opened and a base voltage line VSSL formed in the open area. may be connected to the impedance matching circuit IMC through the connection circuit CC.

The impedance matching circuit (IMC) is a resistor (R), a capacitor (C), and an inductor (R) to control the resonant frequency characteristics of a radio signal transmitted or received through a base voltage line pattern (VSSL_P) used as an antenna pattern ( L) may include at least one or more impedance elements E1, E2, and E3.

For example, in the impedance matching circuit IMC, the first impedance element E1 and the third impedance element E3 are connected in series between the base voltage pad VSSP and the base voltage line pattern VSSL_P, and the first The second impedance element E2 may be connected between the node between the impedance element E1 and the third impedance element E3 and the ground node.

In this case, in the impedance matching circuit IMC, all three impedance elements E1, E2, E3 composed of the first impedance element E1 to the third impedance element E3 are used, or more impedance elements may be used. , may consist of one or two impedance elements.

In addition, the impedance elements E1 , E2 , and E3 may be selected from a resistor R, a capacitor C, and an inductor L, respectively. For example, all of the first impedance element E1 to the third impedance element E3 may be formed of a resistor, or may be formed of one resistor and two capacitors. That is, the number and type of impedance elements constituting the impedance matching circuit IMC may be variously changed.

The connection circuit CC may include two connection elements E4 and E5 that connect the two base voltage lines VSSL extending in the open region of the base voltage line pattern VSSL_P in series.

Each of the connection elements E4 and E5 included in the connection circuit CC may be formed of a resistor. At this time, since the base voltage line VSSL is made of a conductive conductor and may include a resistance component by itself, the connection circuit CC is omitted and the base voltage line VSSL is directly connected to the impedance matching circuit IMC. may be connected.

As described above, the display device 100 of the present invention uses the base voltage line pattern VSSL_P disposed on the display panel 110 as an antenna pattern, so that there is no need to mount an additional antenna pattern, and as a result, the display device It is possible to manufacture a thin film of (100) and improve the antenna performance.

In addition, the display apparatus 100 of the present invention may improve the antenna resonance characteristic by connecting the impedance matching circuit IMC to the base voltage line pattern VSSL_P used as the antenna pattern.

In addition, the display device 100 of the present invention opens a partial region of the base voltage line pattern VSSL_P used as the antenna pattern, and connects the base voltage line VSSL through the connection circuit CC to the impedance matching circuit IMC. By connecting to , it is possible to extend the control range of the resonant frequency.

The above description is merely illustrative of the technical spirit of the present invention, and various modifications and variations will be possible without departing from the essential characteristics of the present invention by those skilled in the art to which the present invention pertains. In addition, since the embodiments disclosed in the present invention are not intended to limit the technical spirit of the present invention, but to explain, the scope of the technical spirit of the present invention is not limited by these embodiments. The protection scope of the present invention should be construed by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

100: display device
110: display panel
120: gate driving circuit
130: data driving circuit
140: timing controller
150: power management integrated circuit
160: main power management circuit
170: set board

Claims (12)

a display panel in which a plurality of sub-pixels are arranged and a base voltage line pattern for applying a base voltage is disposed along an outer side of a display area where an image is displayed;
one or more data driving circuits including a source driving integrated circuit for supplying a data voltage to the display panel through a data line; and
and an impedance matching circuit connected to one or more base voltage lines extending from an arbitrary point of the base voltage line pattern.
According to claim 1,
The data driving circuit is
a source-side circuit film having one side connected to the display panel and the other side connected to the source printed circuit board; and
and the source driving integrated circuit mounted on the source-side circuit film.
3. The method of claim 2,
The base voltage line is
A display device disposed on the source-side circuit film and connected to a base voltage pad of the source printed circuit board.
According to claim 1,
The impedance matching circuit is
A display device comprising at least one impedance element among a resistor, a capacitor, and an inductor.
4. The method of claim 3,
The impedance matching circuit is
a first impedance element and a third impedance element connected in series between the base voltage pad and the base voltage line pattern; and
and a second impedance element connected between a node between the first impedance element and the third impedance element and a ground node.
6. The method of claim 5,
The first impedance element is a capacitor,
The second impedance element and the third impedance element are resistors.
6. The method of claim 5,
the first impedance element and the second impedance element are capacitors;
The third impedance element is a resistor.
According to claim 1,
The base voltage line pattern is
A display device having a closed loop shape surrounding the display area of the display panel.
According to claim 1,
The base voltage line pattern is
and an open area in which a partial section is opened outside the display area of the display panel.
10. The method of claim 9,
the open area
A display device formed to correspond to a space between the data driving circuits.
11. The method of claim 10,
and a connection circuit connecting the base voltage line positioned in the open area and the impedance matching circuit.
12. The method of claim 11,
The connection circuit is
A display device comprising resistance elements each connected to the base voltage line.

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