KR20220075819A - Data recovery method of USB memory device having multi-layered printed circuit board - Google Patents

Abstract

The present invention relates to a data recovery method of a USB memory device having a multilayer printed circuit board, and by using a USB connection device to electrically connect a malfunctioning USB memory device in a decap state and a normal USB memory device to the data of the failed USB memory device It provides a data recovery method of a USB memory device having a multi-layer printed circuit board for recovering.

Description

Data recovery method of USB memory device having multi-layered printed circuit board

The present invention relates to a data recovery method of a USB memory device having a multilayer printed circuit board, and more particularly, to a method for recovering data of a COB (Chip on board) type USB memory device with poor recognition.

A USB (universal serial bus) memory device comprising a flash memory that stores data and a controller that controls it is small in size, convenient to carry, and easy to use. It is one of the indelible storage media. In particular, USB memory devices are widely used as portable memory devices because they have the advantage that data can be freely deleted and stored, unlike CDs and DVDs. However, the USB memory device has a high risk of loss due to its small size, a risk of virus infection, and a weak electrical shock due to a flash memory made of a semiconductor. Accordingly, when the USB memory device is damaged or broken due to an external shock, it is difficult to recover data.

Meanwhile, the USB memory device may be classified into various types according to the implementation form of the flash memory and the controller. For example, there is a general form in which the flash memory and the controller are separated in the form of respective chips and implemented on a board. Such a general USB memory device has limitations in miniaturization of the device because the flash memory and the controller are implemented in the form of separate chips. have. For example, a general USB memory device uses a TSOP-48 chip as a flash memory. In this case, the output position of the data signal of the flash memory chip is standardized. Accordingly, when the host does not recognize a failure due to a failure, the TSOP chip used as a flash memory is removed and inserted into the USB recovery device, so that the data recovery operation can be easily performed.

Recently, the size of a universal serial bus (USB) memory device is gradually decreasing, and in order to implement a memory device having a desired capacity in a narrow space, it is necessary to increase the mounting density of the memory device. In order to solve this problem, memory devices have recently been implemented using a chip on board (hereinafter 'COB') process. That is, as another implementation example of the USB memory device, there is a COB type USB memory device in which a flash memory and a controller are implemented together in the form of a chip on board. Such a COB-type USB memory device has improved performance compared to a general USB memory device, is advantageous for miniaturization, and has advantages of reducing manufacturing cost.

However, in the COB type USB memory device, the output location of the data signal of the flash memory is not determined, and the manufacturer does not provide this information. There are problems that are difficult to recover from.

The technology that is the background of the present application is disclosed in Korean Patent Application Laid-Open No. 10-2014-0143015.

The technical problem to be solved by the present invention is to provide a data recovery method for accurately and quickly recovering data of a defective COB type USB memory device having a multilayer printed circuit board and having a malfunction.

A data recovery method of a USB memory device having a multilayer printed circuit board according to embodiments of the present invention for achieving the above object includes a multilayer printed circuit board and a flash memory mounted on the multilayer printed circuit board, a controller and a manual A method for recovering data from a COB type USB memory device including a device, comprising: a first multilayer printed circuit board; a first flash memory mounted on the first multilayer printed circuit board; a first controller; and a first passive A first USB memory device including a device, a second multi-layer printed circuit board, a second flash memory mounted on the second multi-layer printed circuit board, a second USB memory including a second controller, and a second passive device preparing the device; disconnecting logic data signal lines electrically connected to the first controller and the first passive element among data signal lines of a lowermost layer of a first multilayer printed circuit board; disconnecting memory data signal lines electrically connected to the second flash memory among the data signal lines of a lowermost layer of a second multilayer printed circuit board; exposing memory upper pads electrically connected to the first flash memory among upper connection pads of an uppermost layer of the first multilayer printed circuit board by performing a decapping process; exposing logic upper pads electrically connected to the second controller and the second passive element among upper connection pads of the uppermost layer of the second multilayer printed circuit board by performing a decapping process; and electrically connecting the upper memory pads and the logic upper pads using a USB connection device, wherein the first USB memory device and the second USB memory device are the same USB memory device. The first USB memory device is a faulty USB memory device with poor recognition, and the second USB memory device is a normally operating USB memory device.

According to an embodiment, the USB connection device includes: a plate-shaped base body; a socket unit provided on the base body and having a pair of socket grooves in which the first USB memory device in the decap state and the second USB memory device in the decap state are respectively mounted; a cover part hinged to one side of the socket part to open and close the socket grooves, and a cover part having a pair of connection members respectively connected to the first USB memory device and the second USB memory device mounted on a lower surface thereof; and a host connection part disposed on the base body to be spaced apart from the socket part and having a connection terminal electrically connected to the host.

According to an embodiment, the first USB memory device and the second USB memory device in the decap state are mounted in the socket grooves of the USB connection device, respectively, and elastic probes provided in the connection members are respectively connected to the upper part of the memory. By covering the cover so as to be in contact with the pads and the logic upper connection pads, the memory upper connection pads of the first USB memory device and the logic upper connection pads of the second USB memory device may be electrically connected .

According to an embodiment, disconnecting the logic data signal lines includes cutting the logic data signal lines using a laser marker, and disconnecting the memory data signal lines using a laser marking machine. and cutting the memory data signal lines.

According to embodiments of the present invention, by electrically connecting the uppermost connection pads of the uppermost layer of a malfunctioning USB memory device with poor recognition and a normally operating USB memory device using a USB connection device that is a socket-type adapter, it is better than the wire bonding method. Data can be read and recovered accurately and quickly.

1 is a schematic cross-sectional view illustrating a COB type USB memory device having a multilayer printed circuit board.
FIG. 2 is a schematic cross-sectional view illustrating the multilayer printed circuit board of FIG. 1 .
3 is a plan view illustrating a first substrate of the multilayer printed circuit board of FIG. 1 .
4 is a block diagram showing a schematic configuration of a data recovery system according to embodiments of the present invention.
5 is a diagram for explaining a USB connection device according to embodiments of the present invention.
6 is a flowchart illustrating a data recovery method of a USB memory device having a multilayer printed circuit board according to embodiments of the present invention.
7 and 8 are cross-sectional views for explaining step S10 of FIG. 6 .
9 is a cross-sectional view for explaining step S20 of FIG. 6 .
FIG. 10 is a cross-sectional view for explaining step S30 of FIG. 6 .
11 is a cross-sectional view for explaining step S40 of FIG. 6 .
12 is a cross-sectional view for explaining step S50 of FIG. 6 .
13 and 14 are cross-sectional views for explaining step S60 of FIG. 6 .

Advantages and features of the present invention, and methods for achieving them, will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but may be implemented in various different forms, and only this embodiment serves to complete the disclosure of the present invention, and to obtain common knowledge in the technical field to which the present invention pertains. It is provided to fully inform the possessor of the scope of the invention, and the present invention is only defined by the scope of the claims. Like reference numerals refer to like elements throughout.

In the present specification, when a member is said to be located “on” another member, this includes not only a case in which a member is in contact with another member but also a case in which another member is present between the two members. In addition, in the present specification, when a part "includes" a certain component, this means that other components may be further included, rather than excluding other components, unless specifically stated to the contrary.

As used throughout this specification, the terms "about," "substantially," and the like, are used in a sense at or close to the numerical value when the manufacturing and material tolerances inherent in the stated meaning are presented, and are used in the understanding of this application. It is used to prevent unfair use by unconscionable infringers of the disclosure in which exact or absolute figures are mentioned to help

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a schematic cross-sectional view illustrating a COB type USB memory device having a multilayer printed circuit board.

Referring to FIG. 1 , the USB memory device 10 is a COB type USB memory device, and includes a multilayer printed circuit board 100 , a plurality of circuit elements mounted on the multilayer printed circuit board 100 , and these circuit elements. The sealing member 130 may be included. The plurality of circuit elements may include, for example, the flash memory 200 , the controller 300 , and passive elements (not shown).

The multilayer printed circuit board 100 has a first surface 101 and a second surface 102 opposite to each other, and a plurality of conductive paths (not shown) are formed therein, and are mounted on the first surface 101 . A circuit in which circuit elements such as the flash memory 200 and the controller 300 are electrically connected may be configured. The multilayer printed circuit board 100 will be described in detail later.

The flash memory 200 may include a NAND flash memory, and is mounted on the first surface 101 of the multilayer printed circuit board 100 by wire bonding in a bare chip state. . The controller 300 controls the flash memory 200 in response to a request from the host. For example, the controller 300 may provide data read from the flash memory 200 to the host, and store the data provided from the host in the flash memory 200 . To this end, the controller 300 controls operations such as reading, writing, and erasing of the flash memory 200 .

Interface terminals (not shown) connected to an external device (ie, host) are provided on the second surface 102 of the multilayer printed circuit board 100 , and in a packaging state, the interface terminals are exposed by the molding member 130 . do. The molding member 130 may include, for example, an epoxy molding resin, but is not limited thereto.

FIG. 2 is a schematic cross-sectional view illustrating the multilayer printed circuit board of FIG. 1 . 3 is a plan view illustrating a first substrate of the multilayer printed circuit board of FIG. 1 .

2 and 3 , the multilayer printed circuit board 100 includes a plurality of stacked substrates. For example, a COB type USB memory device may include two or four substrates, but the present invention is not limited thereto. For convenience of description, the multilayer printed circuit board 100 in FIG. 2 is exemplified as including two substrates.

In detail, the multilayer printed circuit board 100 includes a first substrate 110 adjacent to a first surface 101 and a second substrate 120 on the first substrate 110 .

The first substrate 110 includes a first core board 111 , memory connection pads 112 and 113 , logic connection pads 114 and 115 , a first resin layer 116 , and through vias 117 . may include Also, the first substrate 110 may include a first upper surface and a first lower surface that face each other. Here, the first lower surface may correspond to the first surface 101 of the multilayer printed circuit board 100 .

The first core board 111 may include an epoxy resin, a polyimide resin, a bismalemide triazine (BT) resin, FR-4 (Flame Retardant 4), FR-5, ceramic, silicon, or glass. However, this is exemplary, and the present invention is not limited thereto.

The first core board 111 may have a single layer or a multilayer structure including wiring patterns therein. For example, the first core board 111 may be formed by bonding a single rigid flat plate, a plurality of rigid flat plates, or bonding a thin flexible printed circuit board and a rigid flat plate. A plurality of rigid flat plates or printed circuit boards bonded to each other may each include a wiring pattern.

The memory connection pads 112 and 113 are disposed on one side of the first substrate 110 adjacent to the flash memory 200 , and the logic connection pads 114 and 115 are disposed on the first substrate 110 adjacent to the controller 300 . ) may be disposed on the other side.

In detail, the memory connection pads 112 and 113 are disposed on the first lower surface 112 of the first substrate 110 and include lower memory connection pads 112 electrically connected to the flash memory 200 and; It may include upper memory connection pads 113 disposed on the first core board 111 and connected to the lower memory connection pads 112 through the first connection members 118 . The first connecting members 118 may be, for example, bonding wires.

The logic connection pads 114 and 115 are disposed on the first lower surface 112 of the first substrate 110 and are electrically connected to the controller 300 and the passive element (not shown). ) and upper logic connection pads 115 disposed on the first core board 111 and connected to the lower logic connection pads 114 through the second connection members 119 . The second connecting members 119 may be, for example, bonding wires.

The memory connection pads 112 and 113 and the logic connection pads 114 and 115 may include a conductive material. For example, the memory connection pads 112 and 113 and the logic connection pads 114 and 115 may include aluminum (Al), copper (Cu), gold (Au), silver (Ag), tin (Sn), and chromium (Cr). ), palladium (Pd), or an alloy thereof.

The first resin layer 116 may cover the first core board 111 , the memory connection pads 112 and 113 , and the logic connection pads 114 and 115 . The first resin layer 116 may have a multi-layered structure, and a signal layer, a grounding layer, or a power source layer may be interposed between the multi-layered structures, and these may form a wiring pattern.

The through vias 117 may pass through the first resin layer 116 to be connected to the first core board 111 . The through vias 117 may be formed of a conductive material, for example, aluminum (Al), copper (Cu), gold (Au), silver (Ag), tin (Sn), chromium (Cr), palladium (Pd), or a combination thereof. alloys may be included. Each of the through vias 117 may be electrically connected to a corresponding upper memory connection pad 113 or an upper logic connection pad 115 through wiring patterns inside the first core board 111 .

The second substrate 120 may be disposed on the first upper surface of the first substrate 110 . The second substrate 120 may include a second core board 121 , upper connection pads 123 , and a second resin layer 125 . Also, the second substrate 120 may include a second upper surface and a second lower surface that face each other. Here, the second upper surface may correspond to the second surface 102 of the multilayer printed circuit board 100 .

Like the first core board 111 , the second core board 121 is formed of epoxy resin, polyimide resin, bismalemide triazine (BT) resin, FR-4 (FlameRetardant 4), FR-5, ceramic, silicon. or glass. The second core board 121 may have a single layer or a multilayer structure including wiring patterns therein. For example, the second core board 121 may be formed by bonding a single rigid flat plate, a plurality of rigid flat plates, or bonding a thin flexible printed circuit board and a rigid flat plate. A plurality of rigid flat plates or printed circuit boards bonded to each other may each include a wiring pattern.

The upper connection pads 123 may be disposed on the second core board 121 and may be electrically connected to wiring patterns inside the second core board 121 .

The second resin layer 125 may cover the second core board 121 and the upper connection pads 123 . The second resin layer 125 may have a multilayer structure, and a signal layer, a ground layer, or a power source layer may be interposed between the multilayer structures, and these may form a wiring pattern.

Some of the upper connection pads 123 are electrically connected to the flash memory 200 through corresponding through-vias 117 and memory connection pads 112 and 113 , and some of the upper connection pads 123 are electrically connected to the corresponding through-vias 117 . And it may be connected to the controller 300 or a passive element (not shown) through the logic connection pads (114, 115). In other words, the memory connection pads 112 and 113 electrically connected to the flash memory 200 are connected via the corresponding through via 117 , the upper connection pads 123 and the logic connection pads 114 and 115 . It may be electrically connected to the controller 300 .

As a result, the controller 300 and the flash memory 300 are electrically connected through the upper connection pads 123 of the second substrate 120 (in other words, the uppermost substrate), so that the controller 300 is flash The memory 300 is controlled.

Meanwhile, as shown in FIG. 3 , the through vias 117 may correspond to the via pads 117V.

The memory connection pads 112 and 113 , the logic connection pads 114 and 115 , the via pads 117V and the upper connection pads 123 are the flash memory 200 , the controller 300 , and the passive device. A circuit pattern electrically connected to circuit elements such as (not shown) may be formed. As an example, the memory connection pads 112 and 113 , the logic connection pads 114 , 115 , and the via pads 117V are input to the flash memory 200 or a power signal output from the flash memory 200 (eg, , Vcc, Vss, etc.) or data signals (e.g., I/O0~I/15, CLE, ALE, WE, WP, R/B1~R/B4, RE, CE1~CE4 signals, etc.) They may correspond to pin-out points. In other words, some of the memory connection pads 112 and 113 may be electrically connected to a power source (ie, form a power signal line), and other portions may be electrically connected to the flash memory 200 (ie, data to form a signal line). Similarly, some of the logic connection pads 114 and 115 may be electrically connected to a power source (ie, form a power signal line), and other portions may be electrically connected to the controller 300 or a passive element (not shown). (i.e. to form a data signal line).

In the present invention, among the memory connection pads 112 and 113 , the memory connection pads 112 and 113 connected to the flash memory 200 and their connection lines (eg, the first connection member 118 ) are connected to memory data. Logic connection pads 114 and 115 defined as signal lines and electrically connected to the controller 300 or a passive element (not shown) among the logic connection pads 114 and 115 and their connection lines (eg, first The second connection member 119 may be defined as a logic data signal line.

When the USB memory device 10 having the above-described multilayer printed circuit board is normal, the flash memory 200 is electrically connected to the host through the interface, and the controller 300 drives the interface and the flash memory 200 to It reads, writes, and erases data. However, when the USB memory device 10 is not recognized by the host due to a failure such as a crack or poor connection, the flash memory 200 is electrically connected to the host and driven (eg, data is read). device may be required.

4 is a block diagram showing a schematic configuration of a data recovery system according to embodiments of the present invention.

Referring to FIG. 4 , the data recovery system 1 according to embodiments of the present invention recovers data of a USB memory device 10 having a multilayer printed circuit board with poor recognition, and includes a host 400 and A USB connection device 500 may be included.

The host 400 may include portable electronic devices such as a mobile phone or a notebook computer, or electronic devices such as a desktop computer, TV, projector, and the like. The host 400 may include a data recovery program 410 for recovering data of a broken USB memory device. The data recovery program 410 may include, for example, a flash extractor, but is not limited thereto. The data recovery program 410 may control the operation of the flash memory 200 on behalf of the controller 300 , and may recover data of the flash memory 200 .

The USB connection device 500 is a device for electrically connecting a malfunctioning USB memory device of poor recognition and a normally operating USB memory device, and connects the malfunctioning USB memory device in a decapsulation state and the normal USB memory device to the socket unit. After mounting, they can be electrically connected using elastic probes. As the failed USB memory device and the normal USB memory device are connected to each other through the USB connection device 500 , the flash memory of the failed USB memory device is controlled by the controller of the normal USB memory device and stored in the flash memory of the failed USB memory device. The stored data may be read by the host 400 connected to the USB connection device 500 . Hereinafter, the USB connection device 500 will be described in detail with reference to FIG. 5 .

5 is a diagram for explaining a USB connection device according to embodiments of the present invention.

Referring to FIG. 5 , the USB connection device 500 is a socket-type adapter and may include a base body 510 , a socket part 520 , a cover part 530 , and a host connection part 540 .

The base body 510 has a substantially hexahedral plate shape, and may include an internal wiring electrically connected to the USB memory device mounted on the socket unit 520 .

The socket unit 520 may include a pair of socket grooves 522 in which the USB memory devices in the decap state are respectively mounted. For example, a faulty USB memory device with poor recognition may be mounted in one socket groove 522 , and a normally operating USB memory device may be mounted in the other socket groove 522 .

The cover part 530 may be hinged to one side of the socket part 520 to open and close the socket grooves 522 . When the USB memory devices in the decap state are mounted in the socket grooves 522 , the cover part 530 may cover the socket part 520 . A pair of connection members 532 for connecting to USB memory devices mounted in the socket grooves 522 may be provided on the lower surface of the cover part 530 . Elastic probes 534 (refer to FIGS. 13 and 14 ) contacting upper connection pads of the USB memory devices in the decap state may be provided on the connection members 532 . That is, the elastic probes 534 of one connection member 532 are in contact with upper connection pads of the faulty USB memory device, and the elastic probes 534 of the other connection member 532 are in contact with the normal USB memory device. In contact with the upper connection pads of the two USB memory devices can be electrically connected.

The host connection unit 540 is disposed to be spaced apart from the socket unit 520 on the base body 510 , has a connection terminal electrically connected to the host 400 , and receives data read from two electrically connected USB memory devices. It can be transmitted to the host 400 connected to the connection terminal.

Hereinafter, a data recovery method of the USB memory device 10 having a multilayer printed circuit board using the data recovery system 1 described above will be described.

6 is a flowchart illustrating a data recovery method of a USB memory device having a multilayer printed circuit board according to embodiments of the present invention. 7 and 8 are cross-sectional views for explaining step S10 of FIG. 6 . 9 is a cross-sectional view for explaining step S20 of FIG. 6 . FIG. 10 is a cross-sectional view for explaining step S30 of FIG. 6 . 11 is a cross-sectional view for explaining step S40 of FIG. 6 . 12 is a cross-sectional view for explaining step S50 of FIG. 6 . 13 and 14 are cross-sectional views for explaining step S60 of FIG. 6 .

A data recovery method of a USB memory device having a multilayer printed circuit board according to embodiments of the present invention is a COB type of a multilayer printed circuit board and a flash memory mounted on the multilayer printed circuit board, a controller, and a passive device. How to recover data from a USB memory device.

Referring first to FIGS. 6, 7 and 8 , a first USB memory device 10A having a first multilayer printed circuit board 100A and a second USB memory having a second multilayer printed circuit board 100B The device 10B may be prepared (S10).

The first USB memory device 10A is a defective USB memory device with poor recognition, and includes a first multi-layer printed circuit board 100A, a first flash memory 200A mounted on the first multi-layer printed circuit board 100A, It may include a first controller 300A and a first passive element (not shown). The first multilayer printed circuit board 100A, the first flash memory 200A, and the first controller 300A of the first USB memory device 10A are the USB memory device 10 described with reference to FIGS. 1 to 3 , respectively. Since it is the same as the configurations 100, 200, and 300 of , a detailed description thereof will be omitted.

The second USB memory device 10B is the same USB memory device as the first USB memory device 10A, and may be a normal USB memory device operating normally. That is, the second USB memory device 10B includes a second multilayer printed circuit board 100B, a second flash memory 200B mounted on the second multilayer printed circuit board 100B, a second controller 300B, and a second 2 may include a passive element (not shown). The configurations 100B, 200B, and 300B of the second USB memory device 10B are the same as the configurations 100, 200, and 300 of the USB memory device 10 described with reference to FIGS. 1 to 3, respectively. A detailed description thereof will be omitted.

6 and 9 , the logic data signal lines electrically connected to the first controller 300A and the first passive element among the data signal lines of the lowermost layer of the first multilayer printed circuit board 100A may be disconnected. There is (S20).

In the present invention, logic data signal lines are connected to upper and lower logic connections electrically connected to the first controller 300A and the first passive element in the first substrate 100A, which is the lowermost substrate of the first USB memory device 10A. It may be the pads 114 and 115 and the first connecting member 118 connecting them. Disconnection of the logic data signal lines may include cutting the first connection member 118 using, for example, a laser marking machine, but the present invention is not limited thereto.

The positions of the logic data signal lines can be confirmed using the pin map information of the first USB memory device 10A already obtained through the method disclosed in Patent Registration No. 10-2127768 of the present applicant.

6 and 10 , memory data signal lines electrically connected to the second flash memory 200B among the data signal lines of the lowermost layer of the second multilayer printed circuit board 100B may be disconnected (S30). .

In the present invention, the memory data signal lines are connected to the upper and lower memory connection pads 112 and 113 connected to the second flash memory 200B in the first substrate 100B, which is the lowermost substrate of the second USB memory device 10B. and a second connecting member 119 connecting them. Disconnection of the memory data signal lines may include cutting the second connection member 119 using, for example, a laser marking machine, but the present invention is not limited thereto. The positions of the memory data signal lines can be confirmed using the pin map information of the second USB memory device 10B, which has already been obtained through the method disclosed in Patent Registration No. 10-2127768 of the present applicant.

6 and 11 , the decap process is performed to expose upper connection pads electrically connected to the first flash memory 200A among the upper connection pads of the uppermost layer of the first multilayer printed circuit board 100A. can be (S40).

Decapsulation refers to the removal of an epoxy molding compound (EMC) or plastic part of an IC package to detect defects inside the IC package, and refers to an etching process (etching process) that opens the inside of the IC package. . For example, the decap process may include a method using a chemical etching reaction, a method using a laser, or a method using a plasma.

In this example, the upper connection pads of the uppermost layer of the first multilayer printed circuit board 100A may be the upper connection pads 123 of the second substrate 120A, and among them, the first flash memory 200A and the first flash memory 200A are electrically connected. The connected upper connection pads 123 may be referred to as memory upper connection pads. The memory upper connection pads may be electrically connected to a memory data signal line and a power signal line of the first substrate 100A.

The decapsulation process is performed to remove one surface (that is, the rear surface of the first USB memory device 10A) of the molding member 130 covering the second surface 102 of the first multilayer printed circuit board 100A, and , until the memory upper connection pads provided on the second substrate 120, which is the uppermost substrate, are exposed.

6 and 12 , an upper connection electrically connected to a second controller 300B and a second passive element among upper connection pads of the uppermost layer of the second multilayer printed circuit board 100B by performing a decap process The pads may be exposed (S50).

In this example, the upper connection pads of the uppermost layer of the second multilayer printed circuit board 100B may be the upper connection pads 123 of the second substrate 120B, of which the second flash memory 100B and the second The upper connection pads 123 electrically connected to the passive element may be referred to as logic upper connection pads. The logic upper connection pads may be electrically connected to the logic data signal line and the power signal line of the first substrate 110B.

The decapsulation process is performed to remove one surface of the molding member 130 covering the second surface 102 of the second multilayer printed circuit board 100B (that is, the rear surface of the second USB memory device 10B). , until the logic upper connection pads 123 provided on the second substrate 120B, which is the uppermost substrate, are exposed.

Meanwhile, the positions of the above-described memory logic connection pads and logic upper connection pads are pin maps of the first and second USB memory devices 10A and 10B already obtained through the method disclosed in Patent No. 10-2127768 of the present applicant. information can be verified.

6, 13 and 14 , using the USB memory device 500 , the upper memory connection pads of the first USB memory device 10A and the logic upper connection pad of the second USB memory device 10B are used. may be electrically connected to each other (S60).

In detail, the first USB memory device 10A and the second USB memory device 10B in the decap state are mounted on the socket unit 520 of the USB connection device 500 , respectively, and provided in the connection members 532 . By covering the cover part 530 so that the elastic probes 534 come into contact with the memory upper connection pads and the logic upper connection pads, respectively, the memory upper connection pads of the first USB memory device 10A and the second USB memory The logic upper connection pads of device 10B may be electrically connected. The elastic probes 534 provided in the connection members 532 may be designed based on previously obtained location information of the memory logic connection pads and the logic upper connection pads.

As the first USB memory device 10A and the second USB memory device 10B are connected to each other through the USB connection device 500 , the first flash memory 200A of the first USB memory device 10A becomes the second It may be controlled by the second controller 300B of the USB memory device 10B, and accordingly, the first USB memory device 10A and the second USB memory device 10B are connected to the host 400 connected to the host connection unit 540 . ) can be recognized.

Thereafter, according to the read signal of the host 400 , the data stored in the first flash memory 200A of the first USB memory device 10A is read by the host 400 , and a data recovery program installed in the host 400 ( The data of the first flash memory 200A is recovered through 4100, so that the data recovery process of the first USB memory device 10A having the multilayer printed circuit board with poor recognition can be completed.

In the case of the existing data recovery method, which recovers data by recognizing a USB memory device with poor recognition by connecting pin-out points formed on the lowermost substrate through wire bonding, the time required for the wire bonding operation becomes longer and the pinout Due to the narrow pitch between the points, it was difficult to accurately read and recover data due to high work difficulty. According to embodiments of the present invention, by electrically connecting the uppermost connection pads of the uppermost layer of a malfunctioning USB memory device with poor recognition and a normally operating USB memory device using a USB connection device that is a socket-type adapter, it is better than the wire bonding method. Data can be read and recovered accurately and quickly.

In the present specification, preferred embodiments of the present invention have been disclosed, and although specific terms are used, these are only used in a general sense to easily explain the technical content of the present invention and help the understanding of the present invention, and to limit the scope of the present invention. It is not meant to be limiting. It is apparent to those of ordinary skill in the art to which the present invention pertains that other modifications based on the technical spirit of the present invention can be implemented in addition to the embodiments disclosed herein.

10, 10A, 10B: USB memory device having a multilayer printed circuit board
200, 200A, 200B: Flash memory
300, 300A, 300B: Controller
400: host
500: USB connected device

Claims (4)

A method for recovering data from a COB type USB memory device including a multilayer printed circuit board and a flash memory mounted on the multilayer printed circuit board, a controller, and a passive element, the method comprising:
A first multilayer printed circuit board, a first flash memory mounted on the first multilayer printed circuit board, a first USB memory device including a first controller and a first passive element, and a second multilayer printed circuit board; preparing a second USB memory device including a second flash memory, a second controller, and a second passive device mounted on the second multilayer printed circuit board;
disconnecting logic data signal lines electrically connected to the first controller and the first passive element among the data signal lines of the lowermost layer of the first multilayer printed circuit board;
disconnecting memory data signal lines electrically connected to the second flash memory among the data signal lines of the lowermost layer of the second multilayer printed circuit board;
exposing memory upper pads electrically connected to the first flash memory among upper connection pads of an uppermost layer of the first multilayer printed circuit board by performing a decapping process;
exposing logic upper pads electrically connected to the second controller and the second passive element among upper connection pads of an uppermost layer of the second multilayer printed circuit board by performing a decapping process; and
using a USB connection device to electrically connect the memory upper pads and the logic upper pads;
The first USB memory device and the second USB memory device are the same USB memory device, wherein the first USB memory device is a faulty USB memory device with poor recognition, and the second USB memory device is a normally operating USB memory device. A data recovery method of a USB memory device equipped with a phosphorus multilayer printed circuit board. According to claim 1,
The USB connected device is:
plate-shaped base body;
a socket unit provided on the base body and having a pair of socket grooves in which the first USB memory device in the decap state and the second USB memory device in the decap state are mounted, respectively;
a cover part hinged to one side of the socket part to open and close the socket grooves, and a cover part having a pair of connection members respectively connected to the first USB memory device and the second USB memory device mounted on a lower surface thereof; and
A data recovery method of a USB memory device provided with a multilayer printed circuit board including a host connection part disposed on the base body to be spaced apart from the socket part and having a connection terminal electrically connected to the host. 3. The method of claim 2,
The first USB memory device and the second USB memory device in the decap state are mounted in the socket grooves of the USB connection device, respectively, and elastic probes provided in the connection members are respectively attached to the memory upper connection pads and the logic upper part. A multilayer printed circuit board is provided in which the upper memory connection pads of the first USB memory device and the logic upper connection pads of the second USB memory device are electrically connected to each other by covering the cover portion so as to be in contact with the connection pads. How to recover data from a USB memory device. According to claim 1,
Disconnecting the logic data signal lines includes cutting the logic data signal lines using a laser marking machine,
The step of disconnecting the memory data signal lines includes cutting the memory data signal lines using a laser marking machine.

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