KR20220073318A - Counterfactually implemeting universal logic gate and calculate method using the same - Google Patents

Abstract

The present invention relates to a semi-realistic general-purpose logic gate and an operation method using the same, a qubit state input unit for inputting a plurality of qubit states, and quantum absorption for absorbing the qubit states to transfer the qubit states to a quantum channel It may include a logic matching unit that interprets the state of the qubit input to the quantum channel in order to match the state of the quasi-real logic gate, and a reflective logic gate unit that calculates a result value corresponding to the state of the qubit. have.

Description

Counterfactual general purpose logic gate and calculation method using the same

The present invention relates to a semi-realistic general-purpose logic gate and method, and an object of the present invention is to provide a semi-realistic general-purpose logic gate and method capable of calculating a more accurate result and a simplified circuit structure compared to a conventional semi-realistic general-purpose logic gate.

Quantum information may be stored in any of a variety of quantum mechanical systems. Conventionally, quantum information may be stored using quantum bits called qubits, typically two-state quantum mechanical systems.

The ability to prepare and control the quantum state of a quantum system is very important in quantum information processing. In classical computers, gates were determined by a Boolean function.

Such a gate can be implemented through a semi-realistic general-purpose logic gate, but the conventional technology has a problem in that the circuit structure is complicated.

Korean Patent Application Laid-Open No. 10-2018-0104005 (2018.09.19) relates to a technology and related systems and methods for manipulating a 2-qubit quantum state, and is distributed in a first quantum mechanical oscillator. A method of operating a system comprising a multi-level quantum system coupled and distributively coupled to a second quantum mechanical oscillator, the method comprising: applying a first drive waveform to the multi-level quantum system; applying one or more second drive waveforms to the first quantum mechanical oscillator; and applying one or more third drive waveforms to the second quantum mechanical oscillator.

Korean Patent Application Laid-Open No. 10-2009-0127495 (2009.12.14) relates to a multi-quantum bit logic gate, and more specifically, it is applied to the upper silicon layer (top-Si) of a SOI (Silicon On Insulator) substrate. Forming a conduction channel in which a double quantum dot with a line width and length of tens of nanometers or less connecting the source and drain is to be formed and multiple side gates in a vertical direction therewith with a separation distance of tens of nanometers or less, and doping the rest except for the multiple quantum dots After forming a gate oxide film, a control gate for inducing a two-dimensional electron gas layer in the conduction channel is formed, and a conventional metallization process is included. The characteristics of the core operation of the device completed through this structure and manufacturing method are the spin ground state and excited spin of electrons in the system composed of the spin of two electrons in two coupled double quantum dots under magnetic or electric field pulses. It is a device designed to perform quantum computation as desired by using the entanglement phenomenon between states and the spin singlet-triplet transition phenomenon.

Korean Patent Publication No. 10-2018-0104005 (2018.09.19) Korean Patent Publication No. 10-2009-0127495 (2009.12.14)

An embodiment of the present invention is to provide a semi-realistic general-purpose logic gate capable of realizing a logic gate without exchanging particles through the semi-realistic logic gate, and an operation method using the same.

An embodiment of the present invention is to provide a semi-realistic general-purpose logic gate in which complexity is removed from a circuit configuration compared to a conventional semi-realistic logic gate, and an operation method using the same.

In embodiments, the semi-realistic general-purpose logic gate includes a qubit state input for inputting a plurality of qubit states, a quantum absorber for absorbing the qubit state to transfer the qubit states to a quantum channel, and a quantum channel to the quantum channel. It may include a logic matching unit that interprets the input state of the qubit in order to match the state of the reflective logic gate, and a reflective logic gate unit that calculates a result value corresponding to the state of the qubit.

The plurality of qubit states may be independently and discretely defined, and may be input to the quantum absorption unit as the polarized particles of the reflective logic gate unit are input.

The qubit state input unit may input the qubit state in the order of an external cycle and an internal cycle, and the number of internal cycles may be greater than the number of external cycles.

The quantum absorber may separately absorb each of the qubit states through an absorber for each of the qubit states.

The logic matching unit may sequentially interpret the states of the qubits through a photon oscillator.

The reflective logic gate unit may operate as a block gate or a non-block gate in which the operation of the inner cycle blocks the operation of the outer cycle based on input values of the qubit states.

The reflective logic gate unit may derive a result value corresponding to the qubit state as in [Equation 1].

[Equation 1]

은 큐비트 상태 입력이 0,0인 경우 m 번의 내부 싸이클 후의 결과 값, M은 수행할 내부 싸이클의 횟수,

,

,

이다.)(From here,

is the result value after m internal cycles when the qubit state input is 0,0, M is the number of internal cycles to be performed,

,

,

to be.)

The reflective logic gate unit may differently calculate a result value corresponding to the qubit state through Pauli transformation.

In embodiments, the calculation method using a semi-realistic general-purpose logic gate includes a qubit state input step of inputting a plurality of qubit states, a quantum absorption step of absorbing the qubit state to transfer the qubit states to a quantum channel. , a logic matching step of sequentially interpreting the state of the qubits input to the quantum channel to match the semi-realistic logic gate, and a result value calculating step of calculating a result value corresponding to the state of the qubit.

The plurality of qubit states may be independently and discretely defined, and may be input to the quantum absorbing member as the polarized particles of the reflective logic gate are input.

In the step of inputting the qubit state, the qubit state may be input in the order of an external cycle and an internal cycle, and the number of internal cycles may be greater than the number of external cycles.

In the quantum absorption step, each of the qubit states may be separately absorbed through an absorber for each of the qubit states.

In the logic matching step, the qubit states may be sequentially interpreted through a photon oscillator.

In the calculating of the result value, the operation of the inner cycle may operate as a block gate or a non-block gate that blocks the operation of the outer cycle based on the input values of the qubit states.

In the step of calculating the result value, a result value corresponding to the qubit state may be derived as in [Equation 1].

[Equation 1]

은 큐비트 상태 입력이 0,0인 경우 m 번의 내부 싸이클 후의 결과 값, M은 수행할 내부 싸이클의 횟수,

,

,

이다.)(From here,

is the result value after m internal cycles when the qubit state input is 0,0, M is the number of internal cycles to be performed,

,

,

to be.)

In the step of calculating the result value, the result value corresponding to the qubit state may be differently calculated through Pauli transformation.

Among the embodiments, the calculation method using a semi-realistic general-purpose logic gate includes a qubit state input step of inputting three or more qubit states in the order of an external cycle and an internal cycle, and the qubit state to transfer the qubit states to the quantum channel. A quantum absorption step of absorbing the bit state, a logic matching step of sequentially interpreting the qubit state input to the quantum channel to match the semi-realistic logic gate unit, and a different internal cycle of a result value corresponding to the qubit state It may include a step of calculating a result value that is calculated to be probabilistically distinguished according to the number of times performed.

The disclosed technology may have the following effects. However, this does not mean that a specific embodiment should include all of the following effects or only the following effects, so the scope of the disclosed technology should not be understood as being limited thereby.

A semi-realistic general-purpose logic gate and a calculation method using the same according to an embodiment of the present invention can implement a logic gate without exchanging particles through the semi-realistic logic gate.

The semi-realistic general-purpose logic gate and the calculation method using the same according to an embodiment of the present invention can eliminate complexity in circuit configuration compared to the conventional semi-realistic logic gate.

1 is a diagram illustrating a functional configuration of a semi-realistic general-purpose logic gate according to an embodiment of the present invention.
2 is a diagram illustrating a conventional semi-realistic logic gate.
3 is a view for explaining the operating principle of a semi-realistic general-purpose logic gate according to an embodiment of the present invention.
4 is a diagram for explaining the operating principle of a semi-realistic general-purpose logic gate according to states of three or more qubits according to an embodiment of the present invention.
5 is a diagram illustrating a success probability of a semi-realistic general-purpose logic gate according to an embodiment of the present invention.
6 is a diagram illustrating input and result values of a semi-realistic general-purpose logic gate according to an embodiment of the present invention.
7 is a diagram illustrating a flowchart of an operation method using a semi-realistic general-purpose logic gate according to an embodiment of the present invention.

Specific structural or functional descriptions of the embodiments of the present invention disclosed in the present specification or application are only exemplified for the purpose of describing the embodiments according to the present invention, and the embodiments according to the present invention may be implemented in various forms. and should not be construed as being limited to the embodiments described in the present specification or application.

Since the embodiment according to the present invention can have various changes and can have various forms, specific embodiments are illustrated in the drawings and described in detail in the present specification or application. However, this is not intended to limit the embodiment according to the concept of the present invention with respect to a specific disclosed form, and should be understood to include all changes, equivalents or substitutes included in the spirit and scope of the present invention.

Terms such as first and/or second may be used to describe various elements, but the elements should not be limited by the terms. The above terms are used only for the purpose of distinguishing one element from another element, for example, without departing from the scope of the present invention, a first element may be called a second element, and similarly The second component may also be referred to as the first component.

When an element is referred to as being “connected” or “connected” to another element, it is understood that it may be directly connected or connected to the other element, but other elements may exist in between. it should be On the other hand, when it is said that a certain element is "directly connected" or "directly connected" to another element, it should be understood that the other element does not exist in the middle. Other expressions describing the relationship between elements, such as "between" and "immediately between" or "neighboring to" and "directly adjacent to", etc., should be interpreted similarly.

The terms used herein are used only to describe specific embodiments, and are not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly dictates otherwise. In the present specification, terms such as “comprise” or “have” are intended to designate that the described feature, number, step, operation, component, part, or a combination thereof exists, and includes one or more other features or numbers. , it should be understood that it does not preclude the existence or addition of steps, operations, components, parts, or combinations thereof.

Unless defined otherwise, all terms used herein, including technical and scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries should be interpreted as having meanings consistent with the context of the related art, and unless explicitly defined in the present specification, they are not to be interpreted in an ideal or excessively formal meaning. .

Hereinafter, the present invention will be described in detail by describing preferred embodiments of the present invention with reference to the accompanying drawings. Like reference numerals in each figure indicate like elements.

1 is a diagram illustrating a functional configuration of a semi-realistic general-purpose logic gate 100 according to an embodiment of the present invention. Referring to FIG. 1 , a semi-realistic general-purpose logic gate 100 includes a qubit state input unit 110 , a quantum absorber 130 , a logic matching unit 150 , a reflective logic gate unit 170 , and a control unit 190 . may include

The qubit state input unit 110 may input a plurality of qubit states. For example, the qubit state input unit 110 may encode two qubit states through Alice and Bob. In the present invention, qubits may serve as logical qubits, and entangling and disentangling operations between two or more qubits may be performed. In the present invention, it may be possible to perform logical operations on a plurality of qubits.

A plurality of qubit states are independently and discretely defined, and may be input to the quantum absorber as the polarized particles of the reflective logic gate part are input. For example, a plurality of qubit states may be input through Alice and Bob, and Alice and Bob may each independently encode the state of a qubit. For example, Charlie of a semi-realistic logic gate can pass a vertically polarized particle to a photon oscillator, and Alice and Bob can encode the state of a qubit as the vertically polarized particle is received.

In an embodiment, the qubit state input unit 110 may input the qubit state in the order of an external cycle and an internal cycle, and the number of internal cycles may be greater than the number of external cycles. The outer cycle can be performed M times, the states of qubits encoded from Alice and Bob are all 0, and when implementing the NOR gate, the probability that the qubits are discarded while performing the outer cycle is as shown in [Equation 1] can indicate

[Equation 1]

는 큐비트가 폐기될 확률, M은 외부 싸이클을 수행하는 횟수,

이다.)(From here,

is the probability that the qubit will be discarded, M is the number of times an external cycle is performed,

to be.)

The qubit state input unit 110 may maintain a high output value derivation probability by performing an external cycle and an internal cycle exceeding a specific standard. For example, referring to FIG. 5 , FIG. 5 shows the output value derivation probability according to the number of external cycles M and the number of internal cycles N, and it can be seen that the success probability increases as the number of cycles increases. For example, the qubit state input unit 110 may determine the number of external cycles and internal cycles that guarantee a success rate greater than or equal to a specific probability according to a user's setting. Specifically, when it is determined that the user can be guaranteed a success probability of 90% or more, the qubit state input unit 110 determines the number of external and internal cycles having a high probability of 0.9 classification line or higher, which can be confirmed in FIG. 5 . can

In another embodiment, the state of the qubit encoded by Alice is 0, the state of the qubit encoded by Bob is 1, and when implementing the NOR gate, the qubit is discarded while performing the outer cycle and inner cycle The probability can be expressed as [Equation 2].

[Equation 2]

는 큐비트가 폐기될 확률, N은 내부 싸이클 횟수,

,

이다.)(From here,

is the probability that the qubit will be discarded, N is the number of internal cycles,

,

to be.)

In another embodiment, regardless of Bob's encoding value, if the state of the qubit encoded by Alice is 1, and when implementing the NOR gate, the probability that the qubit will be discarded while performing the outer cycle and the inner cycle is It can be expressed as [Equation 2] above.

In another embodiment, when the semi-realistic general-purpose logic gate 100 operates like a NAND gate, the probability that the qubits are discarded may be determined according to the result of [Equation 3].

[Equation 3]

는 입력이 0,0일 때 큐비트가 폐기될 확률,

는 입력이 1,1일 때 큐비트가 폐기될 확률이다.)(From here,

is the probability that the qubit will be discarded when the input is 0,0,

is the probability that the qubit will be discarded when the input is 1, 1.

The quantum absorber 130 may absorb the qubit states in order to transmit them to the quantum channel. Referring to FIGS. 2 and 3 , the structure of the reflective logic gate can be confirmed. The quantum absorber 130 may absorb the corresponding qubit state in order to transfer the qubit state to a quantum channel located between the input of Alice and Bob and the output of Charlie.

In an embodiment, the quantum absorber 130 may separately absorb each of the qubit states through an absorber for each of the qubit states. Referring to FIG. 3 , the quantum absorber 130 may absorb the qubit states of Alice and Bob through separate absorbers.

The logic matching unit 150 may interpret the states of the qubits input to the quantum channel in order to match them with the semi-realistic logic gate unit. For example, the logic matching unit 150 may determine whether to consider Bob's input according to Alice's input, and conversely may determine whether to consider Alice's input according to Bob's input. Specifically, when the semi-realistic general-purpose logic gate 100 operates as a NOR gate, if Alice's input is 1, the output value may be determined regardless of Bob's input. Also, when the semi-realistic general purpose logic gate 100 operates as a NAND gate, when Bob's input is 0, the output value can be determined regardless of Alice's input.

In an embodiment, the logic matching unit 150 may sequentially interpret the qubit states through the photon oscillator. The photon oscillator can determine the order of qubits to be interpreted according to the role of the semi-realistic general-purpose logic gate 100 . For example, the photon oscillator may consider Alice's input first, when the semi-realistic general-purpose logic gate 100 operates as a NOR gate, and Bob's The input can be considered first.

The semi-realistic logic gate unit 170 may calculate a result value corresponding to the state of the qubit. Referring to FIG. 6 , input and output values of the semi-realistic general-purpose logic gate 100 according to an embodiment of the present invention can be confirmed.

In an embodiment, the operation of the inner cycle may operate as a block gate or a non-block gate that blocks the operation of the outer cycle based on input values of qubit states. For example, if the semi-realistic general-purpose logic gate 100 operates as a NOR gate and Alice's input and Bob's input are zero, the operation of the inner cycle may operate as a block gate. As another example, if the semi-realistic general-purpose logic gate 100 operates as a NOR gate and Alice's input is 0 and Bob's input is 1, the operation of the inner cycle may operate as a non-blocking gate. As another example, if the semi-realistic general-purpose logic gate 100 operates as a NOR gate and Alice's input is 1, the operation of the inner cycle may operate as a non-blocking gate, regardless of Bob's input.

In an embodiment, the semi-realistic logic gate unit 170 may derive a result value corresponding to the qubit state as in [Equation 4].

[Equation 4]

은 큐비트 상태 입력이 0,0인 경우 m 번의 외부 싸이클 후의 결과 값, M은 수행할 외부 싸이클의 횟수,

,

,

이다.)(From here,

is the result value after m external cycles when the qubit state input is 0,0, M is the number of external cycles to be performed,

,

,

to be.)

Worse still, if the semi-realistic logic gate unit 170 operates as a NOR gate, and the inputs of Alice and Bob are 0 and M is sufficiently large, the resulting value may be 1. As another example, when the semi-realistic logic gate unit 170 operates as a NOR gate, and Alice's input is 0 and Bob's input is 1, a result value may be derived according to [Equation 5].

[Equation 5]

은 큐비트 상태 입력이 0,1인 경우 m 번의 외부 싸이클 후의 결과 값, M은 수행할 외부 싸이클의 횟수,

,

,

이다.)(From here,

is the result value after m external cycles when the qubit state input is 0,1, M is the number of external cycles to be performed,

,

,

to be.)

As another example, if the semi-realistic logic gate unit 170 operates as a NOR gate and Alice's input is 1, a result value can be derived according to the relationship shown in [Equation 6] regardless of Bob's input. have.

[Equation 6]

는 큐비트 상태 입력이 1,Y인 경우 m 번의 외부 싸이클 후의 결과 값,

는 큐비트 상태 입력이 0,1인 경우 m 번의 외부 싸이클 후의 결과 값이다.)(From here,

is the result value after m external cycles when the qubit state input is 1, Y,

is the result value after m external cycles when the qubit state input is 0,1.)

)은 도 3과 같이 Alice 및 Bob의 입력 그리고 반사실적 논리게이트 후단에서 적용될 수 있다.In an embodiment, the reflective logic gate unit 170 may differently calculate a result value corresponding to the qubit state through Pauli transformation. For example, the reflective logic gate unit 170 may change the operation of the reflective general-purpose logic gate 100 from a NOR gate to a NAND gate through Pauli transformation. The Pauli transformation may correspond to a phase change method that rotates the direction of an input value. For example, the Pauli variant (

) can be applied to the inputs of Alice and Bob and the rear end of the semi-realistic logic gate as shown in FIG. 3 .

For example, when the reflective logic gate unit 170 operates as a NAND gate, a result value may be derived according to [Equation 7].

[Equation 7]

는 입력이 0,0일 때 m번의 외부 싸이클 후의 결과 값,

는 입력이 1,1일 때 m번의 외부 싸이클 후의 결과 값이다.)(From here,

is the result value after m external cycles when the input is 0,0,

is the result value after m external cycles when the input is 1,1.)

The controller 190 controls the overall operation of the reflective general purpose logic gate 100 , and includes a qubit state input unit 110 , a quantum absorber 130 , a logic matching unit 150 , and a reflective logic gate unit 170 . It can manage the control flow or data flow between them.

4 is a diagram for explaining the operating principle of a semi-realistic general-purpose logic gate according to states of three or more qubits according to an embodiment of the present invention. Referring to FIG. 4 , the calculation method using a semi-realistic general-purpose logic gate includes a qubit state input step of inputting three or more qubit states in the order of an external cycle and an internal cycle, and a qubit state to transfer the qubit states to the quantum channel. The quantum absorption step of absorbing the state, the logic matching step of interpreting the qubit state input to the quantum channel in order to match the semi-realistic logic gate unit, and the result value corresponding to the qubit state according to the number of executions of the internal cycle It may include a step of calculating a result value that is calculated to be probabilistically distinguished. For example, in the step of calculating the result value, as in [Equation 4] to [Equation 6], the result value may be different depending on the number of times the internal cycle is performed, which can be confirmed probabilistically in FIG. have.

In an embodiment, when the semi-realistic general-purpose logic gate 100 operates as a NOR gate and three or more qubit states are input, it may have a result value corresponding to [Equation 8].

[Equation 8]

는 입력 큐비트가 모두 0인 경우 결과 값,

는 입력 큐비트 중 어느 하나라도 1이 있는 경우 결과 값이다.)(From here,

is the result value when all input qubits are 0,

is the result value if any of the input qubits is 1.)

In an embodiment, when the semi-realistic general-purpose logic gate 100 operates as a NOR gate and three or more qubit states are input, the qubit corresponding to [Equation 9] may have a probability of being discarded.

[Equation 9]

는 입력 큐비트가 모두 0인 경우 큐비트가 폐기될 확률,

는 입력 큐비트 중 어느 하나라도 1이 있는 경우 큐비트가 폐기될 확률이다.)(From here,

is the probability that a qubit will be discarded if all input qubits are 0,

is the probability that the qubit will be discarded if any of the input qubits are 1.

In an embodiment, when the semi-realistic general-purpose logic gate 100 operates as a NAND gate and three or more qubit states are input, a result value corresponding to [Equation 10] may be obtained.

[Equation 10]

는 입력 큐비트 중 어느 하나라도 0이 있는 경우의 결과 값,

는 입력 큐비트가 모두 1인 경우 결과 값이다.)(From here,

is the result value when any of the input qubits is 0,

is the result value when all input qubits are 1.)

In an embodiment, when the semi-realistic general-purpose logic gate 100 operates as a NAND gate and three or more qubit states are input, the qubit corresponding to [Equation 11] may have a probability of being discarded.

[Equation 11]

는 입력 큐비트 중 어느 하나라도 0이 있는 경우 큐비트가 폐기될 확률,

는 입력 큐비트 모두 1인 경우 큐비트가 폐기될 확률이다.)(From here,

is the probability that a qubit will be discarded if any of the input qubits are zero,

is the probability that the qubit will be discarded if all of the input qubits are 1.)

7 is a diagram illustrating a flowchart of an operation method using a semi-realistic general-purpose logic gate according to an embodiment of the present invention.

Referring to FIG. 7 , in the calculation method using the semi-realistic general purpose logic gate, a plurality of qubit states may be input in the qubit state input step ( S710 ).

The computation method using the semi-realistic general purpose logic gate can absorb the qubit state in order to transfer the states to the quantum channel in the quantum absorption step (S730).

The calculation method using the semi-realistic general-purpose logic gate may interpret the states of the qubits input to the quantum channel in order to match them to the semi-realistic logic gate ( S750 ).

The calculation method using the semi-realistic general purpose logic gate may calculate a result value corresponding to the qubit state in the result value calculation step (S770).

Although the above has been described with reference to preferred embodiments of the present invention, those skilled in the art can variously modify and change the present invention within the scope without departing from the spirit and scope of the present invention as set forth in the claims below. You will understand that it can be done.

100: semi-realistic general purpose logic gate
110: qubit state input unit 130: quantum absorption unit
150: logic matching unit 170: semi-realistic logic gate unit
190: control unit

Claims (17)

a qubit state input unit for inputting a plurality of qubit states;
a quantum absorber for absorbing the qubit state to transfer the qubit state to the quantum channel;
a logic matching unit that sequentially interprets the state of the qubits input to the quantum channel and matches the state of the semi-realistic logic gate; and
and a reflective logic gate unit for calculating a result value corresponding to the state of the qubit.
According to claim 1,
The plurality of qubit states are
A reflective general purpose logic gate defined independently and discretely, wherein the polarized particles of the reflective logic gate are input to the quantum absorber as they are input.
According to claim 1,
The qubit state input unit,
The semi-realistic general purpose logic gate, characterized in that the qubit states are input in the order of an outer cycle and an inner cycle, and the number of the inner cycles is greater than the number of the outer cycles.
According to claim 1,
The quantum absorption unit,
and absorbing each of the qubit states separately through an absorber for each of the qubit states.
According to claim 1,
The logic matching unit,
A semi-realistic general-purpose logic gate, characterized in that it sequentially interprets the states of the qubits through a photon oscillator.
4. The method of claim 3,
The operation of the inner cycle is,
The semi-realistic general purpose logic gate of claim 1, wherein the gate operates as a block gate or a non-block gate that blocks the operation of the external cycle based on the input values of the qubit states.
4. The method of claim 3,
The reflective logic gate part,
A semi-realistic general-purpose logic gate, characterized in that a result value corresponding to the qubit state is derived as in [Equation 1].
[Equation 1]

(From here,

is the result value after m internal cycles when the qubit state input is 0,0, M is the number of internal cycles to be performed,

,

,

to be.)
According to claim 1,
The reflective logic gate part,
A semi-realistic general-purpose logic gate, characterized in that the result value corresponding to the qubit state is calculated differently through Pauli transformation.
a qubit state input step of inputting a plurality of qubit states;
a quantum absorption step of absorbing the qubit state to transfer the qubit state to a quantum channel;
a logic matching step of sequentially interpreting the state of the qubits input to the quantum channel and matching them to a semi-realistic logic gate; and
and calculating a result value of calculating a result value corresponding to the state of the qubit.
10. The method of claim 9,
The plurality of qubit states are
A calculation method using a reflective general-purpose logic gate, which is defined independently and discretely and is input to a quantum absorbing member as the polarized particles of the reflective logic gate are input.
10. The method of claim 9,
The qubit state input step includes:
An operation method using a semi-realistic general-purpose logic gate, characterized in that the qubit state is input in the order of an external cycle and an internal cycle, and the number of the internal cycle is greater than the number of the external cycle.
10. The method of claim 9,
The quantum absorption step is
A calculation method using a semi-realistic general-purpose logic gate, characterized in that each of the qubit states is separately absorbed through an absorber for each of the qubit states.
10. The method of claim 9,
The logical matching step is
A calculation method using a semi-realistic general-purpose logic gate, characterized in that the qubit states are sequentially interpreted through a photon oscillator.
12. The method of claim 11,
The operation of the inner cycle is,
A calculation method using a semi-realistic general-purpose logic gate, characterized in that it operates as a block gate or a non-block gate that blocks the operation of the external cycle based on the input values of the qubit states.
12. The method of claim 11,
The step of calculating the result value is
A calculation method using a semi-realistic general-purpose logic gate, characterized in that a result value corresponding to the qubit state is derived as in [Equation 1].
[Equation 1]

(From here,

is the result value after m internal cycles when the qubit state input is 0,0, M is the number of internal cycles to be performed,

,

,

to be.)
10. The method of claim 9,
The step of calculating the result value is
A calculation method using a semi-realistic general-purpose logic gate, characterized in that the result value corresponding to the qubit state is differently calculated through Pauli transformation.
A qubit state input step of inputting three or more qubit states in the order of an outer cycle and an inner cycle;
a quantum absorption step of absorbing the qubit state to transfer the qubit state to a quantum channel;
a logic matching step of sequentially interpreting the state of the qubits input to the quantum channel and matching them to a semi-realistic logic gate unit; and
and calculating a result value corresponding to the qubit state to be probabilistically distinguished according to the number of executions of the internal cycle.

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