KR20220072186A - SAR SYSTEM BASED ON SoC TECHNOLOGY - Google Patents

Abstract

An SoC technology-based SAR system according to an embodiment is disclosed. The SAR system includes: a signal processing unit that implements a plurality of predetermined functions as each IP (Intellectual Property) and integrates them into an FPGA; and a digital IQ modulator that modulates the baseband digital data generated by the signal processing unit into IF band digital data, a digital upconverter that up-converts the IF band digital data into RF band transmit data, and the received RF band. Transceiver SoC (System on Chip) consisting of a digital down converter that down-converts received data into IF band digital data and a digital IQ demodulator that demodulates the IF band digital data into baseband digital data and outputs it to the signal processing unit. include

Description

SAR system based on SoC technology {SAR SYSTEM BASED ON SoC TECHNOLOGY}

An embodiment of the present invention relates to a SAR system based on SoC technology.

In general, the SAR (Synthetic Aperture Radar) system is a radar that acquires an image of a distant target using electromagnetic waves, and is used to show the characteristics and topography of the earth's surface.

1 is a diagram showing a general SAR system, FIG. 2 is a diagram showing the configuration of a chirp generator of a general SAR system, FIG. 3 is a diagram showing the configuration of a reception data processing device of a general SAR system, and FIG. 4 is a general diagram It is a figure which shows the structure of the timing generator of a SAR system.

Referring to FIG. 1 , the SAR system is composed of a chirp generator for generating a transmission signal, a data processing device for acquiring a reception signal reflected from a target, and a transmission/reception operation timing (Timing) generator of the SAR system.

In order to implement a required function, it is generally composed of a digital assembly, an RF assembly, and an antenna, and is implemented in units or boxes. Since the SAR system is a system built by integrating these components, it can be classified as a medium-large system when classified by size.

Referring to FIG. 2 , a chirp is a pulse-shaped signal having a frequency bandwidth, and the SAR system requires high-quality frequency characteristics and low IMD characteristics to acquire high-resolution images. A chirp is generally generated by controlling a Digital Direct Synthesizer (DDS) or Digital to Analog Converter (DAC) with an FPGA to generate an IQ signal having a bandwidth, and modulating it with an IQ modulator.

Referring to FIG. 3 , the reception data processing device is a device for receiving a signal reflected from a target in the SAR system, and generally uses an IQ demodulator to convert a reception signal down-converted to an IF band to a baseband IQ signal. It is a structure in which the digital data converted by ADC (Analog to Digital Converter) is acquired by FPGA after separation.

Referring to Figure 4, the timing (timing) generating device is a device for generating a PRI (Pulse Repetition Interval) synchronization signal, a transmission synchronization signal, and a reception synchronization signal necessary for coherence of the SAR system, generally SAR It has a structure that generates a synchronization signal to the FPGA by receiving the reference clock of the high-stability oscillator to the device that manages the transmission/reception timing of the system.

In order to miniaturize the SAR system, the integration of the main devices described above is essential. In the existing method, it is possible to implement in a separate device or partially integrated form depending on the function, but it is impossible to implement the main core function by integrating it in the form of a board of 3U size or less due to the number and size of parts.

In the conventional integration method using SoC, the function of generating and processing baseband digital data is implemented in FPGA, but it is impossible to process the frequency of IF or RF band using FPGA in the current method.

Therefore, a method for downsizing the SAR system by integrating the main devices is required.

An object of the present invention for solving the above-mentioned conventional problems is to provide a SAR system based on SoC technology.

The SAR system according to the embodiment includes: a signal processing unit that implements a plurality of predetermined functions as each IP (Intellectual Property) and integrates them into an FPGA; and a digital IQ modulator that modulates the baseband digital data generated by the signal processing unit into IF band digital data, a digital upconverter that up-converts the IF band digital data into RF band transmit data, and the received RF band. Transceiver SoC (System on Chip) consisting of a digital down converter that down-converts received data into IF band digital data and a digital IQ demodulator that demodulates the IF band digital data into baseband digital data and outputs it to the signal processing unit. may include

The plurality of functions may include a function commonly used in a data processing process, a function of generating a transmission chirp, a function of processing received data, and a function of generating a timing signal.

The transceiver SoC includes a DAC that converts the up-converted transmission data of the RF band into a transmission signal of an RF band, which is an analog signal, and outputs it through an antenna; It may further include an ADC that converts the received data and provides it to the digital down-converter.

The transceiver SoC further includes a first digital clock unit providing a first digital clock to the digital IQ modulator and the digital IQ demodulator, and a second digital clock unit providing a second digital clock to the digital up-converter and the digital down-converter. may include

According to the embodiment, the SAR digital processing apparatus can be miniaturized by distributing and integrating the transmission chirp generation function, data processing function, synchronous timing signal generation function, frequency conversion function, and modulation/demodulation function into Soc for each function.

According to the embodiment, since major functions are distributed and integrated into SoCs for each function, a SAR system with guaranteed stability can be implemented by reducing excessive concentration of functions on a specific IC.

1 is a diagram illustrating a general SAR system.
2 is a diagram showing the configuration of a chirp generator of a general SAR system.
3 is a diagram showing the configuration of a reception data processing apparatus of a general SAR system.
4 is a diagram showing the configuration of a timing generator of a general SAR system.
5 is a diagram illustrating a SAR system according to an embodiment of the present invention.
FIG. 6 is a diagram showing a detailed configuration of the digital IQ modulator shown in FIG. 5 .
7 is a diagram showing a detailed configuration of the digital IQ demodulator shown in FIG.
8 is a diagram illustrating an FPGA SoC in which IP for each signal processing function is integrated.
9 is a diagram illustrating a SAR system based on SoC technology according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

However, the technical spirit of the present invention is not limited to some embodiments described, but may be implemented in various different forms, and within the scope of the technical spirit of the present invention, one or more of the components may be selected between the embodiments. It can be used by combining or substituted with .

In addition, terms (including technical and scientific terms) used in the embodiments of the present invention may be generally understood by those of ordinary skill in the art to which the present invention belongs, unless specifically defined and described explicitly. It may be interpreted as a meaning, and generally used terms such as terms defined in advance may be interpreted in consideration of the contextual meaning of the related art.

In addition, the terminology used in the embodiments of the present invention is for describing the embodiments and is not intended to limit the present invention.

In this specification, the singular form may also include the plural form unless otherwise specified in the phrase, and when it is described as “at least one (or more than one) of A and (and) B, C”, it is combined with A, B, and C It may include one or more of all possible combinations.

In addition, in describing the components of the embodiment of the present invention, terms such as first, second, A, B, (a), (b), etc. may be used.

These terms are only for distinguishing the component from other components, and are not limited to the essence, order, or order of the component by the term.

And, when it is described that a component is 'connected', 'coupled' or 'connected' to another component, the component is not only directly connected, coupled or connected to the other component, but also with the component It may also include a case of 'connected', 'coupled' or 'connected' due to another element between the other elements.

In addition, when it is described as being formed or disposed on “above (above) or under (below)” of each component, the top (above) or bottom (below) is one as well as when two components are in direct contact with each other. Also includes a case in which another component as described above is formed or disposed between two components. In addition, when expressed as “upper (upper) or lower (lower)”, the meaning of not only the upward direction but also the downward direction based on one component may be included.

In the embodiment, a new method is proposed in which a transmission chirp generation function, a data processing function, a synchronization timing signal generation function, a frequency conversion function, and a modulation/demodulation function are distributed and integrated into Soc for each function. In other words, the chirp generation of the C, X, and Ku bands of the SAR system, reception data processing, and synchronization timing signal generation are integrated at the board level using SoC-based digital processing technology.

5 is a diagram showing a SAR system according to an embodiment of the present invention, FIG. 6 is a diagram showing a detailed configuration of the digital IQ modulator shown in FIG. 5, and FIG. 7 is a detailed configuration of the digital IQ demodulator shown in FIG. 5 It is a drawing showing

Referring to FIG. 5 , the SAR system according to an embodiment of the present invention includes a signal processing unit 100 , a digital IQ modulator 210 , a digital IQ demodulator 220 , and a first digital clock unit 230 . , digital up converter 240 , digital down converter 250 , second digital clock unit 260 , DAC (Digital Analog Converter) 270 , ADC (Analog Digital Converter) 280 , a High Power Amplifier (HPA) 300 , a Low Noise Amplifier (LNA) 400 , a circulator 500 , and an antenna 600 may be included.

At this time, the digital IQ modulator 210, the digital IQ demodulator 220, the first digital clock unit 230, the digital up-converter 240, the digital down-converter 250, the second digital clock unit 260, the DAC ( 270) and ADC 280 may be integrated with SoC (System on Chip) technology and implemented as one transceiver. The transceiver SoC can be used to integrate the signal conversion function of the SAR system. Here, SoC technology refers to a technology-intensive semiconductor or technology that implements a system with multiple functions into a single chip.

In the case of a transmitting device that transmits a signal, the signal processing unit 100 may generate digital data I and digital data Q of a baseband.

The digital IQ modulator 210 receives the baseband digital data I and Q generated from the signal processing unit 100 and modulates the digital data I and Q of the IF (Intermediate Frequency) band, and modulates the digital data I and Q of the modulated IF band. By combining digital data I and Q, it is possible to output a transmission signal in the IF band.

Referring to FIG. 6 , the digital IQ modulator 210 according to the embodiment may include an I channel mixer 211 , a Q channel mixer 212 , and a phase shifter 213 .

The I-channel mixer 211 may convert the digital data I of the IF band into digital data I of the IF band by using the digital clock of the predetermined phase and the digital data I of the baseband.

The Q channel mixer 212 may use the baseband digital data Q and the digital clock to convert the IF band digital data Q to output.

The first digital clock unit 230 may provide a digital clock to the I-channel mixer 211 and the Q-channel mixer 212 to convert the baseband signal to be transmitted. In this case, the first digital clock unit 230 may provide the digital clock through the phase converter 213 instead of directly providing the digital clock to the I channel mixer 211 so that the digital data I and Q have a phase difference of 90 degrees.

The phase converter 213 may convert the phase of the digital clock provided from the first digital clock unit 300 so that digital data I and Q have a phase difference of 90 degrees to output. The phase converter 213 may provide the digital clock whose phase is changed by 90 degrees to the I-channel mixer 211 .

Here, the phase shifter 213 is connected to the I-channel mixer 211 , but is not limited thereto, and may be connected to both the I-channel mixer 211 and the Q-channel mixer 212 .

The digital data I of the IF band output from the I channel mixer 211 and the digital data Q of the IF band output from the Q channel mixer 212 may be combined and output as transmission data of one IF band.

The digital up-converter 240 may up-convert and output the transmission data of the RF band using the IF band transmission data output from the IQ modulator 210 and a predetermined digital clock.

The second digital clock unit 260 may provide the digital clock to the digital up-converter 240 .

The DAC 270 may convert RF band transmission data that is digital data output from the digital up-converter 240 into an analog signal to output a RF band transmission signal.

The HPA 300 may amplify the power to transmit the RF band transmission signal output from the DAC 270 to the destination, and may output it through the antenna 600 through the circulator 500 .

As described above, in the embodiment, when transmitting a signal, digital data of a baseband is converted into digital data of an RF band in a digital manner, and then converted into an analog signal. That is, in the SAR system according to the embodiment, loss and imbalance characteristics of a transmission signal can be improved by digitally processing the modulation function and the frequency conversion function.

In the case of a receiving device that receives a signal, the LNA 400 receives a received signal in the RF band received through the antenna 600 through the circulator 500, and minimizes noise from the received signal in the RF band. power can be amplified.

The ADC 280 may convert a reception signal of an RF band, which is an analog signal output from the LNA 400 , into digital data to output reception data of the RF band.

The digital down converter 250 may down-convert and output the received data of the IF band using the RF band received data output from the ADC 280 and a predetermined digital clock.

The converted received data of the IF band may be divided into digital data I and Q of the IF band.

The digital IQ demodulator 220 may demodulate the digital data I and Q of the IF band output from the digital down converter 250 into digital data I and Q of the baseband and output the demodulated data to the signal processing unit 100 .

Referring to FIG. 7 , the digital IQ demodulator 220 according to the embodiment may include an I channel mixer 221 , a Q channel mixer 222 , and a phase converter 223 .

The I-channel mixer 221 may convert the digital data I of the IF band and the digital clock from the digital down converter 420 into digital data I of the baseband and output the converted data.

The Q channel mixer 222 may convert the digital data Q of the IF band and the digital clock in which a predetermined phase is converted from the digital down converter 420 into digital data I of the baseband and output the converted digital data I.

The second digital clock unit 260 may provide a digital clock to the I-channel mixer 221 and the Q-channel mixer 222 to convert the IF band signal into a baseband signal. In this case, the second digital clock unit 260 may provide the digital clock through the phase converter 223 instead of directly providing the digital clock to the Q channel mixer 222 so that the digital data I and Q have a phase difference of 90 degrees.

The phase converter 223 may convert the phase of the digital clock provided from the second digital clock unit 260 so that the digital data I and Q have a phase difference of 90 degrees and output the same. The phase converter 223 may provide the digital clock whose phase is changed by 90 degrees to the Q channel mixer 222 .

Here, the phase shifter 223 is connected to the Q channel mixer 222 , but is not limited thereto, and may be connected to both the I channel mixer 221 and the Q channel mixer 222 .

8 is a diagram illustrating an FPGA SoC in which IP for each signal processing function is integrated.

Referring to FIG. 8 , the signal processing unit according to the embodiment performs generation of waveform data for chirp generation, processing of received data, generation of a synchronous timing signal, and high-speed transmission of transmitted/received digital data to IP (Intellectual Property) It can be implemented as an FPGA and integrated into an FPGA to implement an FPGA SoC.

For example, the signal processing unit according to the embodiment implements a common function used in a data processing process such as a function of generating a control clock or transmitting or storing data, a transmission chirp generation function, a reception data processing function, and a timing generation function in IP. It can be integrated into an FPGA.

Here, IP may mean a logic circuit block that can be used when making an FPGA.

9 is a diagram illustrating a SAR system based on SoC technology according to an embodiment of the present invention.

Referring to FIG. 9, the SAR system according to an embodiment of the present invention distributes and integrates major functions into SoC, so that FPGA SoC (100), transceiver SoC (200), HPA (300), LNA (400), circulator ( 500) and the antenna 600, the SAR digital processing device can be miniaturized.

The term '~ unit' used in this embodiment means software or hardware components such as field-programmable gate array (FPGA) or ASIC, and '~ unit' performs certain roles. However, '-part' is not limited to software or hardware. '~' may be configured to reside on an addressable storage medium or may be configured to refresh one or more processors. Accordingly, as an example, '~' indicates components such as software components, object-oriented software components, class components, and task components, and processes, functions, properties, and procedures. , subroutines, segments of program code, drivers, firmware, microcode, circuitry, data, databases, data structures, tables, arrays, and variables. The functions provided in the components and '~ units' may be combined into a smaller number of components and '~ units' or further separated into additional components and '~ units'. In addition, components and '~ units' may be implemented to play one or more CPUs in a device or secure multimedia card.

Although the above has been described with reference to the preferred embodiment of the present invention, those skilled in the art can variously modify and change the present invention within the scope without departing from the spirit and scope of the present invention as described in the claims below. You will understand that it can be done.

100: signal processing unit
200: transceiver
210: digital IQ modulator
220: digital IQ demodulator
230: first digital clock unit
240: digital up-converter
250: digital down converter
260: second digital clock unit
270: DAC
280: ADC
300: HPA
400: LNA
500: circulator
600: antenna

Claims (4)

a signal processing unit integrating a plurality of predetermined functions into an FPGA by implementing each IP (Intellectual Property); and
A digital IQ modulator for modulating the baseband digital data generated from the signal processing unit into IF band digital data, a digital upconverter for up-converting the IF band digital data into RF band transmission data, and reception of the received RF band Transceiver SoC (System on Chip) comprising a digital down converter that down-converts data into IF band digital data and a digital IQ demodulator that demodulates the IF band digital data into baseband digital data and outputs it to the signal processing unit which, SAR system. According to claim 1,
The plurality of functions are
A SAR system comprising a function commonly used in a data processing process, a function for generating a transmission chirp, a function for processing received data, and a function for generating a timing signal. According to claim 1,
The transceiver SoC,
A DAC that converts the up-converted RF band transmission data into an analog RF band transmission signal and outputs it through an antenna, and converts the RF band reception signal received through the antenna into digital data, which is RF band reception data Further comprising an ADC to provide to the digital down-converter, SAR system. According to claim 1,
The transceiver SoC,
The SAR further comprising: a first digital clock unit providing a first digital clock to the digital IQ modulator and the digital IQ demodulator; and a second digital clock unit providing a second digital clock to the digital up-converter and the digital down-converter system.

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