KR20220061814A - Semiconductor Package - Google Patents

Abstract

The present invention relates to a semiconductor package. According to one aspect of the present invention, a semiconductor package includes: a semiconductor chip having a plurality of signal pads and a plurality of non-signal pads formed on a first surface; a redistribution pattern layer including a redistribution part electrically connecting the plurality of non-signal pads and a dummy redistribution part formed on the plurality of signal pads; and a conductive pillar formed in the redistribution part and the dummy redistribution part.

Description

Semiconductor Package {Semiconductor Package}

The present invention relates to a semiconductor package.

In general, a semiconductor package is manufactured by performing a semiconductor package process on semiconductor chips manufactured by performing various semiconductor processes on a wafer. Recently, in order to reduce the production cost of a semiconductor package, a wafer level package technology in which a semiconductor package process is performed at the wafer level and the semiconductor package at the wafer level that has undergone the semiconductor package process is individualized into individual units has been proposed.

As shown in FIG. 1 , in the semiconductor package 10 , an insulator pattern layer 40 and solder 50 are formed on a semiconductor chip 20 on which a plurality of conductive pads 30a, 30b, and 30c are formed. can be

On the other hand, in general, a plurality of conductive pads 30a, 30b, and 30c of the semiconductor chip 20 are formed, some of which are for power application 30a and ground 30b, and the rest are for signal application 30c. ) are for

On the other hand, as shown in FIG. 1 , the semiconductor package 10 is mounted on a PCB substrate 1 and the like. In order to ground the semiconductor package 10 , a ground pattern 5 must be formed on the PCB substrate 1 . However, for this purpose, there is a problem in that the structure of the PCB substrate 1 becomes complicated and expensive.

SUMMARY OF THE INVENTION The present invention is to solve the above problems, and an object of the present invention is to provide a semiconductor package in which a structure capable of forming a ground is provided in the semiconductor package.

The problems of the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

In order to solve the above problems, according to an aspect of the present invention, there is provided a semiconductor chip comprising: a semiconductor chip having a plurality of signal pads and a plurality of non-signal pads formed on a first surface; a redistribution pattern layer including a redistribution portion electrically connecting the plurality of non-signal pads and a dummy redistribution portion formed on the plurality of signal pads; A semiconductor package including conductive pillars formed in the redistribution portion and the dummy redistribution portion is provided.

The signal pad is formed in an edge area of the first surface, the non-signal pad is located in the center area of the first surface, and the non-signal pad includes a power pad connected to a power source and a ground pad connected to a ground, , the redistribution unit may include a power redistribution connecting the power pad and a ground redistribution connecting the grounding pad.

The ground rewiring may be formed in a line shape, a plate shape having a plurality of holes, or a plate shape having a distortion prevention hole having any one shape of a circle, an ellipse, a polygon, a curve, and a straight line.

The apparatus may further include an insulator pattern layer positioned between the redistribution part and the dummy redistribution part and a semiconductor chip, a connection terminal provided on the conductive pillar, and a barrier layer positioned between the conductive pillar and the connection terminal.

The barrier layer may be formed of nickel or an alloy material containing nickel.

The conductive pillar is formed in a cylindrical or polygonal shape, and a lower end edge thereof is connected to a redistribution unit or a dummy redistribution pattern unit, or a lower end edge thereof is connected to a semiconductor chip or an insulator pattern layer located on the semiconductor chip. can be

A width of the conductive pillar corresponding to the signal pad may be greater than a width of the dummy redistribution part.

A width of the conductive pillar corresponding to the signal pad may be smaller than a width of the dummy redistribution part.

The width of the conductive pillar corresponding to the signal pad may be the same as the width of the dummy redistribution part.

The ground redistribution is an electrically conductive material and is formed in a plate shape to cover the entire first area where the ground pad is disposed and the second area where the signal pad and power pad outside the first area are disposed, An arrangement hole is formed in the area corresponding to the signal pad and the power pad of the area to be inserted and disposed while the dummy redistribution part is spaced apart, and the dummy redistribution part is spaced apart from the inner circumferential surface of the arrangement hole inside the arrangement hole and is electrically shorted can be arranged as much as possible.

The ground redistribution is an electrically conductive material and is formed in a plate shape covering a first area in which the ground pad of the semiconductor chip is disposed, and the dummy redistribution unit includes a signal pad and a power pad outside the first area. The second region may be disposed at a position corresponding to the conductive pad and spaced apart from the redistribution part.

A heat transfer blocking slit may be formed around a region corresponding to the conductive pad of the first region of the redistribution part.

A metal distribution per unit area of the redistribution pattern layer may be uniform over the edge region and the central region.

The redistribution pattern layer may further include a dummy plate disposed in an area corresponding to the signal pad and disposed to form a vertical or left-right symmetrical shape together with the ground redistribution part.

According to another aspect of the present invention, there is provided a semiconductor chip comprising: a semiconductor chip having a plurality of signal pads and a plurality of non-signal pads formed on a first surface; a redistribution pattern layer including a redistribution portion electrically connecting the plurality of non-signal pads and a dummy redistribution portion formed on the plurality of signal pads; conductive pillars formed on the redistribution part and the dummy redistribution part; an external connection substrate to which the conductive filler is electrically connected; A semiconductor package including an encapsulation layer positioned between the external connection substrate and the semiconductor chip is provided.

It may further include a connection terminal positioned between the conductive pillar and the external connection substrate, and the encapsulation layer may be formed to directly contact the upper surface and the side surface of the redistribution part that are not in contact with the conductive pillar.

According to the semiconductor package of the present invention, since the redistribution layer forming the ground is formed in the semiconductor package, there is no need to form a ground pattern for each conductive pillar on the PCB substrate on which the semiconductor package is mounted, thereby simplifying the structure of the PCB substrate and reducing the price. It has the effect of being cheaper.

The problems of the present invention are not limited to the problems mentioned above, and other problems not mentioned will be clearly understood by those skilled in the art from the following description.

The summary set forth above as well as the detailed description of the preferred embodiments of the present application set forth below may be better understood when read in conjunction with the accompanying drawings. For the purpose of illustrating the invention, there are shown in the drawings preferred embodiments. It should be understood, however, that the present application is not limited to the precise arrangements and instrumentalities shown.
1 is a cross-sectional view illustrating a state in which a conventional semiconductor package is mounted on a substrate;
2 is a cross-sectional view illustrating a semiconductor package according to an embodiment of the present invention;
3 is a perspective view illustrating a state in which a redistribution pattern layer is formed on one surface of a semiconductor chip according to an embodiment of the present invention;
4 is a view illustrating a semiconductor package in a state in which a redistribution pattern layer is formed only in a first region;
5 and 6 are views showing openings formed in the insulator pattern layer. FIG. 5 is a view showing a state in which openings are sequentially patterned in the first insulating layer and the second insulating layer, and FIG. It is a view showing a state in which openings are simultaneously patterned in the first insulating layer and the second insulating layer.
7 to 9 are views illustrating a state in which the widths of the conductive pillar and the dummy redistribution portion are variously changed. FIG. 7 is a view illustrating a state in which the width of the dummy redistribution portion is greater than that of the conductive pillar; A diagram illustrating a state in which the width of the dummy redistribution portion is equal to that of the conductive pillars, and FIG. 9 is a diagram illustrating a state in which the width of the dummy redistribution portion is smaller than the width of the conductive pillars.
10 is a cross-sectional view illustrating a state in which a semiconductor package is mounted on a substrate and underfilled according to an embodiment of the present invention;
11 is a view illustrating an example of a redistribution pattern layer of a semiconductor package according to an embodiment of the present invention;
12 is a view illustrating a form in which a heat-blocking slit is further formed in the redistribution pattern layer of FIG. 11;
FIG. 13 is a view illustrating a form in which a distortion prevention hole is further formed in the redistribution pattern layer of FIG. 12 ;
14 is a view illustrating another example of a redistribution pattern layer of a semiconductor package according to an embodiment of the present invention;
15 is a view illustrating a form in which a heat-blocking slit is further formed in the redistribution pattern layer of FIG. 14;
FIG. 16 is a view illustrating a form in which a distortion prevention hole is further formed in the redistribution pattern layer of FIG. 15 ;
17 and 18 are views illustrating another example of a redistribution pattern layer of a semiconductor package according to an embodiment of the present invention. One view, and FIG. 18 is a view showing a state in which a plurality of connection line patterns of the redistribution pattern layer are formed.
19 is a diagram illustrating an example in which a dummy plate is disposed on a redistribution pattern layer of a semiconductor package according to an embodiment of the present invention.

Hereinafter, preferred embodiments of the present invention concept will be described in detail with reference to the accompanying drawings. However, the embodiments of the inventive concept may be modified in various other forms, and the scope of the inventive concept should not be construed as being limited by the embodiments described below. The embodiments of the inventive concept are preferably interpreted as being provided in order to more completely explain the inventive concept to those of ordinary skill in the art. The same symbols refer to the same elements from time to time. Furthermore, various elements and regions in the drawings are schematically drawn. Accordingly, the inventive concept is not limited by the relative size or spacing drawn in the accompanying drawings.

Terms such as first, second, etc. may be used to describe various elements, but the elements are not limited by the terms. The above terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the inventive concept, a first component may be referred to as a second component, and conversely, the second component may be referred to as a first component.

The terms used in the present application are only used to describe specific embodiments, and are not intended to limit the inventive concept. The singular expression includes the plural expression unless the context clearly dictates otherwise. In the present application, expressions such as “comprises” or “have” are intended to designate that a feature, number, step, operation, component, part, or a combination thereof described in the specification exists, and includes one or more other features or It should be understood that the existence or addition of numbers, operations, components, parts or combinations thereof is not precluded in advance.

Unless defined otherwise, all terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the inventive concept belongs, including technical and scientific terms. In addition, commonly used terms as defined in the dictionary should be construed as having a meaning consistent with their meaning in the context of the relevant technology, and unless explicitly defined herein, in an overly formal sense. It will be understood that they shall not be construed.

In cases where certain embodiments may be implemented otherwise, a specific process sequence may be performed different from the described sequence. For example, two processes described in succession may be performed substantially simultaneously, or may be performed in an order opposite to the described order.

In the accompanying drawings, variations of the illustrated shapes can be expected, for example depending on manufacturing technology and/or tolerances. Accordingly, the embodiments of the present invention should not be construed as limited to the specific shape of the region shown in the present specification, but should include, for example, changes in shape resulting from the manufacturing process. As used herein, all terms “and/or” include each and every combination of one or more of the recited elements. Also, as used herein, the term “substrate” may refer to a substrate itself or a laminate structure including a substrate and a predetermined layer or film formed on the surface thereof. Also, in this specification, the term "surface of a substrate" may mean an exposed surface of the substrate itself, or an outer surface of a predetermined layer or film formed on the substrate.

As shown in FIG. 2 , the semiconductor package 100 according to the present embodiment includes a semiconductor chip 110 , an insulator pattern layer 130 , a redistribution pattern layer 140 , a conductive pillar 150 , and a connection terminal 160 . ) may be included.

The semiconductor chip 110 may include, for example, silicon (Si, silicon). Alternatively, it may include a semiconductor element such as germanium (Ge, germanium), or a compound semiconductor such as silicon carbide (SiC), gallium arsenide (GaAs), indium arsenide (InAs), and indium phosphide (InP). In addition, the semiconductor chip 110 may include a conductive region, for example, a well doped with an impurity or a structure doped with an impurity. In addition, it may have various device isolation structures such as a shallow trench isolation (STI) structure.

In addition, a plurality of pads 120a , 120b , and 120c may be provided on the semiconductor chip 110 . The pads 120a, 120b, and 120c include copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), It may be a metal or an alloy thereof, such as cobalt (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), etc. It is not limited to these.

The pads 120a, 120b, and 120c may be separated by the insulator pattern layer 130 . The insulator pattern layer 130 may be formed of, for example, a photo imageable dielectric (PID), an Ajinomoto build-up film (ABF), or a photosensitive polyimide (PSPI).

A portion of the insulator pattern layer 130 corresponding to the pads 120a, 120b, and 120c may be opened to expose the signal pads 120a, 120b, and 120c.

In addition, a redistribution pattern layer 140 may be disposed. The redistribution pattern layer 140 may be disposed on the pads 120a, 120b, and 120c and the insulator pattern layer 130 and may be electrically connected to the pads 120a, 120b, and 120c.

In addition, conductive pillars 150 corresponding to the respective pads may be formed on the redistribution pattern layer 140 , and a connection terminal 160 may be provided at an end of the conductive pillar 150 .

Meanwhile, a plurality of pads are formed on the first surface of the semiconductor chip 110 , some of which are for power application and grounding, and the rest are for signal application.

Hereinafter, among the pads 120a, 120b, and 120c, those for applying a signal will be referred to as signal pads 120c, and those for applying power and grounding will be referred to as non-signal pads 120a and 120b.

In addition, among the non-signal pads 120a and 120b, those for applying power will be referred to as power pads 120a, and those for grounding will be referred to as ground pads 120b.

However, in the present embodiment, the power pad 120a for applying power is formed in the center of the semiconductor chip 110 , and the ground pad 120b for grounding is adjacent to the periphery of the power pad 120a for applying power. and placed In addition, the signal pad 120c for applying a signal is disposed outside the signal pad 120c.

In this case, an area in which the grounding pad 120b responsible for grounding is disposed among the pads 120a, 120b, and 120c is referred to as a first area 101, and the first area among the pads 120a, 120b and 120c is referred to as a first area. A region in which the power pad and signal pads 120a and 120c are disposed outside 101 will be referred to as a second region 102 .

A ground pad 120b for grounding is disposed in the first region 101 , and a power pad 120a for applying power may be disposed at the center thereof. The power pad 120a for applying power is excluded from the first area 101 and may belong to the second area 102 .

That is, the signal pad 120c is formed in an edge region of the first surface of the semiconductor chip 110 , and the ground pad 120b and the power pad 120c, which are non-signal pads, are of the semiconductor chip 110 . It may be located in the central area.

However, as shown in FIGS. 2 and 3 , since the ground pad 120b for grounding requires a lot of redistribution for power supply, the redistribution pattern layer 140 electrically connected to each other may be formed.

The redistribution pattern layer 140 includes copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), indium (In), molybdenum (Mo), manganese (Mn), and cobalt. It may be a metal such as (Co), tin (Sn), nickel (Ni), magnesium (Mg), rhenium (Re), beryllium (Be), gallium (Ga), ruthenium (Ru), etc. or an alloy thereof, but these is not limited to

At this time, as shown in FIG. 4 , since the ground pad 120b for grounding requires a lot of redistribution for power supply, the redistribution pattern layer 140 electrically connected to each other may be formed. In the signal pad 120c for the signal pad 120c, if the redistribution pattern layer 140 is not formed due to a low redistribution requirement, and the conductive pillar 150 and the connection terminal 160 are directly formed on the signal pad 120c, the culture A height difference h may occur between the conductive pillars 150 in the first region 101 in which the line pattern layer 140 is formed and the second region 102 in which the redistribution pattern layer 140 is not formed, In order to compensate for this, it is inconvenient to have the conductive pillar 150 and the connection terminal 160 have different heights from each other.

Accordingly, a portion of the redistribution pattern layer 140 is in contact with the pad of the first region 101 to form a redistribution portion 141 electrically connected to each other, and the other portion of the redistribution pattern layer 140 is It is in contact with the pad of the second region 102, is formed to have the same thickness as the redistribution portion 141, and is formed to be electrically shorted from the redistribution portion 141 and adjacent pads 120a, 120b, and 120c. A dummy redistribution unit 148 may be formed.

Also, a portion of the redistribution unit 141 electrically connected to the power pad 120a will be referred to as a power rewiring, and a portion electrically connected to the ground pad 120b will be referred to as a ground rewiring.

That is, the redistribution pattern layer 140 is formed in both the first area 101 and the second area 102 , and the dummy redistribution unit 148 of the second area 102 is formed by another redistribution unit adjacent thereto. (141) is to be formed so as to be electrically short-circuited.

In this case, the redistribution pattern layer 140 corresponding to the power supply pad 120a for applying power disposed in the center among the pads 120a, 120b, and 120c disposed in the first region 101 is formed in the surrounding redistribution part. It may be a dummy redistribution unit 148 electrically shorted to 141 .

Accordingly, since the height of the conductive pillar 150 and the connection terminal 160 formed on the semiconductor chip 110 is the same in both the first region 101 and the second region 102 , the semiconductor package 100 can be easily manufactured and mounted. It works.

In addition, since the redistribution unit 141 for grounding is formed inside the semiconductor package 100 , a pattern for grounding on the substrate 10 can be minimized, thereby simplifying and inexpensive manufacturing the substrate 10 .

In addition, the insulator pattern layer 130 may include a first insulating layer 131 and a second insulating layer 132 . The first insulating layer 131 may be formed on one surface of the semiconductor chip 110 on which the pad 120 is formed.

In this case, the first insulating layer 131 and the second insulating layer 132 may form an opening 135 that is opened to expose the pad 120 . In the related art, the first insulating layer 131 is After this is formed, an opening is formed, and the pad 120 is exposed through two patterning processes of forming an opening again after forming the second insulating layer 132 .

As shown in FIG. 5, the opening ( 135) Since the second insulating layer 132 is formed on the inner circumferential surface, the opening width W1 of the conductive pad may be reduced by that much.

Therefore, according to the embodiment of the present invention, after both the first insulating layer 131 and the second insulating layer 132 are formed, the openings 135 are patterned at positions corresponding to the pads 120a, 120b, and 120c. can be formed at once.

When the openings 135 are formed at once in this way, as shown in FIG. 6 , the pads 120 are formed due to the openings 135 formed in the first and second insulating layers 131 and 132 . In this case, cross-sections of the first insulating layer 131 and the second insulating layer 132 may be exposed on the inner circumferential surface of the opening 135 .

As such, when the first insulating layer 131 and the second insulating layer 132 are patterned and opened at once, the width W2 of the opening is maximized, and the footprint value of the exposed pad 120 can be increased. There is a point.

In addition, as shown in FIG. 2 , the connection terminal formed at the end of the conductive pillar 150 may also be reflowed to form a round shape, and there is a barrier between the connection terminal 160 and the conductive pillar 150 . A layer 170 may be formed. The barrier layer 170 may be made of nickel or an alloy containing nickel, and since the barrier layer 170 is provided, reliability such as electro-migration (EM) improvement at high current may be reinforced.

Meanwhile, FIGS. 7 to 9 are enlarged views of a portion in which the dummy redistribution unit 148 and the conductive pillar 150 of FIG. 2 are positioned.

7 (a) is a cross-sectional view illustrating a portion in which the dummy redistribution part 148 is formed from the side, and FIG. 7 (b) is a plan view of FIG. 7 (a). 7 , the width Wa of the conductive pillar 150 may be smaller than the width W _D1 of the dummy redistribution part 148 .

8(a) is a cross-sectional view illustrating a portion in which the dummy redistribution part 148 is formed from the side, and FIG. 8(b) is a plan view of FIG. 8(a). As shown in FIG. 8 , the width Wa of the conductive pillar 150 may be substantially the same as the width W _D2 of the dummy redistribution part 148 .

9 (a) is a cross-sectional view illustrating a portion in which the dummy redistribution part 148 is formed from the side, and FIG. 9 (b) is a plan view of FIG. 9 (a). 9 , the width Wa of the conductive pillar 150 may be greater than the width W _D3 of the dummy redistribution part 148 .

Also, as shown in FIG. 9 , the upper surface of the conductive pillar 150 may have a stepped portion S. The width Ws of the upper surface of the step portion S may be substantially the same as or similar to the width W _D3 of the dummy redistribution portion 148 ).

Accordingly, as described above, the width of the dummy redistribution unit 148 may be diversified into an optimal shape according to conditions, and the dummy redistribution unit 148 may be miniaturized if necessary.

Meanwhile, in the semiconductor package 100 shown in FIG. 2, as shown in FIG. 10, the semiconductor chip 110 is surrounded by an epoxy mold compound (EMC: 180) and buried, and the connection terminal 160 is the It may be exposed to the outside of the epoxy mold compound 180 .

In addition, the semiconductor package 100 may be mounted on the substrate 10 as shown in FIG. 10 . After the semiconductor package 100 is mounted on the substrate 10 , an encapsulation layer 190 may be filled between the semiconductor package 100 and the substrate 10 to form an electrically insulating layer.

In this case, the redistribution pattern layer 140 and the insulator pattern layer 130 of the semiconductor package 100 and the conductive pillar 150 may directly contact the encapsulation layer 190 . In addition, the encapsulation layer 190 may be formed to surround the redistribution unit 141 by directly contacting the upper and side surfaces of the redistribution unit 141 exposed without contacting the conductive pillar 150 .

That is, the epoxy mold compound 180 is not formed on the surface of the semiconductor chip 110 on which the insulator pattern layer 130 and the redistribution pattern layer 140 are formed, and the encapsulation layer 190 is not formed. ) may fill the redistribution pattern layer 140 , the insulator pattern layer 130 , and the conductive pillar 150 of the semiconductor package 100 .

In this case, known materials may be used for the encapsulation layer 190 , or the same material as the epoxy mold compound 180 may be used as the encapsulation layer 190 .

Meanwhile, as described above, the redistribution pattern layer 140 includes the redistribution part 141 electrically connected to the ground pad 120b of the first region 101 ) and the conductive pad ( of the second region 102 ). A dummy redistribution unit 148 in contact with 120a and 120c may be included.

At this time, as shown in FIG. 11 , the redistribution part 141 is an electrically conductive material and is formed in a plate shape to cover the entire first region 101 and the second region 102 of the semiconductor chip 110 . can be

In addition, in the region corresponding to the conductive pads 120a and 120c of the second region 102 of the redistribution unit 141 , the arrangement hole 142 is provided so that the dummy redistribution units 148 are inserted and disposed to be spaced apart. can be formed.

The arrangement hole 142 has a size larger than the size of the conductive pads 120a and 120c of the second region 102 so as not to come into contact with the conductive pads 120a and 120c of the second region 102 . can be formed.

In addition, the dummy redistribution part 148 is disposed inside the arrangement hole 142 , and may be spaced apart from an inner circumferential surface of the arrangement hole 142 to be electrically shorted from the redistribution part 141 .

In this case, the arrangement hole 142 is also formed at a position corresponding to the pad 120 for power application located in the central portion of the semiconductor chip 110 , and the dummy redistribution unit 148 may be arranged. .

The dummy redistribution unit 148 may be spaced apart from the redistribution unit 141 as well as from the adjacent dummy redistribution unit 148 .

Also, as shown in FIG. 12 , a heat transfer blocking slit 143 may be formed around an area corresponding to the ground pad 120b of the first area 101 of the redistribution unit 141 . A plurality of the heat transfer blocking slits 143 may be divided so as to be spaced apart from each other around a region corresponding to the conductive pad of the first region 101 .

Accordingly, transfer of heat generated from the ground pad 120b of the first region 101 to the surroundings can be reduced.

On the other hand, thermal deformation may occur in the redistribution layer due to heat generated when power flows to the grounding pad 120b for grounding, and warpage may occur. For this purpose, as shown in FIG. 13 , the redistribution An anti-distortion hole 144 may be formed between a region corresponding to the pad 120 of the first region 101 and the second region 102 of the pattern layer 140 .

The distortion prevention hole 144 may be formed in various shapes including a circle or a polygon, or a curved line and a straight line.

Therefore, even if distortion is generated by the heat generated in the redistribution pattern layer 140, the distortion is prevented from propagating to the surroundings by the distortion prevention hole 144, thereby minimizing the distortion region. .

In the redistribution pattern layer 140 , the distribution of metal per unit area may be substantially uniform over the first region 101 and the second region 102 .

Alternatively, as shown in FIG. 14 , the redistribution part 241 is an electrically conductive material and has a plate-like shape that covers only the first region 101 of the semiconductor chip 110 and does not cover the second region 102 . , and the dummy redistribution part 248 may be disposed at a position corresponding to each of the conductive pads 120a and 120b of the second region 102 to be spaced apart from the redistribution part 241 . Also in this case, an arrangement hole 242 into which the dummy redistribution unit 248 corresponding to the power pad 120a for applying power is inserted may be formed in the center of the redistribution unit 241 .

Alternatively, as shown in FIG. 15 , a heat transfer blocking slit 243 may be formed around an area corresponding to the ground pad 120b of the first area 101 of the redistribution part 241 . A plurality of the heat transfer blocking slits 243 may be divided so as to be spaced apart from each other around a region corresponding to the ground pad 120b of the first region 101 .

Accordingly, transfer of heat generated from the ground pad 120b of the first region 101 to the surroundings can be reduced.

Alternatively, as shown in FIG. 16 , a distortion prevention hole 144 may be formed between a region corresponding to the ground pad 120b of the first region 101 of the redistribution unit 241 .

The distortion prevention hole 144 may be formed in various shapes including a circle or a polygon, or a curved line and a straight line.

Therefore, even if distortion occurs due to the heat generated by the redistribution unit 241 , the distortion is prevented from propagating to the surroundings by the distortion prevention hole 144 , thereby minimizing the distortion region.

As described above, the redistribution part 141 may be formed in a plate shape. Alternatively, the redistribution part may be formed in a line pattern shape instead of a plate shape.

17 and 18 are views illustrating an example in which the redistribution unit 341 is formed in a line pattern shape.

17 , the redistribution part 341 includes a sheet part 345 and a sheet part 345 in which conductive pillars 150 corresponding to the ground pad 120b of the first region 101 are formed. ) and a connection line pattern 346 for electrically interconnecting them, and the dummy redistribution part 348 is located at a position corresponding to the conductive pads 120a and 120c of the second region 102 , the redistribution part 341 . ) and can be arranged in a spaced apart state.

That is, the redistribution part 341 includes the sheet part 345 and the connection line pattern 346 , and the sheet part 345 corresponds to each ground pad 120b of the first region 101 . It is formed in a circular or polygonal shape to form a point where the conductive pillar 150 is formed, and the connection line pattern 346 is a sheet portion 345 formed to correspond to each ground pad 120b of the first region 101 . may be formed to electrically interconnect.

Also, the dummy redistribution part 348 may be disposed to be spaced apart from the redistribution part 341 at a position corresponding to each of the conductive pads 120a and 120c of the second region 102 .

The dummy redistribution unit 348 may be spaced apart from the redistribution unit 341 as well as from the adjacent dummy redistribution unit 348 .

At this time, the connection line pattern 346 of the redistribution unit 341 is formed of one single line 346 as shown in FIG. 17 or a plurality of lines 347 as shown in FIG. 18 . can be connected

In the above-described embodiment, the redistribution units 141 , 241 , and 341 may be formed in a symmetrical shape. That is, it may be formed to have a mutually symmetrical shape in up-down or left-right directions on a plane. Through this, even when deformation such as thermal expansion and thermal contraction occurs in the redistribution portions 141 , 241 , and 341 , it is deformed in a symmetrical form and excessive stress is prevented from being concentrated in one part of the semiconductor package. .

In the above-described embodiments, the first region 101 is formed in a rectangular shape that is generally symmetrical in the vertical, left, and right directions as an example, but it is not necessarily limited thereto. As shown in FIG. 19 , the pad at the corner of the first area 101 having a rectangular shape may be formed as a pad for applying a signal to the second area instead of the first area.

In this case, in order to form the redistribution part 441 symmetrically, it is spaced apart from the redistribution part 441 at a position corresponding to a quadrangular corner of the first region 101 , and is quadrangular together with the redistribution part 441 . A dummy plate 443 may be disposed to form

Also, an arrangement hole 442 may be formed inside the dummy plate 443 , and the dummy redistribution unit 448 may be disposed in the arrangement hole 442 .

The dummy plate 443 may be formed to be spaced apart from the redistribution part 441 and the dummy redistribution part 448 .

That is, when the redistribution portion 441 disposed in the first region 101 is not formed vertically or horizontally symmetrically, the dummy plate 443 is disposed so that the redistribution portion 441 moves up and down together with Alternatively, it may be arranged to form a symmetrical shape left and right.

As described above, preferred embodiments according to the present invention have been reviewed, and the fact that the present invention can be embodied in other specific forms without departing from the spirit or scope of the present invention in addition to the above-described embodiments is one of ordinary skill in the art. It is obvious to them. Therefore, the above-described embodiments are to be regarded as illustrative rather than restrictive, and accordingly, the present invention is not limited to the above description, but may be modified within the scope of the appended claims and their equivalents.

100: semiconductor package 101: first region
102: second region 110: semiconductor chip
120: pad 120a: power pad
120b: ground pad 120c: signal pad
130: insulator pattern layer 131: first insulating layer
132: second insulating layer 135: opening
140: redistribution pattern layer 141: redistribution unit
142: arrangement hole 143: heat blocking slit
144: distortion prevention hole 148: dummy redistribution unit
150: conductive pillar 160: connection terminal
170: barrier layer 345: sheet portion
346: connection line pattern 443: dummy plate

Claims (8)

a semiconductor chip having a plurality of signal pads and a plurality of non-signal pads formed on a first surface;
a redistribution pattern layer including a redistribution portion electrically connecting the plurality of non-signal pads and a dummy redistribution portion formed on the plurality of signal pads;
and a conductive pillar formed in the redistribution portion and the dummy redistribution portion. According to claim 1,
the signal pad is formed in an edge region of the first surface, and the non-signal pad is located in a central region of the first surface;
The non-signal pad includes a power pad connected to a power source and a ground pad connected to a ground, and the redistribution unit includes a power redistribution connecting the power pad and a ground redistribution connecting the ground pad. 3. The method of claim 2,
The ground rewiring is a line shape, a plate shape having a plurality of holes, or a plate shape semiconductor package having a distortion prevention hole having any one shape of a circle, an ellipse, a polygon, a curve, and a straight line. According to claim 1,
an insulator pattern layer positioned between the redistribution unit and the dummy redistribution unit and the semiconductor chip;
a connection terminal provided on the conductive pillar;
The semiconductor package further comprising a barrier layer positioned between the conductive pillar and the connection terminal. According to claim 1,
The conductive pillar is formed in a cylindrical or polygonal shape,
A semiconductor package in which the lower end edge surface is connected to the redistribution part or the dummy redistribution pattern part, or the lower end edge surface is connected to a semiconductor chip or an insulator pattern layer located on the semiconductor chip 3. The method of claim 2,
The redistribution part is formed of an electrically conductive material in a plate-like shape covering the entire first area where the ground pad is disposed and a second area where the signal pad and power pad outside the first area are disposed, and the second area In an area corresponding to the signal pad and the power pad of , an arrangement hole is formed in which the dummy redistribution part is inserted and disposed in a spaced apart state, and the dummy redistribution part is spaced apart from the inner circumferential surface of the arrangement hole and electrically shorted inside the arrangement hole. placed or
The redistribution part is an electrically conductive material and is formed in a plate shape covering the first region in which the ground pad of the semiconductor chip is disposed, and the dummy redistribution part includes a signal pad and a power pad disposed outside the first region. A semiconductor package disposed at a position corresponding to the conductive pad of the second region and spaced apart from the redistribution part a semiconductor chip having a plurality of signal pads and a plurality of non-signal pads formed on a first surface;
a redistribution pattern layer including a redistribution portion electrically connecting the plurality of non-signal pads and a dummy redistribution portion formed on the plurality of signal pads;
conductive pillars formed in the redistribution unit and the dummy redistribution unit;
an external connection substrate to which the conductive filler is electrically connected;
and an encapsulation layer positioned between the external connection substrate and the semiconductor chip. 8. The method of claim 7,
Further comprising a connection terminal located between the conductive pillar and the external connection substrate,
The encapsulation layer is formed to be in direct contact with a top surface and a side surface of the redistribution part that are not in contact with the conductive pillar.

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