KR20220060410A - Synthetic aperture radar and decimation method for synthetic aperture radar data - Google Patents

Abstract

An image radar includes: a memory storing filter coefficients corresponding to the decimation ratio; a controller for selecting the filter coefficients from the memory in response to the decimation rate received from a ground station; an analog-to-digital converter which converts a received signal into a digital signal; and a decimation unit for generating an image radar signal by reducing the digital signal to the first decimation ratio of a non-integer multiple and the second decimation ratio of an integer multiple according to the selected filter coefficient.

Description

SYNTHETIC APERTURE RADAR AND DECIMATION METHOD FOR SYNTHETIC APERTURE RADAR DATA

The present invention relates to an image radar and an image radar data reduction method, and more particularly, to an image radar data reduction method using a polyphase filter resampling technique.

Synthetic Aperture Radar (SAR) mounted on satellites and aircraft is designed to support various operating modes. That is, modes having various reception bandwidths, such as ultra-high-resolution mode, high-resolution mode, standard mode, and wide-area mode, are operated through the same image radar. In the image radar of satellite or aircraft, it is necessary to transmit the photographed data to the ground through wireless communication using data link equipment. may be limited to Therefore, there is a need for a method capable of adjusting a sampling rate of a reception signal to be suitable for a reception bandwidth.

To this end, a decimation filter structure has been conventionally used in an on-board receiver of an imaging radar. However, the decimation filter structure has a problem in that only integer multiples of decimation are possible, and when the decimation ratio increases, the filter size increases exponentially. If only an integer multiple of decimation is possible, the sampling rate of the received signal cannot be optimized to fit the receiving bandwidth. In addition, if the filter size is large, on-board installation of FPGA (Field-Programmable Gate Array), DSP (Digital Signal Processing), etc. Filter implementation may not be possible due to processor resource constraints.

An object of the present invention is to provide an image radar and an image radar data reduction method capable of reducing large-capacity data in real time.

The image radar according to an embodiment of the present invention includes a memory storing filter coefficients corresponding to a decimation rate, a controller that selects filter coefficients from the memory in response to a decimation rate received from a ground station, and converting a received signal into a digital signal. An analog-to-digital converter for converting to , and a decimation unit for reducing the digital signal to a first decimation ratio of a non-integer multiple and a second decimation ratio of an integer multiple according to the selected filter coefficient to generate an image radar signal do.

The decimation unit includes an up-sampling unit for up-sampling the digital signal at an up-sampling ratio, and a first down-sampling unit for down-sampling the digital signal at a first down-sampling ratio to generate a first decimation signal. It may include a filter, and a second filter configured to generate the image radar signal by downsampling the first decimation signal at a second downsampling ratio.

The first filter and the second filter may be a finite impulse response (FIR) filter having a polyphase structure.

The first filter may further include a first filtering unit that removes noise generated during the upsampling process.

The second filter may further include a second filtering unit for removing aliasing generated in the downsampling process of the first filter.

A method for reducing image radar data according to another embodiment of the present invention includes selecting a filter coefficient corresponding to a decimation rate received from a ground station, upsampling a received signal with an upsampling rate according to the filter coefficient, and the filter generating a first decimation signal by downsampling a received signal upsampled at a first downsampling ratio according to a coefficient, and downsampling the first decimation signal by a second downsampling ratio according to the filter coefficient and generating an image radar signal.

The received signal may be reduced to a first decimation ratio of a non-integer multiple by the up-sampling ratio and the first down-sampling ratio.

The first decimation signal may be reduced to a second decimation ratio of an integer multiple by the second downsampling ratio.

Upsampling the received signal at the upsampling ratio and downsampling the upsampled received signal at the first downsampling ratio may be performed by a first filter having a polyphase structure.

Downsampling the first decimation signal at the second downsampling ratio may be performed by a second filter having a polyphase structure.

In the present invention, by using a polyphase filter-based resampling filter and a decimation filter to reduce the large-capacity data of the image radar, it is possible to support a decimation ratio of a non-integer multiple, and thus sampling the data to fit the reception bandwidth. ratio can be optimized.

In particular, when the reception bandwidth is large, the sampling rate may be optimized at a value with a small decimation rate, and the effect of reducing the data amount may be improved.

In addition, a large number of combinable damation ratios can be expressed through the combination of the resampling filter of the front stage and the decimation filter of the rear stage. This means that less memory space is used for storing filter coefficients.

In addition, as the transition band of the front-end filter of the front-end can be widened through the front-end structure, the effect of reducing the required filter size can be obtained.

In addition, since it is designed based on the polyphase filter structure, resource usage and computation of the onboard processor can be greatly reduced.

On the other hand, the decimation filter resampling filter structure can also be considered, but the resampling filter-decimation filter structure according to an embodiment of the present invention shows better performance in terms of resources and computational amount of the processor.

If necessary, the embodiments of the present invention may be extended to a resampling filter-resampling filter structure or a resampling filter-decimation filter-decimation filter structure. However, considering the possibility of combining decimation by filter combination, system complexity, etc., the resampling filter-decimation filter structure may be the most suitable choice in practice.

1 is a block diagram illustrating an image radar according to an embodiment of the present invention.
FIG. 2 is a block diagram illustrating the first filter of FIG. 1 .
3 is a block diagram illustrating a second filter of FIG. 1 .
4 is an exemplary diagram illustrating a pass band and a stop band of the first filter and the second filter of FIG. 1 .
5 is a block diagram illustrating a polyphase structure of the first filter of FIG. 1 .
6 is a block diagram illustrating a polyphase structure of the second filter of FIG. 1 .
7 is a simulation of resource requirements in a case where a two-stage series filter is designed using a general filter and a two-stage series filter is designed using a filter having a polyphase structure according to an embodiment of the present invention. shows the results.

Hereinafter, with reference to the accompanying drawings, embodiments of the present invention will be described in detail so that those of ordinary skill in the art to which the present invention pertains can easily implement them. The present invention may be embodied in several different forms and is not limited to the embodiments described herein.

In order to clearly explain the present invention, parts irrelevant to the description are omitted, and the same reference numerals are assigned to the same or similar components throughout the specification.

In addition, throughout the specification, when a part "includes" a certain component, this means that other components may be further included, rather than excluding other components, unless otherwise stated.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating an image radar according to an embodiment of the present invention.

Referring to FIG. 1 , the image radar 200 is mounted on a satellite or an aircraft, receives a decimation ratio (D-ratio) from the ground station 100, and transmits a chirp signal to the target 300. Receives an echo signal reflected by the target 300 and returns, converts the reflected signal to a digital signal, and performs decimation in response to a decimation ratio to reduce the data amount of the received signal to obtain an image radar signal reduce the data of

The image radar 200 includes a controller 210 , a memory 220 , a radio frequency device 230 , an analog-to-digital converter 240 , and a digital receiver 250 . The radio frequency device 230 may include a transmitter 231 and a receiver 232 . The digital receiver 250 may include an analog-to-digital conversion interface 251 and a decimation unit 260 , and the decimation unit 260 may include a first filter 261 and a second filter 262 . .

The memory 220 stores the filter coefficients corresponding to the decimation ratio (D-ratio). The memory 220 may be a nonvolatile memory device such as an Electrically Erasable Programmable Read-Only Memory (EEPROM).

When the ground station 100 determines and transmits the decimation ratio (D-ratio), the controller 210 receives the decimation ratio (D-ratio) and corresponds to the decimation ratio (D-ratio) in the memory 220 . The selected filter coefficients are transmitted to the digital receiver 250 . The filter coefficients may include filter coefficients for upsampling, filter coefficients for first downsampling, and filter coefficients for second downsampling.

The transmitter 231 transmits a chirp signal to the target 300 , and the receiver 232 receives a reflected signal reflected back by the target 300 .

The analog-to-digital converter 240 converts the received reflected signal into a digital signal and transmits it to the digital receiver 250 . The digital signal is transmitted to the decimation unit 260 through the analog-to-digital conversion interface 251 .

The decimation unit 260 generates an image radar signal with a reduced data amount by performing decimation of the digital signal according to the filter coefficients. The decimation unit 260 may be formed of a two-stage FIR (Finite Impulse Response) filter having a polyphase structure in series. That is, the first filter 261 and the second filter 262 included in the decimation unit 260 may be FIR filters having a polyphase structure.

The first filter 261 is composed of a combination of upsampling and downsampling to implement a non-integer multiple decimation ratio, and the second filter 262 is a first filter 261 for a reduction ratio combination. ) can be configured with downsampling with a large reduction ratio compared to . The first filter 261 may be referred to as a resampling filter, and the second filter 262 may be referred to as a decimation filter.

The data amount of the digital signal can be effectively reduced with a small amount of resources and a small amount of computation by the first filter 261 and the second filter 262 of the serial type having a polyphase structure.

Hereinafter, the first filter 261 and the second filter 262 will be described in more detail with reference to FIGS. 2 and 3 .

FIG. 2 is a block diagram illustrating the first filter of FIG. 1 .

Referring to FIG. 2 , the first filter 261 includes an upsampling unit 2611 , a first filtering unit 2612 , and a first downsampling unit 2613 . The upsampling unit 2611 upsampling the digital signal Fs at an upsampling ratio of 1:L to generate an upsampling signal Fs×L. That is, the digital signal Fs is up-sampled by L times. The first filtering unit 2612 considers the copied image generated in the upsampling process as noise and removes it. The first downsampling unit 2613 downsamples the upsampling signal Fs×L at a first downsampling ratio of M1:1 to generate a first decimation signal Fs1. That is, the up-sampling signal (Fs×L) is downsampled by M1 times, and eventually the first decimation signal Fs1 is a non-integer multiple signal (Fs×L/M1) reduced by the first decimation ratio (L/M1). ) can be The first decimation ratio (L/M1) corresponds to the product of the upsampling ratio 1:L and the first downsampling ratio M1:1. L and M1 are integers greater than zero. The first decimation signal Fs1 is input to the second filter 262 .

3 is a block diagram illustrating a second filter of FIG. 1 .

Referring to FIG. 3 , the second filter 262 includes a second filtering unit 2621 and a second downsampling unit 2622 . The second filtering unit 2621 removes aliasing generated in the first decimation signal Fs1 in the preceding downsampling process. The second downsampling unit 2622 down-samples the first decimation signal Fs1 at a second downsampling ratio of M2:1 to generate a second decimation signal Fs2. The second downsampling ratio becomes the second decimation ratio (1/M2). That is, the first decimation signal Fs1 is downsampled by M2 times. Finally, the second decimation signal Fs2 is weighted by the product of the first decimation ratio (L/M1) and the second decimation ratio (1/M2) to the digital signal Fs (Fs×L/M1) )/M2. M2 is an integer greater than zero. The second decimation signal Fs2 is output as an image radar signal.

As such, a combination of a first filter 261 having a first decimation ratio (L/M1) of a non-integer multiple and a second filter 262 having a second decimation ratio (1/M2) of an integer multiple is a series type By configuring the decimation unit 260 of the two-stage structure, the efficiency of the resolution of the decimation ratio in the final output may be improved. The proposed technique can solve the disadvantage of increasing the resolution of the decimation ratio in the final output when it is composed only of a filter having a decimation ratio of an integer multiple of the prior art.

4 is an exemplary diagram illustrating a pass band and a stop band of the first filter and the second filter of FIG. 1 .

Referring to FIG. 4 , the filter coefficient L of the upsampling ratio of the first filter 261 is 2, the filter coefficient M1 of the first downsampling ratio is 3, and the filter of the second downsampling ratio of the second filter 262 is The case where the coefficient M2 is 2 is exemplified.

When the decimation rate is received from the ground station 100 , the image radar 200 selects a filter coefficient corresponding to the decimation rate from the memory 220 . The image radar 200 upsamples the received signal (digital signal) at an upsampling ratio (eg, 1:L (L=2)) according to the selected filter coefficient, and a first downsampling ratio ( For example, a first decimation signal is generated by down-sampling a received signal upsampled to M1:1 (M1=3)). The received signal is reduced by the first decimation ratio of a non-integer multiple by the up-sampling ratio and the first down-sampling ratio. The image radar 200 generates a decimated image radar signal by downsampling the first decimation signal at a second downsampling ratio (eg, M2:1 (M2=2)) according to the filter coefficient. The first decimation signal is reduced to an integer multiple of the second decimation ratio by the second downsampling ratio.

In order to design a filter with decimation, it is necessary to consider the radiated image and aliasing of the frequency spectrum that occurs according to the sampling frequency that changes between the input and the output. The radiated image generated during the upsampling process is considered noise, and the aliasing generated during the downsampling process causes spectrum distortion. Therefore, before selecting the passband and stopband of the filter, it is necessary to consider the frequency spectrum of the output stage rather than the frequency spectrum in terms of the sampling frequency of the input stage.

Hereinafter, the polyphase structure of the first filter 261 will be described with reference to FIG. 5 , and the polyphase structure of the second filter 262 will be described with reference to FIG. 6 .

5 is a block diagram illustrating a polyphase structure of the first filter of FIG. 1 .

Referring to FIG. 5 , a filter having a non-integer multiple decimation ratio is implemented as a product of L times upsampling and M times downsampling. Due to the polyphase structure, a required filter order N can be implemented with L filter banks having an order of N/L. Accordingly, the required amount of resources required for filter operation is reduced by 1/L. It is possible to configure the necessary resources for the operation by 1/L times and to use a commutator to physically replace the filter banks in order and to be implemented, so that the required amount of resources can be reduced while performing the same filter operation. The principle of the polyphase structure is a concept that considers only the operations necessary for the final output by upsampling and downsampling in the process of calculating the convolution between input data (Input) and filter coefficients.

For example, when L=2 and M=3, the operation of the first filter 261 may be calculated as in Equation 1.

A term containing 0 in Equation 1 is a garbage value for oversampling input by upsampling, and from the standpoint of an actual output value, it is the same as an unnecessary operation, and the output for the upsampled input signal is equal to Equation 1 2 can be calculated.

When only a necessary output is considered by applying actual decimation, a final output may be generated as shown in Equation (3).

Looking at the final output in Equation 3, it can be seen that the 0th filter bank is involved in the 0th output, the 1st filter bank is involved in the 1st output, and thereafter, the two filter banks alternately and independently participate in the output. This can be performed by dividing the filter coefficients of length N into L filter banks, and it can be seen that the desired output can be obtained by reducing the resource usage of the FPGA based on this result.

When the decimation ratio is a non-integer multiple, the order of each filter bank and the shift of the initial input each filter bank receives because the order of the filter banks affecting the final output operation may vary depending on the L and M values. It is necessary to examine how much the shift differs from each other.

The input shift and the operation order of the initial operation for each filter bank can be expressed as in Equation (4).

The physical implementation of the input shift of the initial operation and the shift operation by M of each filter bank input can be implemented with a commutator as illustrated in FIG. 5 .

6 is a block diagram illustrating a polyphase structure of the second filter of FIG. 1 .

Referring to FIG. 6 , a filter having a decimation ratio of an integer multiple may be implemented as M filter banks in which the order N of the required filter is N/M. Like the polyphase structure of a filter having a decimation ratio of a non-integer multiple, a filter having a decimation ratio of an integer multiple can reduce resource usage by 1/M times. This can be implemented using a summer (Summer) according to the final output equation. Since a filter with an integer multiple of decimation ratio depends on the shape of the final output rather than the concept of excluding the operation on the garbage value for oversampling input by upsampling, a polyphase structure with a non-integer multiple decimation ratio and has a structure with a delay for the output rather than a delay for the input differently.

For example, when M=3, the operation of the second filter 262 may be calculated as in Equation 5.

In Equation 5, the filter output of the polyphase structure having a decimation ratio of an integer multiple is made by the sum of M products of each filter bank sequentially with the input value, and as the output proceeds, the input value is shifted, When viewed as a dummy, it can be confirmed that it is the sum of the dummy. That is, the dummy composed of M sums is implemented by a summer, and the sum of the dummy is implemented by an adder at a later stage, and the output proceeds. Implemented by Delay.

As a result, in preparation for a general filter operation, it is possible to reduce the resource requirement by summing the M operations as the resource amount and obtaining the final output by the delay-sum of the summed dummy.

Since the filter operation considering only downsampling is performed by shifting M each time, the filter bank is arranged in the reverse order of the input. This is related to the fact that the delay is at the rear, and the operation order can be expressed as in Equation (6).

The physical implementation of the operation order of the filter bank according to the input is implemented as a commutator as illustrated in FIG. 6 .

7 is a simulation of resource requirements in a case where a two-stage series filter is designed using a general filter and a two-stage series filter is designed using a filter having a polyphase structure according to an embodiment of the present invention. An example is shown.

Referring to FIG. 7 , the required amount of resources is shown when the decimation ratio and the filter order are arbitrarily given as examples. It can be seen that the required amount of resources is reduced when a filter having a polyphase structure is used.

As described above, the proposed image radar data reduction method supports a decimation ratio of a non-integer multiple to optimize the sampling rate of the received signal to fit the reception bandwidth, and filter coefficients of various filter combinations in a small memory space. It can be stored, the size of the filter can be reduced, and the resource usage and calculation amount of the onboard processor can be greatly reduced. Through this, the effect of increasing the image capture time, storage time, and transmission capability of the image radar can be expected.

The drawings and the detailed description of the described invention referenced so far are merely exemplary of the present invention, which are only used for the purpose of explaining the present invention, and are used to limit the meaning or the scope of the present invention described in the claims. it is not Therefore, it will be understood by those of ordinary skill in the art that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the true technical protection scope of the present invention should be defined by the technical spirit of the appended claims.

100: ground station 200: video radar
210: controller 220: memory
230: radio frequency device 240: analog-to-digital converter
250: digital receiver 260: decimation unit
261: first filter 262: second filter
2611: up-sampling unit 2612: first filtering unit
2613: first downsampling unit 2621: second filtering unit
2622: second down-sampling unit

Claims (10)

a memory storing filter coefficients corresponding to the decimation ratio;
a controller for selecting filter coefficients from the memory in response to a decimation rate received from a ground station;
an analog-to-digital converter that converts a received signal into a digital signal; and
and a decimation unit for reducing the digital signal by a first decimation ratio of a non-integer multiple according to the selected filter coefficient and reducing the digital signal by a second decimation ratio of an integer multiple to generate an image radar signal. According to claim 1,
The decimation unit,
a first filter including an up-sampling unit for up-sampling the digital signal at an up-sampling ratio and a first down-sampling unit for down-sampling the digital signal at a first down-sampling ratio to generate a first decimation signal; and
and a second filter for generating the image radar signal by downsampling the first decimation signal at a second downsampling ratio. 3. The method of claim 2,
and the first filter and the second filter are Finite Impulse Response (FIR) filters having a polyphase structure. 3. The method of claim 2,
The first filter may further include a first filtering unit that removes noise generated during an upsampling process. 3. The method of claim 2,
The second filter may further include a second filtering unit configured to remove aliasing generated in the downsampling process of the first filter. selecting a filter coefficient corresponding to a decimation rate received from a ground station;
upsampling the received signal at an upsampling ratio according to the filter coefficients;
generating a first decimation signal by downsampling the received signal upsampled at a first downsampling ratio according to the filter coefficient; and
and generating an image radar signal by downsampling the first decimation signal at a second downsampling ratio according to the filter coefficient. 7. The method of claim 6,
The image radar data reduction method in which the received signal is reduced to a first decimation ratio of a non-integer multiple by the up-sampling ratio and the first down-sampling ratio. 8. The method of claim 7,
The image radar data reduction method in which the first decimation signal is reduced to a second decimation ratio of an integer multiple by the second downsampling ratio. 7. The method of claim 6,
The upsampling of the received signal at the upsampling ratio and the downsampling of the upsampled received signal at the first downsampling ratio are performed by a first filter having a polyphase structure. 10. The method of claim 9,
The downsampling of the first decimation signal at the second downsampling ratio is performed by a second filter having a polyphase structure.

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