KR20220058414A - Method for chemical-mechanical polishing and method for manufacturing semiconductor by using the same - Google Patents

Abstract

One embodiment of the present invention provides a chemical mechanical polishing method comprising a step of forming a through-base wafer via in at least one base wafer including a dielectric layer and a metal electrode part. The step may include: a first chemical mechanical polishing (CMP) process of exposing the metal electrode part by removing at least a portion of the dielectric layer using a first CMP slurry; and a second chemical mechanical polishing process of removing at least a portion of the metal electrode part using a second CMP slurry.

Description

Chemical mechanical polishing method and manufacturing method of a semiconductor device using the same

The present invention relates to a chemical mechanical polishing method including a novel step of forming a base wafer through-via, particularly a through-silicon via (TSV), and a method for manufacturing a semiconductor device using the same.

Three-dimensional (3D) integration of IC devices promises to reduce the system form factor to a single system through direct stacking and interconnection of chips made using different technologies. For this 3D integration, semiconductor wafers carrying chips and arranged on top of each other must be electrically connected. Methods for interconnection of such 3D architectures and wafers are well known in the art.

In order to build such 3D architectures, stacked semiconductor wafers must include metal, in particular copper, interconnects in the form of nails or base wafer through vias, in particular through silicon vias (TSV). One of the possible techniques for achieving such a TSV is the formation of trenches in semiconductor wafer substrates that reach deep into the semiconductor wafer material but do not penetrate completely. Since semiconductor wafers are typically 300-800 μm thick, the trenches have a depth of about 50 to about 600 μm. They may have different cross-sections with a diameter of about 1-200 μm, such as square, rectangular, triangular, circular, oval, and the like. Next, the trenches are filled with an electrically conductive material (eg, copper) by various well-known deposition methods.

Thereafter, the semiconductor wafers with the filled trenches are thinned by removing the semiconductor wafer material (eg, silicon in the case of silicon wafer processing) from the backside of the wafer. This entails gluing the front side of the semiconductor wafer, the side from which the filled trenches are open, to the carrier wafer and chemical mechanical polishing (CMP) the back side of the semiconductor wafer until the bottom of the filled trenches are exposed. can do. By this thinning process, electrically conductive through-base wafer vias are formed.

Chemical mechanical planarization or polishing (CMP) is a major process for achieving local and global planarity of integrated circuit (IC) devices. The technique applies a CMP composition or slurry containing an abrasive and other additives as an active chemistry between a polishing pad and a rotating substrate surface under an applied load. Thus, the CMP process combines a physical process such as polishing and a chemical process such as oxidation or chelation. In order to achieve high-speed and uniform removal, it is preferred that the removal or polishing of the substrate material does not consist of pure physical or pure chemical action, but rather a synergistic combination of both.

High dielectric polishing rate and dishing control of Cu via electrode are very important issues in CMP application of through silica via (TSV).

However, in the case of the conventional CMP slurry, it is difficult to control the selectivity ratio for the dielectric and Cu polishing rates, so proper dishing of the copper via cannot be controlled. In terms of the selectivity between dielectric and copper, if the polishing rate of the dielectric is too fast compared to that of copper, the desired copper via electrode dishing cannot be formed and the bonding process cannot proceed. Since dishing of the via electrode is deep, bonding of the copper via electrode may not be formed during the bonding process.

An object of the present invention is to provide a chemical mechanical polishing method including forming a through-base wafer via in at least one base wafer including a dielectric layer and a metal electrode part.

Another object of the present invention is to provide a method of manufacturing a semiconductor device, which includes performing chemical mechanical polishing using the method.

The technical problems to be achieved by the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned can be clearly understood by those of ordinary skill in the art to which the present invention belongs from the description below. There will be.

In order to achieve the above technical object, an embodiment of the present invention is a chemical mechanical polishing method comprising the step of forming a through-base wafer via (through-base wafer via) in at least one base wafer including a dielectric layer and a metal electrode portion. , the step may include: a first chemical mechanical polishing process of removing at least a portion of the dielectric layer using a first chemical mechanical polishing (CMP) slurry to expose the metal electrode; and a second chemical mechanical polishing process of removing at least a portion of the metal electrode part using a second chemical mechanical polishing (CMP) slurry.

The metal electrode part may be a copper via (Cu Via).

The base wafer may be a silicon wafer, and the base wafer through-via may be a through-silica via (TSV).

The dielectric layer may include PETEOS, a resin, and a low-K insulating film.

A second chemical mechanical polishing process of removing at least a portion of the metal electrode part using the second chemical mechanical polishing (CMP) slurry may include forming a dishing on the metal electrode part.

It may be characterized in that the absolute value of the difference between the height of the lowest point and the highest point of the dishing is 10 to 15 nm.

The first and second chemical mechanical polishing processes may be characterized in that the chemical mechanical polishing is performed under a downforce of 0.2 to 1.0 psi or less and a rotational speed of 35 to 100 rpm.

The first chemical mechanical polishing process may be characterized in that the (dielectric layer polishing rate)/(metal electrode part polishing rate) selectivity value is 5 or more.

The second chemical mechanical polishing process may be characterized in that the (metal electrode part polishing rate)/(dielectric layer polishing rate) selectivity value is 10 or more.

The surface roughness (Ra: Å) value measured after the second chemical mechanical polishing process may be 3.0 or less.

Rounding the ratio (A _a /A _t ) of the area (A _a ) of the cross-section of the dielectric layer formed after the second chemical mechanical polishing process to the area (A _t ) of the cross-section of the theoretical dielectric layer after the chemical mechanical polishing process (A a t ) When defined as a value, the rounding value may be characterized in that it is 0.9 to 1.0.

Another embodiment of the present invention provides a method of manufacturing a semiconductor device comprising the step of performing chemical mechanical polishing using the method.

According to an embodiment of the present invention, the TSV process can be effectively performed by effectively removing the dielectric layer and then forming a dishing of the metal via electrode.

The effects of the present invention are not limited to the above effects, but it should be understood to include all effects that can be inferred from the configuration of the invention described in the description or claims of the present invention.

1 illustrates a base wafer through-via forming process according to an embodiment of the present invention.
FIG. 2 shows an AFM analysis image and a height profile result value for calculating a rounding value around a base wafer through-via dishing formed according to an embodiment of the present invention.

Hereinafter, the present invention will be described with reference to the accompanying drawings. However, the present invention may be embodied in several different forms, and thus is not limited to the embodiments described herein. And in order to clearly explain the present invention in the drawings, parts irrelevant to the description are omitted, and similar reference numerals are attached to similar parts throughout the specification.

Throughout the specification, when a part is said to be “connected (connected, contacted, coupled)” with another part, it is not only “directly connected” but also “indirectly connected” with another member interposed therebetween. "Including cases where In addition, when a part "includes" a certain component, this means that other components may be further provided without excluding other components unless otherwise stated.

The terminology used herein is used only to describe specific embodiments, and is not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly dictates otherwise. In the present specification, terms such as “comprise” or “have” are intended to designate that a feature, number, step, operation, component, part, or combination thereof described in the specification exists, but one or more other features It should be understood that this does not preclude the existence or addition of numbers, steps, operations, components, parts, or combinations thereof.

One embodiment of the present invention is a chemical mechanical polishing method comprising the step of forming a through-base wafer via in at least one base wafer comprising a dielectric layer and a metal electrode portion, wherein the step includes: a first chemical mechanical polishing process of removing at least a portion of the dielectric layer using a chemical mechanical polishing (CMP) slurry to expose the metal electrode; and a second chemical mechanical polishing process of removing at least a portion of the metal electrode part using a second chemical mechanical polishing (CMP) slurry.

Hereinafter, the chemical mechanical polishing method according to an embodiment of the present application will be described in detail.

The method of the present invention is used to manufacture semiconductor wafers having at least one, preferably more than one, through-base wafer via via.

In one embodiment of the present application, a semiconductor wafer, preferably a silicon or silicon alloy wafer, more preferably a silicon wafer and most preferably, having at least one electrically conductive metal electrode part comprising at least one electrically conductive metal A silicon wafer is provided. Preferably, standard semiconductor wafers customarily used in the manufacture of IC devices with large-scale integration (LSI), ultra-large-scale integration (VLSI) and extremely large-scale integration (ULSI) are used.

In one implementation of the present application, any metal conventionally used to fabricate IC devices, particularly three-dimensionally integrated IC devices, may be used for the metal electrode portion. Preferably, the metal is vanadium, niobium, tantalum, chromium, molybdenum, tungsten, rhenium, ruthenium, osmium, rhodium, iridium, palladium, platinum, copper, silver and gold, including at least two of said metals. alloys and alloys thereof containing at least one of said metals and at least one metal different from said metals. More preferably, the metal is selected from tungsten and copper. Most preferably, copper is used.

In one embodiment of the present application, the metal electrode part may have various cross-sections when viewed from the base wafer. Accordingly, the cross-sections may be selected from the group consisting of square, rectangular, trapezoidal, triangular, pentagonal, hexagonal, circular and oval. The maximum diameter of a given cross-section can vary widely, eg, the diameter of a circle, the diagonal of a square or rectangle, or the longest side of a triangle, and thus can be most advantageously adjusted to the specific requirements of three-dimensional integrated IC devices. Preferably, the maximum diameter of the cross-sections may range from 2 to 200, preferably from 2 to 150 and most preferably from 2 to 100 μm.

In one embodiment of the present application, the entire surface of the base wafer may be formed of a dielectric layer, except for regions in which upper ends of the metal electrode part are exposed. The dielectric layer may have patterned or unpatterned thin films made of or containing materials customarily used in the manufacture of IC devices. These patterned or unpatterned thin films may or may not completely cover the upper ends of the metal electrode parts. The dielectric layer may consist of or contain silicon oxide dielectric materials, in particular silicon dioxide materials and low-K and ultra-low-K dielectric materials, preferably PETEOS, resin, and a low-K insulating film. It may be characterized in that it comprises a.

In one embodiment of the present application, the method for forming the base wafer through-via includes: a first chemical mechanical polishing process of removing at least a portion of the dielectric layer using a first chemical mechanical polishing (CMP) slurry to expose the metal electrode; includes

In one embodiment of the present application, the base wafer is attached to the carrier, and the fixation is facilitated after CMP without affecting the polished base wafer, rather than the connection between the base wafer and the carrier being loosened during the CMP process. This can be achieved in such a way that it can be cut sharply.

In one embodiment of the present application, the base wafer may be contacted with a polishing pad and an aqueous chemical mechanical polishing composition or CMP slurry. The CMP slurry to be used in the methods herein is an aqueous composition. This means that it contains water, especially ultrapure water, as the main solvent and dispersant. Preferably, the CMP slurry comprises water in an amount of 60 to 99.95% by weight, more preferably 70 to 99.9% by weight, still more preferably 80 to 99.9% by weight, and most preferably 90 to 99.9% by weight of water. %, the weight percentages may be based on the total weight of the CMP slurry. The CMP slurry may contain abrasive particles, preferably organic or inorganic particles. Preferably, inorganic abrasive particles may be used. Most preferably, the inorganic abrasive particles are selected from the group of particles consisting of or containing metal oxides, metal carbides, metal borides, co-formed products thereof, and mixtures thereof. Even more preferably, metal oxides can be used as inorganic abrasive particles. Even more preferably, the metal oxide may be selected from the group consisting of silica, alumina, titania, zirconia, germania, ceria, co-formed products thereof and mixtures thereof, and most preferably, silica is an inorganic abrasive particle can be used as

In one embodiment of the present application, in the first chemical mechanical polishing process, chemical mechanical polishing may be performed until at least one metal electrode part, preferably, all metal electrode parts are exposed.

In one embodiment of the present disclosure, conventional equipment for CMP in the art may, by way of non-limiting example, consist of a rotating platen covered with a polishing pad. The wafer is mounted on a carrier or chuck with its top side down towards the polishing pad. The carrier holds the wafer in a horizontal position. This specific arrangement of abrasive and retaining devices is also known as a hard-platen design. The carrier may have a carrier pad that lies between the holding surface of the carrier and the surface of the unpolished wafer. This pad can act as a cushion for the wafer. Under the carrier, a larger diameter platen is also positioned generally horizontally and provides a surface parallel to the surface of the wafer to be polished. Its polishing pad contacts the wafer surface during the planarization process. During the CMP process of the present invention, the composition of the present invention may be applied onto the polishing pad either as a continuous stream or in a dropwise manner. Both the carrier and platen rotate about their respective shafts extending perpendicularly from the carrier and platen. The rotating carrier shaft may remain fixed in position relative to the rotating platen or may vibrate horizontally with respect to the rotating platen. The direction of rotation of the carrier is usually the same as the platen, but it need not be. The speed of rotation relative to the carrier and platen is usually set to different values, although this need not be the case. Preferably, the first and second chemical mechanical polishing processes may be characterized in that the chemical mechanical polishing is performed under a downforce of 0.2 to 1.0 psi or less and a rotational speed of 35 to 100 rpm. Also preferably, the temperature of the pressure plate may be set to a temperature of 10 to 70 ℃.

In one embodiment of the present application, in the first chemical mechanical polishing process, the (dielectric layer polishing rate)/(metal electrode portion polishing rate) selectivity value is 5 or more, preferably 7 or more, more preferably 9 or more can be characterized as By satisfying the above-described selectivity value, it may be possible to selectively polish only the dielectric layer without damaging the metal electrode part.

In one embodiment of the present application, the method of forming the base wafer through-via includes a second chemical mechanical polishing process of removing at least a portion of the metal electrode part using a second chemical mechanical polishing (CMP) slurry.

In one embodiment of the present application, in the second chemical mechanical polishing process, the (metal electrode part polishing rate)/(dielectric layer polishing rate) selectivity value is 10 or more, preferably 15 or more, more preferably 20 or more It may be characterized in that, the proper dishing of the metal electrode portion may be formed while minimizing damage to the dielectric layer only when polishing is performed using a slurry that satisfies these conditions.

In one embodiment of the present application, a second chemical mechanical polishing process of removing at least a portion of the metal electrode portion using the second chemical mechanical polishing (CMP) slurry forms a dishing on the metal electrode portion can do. The absolute value of the difference between the height of the lowest point and the highest point of the dishing may be 10 to 15 nm.

In one embodiment of the present application, the surface roughness (Ra: Å) value measured after the second chemical mechanical polishing process may be 3.0 or less, preferably 1.5 or less, more preferably 1.2 or less. This may be a range achieved by a chemical mechanical polishing process using a CMP slurry in which the (metal electrode part polishing rate)/(dielectric layer polishing rate) selectivity value satisfies the above-mentioned predetermined range.

In one embodiment of the present application, the ratio of the area (A _a ) of the cross-section of the dielectric layer formed after the second chemical mechanical polishing process to the area (A _t ) of the cross-section of the theoretical dielectric layer after the chemical mechanical polishing process (A t ) When A _a /A _t ) is defined as a rounding value, the rounding value may be 0.9 to 1.0, and the rounding value is preferably 0.91 to 1.0, more preferably 0.92 to 1.0, still more preferably 0.93 to 0.93. may be 1.0. At this time, the theoretical area of the cross-section of the dielectric layer is an ideally planarized wafer in which the dielectric layer (insulation film) around the metal electrode part is maintained without collapsing due to the chemical mechanical polishing process, and the degree of protrusion and dishing of the metal electrode part is 0. It may mean the area of the cross-section of the dielectric layer in a polished state. When the rounding value is in the range of 0.9 to 1.0, the flatness of the metal electrode part and the dielectric layer on the wafer is excellent, so that the bonding degree during bonding between wafers may be improved. When the rounding value is less than 0.9, the degree of dishing of the metal electrode part is large, so that the bonding degree is lowered during wafer bonding or the dielectric layer around the metal electrode part collapses and a short circuit of the chip may occur, which may act as a defect, and the rounding value is 1.0 If it exceeds, the metal electrode may protrude and the bonding process may not be possible.

Another embodiment of the present invention provides a method of manufacturing a semiconductor device comprising the step of performing chemical mechanical polishing using the method.

In the above-described method for manufacturing a semiconductor device according to another embodiment of the present invention, a description thereof will be omitted in the overlapping portion with the chemical mechanical polishing method according to the embodiment of the present invention.

The above description of the present invention is for illustration, and those of ordinary skill in the art to which the present invention pertains can understand that it can be easily modified into other specific forms without changing the technical spirit or essential features of the present invention. will be. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. For example, each component described as a single type may be implemented in a dispersed form, and likewise components described as distributed may be implemented in a combined form.

Hereinafter, embodiments of the present invention will be described in detail so that those of ordinary skill in the art can easily carry out the present invention. However, the present invention may be embodied in several different forms and is not limited to the embodiments described herein.

Example 1. Perform a first chemical mechanical polishing process exposing copper vias

1 illustrates a base wafer through-via forming process according to an embodiment of the present invention.

In this embodiment, AP-300 (manufactured by CTS) was used as equipment for the polishing process, and detailed conditions such as rotation speed and downforce conditions are as follows.

- Grinding process equipment: AP-300 (manufactured by CTS)

- Polishing pad: IC1010

- Thin film measuring equipment: ST-5000 (manufactured by K-Mac)

- Cu Via analysis equipment: Dimension Edge (manufactured by Bruker)

- Platen rpm: 90 rpm

- Head rpm: 90 rpm

- Flow rate: 300 ml/mi

- Pressure.: 1.0 psi

An insulating film polishing process was performed using the various CMP slurry compositions of Examples 1-1 to 1-3, and the results are shown in Table 1 below.

division Example 1-1 Example 1-2 Examples 1-3 Cu polishing rate
(Å/min) 417 3151 650 PETEOS polishing rate
(Å/min) 3153 3078 15 Cu/PETEOS selectivity 1 : 9 1:1 43:1 Cu protrusion (Å) 52 dishing formation dishing formation

Referring to Table 1, it was confirmed that the copper via electrode protruded only when the Cu/PETEOS polishing selectivity condition as in Example 1-1 was satisfied. That is, it can be confirmed that under these conditions, the insulating film having a low dielectric constant has a high polishing rate and high planarization characteristics without defects, and can suppress dishing or surface roughness of the through-copper via electrode to a low level.

Example 2. Formation of Optimized Disishing of Copper Vias (Second Chemical Mechanical Polishing Process)

For the bonding process of the through-Cu via electrode protruding through Example 1, polishing was performed in a 10 nm level dishing form. In this embodiment, detailed conditions such as rotation speed and downforce conditions are as follows.

- Grinding process equipment: AP-300 (manufactured by CTS)

- Polishing pad: FUJIBO H800

- Thin film measuring equipment: ST-5000 (manufactured by K-Mac)

- Cu Via analysis equipment: Dimension Edge (manufactured by Bruker)

- Platen rpm: 50 rpm

- Head rpm: 50 rpm

- Flow rate: 200 ml/mi

- Pressure.: 0.5 psi

The through-copper via electrode polishing process was performed using the various CMP slurry compositions of Examples 2-1 to 2-4, and the results are shown in Table 2 below.

division Example 2-1 Example 2-2 Example 2-3 Example 2-4 Cu polishing rate
(Å/min) 150 150 417 425 PETEOS polishing rate
(Å/min) 5 30 3153 478 Cu/PETEOS selectivity 30 :1 5 : 1 0.13:1 1:1 Cu Dishing formation formation Cu protrusion formation unformed rounding 0.93 0.94 not measurable not measurable surface roughness
(Ra: Å) 1.2 1.5 3.5 3.7

The rounding value is the area (A _t ) of the cross-section of the dielectric layer that can be theoretically formed after the chemical mechanical polishing process in the TSV structure in which the copper through-via electrode size (diameter) is 5 µm and the insulating film between the copper vias is 32.5 µm ) to the ratio (A _a /A _t ) of the area (A _a ) of the cross-section of the dielectric layer formed after the second chemical mechanical polishing process was defined as the rounding value. 2 shows an AFM analysis image and a height profile result for calculating a rounding value around a base wafer through-via dishing formed according to an embodiment of the present invention.

Referring to Table 2 and FIG. 2, under the conditions of Examples 2-1 and 2-2, the rounding value of the insulating film on both sides of the predetermined through-copper via electrode is maintained within the range of 0.9 to 1.0, and the low surface It can be seen that dishing having roughness can be formed. On the other hand, in Examples 2-3 and 2-4, it can be seen that the copper via is not polished or dishing is not formed, and the rounding value cannot be measured. It can be estimated that the rounding value exceeds 1.0 and cannot be measured as the copper via electrode is not protruded or dishing is not formed, and as a result, Examples 2-3 and 2-4 have high surface roughness. can be checked

Claims (12)

A method of chemical mechanical polishing comprising forming a through-base wafer via in at least one base wafer comprising a dielectric layer and a metal electrode, the method comprising:
a first chemical mechanical polishing (CMP) process of removing at least a portion of the dielectric layer to expose the metal electrode using a first chemical mechanical polishing (CMP) slurry; and
and a second chemical mechanical polishing process of removing at least a portion of the metal electrode part using a second chemical mechanical polishing (CMP) slurry.
The chemical mechanical polishing method according to claim 1, wherein the metal electrode part is a copper via (Cu Via).
The method of claim 1 , wherein the base wafer is a silicon wafer and the base wafer through-via is a through-silica via (TSV).
The method of claim 1 , wherein the dielectric layer comprises PETEOS, a resin, and a low-K insulating film.
The method of claim 1, wherein a second chemical mechanical polishing process of removing at least a portion of the metal electrode part using the second chemical mechanical polishing (CMP) slurry comprises forming a dishing on the metal electrode part. Characterized in the chemical mechanical polishing method.
The chemical mechanical polishing method according to claim 5, characterized in that the absolute value of the difference between the height of the lowest point and the highest point of the dishing is 10 to 15 nm.
The chemical mechanical polishing method of claim 1, wherein the first and second chemical mechanical polishing processes are chemical mechanical polishing at a downforce of 0.2 to 1.0 psi or less and a rotational speed of 35 to 100 rpm.
The method of claim 1, wherein the first chemical mechanical polishing process is
(Removing rate of dielectric layer)/(Removing rate of metal electrode part) A chemical mechanical polishing method, characterized in that the selectivity value is 5 or more.
The method of claim 1, wherein the second chemical mechanical polishing process is
A chemical mechanical polishing method, characterized in that the (metal electrode part polishing rate)/(dielectric layer polishing rate) selectivity value is 10 or more.
The chemical mechanical polishing method according to claim 1, wherein the surface roughness (Ra: Å) value measured after the second chemical mechanical polishing process is 3.0 or less.
According to claim 1,
Rounding the ratio (A _a /A _t ) of the area (A _a ) of the cross-section of the dielectric layer formed after the second chemical mechanical polishing process to the area (A _t ) of the cross-section of the theoretical dielectric layer after the chemical mechanical polishing process (A a t ) A chemical mechanical polishing method, characterized in that, when defined as a value, the rounding value is 0.9 to 1.0.
A method of manufacturing a semiconductor device comprising the step of performing chemical mechanical polishing using the method according to any one of claims 1 to 11.

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