KR20220053193A - Circuit board and mehod of manufacturing thereof - Google Patents

Abstract

A circuit board according to an embodiment includes: a first substrate layer; a second substrate layer which is disposed on the first substrate layer; a third substrate layer which is disposed under the first substrate layer; a first solder resist layer which is disposed on the second substrate layer; and a second solder resist layer which is disposed under the third substrate layer. The third substrate layer constitutes an antenna unit. The second substrate layer constitutes a driving unit for driving the antenna unit. The thickness of the first solder resist layer is greater than the thickness of the second solder resist layer.

Description

Circuit board and manufacturing method thereof

The embodiment relates to a circuit board, and more particularly, to a circuit board capable of minimizing the occurrence of warpage of the circuit board and a method of manufacturing the same.

A printed circuit board (PCB) is a circuit board that electrically connects or mechanically fixes predetermined electronic components. It is composed of a copper foil layer.

Such a circuit board is broadly classified into a single-sided circuit board in which wiring is formed on only one side of an insulating layer, a double-sided circuit board in which wiring is formed on both sides of an insulating layer, and a multi-layer circuit board in which wiring is formed in multiple layers according to the number of layers.

In the manufacturing process of such a circuit board, warpage may occur while the circuit board is subjected to a heat treatment process. As electronic products become smaller and thinner, circuit boards are also becoming thinner, and as the thinning progresses, the defect rate due to warpage can become a problem. The causes of warpage are various, such as the difference in the coefficient of thermal expansion (CTE) between the insulating material and the metal circuit, and the difference in the elastic modulus.

In addition, in recent years, in order to improve productivity in the manufacturing process of the substrate package, a plurality of circuit board units are manufactured in a single strip structure, which is commonly referred to as a circuit board strip.

In this case, in the circuit board strip, circuit board units are disposed in a central area, and alignment holes for automating the strip inspection process or assembly process are formed in the outer area.

At this time, when the strip bending phenomenon occurs during the manufacturing of the circuit board strip as described above, there is a problem in that the automated process such as the strip inspection process and the assembly process cannot proceed.

An embodiment is to provide a circuit board capable of improving reliability by minimizing the occurrence of warpage of the circuit board and a method of manufacturing the same.

In addition, the embodiment intends to provide a circuit board and a method of manufacturing the same to minimize the overall warpage of the circuit board by controlling the thickness of the first solder resist layer disposed on the top of the circuit board.

In addition, the embodiment intends to provide a circuit board capable of minimizing the overall warpage of the circuit board by controlling the thickness of the second solder resist layer disposed on the lowermost portion of the circuit board, and a method of manufacturing the same.

In addition, the embodiment intends to provide a circuit board capable of minimizing the overall warpage of the circuit board by controlling the thickness of the first outermost circuit pattern layer disposed on the uppermost portion of the circuit board, and a method of manufacturing the same.

In addition, in the embodiment, the overall warpage of the circuit board can be minimized by adjusting the thickness of the second outer layer circuit pattern disposed on the lowermost part of the circuit board.

Technical tasks to be achieved in the proposed embodiment are not limited to the technical tasks mentioned above, and other technical tasks not mentioned are clear to those of ordinary skill in the art to which the proposed embodiment belongs from the description below. can be understood clearly.

A circuit board according to an embodiment includes a first substrate layer; a second substrate layer disposed on the first substrate layer; a third substrate layer disposed under the first substrate layer; a first solder resist layer disposed on the second substrate layer; and a second solder resist layer disposed under the third substrate layer, wherein the third substrate layer constitutes an antenna unit, and the second substrate layer constitutes a driving unit for driving the antenna unit, wherein the first The thickness of a soldering resist layer is larger than the thickness of a said 2nd soldering resist layer.

In addition, the thickness of the first solder resist layer has a range of 130% to 200% of the thickness of the second solder resist layer.

In addition, the thickness of the first solder resist layer satisfies the range of 16 μm to 20 μm, and the thickness of the second solder resist layer satisfies the range of 10 μm to 15 μm.

In addition, the second substrate layer includes a first inner circuit pattern layer and a first outermost circuit pattern layer, and the third substrate layer includes a second inner circuit pattern layer and a second outermost circuit pattern layer, , A thickness of the first inner circuit pattern layer is greater than each of the first inner circuit pattern layer, the second inner circuit pattern layer, and the second outermost circuit pattern layer.

In addition, the first inner circuit pattern layer is plural, and the thickness of the first outermost circuit pattern layer is greater than an average value of the thicknesses of the plurality of first inner circuit pattern layers.

In addition, the thickness of the first outermost circuit pattern layer satisfies the range of 16 μm to 20 μm.

In addition, the average value of the respective areas of the first inner circuit pattern layer and the first outermost circuit pattern layer is larger than the average value of the respective areas of the second inner circuit pattern layer and the second outermost circuit pattern layer.

In addition, the second substrate layer includes a first inner insulating layer and a first outermost insulating layer, the third substrate layer includes a second inner insulating layer and a second outermost insulating layer, 1 inner circuit pattern layer is disposed on the first inner insulating layer, the first outermost circuit pattern layer is disposed on the first outermost insulating layer, and the second inner circuit pattern layer is disposed on the second inner insulating layer disposed below, and the second outermost circuit pattern layer is disposed under the second outermost insulating layer.

In addition, the average value of the respective thicknesses of the first inner insulating layer and the first outermost insulating layer is smaller than the average value of the respective thicknesses of the second inner insulating layer and the second outermost insulating layer.

In addition, the average value of the respective thermal expansion coefficients of the first inner insulating layer and the first outermost insulating layer is smaller than the average value of the respective thermal expansion coefficients of the second inner insulating layer and the second outermost insulating layer.

In addition, the average value of the respective dielectric constants of the first inner insulating layer and the first outermost insulating layer is smaller than the average value of the respective dielectric constants of the second inner insulating layer and the second outermost insulating layer.

Meanwhile, the antenna substrate according to the embodiment is an antenna substrate including a first area and a second area under the first area, and the first area of the antenna substrate is configured to drive the antenna unit included in the second area. a driving unit, and the second region of the antenna substrate operates by driving the driving unit, transmits a transmission signal to the outside, or receives a signal transmitted from the outside, and the first region includes a first solder resist layer and the second region includes a second solder resist layer, and a thickness of the first solder resist layer is greater than a thickness of the second solder resist layer.

In addition, the first region includes a first circuit pattern layer including a first inner circuit pattern layer and a first outermost circuit pattern layer, and the second region includes a plurality of second circuit pattern layers, A thickness of the first outermost circuit pattern layer is greater than a thickness of the first inner circuit pattern layer.

On the other hand, the manufacturing method of the circuit board according to the embodiment, forming a first substrate layer; forming a second substrate layer and a third substrate layer on upper and lower portions of the first substrate layer, respectively; forming a first solder resist layer on the second substrate layer; and forming a second solder resist layer under the third substrate layer, wherein a thickness of the first solder resist layer is greater than a thickness of the second solder resist layer, and the second substrate layer comprises: Corresponding to a driver connected to the device and the receiving device, transmitting the transmission signal transmitted from the transmitting device to the third substrate layer, or transmitting the reception signal transmitted from the third substrate layer to the receiving device, the plurality of of the second inner circuit pattern layer and the second outermost circuit pattern layer, transmitting a transmission signal transmitted from the second substrate layer to the outside, or receiving a signal transmitted from the outside and transferring it to the second substrate layer Corresponds to the antenna part.

In addition, the step of forming the first substrate layer includes preparing a first insulating layer, and forming first and second circuit pattern layers on the upper and lower surfaces of the first insulating layer, respectively, The forming of the second substrate layer and the third substrate layer may include, on the first substrate layer, a plurality of first inner insulating layers, and a first outermost insulating layer on the plurality of first inner insulating layers. , a second substrate layer comprising a plurality of first inner circuit pattern layers over the plurality of first inner insulating layers, and a first outermost circuit pattern layer over the first outermost insulating layer; under the layer, a plurality of second inner insulating layers, a second outermost insulating layer under the plurality of second inner insulating layers, a plurality of second inner circuit pattern layers under the plurality of second inner insulating layers, and forming a third substrate layer including a second outermost circuit pattern layer under the second outermost insulating layer, wherein the first outermost circuit pattern layer includes the plurality of first inner circuit pattern layers The average value of the respective thicknesses of is greater than the average value of the respective thicknesses of the plurality of second inner circuit pattern layers.

The circuit board in the embodiment may be an antenna board. The circuit board may include a first substrate layer, a second substrate layer, and a third substrate layer. The second substrate layer may be a region corresponding to the driver connected to the transmitting element and the receiving element in the antenna substrate. In addition, the third substrate layer may be a region corresponding to the antenna pattern portion including the antenna pattern layer for signal transmission and signal reception.

In this case, the second substrate layer in the embodiment may include a first solder resist layer, and the third substrate layer may include a second solder resist layer. In this case, the thickness of the first solder resist layer may be greater than the thickness of the second solder resist layer. For example, the thickness of the first solder resist layer may range from 130% to 200% of the thickness of the second solder resist layer. In an embodiment, the thickness of the first solder resist layer may be increased, and the thickness of the second solder resist layer may be decreased along with the increase of the thickness of the first solder resist layer. Accordingly, in the embodiment, the overall degree of warpage of the circuit board may be remarkably reduced, and thus reliability may be improved.

In addition, in the embodiment, the thickness of the circuit pattern layer is changed along with the increase in the thickness of the first solder resist layer and the second solder resist layer. For example, the second substrate layer in the embodiment may include a first inner circuit pattern layer and a first outermost circuit pattern layer. In addition, the third substrate layer may include a second inner circuit pattern layer and a second outermost circuit pattern layer. Here, the thickness of the first outermost circuit pattern layer in the embodiment may be greater than that of the first inner circuit pattern layer and the second inner circuit pattern layer. Specifically, a plurality of first inner circuit pattern layers may be included, and an average value of their thicknesses may be smaller than a thickness of the first outermost circuit pattern layer. In addition, a plurality of second inner circuit pattern layers may be included, and an average value of their thicknesses may be smaller than a thickness of the second outermost circuit pattern layer. In addition, the thickness of the first outermost circuit pattern layer may be greater than the thickness of the second outermost circuit pattern layer. Accordingly, in the embodiment, the overall degree of warpage of the circuit board may be reduced, and thus reliability may be improved.

1 is a view showing a circuit board according to a comparative example.
2 is a view schematically showing a basic material of a circuit board according to an embodiment.
3 is a diagram schematically illustrating a circuit board according to the first embodiment.
4 is a view showing a detailed configuration of a circuit board according to an embodiment.
5 is a diagram illustrating a circuit board according to a second embodiment.
6 is a diagram illustrating a circuit board according to a third embodiment.
7 is a view showing a circuit board according to the fourth embodiment.

Hereinafter, the embodiments disclosed in the present specification will be described in detail with reference to the accompanying drawings, but the same or similar components are assigned the same reference numerals regardless of reference numerals, and redundant description thereof will be omitted. The suffixes "module" and "part" for components used in the following description are given or mixed in consideration of only the ease of writing the specification, and do not have distinct meanings or roles by themselves. In addition, in describing the embodiments disclosed in the present specification, if it is determined that detailed descriptions of related known technologies may obscure the gist of the embodiments disclosed in the present specification, the detailed description thereof will be omitted. In addition, the accompanying drawings are only for easy understanding of the embodiments disclosed in the present specification, and the technical idea disclosed herein is not limited by the accompanying drawings, and all changes included in the spirit and scope of the present invention , should be understood to include equivalents or substitutes.

Terms including an ordinal number such as 1st, 2nd, etc. may be used to describe various elements, but the elements are not limited by the terms. The above terms are used only for the purpose of distinguishing one component from another.

When a component is referred to as being “connected” or “connected” to another component, it may be directly connected or connected to the other component, but it is understood that other components may exist in between. it should be On the other hand, when it is said that a certain element is "directly connected" or "directly connected" to another element, it should be understood that the other element does not exist in the middle.

The singular expression includes the plural expression unless the context clearly dictates otherwise.

In the present application, terms such as “comprises” or “have” are intended to designate that a feature, number, step, operation, component, part, or combination thereof described in the specification exists, but one or more other features It should be understood that this does not preclude the existence or addition of numbers, steps, operations, components, parts, or combinations thereof.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

1 is a view showing a circuit board according to a comparative example. In this case, FIG. 1 may be a circuit board including one unit, and may be a partial region of a circuit board strip including a plurality of units.

Referring to FIG. 1A , the circuit board according to the comparative example includes a first substrate layer 10 , a second substrate layer 20 , and a third substrate layer 30 .

In the circuit board according to the comparative example, the second substrate layer 20 and the third substrate layer 30 are respectively disposed on the upper and lower portions of the first substrate layer 10 .

In this case, the circuit board according to the comparative example may have a three-layer structure based on the circuit pattern layer. Accordingly, the first substrate layer 10 is a first circuit pattern layer. In addition, the second substrate layer 20 is a first insulating layer 21 , a second circuit pattern layer 22 , and a first solder resist layer 23 disposed on the first circuit pattern layer as a center.

In addition, the third substrate layer 30 is a second insulating layer 31 , a third circuit pattern layer 32 , and a second solder resist layer 33 disposed below the first circuit pattern layer as a center.

In this case, the second substrate layer 20 and the third substrate layer 30 are respectively disposed above and below the first substrate layer 10 . Here, as the first substrate layer 10 is disposed in the center of the circuit board, the effect of the first substrate layer 10 on the second substrate layer 20 and the effect on the third substrate layer 30 . These may be identical to each other.

Here, in the comparative example, the insulating layer, the circuit pattern layer, and the solder resist layer were respectively laminated in a state in which the coefficient of thermal expansion of the second substrate layer 20 and the third substrate layer 30 was not considered.

At this time, when the second substrate layer 20 and the third substrate layer 30 disposed on the first substrate layer 10 have a mutually symmetric structure, the second substrate layer 20 has The first coefficient of thermal expansion CTE1 ′ and the second coefficient of thermal expansion CTE2 ′ of the third substrate layer 30 may be equal to each other.

However, in a general circuit board, the second substrate layer 20 and the third substrate layer 30 do not have a symmetric structure with respect to the first substrate layer 10 . This is because the design of the second circuit pattern layer 22 constituting the second substrate layer 20 and the third circuit pattern layer 32 constituting the third substrate layer 30 are different from each other. The volume occupied by the second circuit pattern layer 22 and the volume occupied by the third circuit pattern layer 32 are different from each other. Also, as the volumes of the second circuit pattern layer 22 and the third circuit pattern layer 32 are different from each other, the volumes of the first insulating layer 21 and the second insulating layer 31 are also different from each other. In addition, as the volumes of the second circuit pattern layer 22 and the third circuit pattern layer 32 are different from each other, the second circuit pattern layer 22 and the third circuit pattern layer 32 are disposed on the The volumes of the first solder resist layer 23 and the second solder resist layer 33 are also different from each other.

And, a second substrate layer ( 20) has a first coefficient of thermal expansion CTE1'. In addition, the third substrate layer 30 including the second insulating layer 31 , the third circuit pattern layer 32 , and the second solder resist layer 33 disposed below the first substrate layer 10 . has a second coefficient of thermal expansion (CTE2').

In other words, in the comparative example, as the volume of each layer constituting the second substrate layer 20 and the volume of each layer constituting the third substrate layer 30 are different from each other, the second substrate layer 20 A difference occurs in the coefficient of thermal expansion of the and third substrate layer 30 , and the warpage of the circuit board occurs according to the difference in the coefficient of thermal expansion.

That is, referring to FIG. 1B , in the comparative example, the circuit board is manufactured in a state where the difference in the coefficient of thermal expansion of the second substrate layer 20 and the third substrate layer 30 is not taken into account, A bending phenomenon occurs in which the other end of the circuit board is floated by a first height h1 with respect to the reference plane compared to one end of the substrate. At this time, the first height in the comparative example was 2.6 mm level.

Specifically, due to the difference in the coefficient of thermal expansion between the second substrate layer and the third substrate layer as described above, warpage may occur in the circuit board. In this case, the first coefficient of thermal expansion CTE1' of the second substrate layer may be greater than the second coefficient of thermal expansion CTE2' of the third substrate layer. Accordingly, the circuit board in the comparative example may be warped in an upward direction having a high coefficient of thermal expansion.

At this time, when the bending phenomenon of the circuit board occurs, a reliability problem occurs in the manufacturing process of the circuit board, and the automated process cannot proceed normally.

For example, the occurrence of warpage of the circuit board may cause a problem in that a circuit pattern or a via hole cannot be processed at an accurate position, and furthermore, a vacuum adsorption error or an error in a transfer process may occur.

On the other hand, in the prior art, various solutions have been proposed to solve the bending problem of the circuit board as described above. At this time, in the prior art, a solution that takes into account various variables such as changing the material of each layer, changing the design of the circuit pattern layer of each layer, changing the thickness of the circuit pattern layer and the epoxy layer, or changing from a three-layer structure to a single-layer or multi-layer structure presented.

However, in the prior art, the design of the circuit board is usually determined in consideration of the material determined by the customer, the dimensional specification of each layer, the error range, the customer-specified design drawing, etc. were relatively limited.

In addition, in the prior art, the warpage occurrence problem was solved by changing the design of the insulating layer or the circuit pattern layer corresponding to the inner layer of the circuit board, which complicates the manufacturing process of the circuit board and increases the manufacturing process time. It acts as a factor, and furthermore, it can act as a problem that makes the automated process of the circuit board impossible.

Therefore, in the embodiment, it is intended to propose a method for minimizing the occurrence of warpage of the circuit board without causing a problem in the manufacturing process of the circuit board.

2 is a view schematically showing a basic material of a circuit board according to an embodiment.

Referring to FIG. 2 , the base material may be a copper clad laminate (CCL) type panel (PNL). In this case, the width in the horizontal direction of the panel PNL may be 415 to 430 mm. Also, the width in the vertical direction of the panel PNL may be 510 to 550 mm. Here, the width in the horizontal direction of the panel PNL may be the width in the minor axis direction, and the width in the vertical direction may be the width in the major axis direction.

In this case, the panel PNL may be divided into a plurality of strips 100 . The plurality of strips 100 may be spaced apart from each other by a predetermined interval in the horizontal direction and the vertical direction in the panel PNL. For example, one panel PNL may be divided into 16 strips 100 . That is, one panel PNL may be divided into two regions in the horizontal direction and eight regions in the vertical direction, and each of the divided regions may constitute the strip 100 .

Accordingly, the base material may include a first area in which the plurality of strips 100 are disposed and a second area in an outer area excluding the first area. The second area may be a peripheral area of the first area.

In addition, each strip 100 may be divided into a plurality of units 200 . For example, one strip 100 may be divided into 1,275 units 200 . In this case, each unit 200 may have a width in the horizontal axis direction of 3 mm and a width in the vertical direction of 2 mm. Meanwhile, each of the units 200 may constitute one circuit board. In other words, one panel PNL may be divided into 16 strips 100 and 20,400 units 200 .

Meanwhile, a plurality of circuit pattern layers, a plurality of insulating layers, and a plurality of via holes VH having a predetermined size may be formed in one unit 200 . For example, a plurality of trapezoidal via holes VH having an upper width of 80 μm and a lower width of 60 μm may be formed in one unit 200 .

At this time, about 150 via holes VH are formed in one unit 200 . Accordingly, one panel PNL may include 20,400 units 200 in which about 150 via holes VH are formed. As a result, more than 3 million via holes VH are formed in one panel PNL.

In addition, recently, as circuit wiring becomes more complex and highly integrated, patterns constituting the circuit pattern layer are miniaturized, and the number of via holes (VH) is gradually increasing. Accordingly, as at least 3 million via-holes VH are formed in one panel PNL, the panel PNL or strip 200 It is important to maintain flatness. That is, during laser processing for forming via holes, heat is applied to the panel PNL, and accordingly, the surface temperature of the panel PNL increases to a maximum of 700°C. At this time, the expansion and contraction phenomena of the panel PNL occur repeatedly, and accordingly, a bending phenomenon occurs in which wrinkles are generated on the surface of the panel PNL, and when the laser processing occurs in the state in which the wrinkles are generated, The position or shape of the via hole VH is changed. Accordingly, it should be possible to maintain the flatness of the panel PNL by minimizing a problem such as wrinkles occurring in the panel PNL.

Accordingly, in the embodiment, the overall degree of warpage of the circuit board strip 100 is minimized by changing the thickness of the solder resist layer disposed on the outermost side of the circuit board. Furthermore, in the embodiment, the degree of warpage of the entire circuit board strip 100 can be minimized through the change in the thickness of the outermost circuit pattern along with the change in the thickness of the solder resist layer.

3 is a diagram schematically illustrating a circuit board according to the first embodiment. In this case, FIG. 3 may be a circuit board including one unit, and differently, may show a partial region of a strip of a circuit board including a plurality of units.

Referring to FIG. 3 , the circuit board may have a plurality of layer structures.

Specifically, the circuit board may include a first substrate layer, a second substrate layer, and a third substrate layer.

The first substrate layer may be a layer disposed in the center of the circuit board.

The first substrate layer may include an insulating layer and a circuit pattern layer. For example, the first substrate layer may include a first insulating layer 110 , a first circuit pattern layer 112 , and a second circuit pattern layer 114 .

The first insulating layer 110 may be a core layer disposed in the center in a laminate structure of a circuit board having a plurality of layer structures. The first insulating layer 110 may include a prepreg, but is not limited thereto. However, the first insulating layer 110 may be a core layer, and may have a structure in which glass fibers are dispersed in a resin.

The first circuit pattern layer 112 and the second circuit pattern layer 114 are disposed on the upper surface of the first insulating layer 110 to form a plurality of circuit patterns (or wires, not shown) for transmitting electrical signals. may include The first circuit pattern layer 112 and the second circuit pattern layer 114 may be formed of a metal material having high electrical conductivity. To this end, the first circuit pattern layer 112 and the second circuit pattern layer 114 are gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), copper ( It may be formed of at least one metal material selected from Cu) and zinc (Zn). In addition, the first circuit pattern layer 112 and the second circuit pattern layer 114 may include gold (Au), silver (Ag), platinum (Pt), titanium (Ti), tin (Sn), and excellent bonding strength; It may be formed of a paste or solder paste including at least one metal material selected from copper (Cu) and zinc (Zn). Preferably, the first circuit pattern layer 112 and the second circuit pattern layer 114 may be formed of copper (Cu), which has high electrical conductivity and is relatively inexpensive.

The first circuit pattern layer 112 and the second circuit pattern layer 114 are formed by an additive process, a subtractive process, and a modified semi additive process (MSAP), which are typical circuit board manufacturing processes. ) and SAP (Semi Additive Process) method, and the detailed description is omitted here.

The second substrate layer may be disposed above the first substrate layer. For example, the second substrate layer may be disposed on an upper surface of the first substrate layer. Preferably, the second substrate layer may be disposed on an upper surface of the first circuit pattern layer 112 of the first substrate layer.

The second substrate layer may include an insulating layer and a circuit pattern layer. For example, the second substrate layer may include a plurality of insulating layers and a plurality of circuit pattern layers.

Specifically, the second substrate layer may include a second insulating layer 120 and a third insulating layer 130 . In addition, the second substrate layer may include a third circuit pattern layer 122 and a fourth circuit pattern layer 132 .

The second insulating layer 120 may be disposed on the first insulating layer 110 . Preferably, the second insulating layer 120 may be disposed on the first insulating layer 110 to cover the first circuit pattern layer 112 .

In addition, the third circuit pattern layer 122 may be disposed on the second insulating layer 120 . Preferably, the third circuit pattern layer 122 may be formed to protrude on the upper surface of the second insulating layer 120 .

Also, the third insulating layer 130 may be disposed on the second insulating layer 120 . Preferably, it may be disposed on the second insulating layer 120 to cover the third circuit pattern layer 122 . The third insulating layer 130 may be an insulating layer disposed on the uppermost side of the laminate structure of the circuit board. For example, the third insulating layer 130 may be a first outermost insulating layer disposed on the uppermost side in the laminate structure of the circuit board.

The fourth circuit pattern layer 132 may be disposed on the third insulating layer 130 . For example, the fourth circuit pattern layer 132 may be formed to protrude on the upper surface of the third insulating layer 130 . The fourth circuit pattern layer 132 may be a circuit pattern layer disposed on the uppermost side in the laminate structure of the circuit board. For example, the fourth circuit pattern layer 132 may be a first outermost circuit pattern layer disposed on the uppermost side in the laminate structure of the circuit board.

At this time, in the drawing, in the second substrate layer, only the first insulating layer 120 is shown to be disposed between the first insulating layer 110 and the third insulating layer 130 which is the first outermost insulating layer. However, the present invention is not limited thereto. For example, the second substrate layer in the embodiment may include a plurality of second insulating layers disposed between the first insulating layer 110 and the third insulating layer 130 . In this case, a circuit pattern layer may be disposed on the upper surfaces of the plurality of second insulating layers, respectively.

The third substrate layer may be disposed below the first substrate layer. For example, the third substrate layer may be disposed under a lower surface of the first substrate layer. Preferably, the third substrate layer may be disposed on a lower surface of the second circuit pattern layer 114 of the first substrate layer.

The third substrate layer may include an insulating layer and a circuit pattern layer. For example, the third substrate layer may include a plurality of insulating layers and a plurality of circuit pattern layers.

Specifically, the third substrate layer may include a fourth insulating layer 140 and a fifth insulating layer 150 . In addition, the third substrate layer may include a fifth circuit pattern layer 142 and a sixth circuit pattern layer 152 .

The fourth insulating layer 140 may be disposed under the first insulating layer 110 . Preferably, the fourth insulating layer 140 may be disposed under the first insulating layer 110 to cover the second circuit pattern layer 114 .

In addition, the fifth circuit pattern layer 142 may be disposed under the fourth insulating layer 140 . Preferably, the fifth circuit pattern layer 142 may be formed to protrude under the lower surface of the fourth insulating layer 140 .

Also, the fifth insulating layer 150 may be disposed on the fourth insulating layer 140 . Preferably, the fifth insulating layer 150 may be disposed under the fourth insulating layer 140 to cover the fifth circuit pattern layer 142 . The fifth insulating layer 150 may be an insulating layer disposed on the lowermost side in the laminate structure of the circuit board. For example, the fifth insulating layer 150 may be a second outermost insulating layer disposed at the lowermost side in the laminate structure of the circuit board.

The sixth circuit pattern layer 152 may be disposed under the fifth insulating layer 150 . For example, the sixth circuit pattern layer 152 may be formed to protrude under the lower surface of the fifth insulating layer 150 . The sixth circuit pattern layer 152 may be a circuit pattern layer disposed on the lowermost side in the laminate structure of the circuit board. For example, the sixth circuit pattern layer 152 may be a second outermost circuit pattern layer disposed on the lowermost side in the laminate structure of the circuit board.

At this time, in the drawing, in the third substrate layer, only the fourth insulating layer 140 is disposed between the first insulating layer 110 and the fifth insulating layer 150 which is the second outermost insulating layer. However, the present invention is not limited thereto. For example, the third substrate layer in the embodiment may include a plurality of fourth insulating layers disposed between the first insulating layer 110 and the fifth insulating layer 150 . In this case, a circuit pattern layer may be disposed on the lower surfaces of the plurality of fourth insulating layers, respectively.

Meanwhile, the circuit board according to the embodiment may include a first solder resist layer 160 and a second solder resist layer 170 .

The first solder resist layer 160 may be disposed on the second substrate layer. Specifically, the first solder resist layer 160 may be disposed on the third insulating layer 130 that is the first outermost insulating layer disposed on the uppermost side among the second substrate layers. For example, the first solder resist layer 160 may be disposed on the fourth circuit pattern layer 132 that is the first outermost circuit pattern layer disposed on the uppermost side among the second substrate layers. The first solder resist layer 160 serves to protect the surfaces of the first outermost insulating layer and the first outermost circuit pattern layer, the third insulating layer 130 and the fourth circuit pattern layer 132 . can do.

The second solder resist layer 170 may be disposed under the third substrate layer. Specifically, the second solder resist layer 170 may be disposed under the fifth insulating layer 150 , which is the second outermost insulating layer disposed on the lowermost side among the second substrate layers. For example, the second solder resist layer 170 may be disposed under the sixth circuit pattern layer 152 which is the second outermost circuit pattern layer disposed on the lowermost side among the second substrate layers. The second solder resist layer 170 serves to protect the surfaces of the second outermost insulating layer and the second outermost circuit pattern layer, the fifth insulating layer 150 and the sixth circuit pattern layer 152 . can do.

The circuit board of the above embodiment may be an antenna board. To this end, the circuit board may be provided for feeding and supporting the antenna pattern. The circuit board includes a first area in which a driver for processing a signal to be transmitted through the antenna pattern layer or a signal received through the antenna pattern layer is disposed, and a signal transmitted through the driver of the first area is transmitted to the outside or transmitted from the outside. It may include a second region in which an antenna pattern unit including a conductive antenna pattern layer for receiving a transmitted signal is disposed.

For example, in the circuit board, the first substrate layer may be a layer for separating a first region in which the driver is disposed and a second region in which the antenna pattern part is disposed.

The second substrate layer may be disposed on the first substrate layer, and thus may be a first region in which the driving unit is disposed. In addition, the third substrate layer may be a second region in which the antenna pattern part is disposed.

For example, the second substrate layer may include a transmitting element (not shown) for processing a signal to be transmitted through the antenna pattern unit and/or a receiving element (not shown) for processing a signal to be received through the antenna pattern unit. can For example, the transmitting element or the receiving element may be mounted on the third circuit pattern layer 142 disposed on the uppermost side of the second substrate layer. In addition, the second insulating layer 120 , the third insulating layer 130 , the third circuit pattern layer 122 and the fourth circuit pattern layer 132 constituting the second substrate layer include the antenna pattern part and the fourth circuit pattern layer 132 . It may be disposed between the transmitting element/receiving element to transmit a transmit signal or a received signal to the third substrate layer, thereby driving the antenna unit constituted by the third substrate layer.

Also, the third substrate layer may be an antenna unit driven by a driving unit included in the second substrate layer. The third substrate layer may include an antenna pattern part. For example, the third substrate layer may include a conductive antenna pattern layer for transmission of a transmission signal or reception of a reception signal. The conductive antenna pattern layer may include a fifth circuit pattern layer 142 and a sixth circuit pattern layer 152 constituting the third substrate layer. The conductive antenna pattern layer including the fifth circuit pattern layer 142 and the sixth circuit pattern layer 152 as described above may be an antenna that resonates in a plurality of resonant frequency bands. For example, the conductive antenna pattern layer may be a dual resonant antenna resonating in different resonant frequency bands. For example, the conductive antenna pattern layer may be a dual resonance antenna resonating in a first frequency band of 24.03 GHz to 25.81 GHz and a second frequency band of 27.07 GHz to 28.80 GHz, respectively.

In this case, the conductive antenna pattern layer including the fifth circuit pattern layer 142 and the sixth circuit pattern layer 152 may resonate in a resonant frequency band corresponding to a predetermined target frequency. To this end, the third substrate layer including the fifth circuit pattern layer 142 and the sixth circuit pattern layer 152 may be designed to resonate in the resonant frequency band. For example, according to the dielectric constant or thickness of the fourth insulating layer 140 and the fifth insulating layer 150 constituting the third substrate layer, the fifth circuit pattern layer 142 and the sixth circuit pattern layer 152 . The resonant frequency band of may vary. Therefore, the dielectric constant or the dielectric constant of the fourth insulating layer 140 and the fifth insulating layer 150 so that the fifth circuit pattern layer 142 and the sixth circuit pattern layer 152 can resonate in the target frequency band The thickness may be determined.

Accordingly, the second substrate layer and the third substrate layer in the embodiment may have an asymmetric structure. For example, in the circuit board in the embodiment, a second substrate layer disposed on the first substrate layer and a third substrate layer disposed below the first substrate layer have an asymmetric structure with respect to the first substrate layer. can have Here, the asymmetric structure may mean that the thickness and the dielectric constant of the second substrate layer are different from the thickness and the dielectric constant of the third substrate layer.

The dielectric constants of the fourth insulating layer 140 and the fifth insulating layer 150 constituting the third substrate layer are those of the second insulating layer 120 and the third insulating layer 130 constituting the second substrate layer. It may be greater than the permittivity. The thickness of the fourth insulating layer 140 and the fifth insulating layer 150 constituting the third substrate layer is that of the second insulating layer 120 and the third insulating layer 130 constituting the second substrate layer. It may be larger than the thickness.

And, as described above, around the first substrate layer, as the second substrate layer and the third substrate layer have a mutually asymmetric structure, the circuit board in the embodiment may cause warpage in the manufacturing process. can

At this time, various variables may be considered as a way to solve the warpage occurrence. For example, as a material having a property strong against warpage, the material of each layer of the second substrate layer or the third substrate layer is changed, the design of the circuit pattern layer of each layer is changed, the thickness of the insulating layer is changed, , various variables such as changing the number of layers of the circuit board can be considered. However, in general, the specifications of the circuit board are determined according to the product. For example, the material, thickness, error range, pattern design, etc. of each layer constituting the circuit board are already determined by the design drawing corresponding to the product specification, and accordingly, to solve the occurrence of the warpage, changeable Items are relatively limited. Accordingly, in the embodiment, it is possible to minimize the occurrence of warpage of the circuit board by changing the dimensions of the circuit pattern layer while maintaining the product specifications corresponding to the design drawings of the circuit board. For example, in the embodiment, the warpage occurrence problem as described above can be solved by changing the thickness of the first outermost circuit pattern layer and/or the second outermost circuit pattern layer disposed on the outermost side of the circuit board.

At this time, the numerical values of the respective layers of the first substrate layer, the second substrate layer, and the third substrate layer in the comparative example are shown in Table 1 below.

thickness copper foil rate CTE first solder resist layer 160 15㎛ 80% Fourth circuit pattern layer 132 15㎛ 61% third insulating layer 130 20㎛ 2% 1.55ppm/℃ Third circuit pattern layer 122 15㎛ 78% second insulating layer 120 20㎛ 8% 1.41ppm/℃ first circuit pattern layer 112 25㎛ 76% first insulating layer 110 100㎛ 4% second circuit pattern layer 114 25㎛ 72% fourth insulating layer 140 100㎛ 2% 1.57ppm/℃ fifth circuit pattern layer 142 15㎛ 54% fifth insulating layer 150 100㎛ 2% 1.57ppm/℃ 6th circuit pattern layer 152 15㎛ 50% second solder resist layer 170 15㎛ 96%

Referring to Table 1, the first insulating layer 110 in the comparative example may have a first thickness T1. The first insulating layer 110 is a core layer, and thus may have a relatively large thickness. For example, the first insulating layer 110 may be 100 μm.

The second insulating layer 120 and the third insulating layer 130 may be formed on the upper side of the first insulating layer 110 to have a second thickness T2 and a third thickness T3, respectively. For example, each of the second thickness T2 and the third thickness T3 may be 20 μm.

The fourth insulating layer 140 and the fifth insulating layer 150 may be formed under the first insulating layer 110 to have a fourth thickness T4 and a fifth thickness T5, respectively. For example, each of the fourth thickness T4 and the fifth thickness T5 may be 100 μm.

Also, the first circuit pattern layer 112 and the second circuit pattern layer 114 may be formed on an upper surface and a lower surface of the first insulating layer 110 to have a sixth thickness T6, respectively. For example, the sixth thickness T6 may be 25 μm.

In addition, the third circuit pattern layer 122, the fourth circuit pattern layer 132, the fifth circuit pattern layer 142, and the sixth circuit pattern layer 152 have a seventh thickness ( T7) and can be formed. The seventh thickness T7 may be 15 μm.

In addition, the first solder resist layer 160 and the second solder resist layer 170 in the comparative example have the same thickness. For example, the first solder resist layer 160 and the second solder resist layer 170 may be 15 μm.

At this time, in the case of the comparative example as shown in Table 1, the second substrate layer disposed on the upper side of the first substrate layer and the third substrate layer disposed below the first substrate layer have a thickness or dielectric constant of each insulating layer. These are different from each other, and the copper foil rate of each circuit pattern layer also differs from each other. Here, the copper foil rate may mean a ratio of an area in which the circuit pattern layer is disposed to the total surface area of the insulating layer.

Accordingly, in the case of the structure of the comparative example as shown in Table 1, the circuit board is warped due to the mutually asymmetric structure of the second substrate layer and the third substrate layer. For example, in the case of the structure of the comparative example shown in Table 1, the second substrate layer may be bent in the direction in which the third substrate layer is disposed. For example, a smile shape (^) in which the edge regions of the first substrate layer, the second substrate layer, and the third substrate layer of the structure of the comparative example shown in Table 1 are curved downward occurs.

At this time, in the embodiment, in the structure of the circuit board, the occurrence of warpage of the circuit board can be minimized by changing the thickness of the first solder resist layer 160 and the second solder resist layer 170 disposed on the outermost side.

Here, in order to improve the warpage occurrence, the degree of warpage occurring when the thickness of the second solder resist layer 170 is changed in a state where the thickness of the first solder resist layer 160 is fixed as follows is confirmed. saw. That is, in a state in which the thickness of the first solder resist layer 160 is fixed, the degree of warpage according to the change in the thickness of the second solder resist layer 170 is shown in Table 2 below. In this case, the thickness of the solder resist layer in the embodiment should generally have a value between 10 μm and 20 μm. Table 2 shows the degree of warpage according to the change in the thickness of the second solder resist layer 170 in a state where the thickness of the first solder resist layer 160 is fixed to 15 μm.

Thickness of the second solder resist layer 170 degree of warpage 10㎛ 0.35241mm 12㎛ 0.37547mm 14㎛ 0.38942mm 16㎛ 0.4095mm 18㎛ 0.4154mm 20㎛ 0.4352mm

In general, when the degree of warpage has a value of less than 0.4 mm, furthermore, less than 0.3 mm, normal manufacturing may be possible without a reliability problem in the manufacturing process of the circuit board.

However, as shown in Table 2, when the thickness of the second solder resist layer 170 is changed while the thickness of the first solder resist layer 160 is fixed, the degree of warpage of the circuit board is not greatly affected. could confirm that it was not.

Next, in order to improve the warpage occurrence, the degree of warpage occurring when the thickness of the first solder resist layer 160 is changed while the thickness of the second solder resist layer 170 is fixed as follows is confirmed. saw. That is, in a state in which the thickness of the second solder resist layer 170 is fixed, the degree of warpage according to the change in the thickness of the first solder resist layer 160 is shown in Table 3 below. In this case, the thickness of the solder resist layer in the embodiment should have a value between 10 μm and 20 μm. Table 3 shows the degree of warpage according to the change in the thickness of the first solder resist layer 160 in a state where the thickness of the second solder resist layer 170 is fixed to 15 μm.

Thickness of the first solder resist layer 160 degree of warpage 10㎛ 0.4924mm 12㎛ 0.4752mm 14㎛ 0.4254mm 16㎛ 0.3652mm 18㎛ 0.2592mm 20㎛ 0.2339mm

As shown in Table 3, when the thickness of the first solder resist layer 160 decreases while the thickness of the second solder resist layer 170 is fixed, it can be seen that the degree of warpage according to this is further increased. could And, when the thickness of the first solder resist layer 160 increases while the thickness of the second solder resist layer 170 is fixed, it was confirmed that the degree of occurrence of warpage according to the increase was confirmed.

For example, as shown in Table 3, when the first solder resist layer 160 is formed with a maximum thickness within the thickness range that the first solder resist layer 160 can have, the smallest degree of warpage occurs. could be seen to appear. In addition, it was confirmed that, when the first solder resist layer 160 is formed with a minimum thickness within the thickness range that the first solder resist layer 160 can have, the largest degree of warpage occurs.

Therefore, in the embodiment, the thickness of the first solder resist layer 160 is increased to minimize the degree of warpage of the circuit board.

Furthermore, in the embodiment, when the thickness of the second solder resist layer 170 is decreased while increasing the thickness of the first solder resist layer 160 within a limited range, the degree of warpage of the circuit board is minimized. was able to confirm that

In other words, while the thickness of the first solder resist layer 160 is greater than the thickness of the second solder resist layer 170 , the thickness of the first solder resist layer 160 and the second solder resist layer 170 . It was confirmed that the degree of warpage decreased as the difference between the thicknesses increased.

Accordingly, in the embodiment, the thickness of the first solder resist layer 160 is greater than the thickness of the second solder resist layer 170 to reduce the degree of warpage of the circuit board.

The first solder resist layer 160 of the embodiment may have an eighth thickness T8. The eighth thickness T8 may have a value between 16 μm and 20 μm.

Also, the second solder resist layer 170 according to the embodiment may have a ninth thickness T9. The ninth thickness T9 may be smaller than the eighth thickness T8 . For example, the ninth thickness T9 may have a value between 10 μm and 15 μm.

For example, the eighth thickness T8 of the first solder resist layer 160 in the embodiment is between 130% and 200% of the ninth thickness T9 of the second solder resist layer 170 . can have a value. When the eighth thickness T8 is less than 130% of the ninth thickness T9, the reduction level of the degree of warpage may be insignificant. In addition, when the eighth thickness T8 is greater than 200% of the ninth thickness T9 , the overall thickness of the circuit board may increase according to an increase in the thickness of the first solder resist layer 160 .

That is, in the embodiment, in the antenna substrate including the second substrate layer including the driving unit and the third substrate layer including the antenna unit, the thickness of the first solder resist layer 160 disposed on the driving unit is below the antenna unit. By making it smaller than the thickness of the second solder resist layer 170 disposed on the

4 is a view showing a detailed configuration of a circuit board according to an embodiment.

Referring to FIG. 4 , the circuit board may include an insulating layer, a circuit pattern layer, and a solder resist layer corresponding to FIG. 3 .

For example, the circuit board includes a first substrate layer including a first insulating layer 210 , a first circuit pattern layer 212 , and a second circuit pattern layer 214 .

In addition, the circuit board includes a second insulating layer 220 , a third circuit pattern layer 222 , a third insulating layer 230 , and a fourth circuit pattern layer 232 disposed on the first substrate layer. It may include a substrate layer. Such a second substrate layer may constitute a driver in the antenna substrate. For example, the driving unit may drive the antenna unit corresponding to the third substrate layer.

In addition, the circuit board is a third substrate including a fourth insulating layer 240 , a fifth circuit pattern layer 242 , a fifth insulating layer 250 , and a sixth insulating layer 252 under the first substrate layer. layers may be included. The third substrate layer may constitute an antenna unit in the antenna substrate.

In addition, the circuit board may include vias disposed within each insulating layer.

For example, a first via V1 may be disposed in the first insulating layer 210 . The first via V1 may electrically connect between the first circuit pattern layer 212 and the second circuit pattern layer 214 .

For example, a first via V2 may be disposed in the second insulating layer 220 . The second via V2 may electrically connect between the first circuit pattern layer 212 and the third circuit pattern layer 222 .

For example, a third via V3 may be disposed in the third insulating layer 230 . The third via V3 may electrically connect between the third circuit pattern layer 222 and the fourth circuit pattern layer 232 .

For example, a fourth via V4 may be disposed in the fourth insulating layer 240 . The fourth via V4 may electrically connect between the second circuit pattern layer 214 and the fifth circuit pattern layer 242 .

For example, a fifth via V5 may be disposed in the fifth insulating layer 250 . The fifth via V5 may electrically connect between the fifth circuit pattern layer 242 and the sixth circuit pattern layer 252 .

The first through fifth vias V1 , V2 , V3 , V4 , and V5 may be formed by filling an inside of a via hole passing through each insulating layer with a metal material.

The via hole may be formed by a laser processing method. That is, the via hole may be formed by a via hole processing apparatus using a CO ₂ laser method.

In addition, the first vias to the fifth vias V1, V2, V3, V4, and V5 form the inside of the via hole with copper (Cu), silver (Ag), tin (Sn), gold (Au), and nickel (Ni). And it may be formed by filling any one metal material selected from palladium (Pd). In this case, the filling of the metal material may use any one or a combination of electroless plating, electrolytic plating, screen printing, sputtering, evaporation, inkjetting and dispensing. there is.

In addition, the first solder resist layer 160 is disposed on the outermost insulating layer of the second substrate layer. In addition, a second solder resist layer 170 is disposed under the outermost insulating layer of the third substrate layer. In this case, the thickness of the first solder resist layer 160 is greater than the thickness of the second solder resist layer 170 . Accordingly, in the embodiment, the degree of warpage that may occur due to the vertical asymmetric structure of the circuit board may be reduced, and thus reliability may be improved.

5 is a diagram illustrating a circuit board according to a second embodiment, and FIG. 6 is a diagram illustrating a circuit board according to a third embodiment.

5 and 6 , in the circuit boards according to the second and third embodiments, the thickness of the fourth circuit pattern layer 132A and/or the sixth circuit pattern layer 152A is different from that of FIG. 3 . .

At this time, the degree of warpage occurring according to the change in thickness of the first solder resist layer 160 , the second solder resist layer 170 , the fourth circuit pattern layer 132A and the sixth circuit pattern layer 152A is as follows. Table 4 shows. The fourth circuit pattern layer 132A may be referred to as a first outermost circuit pattern layer, and the fifth circuit pattern layer 152A may be referred to as a second outermost circuit pattern layer.

first outermost
circuit pattern layer
Thickness (㎛) of the second outermost circuit pattern layer
Thickness (㎛) first solder
of the resist layer
Thickness (㎛) second solder
of the resist layer
Thickness (㎛) warpage
(mm) 14 16 15 15 0.4095 20 10 0.2339 20 15 10 0.2438 20 15 0.3590 20 16 15 10 0.2198 20 15 0.3388 20 15 15 0.3701 20 10 0.1951

As shown in Table 4, among various variables for improving the occurrence of warpage of the circuit board, in the embodiment, the thickness of the first solder resist layer 160 and the thickness of the second solder resist layer 170 are preferentially changed. For example, by making the thickness of the first solder resist layer 160 greater than the thickness of the second solder resist layer 170 , the occurrence of warpage of the circuit board may be primarily improved. For example, by decreasing the thickness of the second solder resist layer 170 while increasing the thickness of the first solder resist layer 160 , the occurrence of warpage of the circuit board may be primarily improved.

Furthermore, in the embodiment, the thickness of the first outermost circuit pattern layer and the thickness of the second outermost circuit pattern layer are changed together with the change in the thickness of the first solder resist layer 160 and the second solder resist layer 170 . Thus, it is possible to further improve the degree of occurrence of warpage.

In this case, the circuit pattern layer in the comparative example has a thickness of about 15 μm.

Here, as shown in Table 4, when the thickness of the first outermost circuit pattern layer and the thickness of the circuit pattern layer of the second outermost circuit pattern layer increased, it was confirmed that the degree of warpage was further reduced.

Specifically, with the change in the thickness of the first solder resist layer 160 and the second solder resist layer 170 , the thickness of the first outermost circuit pattern layer increases, or the thickness of the second outermost circuit pattern layer increases. When increasing, it was confirmed that the degree of warpage was further decreased.

In this case, when only the thickness of the second outermost circuit pattern layer increased while the thickness of the first outermost circuit pattern layer was maintained at 15 μm, the reduction level of the degree of warpage was insignificant. And, when the thickness of the first outermost circuit pattern layer is increased, it can be confirmed that the reduction level of the degree of warpage is significantly different. In addition, when the thickness of the first outermost circuit pattern layer is increased and the thickness of the second outermost circuit pattern layer is also increased, it can be confirmed that the reduction level of the degree of warpage is the best.

Accordingly, in the embodiment, as in FIG. 5 , the thickness of the second outermost circuit pattern layer is maintained at the seventh thickness (T7), and the thickness of the first outermost circuit pattern layer is set to the seventh thickness (T7−). By increasing to 1), it is possible to improve the occurrence of warpage of the circuit board.

Further, in the embodiment, as in FIG. 6 , while increasing the thickness of the first outermost circuit pattern layer to a 7-1 thickness (T7-1), the thickness of the second outermost circuit pattern layer is also shown in FIG. 7- By increasing it to 1 thickness (T7-1), it is possible to further reduce the occurrence of warpage of the circuit board.

In this case, the 7-1th thickness T7-1 may have a value between 16 μm and 20 μm. For example, the 7-1 th thickness T7 - 1 may have a value between 107% and 135% of the seventh thickness T7 .

That is, in the embodiment, in the antenna substrate including the second substrate layer including the driving unit and the third substrate layer including the antenna unit, the first outermost circuit pattern disposed on the uppermost side among the circuit pattern layers constituting the driving unit. By making the thickness of the layer thicker than other layers, it is possible to dramatically lower the overall degree of warpage of the circuit board.

7 is a view showing a circuit board according to the fourth embodiment.

Referring to FIG. 7 , the circuit board may have a stacked structure of 15 layers based on the number of insulating layers. For example, the circuit board may have a stacked structure of 16 layers based on the number of circuit pattern layers.

7 , the circuit board may include a first substrate layer, a second substrate layer, and a third substrate layer.

The first substrate layer may include an insulating layer 310 and a circuit pattern layer 340 . The circuit pattern layer 340 may include a first circuit pattern layer 341 disposed on an upper surface of the insulating layer 310 and a second circuit pattern layer 342 disposed on a lower surface of the insulating layer 320 . can

The second substrate layer may be disposed over the first substrate layer. The second substrate layer may be a first region of the antenna substrate in which the driver is disposed with the first substrate layer as the center.

The second substrate layer may include an insulating layer 320 and a circuit pattern layer 350 . The insulating layer 320 of the second substrate layer may include a first inner insulating layer 320A and a first outermost insulating layer 320B.

Specifically, the first inner insulating layer 320A includes the 1-1 inner insulating layer 321 , the 1-2 inner insulating layer 322 , the 1-3 inner insulating layer 323 , and the 1-4 inner side insulating layer 321 . It may include an insulating layer 324 , a 1-5 th inner insulating layer 325 , and a 1-6 th inner insulating layer 326 . In addition, the first outermost insulating layer 320B may be disposed on the 1-6th inner insulating layer 326 disposed on the uppermost side of the first inner insulating layers 320A.

Also, the circuit pattern layer 350 of the second substrate layer may include a first inner circuit pattern layer 350A and a first outermost circuit pattern layer 350B.

Specifically, the first inner circuit pattern layer 350A includes the 1-1 inner circuit pattern layer 351 , the 1-2 inner circuit pattern layer 352 , the 1-3 inner circuit pattern layer 353 , and the second inner circuit pattern layer 351 . It may include a 1-4 inner circuit pattern layer 354 , a 1-5th inner circuit pattern layer 355 , and a 1-6th inner circuit pattern layer 356 .

The third substrate layer may be disposed below the first substrate layer. The third substrate layer may be a second region of the antenna substrate in which the antenna unit is disposed with the first substrate layer as the center.

The third substrate layer may include an insulating layer 330 and a circuit pattern layer 360 . The insulating layer 330 of the third substrate layer may include a second inner insulating layer 330A and a second outermost insulating layer 330B.

Specifically, the second inner insulating layer 330A includes the 2-1 inner insulating layer 331 , the 2-2 inner insulating layer 332 , the 2-3rd inner insulating layer 333 , and the 2-4 inner side insulating layer 330A. It may include an insulating layer 334 , a 2-5th inner insulating layer 335 , and a 2-6th inner insulating layer 336 . In addition, the second outermost insulating layer 330B may be disposed under the 2-6th inner insulating layer 336 disposed on the lowermost side among the second inner insulating layers 330A.

Also, the circuit pattern layer 360 of the third substrate layer may include a second inner circuit pattern layer 360A and a second outermost circuit pattern layer 360B.

Specifically, the second inner circuit pattern layer 360A includes the 2-1 inner circuit pattern layer 361 , the 2-2 inner circuit pattern layer 362 , the 2-3rd inner circuit pattern layer 363 , and the second inner circuit pattern layer 361 . It may include a 2-4 inner circuit pattern layer 364 , a 2-5th inner circuit pattern layer 365 , and a 2-6th inner circuit pattern layer 366 . In addition, the second outermost circuit pattern layer 360B may be disposed under the second outermost insulating layer 330B.

In addition, the circuit board may include a first solder resist layer 370 disposed on the second substrate layer and a second solder resist layer 380 disposed below the third substrate layer.

In this case, in the structure of FIG. 7 , the thickness, copper foil rate, and coefficient of thermal expansion (CTE) of each layer may be as shown in Table 5 below.

Thickness (㎛) Copper foil rate (%) CTE (ppm/℃) first solder
resist layer 16-20 80 first outermost
circuit pattern layer 16-20 61 first outermost
insulating layer 20 2 1.55 1-6 inside
circuit pattern layer 15 76 1-6 inside
insulating layer 20 2 1.55 1-5 inside
circuit pattern 15 78 1-5 inside
insulating layer 20 One 1.55 Part 1-4 inside
circuit pattern 20 76 Part 1-4 inside
insulating layer 20 One 1.55 Part 1-3 inside
circuit pattern 15 85 Part 1-3 inside
insulating layer 70 8 1.41 Part 1-2 inside
circuit pattern 15 75 Part 1-2 inside
insulating layer 70 8 1.73 Article 1-1 Inside
circuit pattern 15 86 Article 1-1 Inside
insulating layer 70 6 1.41 first circuit pattern layer 25 76 first insulating layer 100 4 second circuit pattern layer 25 72 2-1 Inner Insulation Layer 70 2 1.73 2-1 inner
circuit pattern layer 15 35 2-2 Inner Insulation Layer 100 2 1.57 2-2 inside
circuit pattern layer 15 36 Section 2-3 Inner Insulation Layer 100 2 1.57 2-3 inside
circuit pattern layer 15 54 2-4 inner insulating layer 100 2 1.57 2-4 inside
circuit pattern layer 15 52 2-5 Inner Insulation Layer 70 One 1.41 2-5 inside
circuit pattern layer 15 36 2-6 inner insulating layer 100 2 1.57 2-6 inside
circuit pattern layer 15 45 2nd outermost
insulating layer 100 2 1.57 2nd outermost
circuit pattern layer 16-20 50 second solder
resist layer 10-15 96

Summarizing the characteristics of Table 5, in the circuit board, the second substrate layer and the third substrate layer may have an asymmetric structure with respect to the first substrate layer. In this case, the asymmetric structure may include at least one of a thickness of an insulating layer constituting the second substrate layer and the third substrate layer, a coefficient of thermal expansion of the insulating layer, and a copper thickness of the circuit pattern layer.

Specifically, the average value of the thicknesses of the plurality of insulating layers (the first inner insulating layer and the first outermost insulating layer) constituting the second substrate layer is an average value of the thicknesses of the plurality of insulating layers (the second inner insulating layer) constituting the third substrate layer. layer and the second outermost insulating layer) may be smaller than the average value of the thicknesses. This is to ensure that the plurality of insulating layers constituting the third substrate layer constitute the antenna unit, and the antenna unit may have a dielectric constant greater than or equal to a certain level to enable resonance in a specific resonant frequency band. Specifically, the average dielectric constant of the plurality of insulating layers constituting the second substrate layer may be smaller than the average value of the dielectric constants of the plurality of insulating layers constituting the third substrate layer.

In addition, the average value of the copper foil ratio of the plurality of circuit pattern layers (the first inner circuit pattern layer and the first outermost circuit pattern layer) constituting the second substrate layer is the plurality of circuit pattern layers (the first circuit pattern layer) constituting the third substrate layer. 2 The inner circuit pattern layer and the second outermost circuit pattern layer) may be larger than the average value of the copper foil ratio.

In addition, the average value of the coefficient of thermal expansion of the plurality of insulating layers (the first inner insulating layer and the first outermost insulating layer) constituting the second substrate layer is an average value of the plurality of insulating layers (the second inner insulating layer) constituting the third substrate layer. layer and the second outermost insulating layer) may be smaller than the average value of the coefficient of thermal expansion.

In the above structure, when the thickness of the first solder resist layer 370 is increased or the thickness of the second solder resist layer 170 is decreased, the degree of warpage of the circuit board can be primarily improved. there is.

In addition, in the above structure, when the thickness of the outermost circuit pattern layer is increased along with the change in the thickness of the first solder resist layer 160 or the second solder resist layer 170 , the overall degree of warpage is further improved can do.

For example, as the thickness of the first solder resist layer 160 increases or the thickness of the second solder resist layer 170 decreases, the thickness of the outermost circuit pattern layer 350B constituting the second substrate layer is increased. In this case, the overall degree of warpage of the circuit board can be improved.

For example, in the comparative example, the thickness of the outermost circuit pattern layer was formed to be the same as that of another circuit pattern layer (eg, the first inner circuit pattern layer or the second inner circuit pattern layer).

Alternatively, in the embodiment, the thickness of the outermost circuit pattern layer 350B is formed to be thicker than that of other circuit pattern layers (eg, the first inner circuit pattern layer or the second inner circuit pattern layer). Accordingly, in the embodiment, it is possible to improve the overall degree of warpage of the circuit board, and thus reliability can be improved.

Such a circuit board may be manufactured by the following manufacturing method.

First, in the embodiment, a process of forming the first substrate layer may be performed.

In an embodiment, when the first substrate layer is formed, a process of forming a second substrate layer and a third substrate layer on both sides of the first substrate layer may be performed, respectively.

In this case, the forming process of the second substrate layer and the third substrate layer may include forming a thickness of the outermost circuit pattern layer of the second substrate layer to be thicker than that of other circuit pattern layers.

In an embodiment, when the second substrate layer and the third substrate layer are formed, the process of forming a first solder resist layer on the second substrate layer and forming a second solder resist layer under the third substrate layer can proceed.

In this case, the thickness of the first solder resist layer 160 is greater than the thickness of the second solder resist layer.

The circuit board in the embodiment may be an antenna board. The circuit board may include a first substrate layer, a second substrate layer, and a third substrate layer. The second substrate layer may be a region corresponding to the driver connected to the transmitting element and the receiving element in the antenna substrate. In addition, the third substrate layer may be a region corresponding to the antenna pattern portion including the antenna pattern layer for signal transmission and signal reception.

In this case, the second substrate layer in the embodiment may include a first solder resist layer, and the third substrate layer may include a second solder resist layer. In this case, the thickness of the first solder resist layer may be greater than the thickness of the second solder resist layer. For example, the thickness of the first solder resist layer may range from 130% to 200% of the thickness of the second solder resist layer. In an embodiment, the thickness of the first solder resist layer may be increased, and the thickness of the second solder resist layer may be decreased together with the increase of the thickness of the first solder resist layer. Accordingly, in the embodiment, the overall degree of warpage of the circuit board may be remarkably reduced, and thus reliability may be improved.

In addition, in the embodiment, the thickness of the circuit pattern layer is changed along with the increase in the thickness of the first solder resist layer and the second solder resist layer. For example, the second substrate layer in the embodiment may include a first inner circuit pattern layer and a first outermost circuit pattern layer. In addition, the third substrate layer may include a second inner circuit pattern layer and a second outermost circuit pattern layer. Here, the thickness of the first outermost circuit pattern layer in the embodiment may be greater than that of the first inner circuit pattern layer and the second inner circuit pattern layer. Specifically, a plurality of first inner circuit pattern layers may be included, and an average value of their thicknesses may be smaller than a thickness of the first outermost circuit pattern layer. In addition, a plurality of second inner circuit pattern layers may be included, and an average value of their thicknesses may be smaller than a thickness of the second outermost circuit pattern layer. In addition, the thickness of the first outermost circuit pattern layer may be greater than the thickness of the second outermost circuit pattern layer. Accordingly, in the embodiment, the overall degree of warpage of the circuit board may be reduced, and thus reliability may be improved.

Features, structures, effects, etc. described in the above embodiments are included in at least one embodiment, and are not necessarily limited to only one embodiment. Furthermore, features, structures, effects, etc. illustrated in each embodiment can be combined or modified for other embodiments by those of ordinary skill in the art to which the embodiments belong. Accordingly, the contents related to such combinations and variations should be interpreted as being included in the scope of the embodiments.

In the above, the embodiment has been mainly described, but this is only an example and does not limit the embodiment, and those of ordinary skill in the art to which the embodiment belongs are provided with several examples not illustrated above within the range that does not deviate from the essential characteristics of the embodiment. It can be seen that the transformation and application of branches are possible. For example, each component specifically shown in the embodiment can be implemented by modification. And differences related to such modifications and applications should be construed as being included in the scope of the embodiments set forth in the appended claims.

Claims (15)

a first substrate layer;
a second substrate layer disposed on the first substrate layer;
a third substrate layer disposed under the first substrate layer;
a first solder resist layer disposed on the second substrate layer; and
a second solder resist layer disposed under the third substrate layer;
The third substrate layer constitutes an antenna unit,
The second substrate layer constitutes a driving unit for driving the antenna unit,
The thickness of the first solder resist layer is larger than the thickness of the second solder resist layer,
circuit board. According to claim 1,
The thickness of the first solder resist layer is,
having a range between 130% and 200% of the thickness of the second solder resist layer;
circuit board. According to claim 1,
The thickness of the first solder resist layer satisfies the range of 16 μm to 20 μm,
The thickness of the second solder resist layer satisfies the range of 10㎛ to 15㎛,
circuit board. According to claim 1,
The second substrate layer includes a first inner circuit pattern layer and a first outermost circuit pattern layer,
The third substrate layer includes a second inner circuit pattern layer and a second outermost circuit pattern layer,
The thickness of the first inner circuit pattern layer is greater than each of the first inner circuit pattern layer, the second inner circuit pattern layer and the second outermost circuit pattern layer,
circuit board. 5. The method of claim 4,
The first inner circuit pattern layer is a plurality,
The thickness of the first outermost circuit pattern layer is greater than the average value of the thicknesses of the plurality of first inner circuit pattern layers,
circuit board. 5. The method of claim 4,
The thickness of the first outermost circuit pattern layer satisfies the range of 16 μm to 20 μm,
circuit board. 5. The method of claim 4,
The average value of each area of the first inner circuit pattern layer and the first outermost circuit pattern layer is,
greater than the average value of each area of the second inner circuit pattern layer and the second outermost circuit pattern layer;
circuit board. 5. The method of claim 4,
The second substrate layer,
a first inner insulating layer and a first outermost insulating layer;
The third substrate layer,
a second inner insulating layer and a second outermost insulating layer;
The first inner circuit pattern layer is disposed on the first inner insulating layer,
The first outermost circuit pattern layer is disposed on the first outermost insulating layer,
The second inner circuit pattern layer is disposed under the second inner insulating layer,
The second outermost circuit pattern layer is disposed under the second outermost insulating layer,
circuit board. 9. The method of claim 8,
The average value of the respective thicknesses of the first inner insulating layer and the first outermost insulating layer is,
smaller than the average value of each thickness of the second inner insulating layer and the second outermost insulating layer;
circuit board. 9. The method of claim 8,
The average value of the respective coefficients of thermal expansion of the first inner insulating layer and the first outermost insulating layer is,
smaller than the average value of the respective coefficients of thermal expansion of the second inner insulating layer and the second outermost insulating layer;
circuit board. 9. The method of claim 8,
The average value of each dielectric constant of the first inner insulating layer and the first outermost insulating layer is,
smaller than the average value of the respective dielectric constants of the second inner insulating layer and the second outermost insulating layer;
circuit board. An antenna substrate comprising a first area and a second area below the first area,
The first region of the antenna substrate is a driving unit for driving the antenna unit included in the second region,
The second region of the antenna substrate operates by driving the driver, transmits a transmission signal to the outside, or receives a signal transmitted from the outside;
The first region includes a first solder resist layer,
The second region includes a second solder resist layer,
The thickness of the first solder resist layer is greater than the thickness of the second solder resist layer,
antenna board. 13. The method of claim 12,
The first region includes a first circuit pattern layer including a first inner circuit pattern layer and a first outermost circuit pattern layer,
The second region includes a plurality of second circuit pattern layers,
The thickness of the first outermost circuit pattern layer is greater than the thickness of the first inner circuit pattern layer,
antenna board. forming a first substrate layer;
forming a second substrate layer and a third substrate layer on upper and lower portions of the first substrate layer, respectively;
forming a first solder resist layer on the second substrate layer; and
forming a second solder resist layer under the third substrate layer;
The thickness of the first solder resist layer is,
greater than the thickness of the second solder resist layer;
The second substrate layer is connected to the transmitting element and the receiving element, and transmits the transmit signal transmitted from the transmitting element to the third substrate layer, or transmits the receive signal transmitted from the third substrate layer to the receiving element Corresponding to the driving part that
The plurality of second inner circuit pattern layers and the second outermost circuit pattern layer transmit a transmission signal transmitted from the second substrate layer to the outside, or receive a signal transmitted from the outside to be applied to the second substrate layer. Corresponding to the antenna unit to transmit,
A method for manufacturing a circuit board. 15. The method of claim 14,
Forming the first substrate layer comprises:
preparing a first insulating layer;
Forming first and second circuit pattern layers on the upper and lower surfaces of the first insulating layer, respectively;
Forming the second substrate layer and the third substrate layer,
on the first substrate layer, a plurality of first inner insulating layers, a first outermost insulating layer over the plurality of first inner insulating layers, a plurality of first inner circuits over the plurality of first inner insulating layers a second substrate layer comprising a pattern layer and a first outermost circuit pattern layer on the first outermost insulating layer;
a plurality of second inner insulating layers under the second substrate layer, a second outermost insulating layer under the plurality of second inner insulating layers, a plurality of second inner circuits under the plurality of second inner insulating layers forming a third substrate layer including a pattern layer and a second outermost circuit pattern layer under the second outermost insulating layer;
The first outermost circuit pattern layer,
greater than an average value of each thickness of the plurality of first inner circuit pattern layers, and an average value of respective thicknesses of the plurality of second inner circuit pattern layers,
A method for manufacturing a circuit board.

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