KR20220044325A - Devices with circuit positioning mechanism - Google Patents

Abstract

The device comprises a substrate; circuit components disposed on the substrate; and a location identifier layer over the circuit, wherein the location identifier layer includes one or more section labels to indicate physical locations of circuit components within the device.

Description

Devices with circuit positioning mechanism

FIELD OF THE INVENTION The disclosed embodiments relate to devices, and more particularly, to electronic devices having a circuit-locating mechanism.

BACKGROUND Electronic devices (eg, silicon-based devices) frequently experience circuit defects that may form during manufacturing, testing, and/or after deployment. For example, memory devices that are often provided as internal, semiconductor, integrated circuits, and/or externally removable devices in computers or other electronic devices may include defective storage circuitry (eg, memory cells). Although other types of memory may exist, such as volatile and non-volatile memory, faulty storage circuitry can occur regardless of type. Volatile memory, including, for example, random access memory (RAM), static random access memory (SRAM), dynamic random access memory (DRAM), and/or synchronous dynamic random access memory (SDRAM) includes defective memory transistors can do. In addition, non-volatile memories such as flash memory (e.g., NAND and NOR), phase change memory (PCM), resistive random access memory (RRAM), and/or magnetic random access memory (MRAM) have defective floating gate transistors. and/or other circuit units. Because such circuit faults can negatively affect other non-faulty circuits, circuit faults are usually located and rectified/removed prior to device placement.

1A is a schematic cross-sectional view of a conventional silicon device 100 (“device 100”). Device 100 includes a silicon substrate 102 and a circuit component layer 106 including electronic circuit components (eg, transistors). Device 100 further includes one or more metal layers (eg, bottom metal layer 104 and/or top metal layer 106 ) coupled to and routing electrical signals to/from electronic circuit components. . Device 100 also includes one or more insulating layers 110 (eg, oxide material) disposed between circuit component layer 106 and metal layers. Thus, the insulating layer 110 provides a limited connection between the circuit components and the metal layers, and otherwise electrically insulates other parts of the circuit from the metal layers. Device 100 includes a passivation layer 112 that forms a top surface over silicon substrate 102 and protects/insulates one or more of metal layers and/or circuit component layer 106 from the external environment. can do.

To illustrate the conventional design, FIG. 1B is a schematic top view of a portion of a silicon device (eg, device 100 ), and FIG. 1C is a conventional top metal layer (eg, top metal layer 106 ). 1D is a top view of a portion of a silicon device including a defective circuit, FIG. 1E is an exemplary display illustrating a silicon device including a defective circuit, and FIG. 1F is a silicon device including a surface defect It is a top view of a part of the device. 1A-1F , device 100 may include circuit 120 with one or more faulty circuits, such as unintentional short circuits, malfunctioning transistors, and the like. However, finding a faulty circuit 120 is generally based on other circuit connections, which may be repetitive and/or bulky. As an illustrative example, where device 100 is a memory device, defective circuitry 120 in a storage circuit (eg, a memory array) can be difficult to find due to the repetitive arrangement of numerous individual cells. The faulty circuit 120 has a first set of marks 122 along one direction (eg, word line marks/connections) and a second set of marks 124 along an orthogonal direction (eg, word line marks/connections). For example, by counting bit line marks/connections). As mentioned, due to the extremely large number of memory cells and the repetitive nature of the circuit connections, this counting is difficult and often error-prone.

The top metal layer 106 may further complicate the effort to find the defective circuit 120 . Top metal layer 106 may include a repeating pattern, such as a mesh pattern or serpentine pattern, as shown in FIGS. Introduce additional patterns. The top metal layer 106 may be visible during visual inspection and/or when viewing the device 100 using a processing tool (eg, a microscope, laser/x-ray/ultraviolet camera, etc.). For example, the top metal layer 106 can be viewed in the circuit viewer display 150 (eg, an emission microscope image). Identifying/referencing potential fault locations 152 (eg, hotspots) displayed on circuit viewer display 150 simultaneously presents a repeating pattern of top metal layer 106 as shown in FIG. 1E . It can be difficult because Similarly, the repeating pattern makes it difficult to locate/refer to the surface defects 132 that may be within/above/below the upper metal layer 106 as shown in FIG. 1F .

1A is a schematic diagram of a silicon device.
1B is a schematic plan view of a portion of a silicon device.
1C is a plan view of a conventional top metal layer.
1D is a top view of a portion of a silicon device including a defective circuit.
1E is an exemplary display illustrating a portion of a silicon device that includes a defective circuit.
1F is a top view of a portion of a silicon device containing surface defects.
2A is a block diagram of an apparatus configured in accordance with an embodiment of the present technology.
2B is a schematic diagram of an integrated circuit device constructed in accordance with an embodiment of the present technology.
3A is a schematic plan view of a portion of an apparatus according to an embodiment of the present technology;
3B is a detailed view of the segment 3B shown in FIG. 3A according to an embodiment of the present technology.
3C is a detailed view of the segment 3C shown in FIG. 3B according to an embodiment of the present technology.
4 is a plan view illustrating surface properties of a portion of an apparatus according to an embodiment of the present technology.
5 is a display illustrating a portion of an apparatus according to an embodiment of the present technology.
6 is a flowchart illustrating an exemplary method of manufacturing an apparatus according to an embodiment of the present technology.
7 is a schematic diagram of a system including an apparatus according to an embodiment of the present technology;

As will be described in greater detail below, the technology disclosed herein relates to electronic devices, systems having electronic devices, and related methods for finding circuitry therein. The device includes a location identifier layer that provides a reference for locating circuit components within the device. In some embodiments, the location identifier layer may be a metal layer comprising a repeating pattern, such as a metal mesh comprising boundaries (eg, metal portions) and slots (eg, areas/spaces bounded by boundaries). The location identifier layer may include section labels, such as symbols, letters, and/or numbers, used to indicate and identify a physical location within the device. That is, the section label can be an easy-to-read text or pattern that can serve as a marking to identify the corresponding area/region. In some embodiments, section labels may be formed by filling select slots with fillers (eg, dummy fillers and/or oxide materials) according to a predetermined pattern. The remaining slots may remain unfilled or may be filled with another filler material (eg, another oxide material).

For purposes of illustration, an apparatus will be described in the context of a flash memory device including one or more two-dimensional (2D) memory arrays. However, the techniques disclosed herein may be applied in other contexts/embodiments, such as for non-memory devices (eg, processors or logic devices) and/or other memory devices (eg, volatile memory devices and/or magnetic memory devices). It is understood that it can be implemented in

2A is a block diagram of a system 201 having an apparatus (eg, memory device 200 ) configured in accordance with an embodiment of the present technology. As shown, memory device 200 includes main memory 202 (eg, NAND flash, NOR flash, chalcogenide PCM, etc.) and main memory 202 to host device 208 (eg, and a controller 206 operatively coupled to an upstream central processing unit (CPU). The main memory 202 includes a plurality of memory areas or memory units 220 each including a plurality of memory cells 222 . The memory units 220 may be individual memory dies, memory planes of a single memory die, a stack of memory dies vertically connected by a through-silicon via (TSV), or the like. For example, in one embodiment, each of the memory units 220 may be formed from a semiconductor die and arranged with other memory unit dies in a single device package (not shown). In another embodiment, multiple memory units 220 may be co-located on a single die and/or distributed across multiple device packages. Memory cells 222 may include, for example, a floating gate, charge trap, phase shift, ferroelectric, magnetoresistive, and/or other suitable storage element configured to store data either persistently or semi-permanently. Main memory 202 and/or individual memory units 220 may also be configured to access and/or program (eg, write to) memory cell 222 and other functions, eg, information processing and/or It may include other circuit components (not shown) such as multiplexers, decoders, buffers, read/write drivers, address registers, data output/data in registers, etc. to communicate with the controller 206 .

Memory cells 222 may be arranged in rows 224 (eg, each corresponding to a word line) and columns 226 (eg, each corresponding to a bit line). Each word line may include one or more memory pages depending on the number of data states that the memory cells 222 of that word line are configured to store. For example, a single word line of memory cells 222 where each memory cell 222 is configured to store one of two data states (eg, SLC memory cells each configured to store one bit) is a single word line. It may contain memory pages. Alternatively, a single word line of memory cells 222 (eg, MLC memory cells each configured to store two bits) each memory cell 222 is configured to store one of four data states may be divided into two It may contain multiple memory pages. The memory pages are also interleaved so that a word line composed of memory cells 222 (eg, SLC memory cells) configured such that each memory cell 222 stores one of two data states is an "even-odd bit line". may span two memory pages in an "even-odd bit line architecture", wherein all memory cells 222 in odd-numbered columns 226 of a single word line are grouped into a first memory page, All memory cells 222 in even-numbered columns 226 of the same word line are grouped as the second memory page. There is an even-odd bit line architecture in the word line of memory cells 222 (eg, memory cells configured as MLC, TLC, QLC, etc.) where each memory cell 222 is configured to store a larger number of data states. When used, the number of memory pages per word line can be much higher (eg, 4, 6, 8, etc.).

Each column 226 may include a string of series-coupled memory cells 222 coupled to a common source. The memory cells 222 of each string may be connected in series between a source select transistor (eg, a field effect transistor) and a drain select transistor (eg, a field effect transistor). The source select transistors may be commonly connected to the source select line, and the drain select transistors may be commonly connected to the drain select line.

In another embodiment, the memory cells 222 may be arranged in a different type of hierarchy and/or group than shown in the illustrated embodiment. Also, although the illustrated embodiment is shown having a specific number of memory cells, rows, columns, blocks, and memory units for purposes of illustration, the number of memory cells, rows, columns, blocks, and memory units may vary, and other Embodiments may be larger or smaller than those shown in the illustrated examples. For example, in some embodiments, memory device 200 may include only one memory unit 220 . Alternatively, memory device 200 may include 2, 3, 4, 8, 20, or more (eg, 26, 32, 64, or more) memory units 220 . . Although the memory unit 220 is shown in FIG. 2 as including two memory blocks 228 each, in other embodiments, each memory unit 220 includes 1, 3, 4, 8, or more. (eg, 26, 32, 64, 200, 228, 256, or more memory blocks). In some embodiments, each memory block 228 may include, for example, 215 memory pages, and each memory page in the block may include, for example, 212 memory cells 222 (eg, “4k”). " page) may be included.

The controller 206 may be a microcontroller, special purpose logic circuit (eg, field programmable gate array (FPGA), application specific integrated circuit (ASIC), etc.), or other suitable processor. The controller 206 may include a processor 230 configured to execute instructions stored in memory. In the illustrated example, the memory of the controller 206 controls the operation of the memory device 200 , including managing the main memory 202 and handling communications between the memory device 200 and the host device 208 . and an embedded memory 232 configured to perform various processes, logic flows, and routines for controlling. In some embodiments, embedded memory 232 may include memory registers that store, for example, memory pointers, fetched data, and the like. Embedded memory 232 may include volatile and/or non-volatile memory (eg, DRAM, SRAM, NAND, NOR, PCM) for storing memory registers, and may also include read-only memory (ROM). There is (eg, for microcode storage). Although in the example illustrated in FIG. 2 the memory device 200 is shown as including a controller 206, in other embodiments of the present technology, the memory device may not include a controller and instead an external control (eg, provided by an external host or provided by a processor or controller separate from the memory device).

In operation, the controller 206 directly writes or programs (eg, writes to) the various memory regions of the main memory 202 , such as by writing to memory pages and/or groups of memory blocks 228 . can be erased). In NAND-based memory, a write operation often involves programming memory cells 222 in selected memory pages with specific data values (eg, a string of data bits having a value of logic 0 or logic 1). An erase operation is similar to a write operation, except that the erase operation resets the entire memory block 228 or multiple memory blocks 228 to the same data state (eg, logic 1).

The controller 206 communicates with the host device 208 via a host-device interface 210 . In some embodiments, the host device 208 and the controller 206 are connected to a Serial Attached SCSI (SAS), Serial AT Attached (SATA) interface, peripheral component interconnect express (PCIe), or other suitable interface (eg, a parallel interface). ) through a serial interface such as The host device 208 may send various requests (eg, in the form of a packet or stream of packets) to the controller 206 . The request may include a command to write, erase, return information, and/or perform a specific operation (eg, a TRIM operation). The request may include an interrupt or other command indicating a change of state (eg, a power loss event), which may trigger implementation of a power loss algorithm.

The host device 208 may be any one of a number of electronic devices or a component thereof that may utilize memory for temporary or permanent storage of information. For example, the host device 208 may be a desktop or portable computer, server, portable device (eg, cell phone, tablet, digital reader, digital media player), or some component thereof (eg, a central processing unit; a computing device, such as a coprocessor, dedicated memory controller, etc.). The host device 208 may be one of a networking device (eg, a switch, router, etc.) or a recorder of digital images, audio and/or video, a vehicle, a home appliance, a toy, or many other products. In one embodiment, the host device 208 may be directly coupled to the memory device 200 , while in another embodiment, the host device 208 may be indirectly coupled to the memory device 200 (eg, a network through a connection or through an intermediary device).

Various portions of system 201 and/or apparatus may be implemented using integrated circuit devices. 2B is a schematic cross-sectional view of an integrated circuit device 250 (“device 250”) constructed in accordance with an embodiment of the present technology. Device 250 may have a substrate 252 and a circuit component layer 256 that may include electronic circuit components (eg, transistors, resistors, capacitors, etc.). Device 250 may further include one or more metal layers 254 coupled to and routing electrical signals to/from electronic circuit components (eg, components within circuit component layer 256 ). there is. Device 250 also includes one or more insulating layers 260 (eg, an oxide material) disposed between circuit component layer 256 and metal layers 254 . Accordingly, the insulating layers 260 provide limited electrical connection between the circuit components and the metal layers 254 , and otherwise electrically insulate other portions of the circuit from the metal layers. Device 250 may include a passivation layer 262 that forms a top surface over silicon substrate 252 that protects/insulates device 250 from the external environment.

As described in detail below, device 250 is a location identifier that includes visual markings/indicators (ie, section labels 272 ) that identify different physical locations and/or areas of device 250 . It may include a location identifier layer 270 . Section labels 272 may include symbols, letters, numbers, or a combination thereof recorded in location identifier layer 270 . The location identifier layer 270 may extend along a horizontal plane and each of the section labels 272 may identify a unique location/region along the horizontal plane. Accordingly, the section labels 272 are a visual reference for locating and/or identifying one or more circuit components and/or other physical aspects (eg, defects) of the device 250 . ) can be used to provide In some embodiments, section labels 272 may replace a wordline mark as a visual reference for locating and/or identifying circuit components or other physical characteristics.

In some embodiments, location identifier layer 270 may be a metal layer, such as an upper metal layer or a different inner metal layer. For example, location identifier layer 270 is coupled to functional circuits (eg, circuit components within circuit component layer 256 ) and routes electrical signals and/or with supply voltage and/or ground It may include an electrically functional metal layer (eg, a top metal layer) that provides the same reference voltage connection. Also, the location identifier layer 270 may not function for electrical connections. In other embodiments, location identifier layer 270 may include an oxide or other non-metallic material such as a polymer material. In some embodiments, the location identifier layer 270 has a repeating pattern (eg, slots) that is surrounded by a material (eg, a metal and/or electrically conductive material) of the location identifier layer 270 . For example, it may be a planar structure having a mesh pattern). In some embodiments, as detailed below, section labels 272 may be formed based on filling slots with, for example, a dummy filler to illustrate/form symbols, characters, etc. . The dummy filler may include the oxide material used for the section labels 272 without necessarily providing other (eg, encapsulating and/or protecting) functions. In some embodiments, the slot may have a dimension (eg, length and/or width) of less than 100 μm. As an illustrative example, the slot may have a rectangular shape with a length of 4 μm and a width of 1 μm.

For purposes of illustration, location identifier layer 270 is described with respect to main memory 202 of FIG. 2 (eg, memory units 220 of FIG. 2 and memory cells 222 of FIG. 2 therein). . However, it is understood that the location identifier layer 270 may overlap and may provide a marker/indicator for locating other circuits (eg, controller 206 , logic circuitry, etc.). For example, section labels 272 may be placed above, below, and/or adjacent to a buffer, amplifier, logic gate, trace, etc. in device 250 .

3A is a schematic top view of a portion of an apparatus (eg, device 250 ) in accordance with an embodiment of the present technology. As described above, device 250 may include a location identifier layer 270 extending along horizontal directions across device 250 . In some embodiments, location identifier layer 270 may include section labels 272 that follow one or more patterns across location identifier layer 270 . For example, section label 272 may include letters and/or numbers that increase along a corresponding direction (eg, along width and/or length). 3A , the section labels 272 may include numbers increasing along a first direction and characters increasing along a second direction orthogonal to the first direction.

As described above, location identifier layer 270 may include section labels 272 that may be used to describe locations/regions along horizontal directions. For example, location identifier layer 270 may be used to identify the physical location of one or more target circuits 302 (eg, defective circuits/components) on device 250 . In the example shown in Figure 3a, the location of the target circuit 302 is above/below region 'AC66' and/or the first '6' therein. Accordingly, section labels 272 may provide a simpler/efficient positioning mechanism, thereby reducing potential user error in locating circuitry as compared to the conventional device described above. For example, section label 272 may reduce or eliminate any counting (eg, for word lines and/or bit lines) needed to locate target circuits 302 . . Further, section labels 272 may be repetitive (eg, having a similar or matching shape, type, arrangement, and/or spacing within a circuit such as target circuit 302 and/or memory cell 222 of FIG. 2A ). may provide an efficient mechanism for finding and/or identifying defects associated with a part (based on a set of components).

To illustrate exemplary details of section label 272 in accordance with embodiments of the present technology, FIG. 3B is a detailed view of segment 3B shown in FIG. 3A , and FIG. 3C is further detail of segment 3C shown in FIG. 3B . It is also Referring together to FIGS. 3B and 3C , the location identifier layer 270 of FIG. 2B is a macro each comprising a unique region or region of the location identifier layer 270 , for example, across a lateral plane/surface thereof. ) cells 310 . Each of the macro cells 310 may correspond to one of the section labels 272 .

In some embodiments, location identifier layer 270 may include a metal layer/structure or a portion thereof having a mesh design. For example, location identifier layer 270 can include boundaries 312 (eg, metal connections) that define slots 314 . Accordingly, section labels 272 are set of slots 314 into identifier filler 320 (eg, dummy filler) according to a predetermined pattern to illustrate/record corresponding symbols, letters, and/or numbers. It may be formed based on filling the That is, each of the section labels 272 may include a set of slots 314 within a corresponding macro cell 310 filled with dummy fillers to form or represent a unique set of letters, numbers and/or symbols. there is. Accordingly, section labels 272 are visual for identifying and/or locating corresponding regions/regions that contain any circuit components and/or physical properties (eg, defects) within device 250 . standards can be provided. In some embodiments, other instances of slots 314 may remain unfilled or may be filled with other material. In some embodiments, identifier filler 320 may have at least one physical property, such as density, color, and/or composition.

In some embodiments, slots 314 may correspond to label pixels 330 and/or associated coordinates along a plane (eg, a lateral/horizontal surface of device 250 ). Symbols, letters, and/or numbers for section labels 272 may be illustrated using label pixels 330 similar to how symbols, letters, and/or numbers are displayed on a digital display. For example, each of the label pixels 330 may include a set of one or more of the slots 314 in the area represented by the section labels 272 (eg, as shown in FIG. 3C ). 4 slots x 4 slots). Each of the label pixels 330 may be identified according to a represented area and/or its relative position within the location identifier layer 270 (eg, bumped and/or according to a coordinate system). The set of label pixels 330 may be populated with an identifier filler 320 to form/show symbols, letters and/or numbers for the corresponding section label 272 . In one or more embodiments, one or more of slots 314 may be marked (eg, visually such as color, density, composition, etc.) in each of label pixels 330 to visually identify corresponding pixels. through different types of fillers with different properties or by leaving the slots unfilled). That is, each of the pixels 330 may include markings that may be used to visually identify the boundaries of the corresponding pixel. Accordingly, the label pixels 330 may be utilized to find a target circuit.

To illustrate example deficiencies for section label 272 , FIG. 4 is a plan view illustrating surface properties of a portion of an apparatus (eg, device 250 ) in accordance with an embodiment of the present technology. Device 250 may include unintended defects 402 in one or more structures above/below location identifier layer 270 and/or location identifier layer 270 of FIG. 2B . For example, device 250 may include defects 402 on the top metal layer, passivation layer 262 of FIG. 2B , insulating layer 260 of FIG. 2B , circuit component layer 256 of FIG. 2B , etc. can

In some embodiments, the defect 402 may be visible to a human inspector with or without a magnifying lens/device. In some embodiments, the defect 402 may be captured by a camera that detects a light wave having a wavelength in the visible spectrum. When viewing defect 402 , section labels 272 may be seen adjacent to and/or overlapping defect 402 . Accordingly, a human inspector may identify that the defect 402 is located in one or more regions corresponding to adjacent/overlapping section labels 272 and/or label pixels 330 . Accordingly, section labels 272 and/or label pixels 330 provide an improved locating mechanism for a human inspector compared to an existing design (eg, FIG. 1F ).

To further illustrate example deficiencies for section labels 272 , FIG. 5 is a display illustrating a portion of an apparatus in accordance with an embodiment of the present technology. In some embodiments, device 250 of FIG. 2B may be inspected using an analysis tool such as an emission microscope, a laser imaging device, an x-ray based imager, an infrared based imager, or the like. The analysis tool detects and/or determines the internal defect 502 of the device 250 based on a detection signal (eg, a light wave) that propagates through and/or reflects off one or more portions therein. can be visualized. For example, the analysis tool may indicate hot spots and/or electrical shorts within device 250 based on thermal sensing (ie, radiated/reflected infrared signals).

In addition to detecting/visualizing the internal defect 502 , the analysis tool may simultaneously delineate section labels. Since the section labels 272 include the identifier filler 320 of FIG. 3C which is different from the other peripheral slots 314 of FIG. 3C , the propagation/reflection of the detection signal is transmitted between the peripheral slots 314 and the section label 272 of FIG. 3C . ) can be affected differently. Accordingly, the analysis tool can detect and visualize the distinction between the section label 272 and the surrounding area along with the internal defect 502 . Accordingly, section labels 272 including identifier filler 320 provide an improved positioning mechanism for locating internal defects 502 compared to existing designs (eg, FIGS. 1D and/or 1E ). do.

6 illustrates an exemplary method 600 of manufacturing an apparatus (eg, memory device 200 of FIG. 2A , a portion thereof, and/or device 250 of FIG. 2B ) in accordance with an embodiment of the present technology. is a flow chart that Method 600 may include a process of manufacturing a device including location identifier layer 270 of FIG. 2B having section labels 272 of FIG. 2B therein.

At block 602 , a substrate (eg, substrate 252 in FIG. 2B ) may be provided for fabricating a device. The substrate may include a semiconductor material (eg, a silicon based material) and/or a core material (eg, a ceramic, glass, and/or epoxy material), eg, for a PCB.

At block 604 , a metal layer (eg, metal layer 254 in FIG. 2B ) may be formed. At block 606 , a circuit layer (eg, circuit component layer 256 of FIG. 2B ) may be formed. In some embodiments, forming the circuit layer includes providing one or more insulating layers (eg, insulating layer 260 of FIG. 2B ) and/or at block 610 as illustrated at block 608 . may include providing circuitry (eg, components of circuit component layer 256 such as transistors, resistors, capacitors, etc.) as illustrated. In some embodiments, blocks 604-610 include depositing material (eg, insulating material, doping material, and/or conductive/metal material), removing removal (eg, etching and and/or via chemical mechanical planarization) and/or doping the region to form semiconductor devices and/or integrated circuits. In some embodiments, blocks 604-610 may include attaching circuit components to each other and/or to a substrate.

At block 612 , an identification layer (eg, location identification layer 270 of FIG. 2B , such as a metal mesh structure) may be deposited over the circuit layer. In some embodiments, such as shown at block 614, labels (eg, section labels 272 in FIG. 2B) may be generated for the identification layer. For example, select instances of slots 314 of FIG. 3C may be filled with identifier filler 320 of FIG. 3C to form/indicate numbers, letters and/or symbols for section labels 272 . The locations of filled instances of section labels 272 and/or slots 314 may correspond to locations of grid system and/or circuit components on substrate 252 . The process of filling the slots 314 with the identifier filler 320 may be implemented before and/or after attaching the identity layer over the circuit layer.

In some embodiments, such as illustrated at block 616 , attaching the identification layer may include electrically coupling the identification layer to one or more circuit components. For example, one or more of the circuit components of the circuit layer may be directly connected to or in direct contact with one or more portions of the metal mesh structure. Further, the metal mesh structure and one or more of the circuit components may be connected via other circuit components and/or conductive structures (eg, metal pillars, through silicon vias (TSVs), wires, etc.). Accordingly, the identification layer may be electrically coupled to one or more circuit components of the circuit layer and/or a reference voltage (eg, a source voltage or electrical ground) (eg, solder reflow and/or a metal structure or through some fusion of those).

At block 618 , an upper passivation layer (eg, passivation layer 262 of FIG. 2B , encapsulant, etc.) may be formed over the identification layer. In some embodiments, one or more physical properties of the top passivation layer may be different from properties of the filler for the section labels 272 as described above. In some embodiments, the top passivation layer may have physical properties to allow light to pass through such that the section labels 272 of the location identifier layer 270 are visible through the top passivation layer. In some embodiments, the top passivation layer, substrate 252 , and/or identifier pillar 320 may have section labels 272 on top passivation layer when viewing circuit component layer 256 through, for example, an analysis tool. and/or have physical properties such that they are visible through the substrate.

7 is a schematic diagram of a system including a memory device in accordance with an embodiment of the present technology. Any one of the memory devices described above with reference to FIGS. 2A-6 may be incorporated into a myriad of larger and/or more complex systems that are representative examples of the system 780 schematically illustrated in FIG. 7 . System 780 may include memory device 700 , power 782 , driver 784 , processor 786 , and/or other subsystems or components 788 . Memory device 700 may include characteristics generally similar to those of the memory device described above with reference to FIGS. 2A-6 , and thus may include various characteristics for performing a read request directly from a host device. . The resulting system 780 may perform any of a variety of functions, such as memory storage, data processing, and/or other suitable functions. Accordingly, representative system 780 may include, but is not limited to, portable devices (eg, cell phones, tablets, digital readers, and digital audio players), computers, vehicles, consumer electronics, and other products. The components of system 780 may be housed in a single unit or distributed over several interconnected units (eg, via a communications network). Components of system 780 may also include remote devices and any of a variety of computer readable media.

It should be noted that the method described above describes possible implementations, and that the acts and steps may be rearranged or otherwise modified, and that other implementations are possible. Also, embodiments from two or more methods may be combined.

The information and signals described herein may be represented using a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may represent voltages, currents, electromagnetic waves, magnetic fields or particles, optical fields or particles, or combinations thereof. can Some figures may represent a signal as a single signal; However, those skilled in the art will appreciate that a signal may represent a bus of a signal, where the bus may have various bit widths.

Devices discussed herein, including memory devices, may be formed on a die or a semiconductor substrate such as silicon, germanium, a silicon-germanium alloy, gallium arsenide, gallium nitride, or the like. In some cases, the substrate is a semiconductor wafer. In other cases, the substrate may be a silicon-on-insulator (SOI) substrate, such as silicon-on-glass (SOG) or silicon-on-sapphire (SOP), or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate, or sub-regions of the substrate, can be controlled through doping using various species including but not limited to phosphorus, boron or arsenic. Doping may be performed during initial formation or growth of the substrate, by ion implantation, or by any other doping means.

The functions described herein may be implemented in hardware, software executed by a processor, firmware, or any combination thereof. Other examples and implementations are within the scope of this disclosure and the appended claims. Features that implement a function may also be physically located in various locations, including distributed such that portions of the functionality are implemented at different physical locations.

As used herein, including in the claims, "or" in a list of items (e.g., a list of items preceded by a phrase such as "at least one" or "one or more") indicates an inclusive list, e.g. , A, B, or C may mean A or B or C or AB or AC or BC or ABC (ie, A and B and C). Also, as used herein, the phrase “based on” should not be construed as a reference to a closed set of conditions. For example, exemplary steps described as “based on condition A” may be based on both condition A and condition B without departing from the scope of this disclosure. In other words, the phrase “based on” as used herein should be interpreted in the same way as the phrase “based at least in part on”.

As described above, while specific embodiments of the invention have been described herein for purposes of illustration, it will be understood that various modifications may be made without departing from the scope of the invention. Rather, in the foregoing description, numerous specific details are discussed in order to provide a thorough and possible description of embodiments of the present technology. However, those skilled in the relevant art will recognize that the present disclosure may be practiced without one or more of the specific details. In other instances, well-known structures or operations often associated with memory systems and devices have not been shown or described in detail in order to avoid obscuring other aspects of the technology. In general, it should be understood that various other devices, systems, and methods in addition to the specific embodiments disclosed herein may be within the scope of the subject technology.

Claims (20)

In the device,
Board;
circuit components disposed on the substrate; and
a location identifier layer over the circuit, the location identifier layer comprising:
planar mesh structure with slots inside;
one or more section labels corresponding to physical locations of the circuit components within the device, wherein the one or more section labels include filler material in one or more sets of slots. The method of claim 1,
the location identifier layer is a metal mesh; And
wherein the filler material is a dummy filler. The apparatus of claim 2 , wherein the metal mesh is electrically conductive and includes an upper metal layer. 4. The apparatus of claim 3, wherein the upper metal layer is electrically connected to one or more of the circuit components. 5. The apparatus of claim 4, wherein the upper metal layer is configured to provide a supply voltage or ground connection to the connected circuit components. 2. The method of claim 1, wherein each of the section labels (1) corresponds to a macro-cell containing a unique region of the location identifier layer, and (2) a number to identify the unique region. , a device comprising a unique set of characters, symbols, or combinations thereof. 7. The apparatus of claim 6, wherein one or more of the slots correspond to pixels selectively filled with the filler material to provide a unique set of the number, letter, symbol, or a combination thereof. 8. The apparatus of claim 7, wherein the pixel corresponds to a coordinate for further locating the circuit components. The method of claim 1,
the circuit components are arranged over a surface of the substrate; And
wherein the planar mesh structure overlaps and extends parallel to the surface. The method of claim 1,
further comprising an upper passivation layer over the location identifier layer; And
here:
wherein the one or more section labels are visible through the top passivation layer. 11. The method of claim 10,
the upper passivation layer comprises a first material; And
and the one or more section labels include a second material having at least one physical property different from the first material. The apparatus of claim 11 , wherein the second material has a different density, color, composition, or combination thereof than the first material. The apparatus of claim 10 , wherein the one or more section labels provide a visual reference for locating a physical feature, defect, or combination thereof within the apparatus. The apparatus of claim 1 , wherein the apparatus comprises a semiconductor device. 15. The apparatus of claim 14, wherein the semiconductor device is a memory device. A method of manufacturing a device, said method comprising:
providing a substrate;
forming circuit components over the substrate; and
depositing a location identifier layer over the circuit components, the location identifier layer comprising:
a planar mesh structure with slots therein, and
one or more section labels for indicating physical locations of the circuit components within the device. 17. The method of claim 16, further comprising filling the set of slots with filler material according to a predetermined pattern to form the one or more section labels. 17. The method of claim 16,
the location identifier layer is a metal mesh; And
and attaching the location identifier layer comprises electrically connecting the location identifier layer to one or more of the circuit components. 17. The method of claim 16,
forming a first metal layer over the substrate; and
forming an upper passivation layer over the location identifier layer;
here:
the location identifier layer comprises a top metal layer; And
Forming the circuit components comprises:
forming at least one insulating layer over the first metal layer; and
forming the circuit components over at least one insulating layer, wherein at least one of the circuit components is electrically connected to the first metal layer. In a semiconductor device,
Board;
a first metal layer over the substrate;
a circuit layer overlying and electrically connected to the first metal layer, wherein the circuit layer comprises a set of components arranged in a repeating pattern along a lateral plane;
an upper metal layer over the circuit layer, wherein the upper metal layer comprises:
a mesh structure with slots therein, and
including filler material in the set of slots to provide a visual reference when looking for and identifying defects and/or components in the circuit layer;
a top passivation layer over the top metal layer; And
here:
wherein the filler material is visible and/or detectable through the top passivation layer.

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