KR20220040202A - Flashless ois driver circuit and ois device - Google Patents

Abstract

An embodiment of the present invention proposes a flashless OIS driver circuit and OIS device capable of reducing size of a camera module. According to an embodiment of the present invention, in a flashless OIS driver circuit having a hand tremor correction function, the flashless OIS driver circuit comprises: a flashless control device that holds reset of an OIS control device for booting and reads driving firmware from an external memory, when the main power is supplied in a low power state, which is the main power off state; and a volatile memory for storing driving firmware read by the flashless control device.

Description

FLASHLESS OIS DRIVER CIRCUIT AND OIS DEVICE

The present invention relates to a flashless OIS (Optical Image Stabilizer, hereinafter referred to as OIS) driver circuit and OIS device.

In general, an optical image stabilization (OIS) technology for correcting hand shake may be applied to a camera device included in a mobile device such as a mobile phone. The OIS technology is a technology for obtaining a clear image even with hand shaking.

In general, as the OIS technology, an electronic OIS technology that detects hand shake from a captured image and corrects it in software has been used. However, it has disadvantages in that there is a low image correction performance and overhead of memory and processor performance according to the number of pixels.

In order to solve the disadvantages of the electronic OIS technology, an optical OIS technology with better performance has been recently applied.

Optical OIS technology detects the user's hand shake and compensates the image by mechanically moving the optical axis (lens or image sensor) in the opposite direction to the camera movement. It requires this and has the disadvantage that it is an expensive system compared to the electronic OIS technology, but it has the advantage that the input image is not damaged, so the correction performance is high and the overhead for high resolution is small.

An existing OIS device may include a plurality of OIS driver circuits provided for each of a plurality of camera modules. Each of the plurality of OIS driver circuits may include a flash memory including driving firmware therein.

Accordingly, the existing OIS device may include a plurality of OIS driver circuits provided for each of the plurality of camera modules. In this case, each of the plurality of OIS driver circuits includes a flash memory that stores driving firmware. should include

In the case of an existing OIS driver circuit (eg, Driver IC), the driving firmware is stored in a flash memory, so that when power is supplied, the OIS driver circuit can operate in synchronization with the system clock.

Accordingly, when the existing OIS device includes a plurality of OIS driver circuits, each of the plurality of OIS driver circuits includes a flash memory for storing driving firmware, and a boosting operation proceeds immediately when power is supplied. , there is an advantage in that there is no need for a prior operation such as separately importing the driving firmware or performing a separate booting operation.

However, when the existing OIS device includes a plurality of OIS driver circuits, each of the plurality of OIS driver circuits must include a flash memory for storing the driving firmware, thereby increasing the circuit size (eg, IC chip size) and cost. There were problems such as increase.

(Prior art literature)

(Patent Document 1) KR Patent Publication No. 10-2006-0069007

(Patent Document 2) KR Patent Publication No. 10-2007-0081597

According to an embodiment of the present invention, the size of the OIS driver circuit can be reduced by removing the internal flash memory from the plurality of OIS driver circuits of the OIS device, and thus the size of the camera module can be reduced. We propose a lease OIS driver circuit and OIS device.

In addition, a flashless OIS driver circuit and an OIS device are proposed in which the OIS driver circuit can stably perform a boosting operation even when an internal flash memory is removed from a plurality of OIS driver circuits of the OIS device.

According to an embodiment of the present invention, in a flashless OIS driver circuit having an image stabilization function, when the main power is supplied in the low power state, which is the main power off state, the booting operation is started to read the driving firmware from the external memory. lease controller; and a volatile memory for storing the driving firmware read by the flashless controller. A flashless OIS driver circuit including

In addition, according to another embodiment of the present invention, in the OIS device having a hand shake correction function, an external memory for storing the driving firmware; and a flashless OIS driver circuit that starts a booting operation when main power is supplied, reads the driving firmware from the external memory and stores it in a volatile memory; An OIS device comprising

According to an embodiment of the present invention, by removing the internal flash memory from the plurality of OIS driver circuits of the OIS device, the size of the OIS driver circuit can be reduced, thereby reducing the size and cost of the camera module. It can be reduced, and when installed in a mobile phone, the space occupied by the camera module can be reduced.

For example, when a plurality of camera modules are installed in a mobile phone, the size of each OIS driver circuit can be reduced in a situation in which the number of OIS driver circuits provided for each camera module to control them also increases. This can be a huge advantage.

In addition, even if the flash memory is removed from the plurality of OIS driver circuits of the OIS device, the OIS driver circuit may stably perform the boosting operation.

1 is an exemplary configuration diagram of an OIS device to which the present invention is applied.
2 is an exemplary diagram of a flashless OIS driver circuit according to an embodiment of the present invention.
3 is an exemplary diagram of an OIS device and a flashless OIS driver circuit according to an embodiment of the present invention.
4 is an exemplary diagram of an Always Power On (APO) register of FIG. 3 .
5 is a diagram illustrating the process of determining the SPI rate and the SPI rate and the memory read operation.
6 is a detailed exemplary diagram of a memory read operation.
7 is a diagram illustrating pin connection in a 3-wire SPI communication mode between a flashless driver circuit and a peripheral device.
8 is a diagram illustrating pin connection in a 4-wire SPI communication mode between a flashless driver circuit and a peripheral device.

Hereinafter, it should be understood that the present invention is not limited to the described embodiments, and various changes may be made without departing from the spirit and scope of the present invention.

In addition, in each embodiment of the present invention, the structure, shape, and numerical value described as an example are only examples for helping the understanding of the technical matters of the present invention, and thus the spirit and scope of the present invention are not limited thereto. It should be understood that various changes may be made without departing from it. The embodiments of the present invention may be combined with each other to form various new embodiments.

In addition, in the drawings referenced in the present invention, components having substantially the same configuration and function will be denoted by the same reference numerals in light of the overall content of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings in order to enable those of ordinary skill in the art to easily practice the present invention.

1 is an exemplary configuration diagram of an OIS device to which the present invention is applied.

Referring to FIG. 1 , the OIS device 1 to which the present invention is applied includes a hand shake correction function, detects information on hand shake, and in the opposite direction to the corresponding hand shake, a lens 40 (or an image sensor) ) to always obtain a clear photographed image even in the presence of hand tremors, and to perform this function, it can be done as follows.

For example, the OIS device 1 may include a gyro sensor unit 10 , an OIS driver circuit 20 , an actuator 30 , a lens 40 (or a lens module), and a hall sensor 50 . can

The gyro sensor unit 10 may provide gyro information (Sgyro) corresponding to hand shaking.

For example, the gyro sensor unit 10 may include a gyro sensor 11 , an integrator 12 , and a filter 13 . The gyro sensor 11 may detect angular velocity information corresponding to X-axis and Y-axis movement with respect to hand shake. The integrator 12 may integrate the angular velocity information to calculate angle information on hand shake. The filter 13 removes noise and DC offset from the angle information, extracts a hand shake frequency component (eg, 2 Hz to 20 Hz), and outputs gyro data (Sgyro) including angle information corresponding to hand shake can do.

The OIS driver circuit 20 includes an error calculator 21, a Proportional-Integral-Derivative (PID) controller 22, a driver 23, an analog amplifier 26, and an analog-to-digital converter (ADC) ( 27) may be included.

The error calculator 21 generates error data Serr between gyro data Sgyro for hand shake by the gyro sensor unit 10 and digital detection data Sdd from the ADC 27 . can

The PID controller 22 may use the error data Serr from the error calculator 21 to generate a control signal S22 for driving the lens.

The driver 23 may output a driving signal Sdr to the actuator 30 based on the control signal S22 from the PID controller 22 .

The actuator 30 may operate according to the driving signal Sdr from the driver 23 to adjust the position of the lens 40 . For example, the actuator 30 may be a VCM (Voice Coil Moto) actuator, but is not limited thereto.

As an example, the VCM actuator may have a structure in which a magnetic circuit is usually formed with a soft magnetic material (Steel) and a permanent magnet, a coil is placed in an air gap inside the magnetic circuit, and a leaf spring is pressed thereon. It is not limited to these examples.

For example, the operation of the VCM actuator may be operated by a Lorentz force generated when a current flows through a coil in a magnetic field formed by a magnet. Here, the direction of the force is determined by Fleming's left hand rule, and it moves by converting electrical energy into mechanical energy and has the characteristic of returning to its original position by a spring.

The hall sensor 50 may detect a position of the lens 40 moved by the actuator 30 and output a detection signal S50 .

The analog amplifier 26 may amplify the detection signal S25 from the Hall sensor 50 and output it to the ADC 27 to enable position detection for a small detection signal.

The ADC 27 may convert the detection signal S26 amplified by the analog amplifier 26 into digital detection data Sdd.

In the OIS device 1 as described above, in order to move the lens as much as movement information corresponding to hand tremor obtained from the gyro sensor 11, control is performed through the PID controller 22, and the PID controller 22 ), the amount of movement of the lens 40 controlled through a feedback loop is monitored through a feedback loop to adjust the amount of control, so that hand shake can be corrected.

On the other hand, the flashless OIS driver circuit ( FIGS. 3 and 100 ) according to an embodiment of the present invention does not include a flash memory, and in this way, the flash memory is removed from the OIS driver circuit 20 . Accordingly, it is necessary to control the oscillator clock and the system booting sequence of the internal functional blocks.

For each drawing of the present invention, unnecessary redundant descriptions of components having the same reference numerals and the same functions may be omitted, and possible differences may be described for each drawing.

2 is an exemplary diagram of a flashless OIS driver circuit according to an embodiment of the present invention, and FIG. 3 is an exemplary diagram of an OIS device and a flashless OIS driver circuit according to an embodiment of the present invention.

2 and 3 , the OIS device 2 according to an embodiment of the present invention may include a flashless OIS driver circuit 100 and an external memory 200 . Here, there may be a plurality of flashless OSI driver circuits. Hereinafter, an operation for one flashless OSI driver circuit will be described, and this description may be equally applied to each of the plurality of flashless OSI driver circuits.

Also, the OIS device 2 may include a gyro sensor unit 10 and a pin selector 300 .

The flashless OIS driver circuit 100 may start a booting operation when main power is supplied, read the driving firmware DFW from the external memory 200 and store it in the volatile memory 130 .

The external memory 200 may store driving firmware DFW and provide it to the flashless OIS driver circuit 100 .

The gyro sensor unit 10 may include gyro data corresponding to hand shake information, and may provide the gyro data to the flashless OIS driver circuit 100 .

Also, the flashless OIS driver circuit 100 may perform a booting operation to read the driving software, and read the gyro data from the gyro sensor unit 10 after the booting operation.

Referring to FIG. 3 , the flashless OIS driver circuit 100 may include a flashless controller 110 and the volatile memory 130 .

Also, the flashless OIS driver circuit 100 may include an OIS controller 101 (eg, microcontroller unit (MCU)).

The flashless controller 110 may include an APO register 115 and a specific register 116 that receive power regardless of main power supply and provide status signals related to downloading of driving firmware.

The APO register 115 includes a plurality of registers that are always supplied with power, and can provide control signals (or status signals) necessary for a booting operation even when the main power is not supplied. It will be described with reference.

The specific register 116 stores a data value related to the oscillator clock. When the data value is a specific value, the SPI speed can be maintained at an initial setting value. When the data value is not a specific value, this data value is It can be used to determine the SPI rate.

In addition, the flashless controller 110 holds the reset of the OIS controller 101 for booting when the main power is supplied in the low power state, which is the main power off state, and refers to the state signals, the external memory The driving firmware may be read from 200 and stored in the volatile memory 130 .

The volatile memory 130 may store the driving firmware DFW read by the flashless controller 110 . Here, the volatile memory 130 may be an SRAM, but is not limited thereto.

Briefly describing the operation of the flashless OIS driver circuit 100 as described above, for example, since the flashless OIS driver circuit 100 does not include a flash memory storing firmware, the driving firmware DFW ) before performing the OIS operation, when the main power is supplied, the booting operation may be started, the driving firmware DFW may be read from the external memory 200 and stored in the volatile memory 130 which is an internal memory.

After the booting operation is completed, the OIS controller 101 may then perform an OIS (Optical Image Stabilization) operation through PID control using the driving firmware DFW.

In addition, the pin selector 300 may select a pin connection with one of the gyro sensor unit 10 and the external memory 200 in the SPI communication mode.

For example, a pin connection between the flashless OIS driver circuit 100 and the external memory 200 may be selected by the pin selector 300 during the booting operation, and after the booting operation, the pin selector 300 may select, A pin connection between the flashless OIS driver circuit 100 and the gyro sensor unit 10 may be selected.

4 is an exemplary diagram of an Always Power On (APO) register of FIG. 3 .

3 and 4 , as described above, the flashless OIS driver circuit 100 may include the APO register 115 .

Since the APO register 115 does not have a flash memory therein, it is stored in the volatile memory 130 (eg, SRAM) that is an internal memory even in an IDLE state that is not used by a user. It must be able to provide the necessary signals so that the data can be maintained, and for this purpose, it can be continuously powered even when the mains is not present.

For example, if power is not supplied to the volatile memory 130 , the inconvenience of bringing the driving firmware from the outside may occur whenever a user performs an operation. In order to prevent such trouble, the APO register 115 may always receive power to provide signals necessary for the volatile memory 130 to retain data.

For example, if the OIS device is a low power system including a power saving mode, and there is no selection by the user, for power saving, the main power is cut off to perform the OIS operation ( power saving mode).

As an example, first read the driving firmware (DFW) from the external memory 200 and store it in the volatile memory 130, even if the main power supply is cut off for power saving and all digital blocks are powered off, the APO The resistor 115 must always be supplied with power.

Referring to FIG. 4 , the APO register 115 includes a first register 115-1, a second register 115-2, and a third register 115-3. and a fourth register 115 - 4 .

First, the first register 115 - 1 may output a flashless busy signal FLS_BUSY indicating whether or not the download of the driving firmware DFW is in progress.

For example, the flashless busy signal FLS_BUSY is a control signal generated by the flashless controller 110 (or flashless controller). When the flashless busy signal FLS_BUSY is “0”, the current flashless controller ( 110) indicates that the driving firmware DFW is being downloaded, and when “1” indicates that all data related to the driving firmware DFW have been downloaded.

The second register 115 - 2 may output a redownload prevention signal DO_NOT_REDOWNLOAD informing whether or not to download in order to prevent repeated download.

For example, the re-download prevention signal DO_NOT_REDOWNLOAD initially has a default value of “0” to download the driving firmware DFW, and all of the driving firmware DFW is stored in the volatile memory 130 . It may be set to "1" after the download is completed.

For example, if the state value of the re-download prevention signal DO_NOT_REDOWNLOAD is set to “1”, the driving firmware DFW stored in the volatile memory 130 is maintained and the download is not performed again.

The third register 115 - 3 may output a flashless initialization signal FLS_BLOCK_INIT indicating whether to start downloading according to initialization.

For example, the flashless initialization signal FLS_BLOCK_INIT may be used as a signal for downloading the driving firmware DFW and updating other driving firmware while the main power is supplied. For example, when the flashless initialization signal FLS_BLOCK_INIT is changed from “0” to “1”, the flashless controller 110 is initialized and the driving firmware starts to be downloaded again. At this time, the re-download prevention signal (DO_NOT_REDOWNLOAD) may also be initialized (reset to “0”).

The fourth register 115 - 4 may output a flashless mode signal FLS_MODE_NEN indicating a download communication method.

For example, in the case of the flashless mode signal (FLS_MODE_NEN), it is a control signal for selecting the download communication method (I2C communication or SPI communication) of the driving firmware (DFW). If the flashless mode signal (FLS_MODE_NEN) is “0”, The SPI communication mode, which is a flashless communication mode, is performed, and when the flashless mode signal (FLS_MODE_NEN) is “1”, the I2C communication mode can be performed.

As described above, the first to fourth registers 115-1 to 115-4 perform a function of supplying a control signal for maintaining information in the low power mode, and these first to fourth registers 115- 1 to 115-4), in Low Power Mode, which turns off all main power of function blocks that are not required for operation, When abnormal operation can be prevented.

5 is a diagram illustrating the process of determining the SPI rate and the SPI rate and the memory read operation.

With reference to FIG. 5 , the SPI speed SPI speed determination and memory read operation performed by the flashless controller 110 will be described.

Referring to FIG. 5 , when the main power is supplied (S101) and the flashless controller 110 is confirmed as a state before the download of the driving firmware DFW based on the re-download prevention signal DO_NOT_REDOWNLOAD (S110) , SPI speed determination, OIS controller 101 reset, and memory read operation may be sequentially performed based on a data value stored in a specific register (eg, HRDATA) (S130) (S150) .

The process shown in FIG. 5 will be described in more detail.

The flashless controller 110 may determine whether the main power is supplied (S101), and when the main power is supplied, the state of the re-download prevention signal DO_NOT_REDOWNLOAD may be determined (S110).

In the determination process (S110), it is determined whether the re-download prevention signal (DO_NOT_REDOWNLOAD) is in the re-download permission mode ("0"), and the re-download prevention signal DO_NOT_REDOWNLOAD is the re-download permission mode ("0") In the case of the re-download prevention mode (“1”) instead of , HRDATA) can be checked (S130).

Next, it is determined whether the data value stored in the specific register (eg, HRDATA) is a “specific value”. The speed can be determined (S140), and when the data value stored in the specific register (eg, HRDATA) is not a “specific value”, the SPI speed can be determined based on the data value stored in the specific register (eg, HRDATA). There is (S150).

Here, when the OIS device includes a plurality of OIS driver circuits (eg, OIS driver IC), the oscillator clock value related to the SPI speed of each of the plurality of OIS driver circuits may be slightly different from each other. The oscillator clock can be set through the trimming process described above.

For example, the SPI speed determination process ( S150 ) may be made of a series of processes as follows.

First, after determining the SPI speed based on the data value stored in the specific register (eg, HRDATA) (S151), the reset of the OIS controller 101 (eg, MCU) is held to prevent the OIS operation (S152) ), the driving firmware DFW may be read from the external memory 200 by performing a memory read operation (S153).

In other words, the SPI speed can be determined by reading a data value stored in a specific register (eg, HRDATA). For example, if the data value stored in a specific register (eg, HRDATA) is “0xMAX(0xFFF)” or “MIN(0)”, the oscillator clock is not a changed value, so the SPI speed is set based on the initial data value. . Because there is no need to read the data value stored in the specific register (eg HRDATA) again when it is switched back from the power down mode (power saving mode) to the power on mode (OIS operation mode), the You can check the status value of the download prevention signal (DO_NOT_REDOWNLOAD).

As described above, after the oscillator clock is determined, a process of reading the driving firmware DFW from the external memory 200 may be performed.

6 is a detailed exemplary diagram of a memory read operation.

3 to 6 , the flashless controller 110 receives the main power supply (S101), resets and holds the OIS controller 101 (eg, MCU) (S210), and performs a flashless mode signal (S210). The communication mode can be checked using the status value of FLS_MODE_NEN (S220).

For example, while the flashless controller 110 operates in the power saving mode, main power may be supplied according to a user's operation selection, and in this case, a booting operation for reading the driving firmware may be performed. In the initial stage of this booting operation, a process of reset-holding the OIS controller 101 (eg, MCU) (S210) and a process of checking the communication mode using the state value of the flashless mode signal (FLS_MODE_NEN) (S220) are performed. can do.

For example, if the communication mode is described, in the flashless controller 110, the SPI communication mode and the application ( Application), it is possible to set and perform any one of the I2C communication modes in which the driving firmware (DFW) is read from the external memory 200 using the I2C communication mode.

For example, the initial setting value of the flashless mode signal FLS_MODE_NEN is “0”, and in this case, the flashless controller 110 operates as an SPI master and drives the firmware from the external memory 200 that is the SPI slave unit. (DFW) can be read and stored in the volatile memory 130 which is an internal memory (S230).

As another example, if the application (Application) wants to download the driving firmware (DFW), if the flashless mode signal (FLS_MODE_NEN) is set to “1”, then based on this, the I2C communication mode is set by the application Using this, an operation of downloading the driving firmware may be performed (S250).

First, the OIS controller 101 (eg, MCU) reset hold process (S210) will be described.

For example, the OIS controller 101 may be reset in order not to be interrupted by other operations while the driving firmware DFW is being downloaded.

In the reset hold process (S210) of the OIS controller 101, the flashless busy signal (FLS_BUSY) is set to “1” to perform the SPI communication mode, and a 12C mode enable signal ( I2C_MODE_EN) is set to “1”, and in this case, the controller reset signal I2C controller reset signal I2c_mcu_resetn may be reset to “0”.

A signal for holding the reset of the OIS controller 101, including the aforementioned flashless busy signal (FLS_BUSY), 12C mode enable signal (I2C_MODE_EN), and controller reset signal I2C controller reset signal (i2c_mcu_resetn) can be used

Here, the reason for holding the reset of the OIS controller 101 is so as not to be disturbed by the OIS controller 101 while the driving firmware is being downloaded.

As such, when the OIS controller 101 is reset and held, the flashless controller 110 does not have the driving firmware DFW, so the operation of the OIS controller 101 is stopped, and thereafter, the flashless mode signal ( FLS_MODE_NEN) to determine the communication mode for performing the drive firmware read operation.

Next, the flashless controller 110 may check the communication mode according to the flashless mode signal FLS_MODE_NEN ( S220 ).

For example, as a result of checking the flashless mode signal (FLS_MODE_NEN), when the SPI communication mode is set (S220), a drive firmware read operation using SP communication may be performed (S230).

For example, a drive firmware read operation ( S230 ) using SP communication will be described.

First, the flashless controller 110 downloads the driving firmware DFW from the external memory 200 using the SPI communication (S231), and after the download of the driving firmware is completed, the flashless busy signal (FLS_BUSY) is released ("1") (S232), the re-download prevention signal (DO_NOT_REDOWNLOAD) is set ("1") (S234), and a channel change is performed according to the pin connection control (S234) ), the controller reset signal I2c_mcu_resetn may be released (“1”) (S235).

On the other hand, when explaining the driving Bumware read operation using SPI communication, if there is an I2C communication interrupt during SPI communication (S241), the state value of the flashless mode signal (FLS_MODE_NEN) is changed, and the flashless mode signal ( As a result of checking FLS_MODE_NEN), if the I2C communication mode is set (S220), a drive firmware read operation using I2C communication may be performed by the application (S250)

For example, during the drive firmware read operation using SPI communication, it is checked whether there is an interrupt for performing the I2C communication mode from the outside, and if there is an interrupt, the communication mode is changed and the I2C communication mode The driving firmware read operation may be performed by the application using , otherwise the driving firmware read operation using the SPI communication mode may be continuously performed.

For example, an I2C communication interrupt check process during SPI communication will be described.

The flashless controller 110 checks whether there is an I2C communication interrupt while performing SPI communication for downloading the driving firmware according to the flashless mode signal FLS_MODE_NEN (S241), and if there is an I2C communication interrupt, To change the communication mode, when a predetermined time elapses after resetting the operation of the flashless controller and changing the pin connection (S242), the drive firmware read operation using the I2C communication mode may be performed by the application.

That is, when the state value of the flashless mode signal FLS_MODE_NEN is “0”, while continuously checking the flashless mode signal FLS_MODE_NEN ( S240 ), the flashless controller 110 continues to external using the SPI communication mode. The driving firmware DFW is read from the memory 200 and stored in the volatile memory 130 (S230).

Here, the reason for continuously checking the flashless mode signal (FLS_MODE_NEN) is that, while performing the I2C communication mode, the control right transfer command requesting the download of the driving firmware using the I2C communication mode from an external application is not known when it will be received. Therefore, continuous verification is necessary.

For example, if there is no interference from an application during download, the download of the driving firmware is continuously performed using the SPI communication mode.

For example, the flashless controller 110 performs the SPI communication mode to operate as an SPI master, and reads the driving firmware (DFW) from the external memory 200 that is an SPI slave and stores it in the volatile memory 130 . During operation, the driving firmware DFW is read while continuously monitoring the state change of the flashless mode signal FLS_MODE_NEN.

If an interrupt comes from the application at this time to change the download method of the driving firmware, that is, when the state value of the flashless mode signal FLS_MODE_NEN is set to “1”, the flashless controller 110 As the SPI master, it stops the operation of reading the driving firmware and transfers the control right to the application.

At this time, the flashless controller 110 stops the firmware read operation using the SPI communication and does not operate until the state value of the flashless initialization signal FLS_BLOCK_INIT is initialized to “0”.

For example, when the I2C communication mode is set according to the flashless mode signal FLS_MODE_NEN (S220), a drive firmware read operation using the I2C communication mode by an application may be performed (S250).

For example, the drive firmware read operation S230 using the I2C communication mode resets the controller reset signal I2c_mcu_resetn and the flashless busy signal FLS_BUSY to stop the operation of the OIS controller 101 . "0") and (S251, S252), the driving firmware (DFW) is downloaded from the external memory 200 using the I2C communication mode (S253), and after the download of the driving firmware is completed, the controller reset signal ( I2c_mcu_resetn) and the flashless busy signal FLS_BUSY may be set (“1”).

Then, when the status value of the flashless mode signal (FLS_MODE_NEN) is changed to “1”, the application uses the I2C communication mode to operate as an I2C master and use the data bus. Thus, the driving firmware DFW may be directly stored in the volatile memory 130 .

In other words, in order to download the driving firmware using the I2C communication mode, the state value of the controller reset signal (I2c_mcu_resetn) is set to “0” so that the OIS controller (MCU) cannot operate, and the flashless busy signal ( FLS_BUSY) can also be set to "0" to indicate that it is not an SPI operation.

In addition, the state value of the controller reset signal (I2c_mcu_resetn) is set to “1” so that the driving firmware is continuously downloaded using the I2C communication mode so that the OIS controller (MCU) can operate when the download of the driving firmware is completed. can be released.

When the download of the above-described driving firmware is completed, the flashless controller 110 resets the flashless busy signal FLS_BUSY to “0”, sets the re-download prevention signal DO_NOT_REDOWNLOAD to “1”, and drives You can avoid downloading the firmware twice.

For example, when the download completion of the driving firmware is confirmed, the flashless controller 110 may change the state values of the flashless busy signal FLS_BUSY and the re-download prevention signal DO_NOT_REDOWNLOAD.

On the other hand, in SPI communication, the flashless controller 110 may change from a pin connection with the external memory to a pin connection with the gyro sensor unit by using the pin selector 300 .

For example, when the flashless controller 110 operates as an SPI master, a peripheral device (eg, external memory 200) and 3-wire SPI communication connection or 4-wire (4-wire) An SPI communication connection can be established. This will be described by way of example with reference to FIGS. 7 and 8 .

7 is a diagram illustrating pin connection of a 3-wire SPI communication mode between a flashless driver circuit and a peripheral device, and FIG. 8 is a 4-wire SPI communication between a flashless driver circuit and a peripheral device. It is an example of pin connection of the mode.

7 and 8 , the flashless controller 110 uses the pin selector 300 to connect a pin with the gyro sensor unit in a pin connection with the external memory (eg, SSX1 pin connection) ( In, SSX2 pin connection) can be changed.

In general, SPI communication consists of a total of 4 pins (SSX1, SCK, MOSI, MISO). If all 4 pins (SSX1, SCK, MOSI, MISO) are used, it becomes a 4-wire communication mode If only 3 pins (SSX1, SCK, MOSI) out of 4 pins (SSX1, SCK, MOSI, MISO) are used, 3-wire communication mode can be established.

Referring to FIG. 7 , if only 3 pins (SSX1, SCK, MOSI) are used, the MISO pin among the 4 pins (SS1, SCK, MOSI, MISO) may be assigned as SSX2 to be used as a chip selector pin.

First, when selecting using SSX1 (chip selector1) among the 3 pins (SSX1, SCK, MOSI), data is fetched from the external memory 200, and when selecting using SSX2 (chip selector2), the gyro sensor unit 10 data is fetched from

Referring to FIG. 8 , if the 4-wire communication mode is used, the MISO pin among the 4 pins (SSX1, SCK, MOSI, MISO) cannot be assigned to SSX2, so SSX2 is assigned as an additional PIN. and the operation is the same as that of the 3-wire operation.

7 and 8, each of the 3-wire communication mode and the 4-wire communication mode is a pin selector whether to bring the driving firmware from the external memory 200 or the gyro data from the gyro sensor unit 10. A corresponding operation may be performed by selecting a corresponding pin (one of SSX1 and SSX2) (eg, channel selection) (dotted arrows in FIGS. 7 and 8 ) through 300 .

As described above, if the flag memory is removed from the OIS driver circuit, the size of the OIS driver circuit can be reduced, and the number of pins of the OIS driver circuit can also be reduced, thereby reducing the size of the OIS device and manufacturing the OIS driver circuit. cost can be reduced.

Meanwhile, the OIS controller and the flashless controller of the OIS device according to an embodiment of the present invention include a processor (eg, a central processing unit (CPU), a graphic processing unit (GPU), a microprocessor, an application specific integrated circuit, ASICs), Field Programmable Gate Arrays (FPGAs), etc.), memory (e.g. volatile memory (e.g. RAM, etc.), non-volatile memory (e.g. ROM, flash memory, etc.), input devices (e.g. keyboard, Mouse, pen, voice input device, touch input device, infrared camera, video input device, etc.), output device (eg display, speaker, printer, etc.) and communication interface (eg modem, network interface card (NIC), integration Computing in which network interfaces, radio frequency transmitters/receivers, infrared ports, USB connectors, etc.) are interconnected (e.g. Peripheral Component Interconnect (PCI), USB, Firmware (IEEE 1394), Optical Bus Architecture, Networks, etc.) It can be implemented in the environment.

The computing environment may be a personal computer, server computer, handheld or laptop device, mobile device (mobile phone, PDA, media player, etc.), multiprocessor system, consumer electronics, minicomputer, mainframe computer, any of the foregoing systems or It may be implemented as a distributed computing environment including devices, but is not limited thereto.

In the above, the present invention has been described as an embodiment, but the present invention is not limited to the above embodiment, and without departing from the gist of the present invention as claimed in the claims, those of ordinary skill in the art to which the invention pertains Anyone can make various modifications.

10: gyro sensor unit
100: flashless OIS driver circuit;
101: OIS controller
110: flashless controller
115: APO register
116: specific register
130: volatile memory
200: external memory
300: pin selector

Claims (17)

In the OIS driver circuit having an image stabilization function,
a flashless controller that reads driving firmware from an external memory by performing a booting operation when main power is supplied in a low power state that is a main power off state; and
a volatile memory for storing the driving firmware read by the flashless controller;
A flashless OIS driver circuit comprising a.
According to claim 1, wherein the flashless controller,
It receives power regardless of mains power supply and includes an Always Power On (APO) register that provides status signals regarding the download of the driving firmware.
Flashless OIS driver circuit.
The method of claim 2, wherein the APO register comprises:
a first register outputting a flashless busy signal (FLS_BUSY) indicating whether the driving firmware is being downloaded;
a second register for outputting a re-download prevention signal (DO_NOT_REDOWNLOAD) informing whether or not to download to prevent repeated download;
a third register outputting a flashless initialization signal (FLS_BLOCK_INIT) indicating whether to start downloading according to initialization; and
a fourth register for outputting a flashless mode signal (FLS_MODE_NEN) indicating a download communication method;
A flashless OIS driver circuit comprising a.
The method of claim 3, wherein the flashless controller,
When the main power is supplied and the state before the download of the driving firmware is confirmed based on the re-download prevention signal (DO_NOT_REDOWNLOAD), the SPI speed is determined based on the data value of a specific register, the OIS controller is reset, and the memory performing a lead operation,
Flashless OIS driver circuit.
4. The method of claim 3, wherein the flashless controller is
When the SPI communication mode is set according to the flashless mode signal (FLS_MODE_NEN), the drive firmware read operation using SP communication is performed.
Flashless OIS driver circuit.
The method of claim 5, wherein the flashless controller is
According to the flashless mode signal (FLS_MODE_NEN), it is checked whether I2C communication is interrupted during SPI communication for downloading the driving firmware, and if there is an I2C communication interrupt, the flashless mode signal is used to process the corresponding interrupt. To change the state value of (FLS_MODE_NEN)
Flashless OIS driver circuit.
4. The method of claim 3, wherein the flashless controller is
When the I2C communication mode is set according to the flashless mode signal (FLS_MODE_NEN), the control is transferred to the application to perform a drive firmware read operation using the I2C communication mode,
Flashless OIS driver circuit.
The method of claim 3, wherein the flashless controller further comprises an OIS controller that is reset for a booting operation when the main power is turned on, and starts an OIS (Optical Image Stabilization) operation after the booting operation,
The flashless controller is
When the download completion of the driving firmware is confirmed, the state values of the flashless busy signal (FLS_BUSY) and the re-download prevention signal (DO_NOT_REDOWNLOAD) are changed, and the gyro sensor unit and the pin connection with the external memory using a pin selector to change to the pin connection of
Flashless OIS driver circuit.
In the OIS device having an image stabilization function,
external memory for storing driving firmware; and
a flashless OIS driver circuit that starts a booting operation when main power is supplied, reads the driving firmware from the external memory and stores it in a volatile memory;
OIS device comprising a.
The method of claim 9, wherein the OIS device,
a gyro sensor unit having gyro data corresponding to hand shake information; further comprising,
The flashless OIS driver circuit comprises:
After the booting operation, the gyro data is read from the gyro sensor unit.
OIS device.
The method of claim 10, wherein the flashless OIS driver circuit comprises:
It receives power regardless of main power supply and includes an APO register that provides status signals related to downloading of driving firmware. Flashless controller that reads firmware; and
the volatile memory for storing the driving firmware read by the flashless controller;
OIS device comprising a.
12. The method of claim 11, wherein the APO register,
a first register outputting a flashless busy signal (FLS_BUSY) indicating whether the driving firmware is being downloaded;
a second register for outputting a re-download prevention signal (DO_NOT_REDOWNLOAD) informing whether or not to download to prevent repeated download;
a third register outputting a flashless initialization signal (FLS_BLOCK_INIT) indicating whether to start downloading according to initialization; and
a fourth register for outputting a flashless mode signal (FLS_MODE_NEN) indicating a download communication method;
OIS device comprising a.
The method of claim 12, wherein the flashless controller,
When the main power is supplied and the state before the download of the driving firmware is confirmed based on the re-download prevention signal (DO_NOT_REDOWNLOAD), SPI speed determination, OIS controller reset, and memory read operation are performed based on a specific register. performing,
OIS device.
13. The method of claim 12, wherein the flashless controller is
When the SPI communication mode is set according to the flashless mode signal (FLS_MODE_NEN), the drive firmware read operation using SP communication is performed.
OIS device.
15. The method of claim 14, wherein the flashless controller,
According to the flashless mode signal (FLS_MODE_NEN), it is checked whether I2C communication is interrupted during SPI communication for downloading the driving firmware, and if there is an I2C communication interrupt, the flashless mode signal is used to process the corresponding interrupt. To change the state value of (FLS_MODE_NEN)
OIS device.
The method of claim 12, wherein the flashless controller,
When the I2C communication mode is set according to the flashless mode signal (FLS_MODE_NEN), the control is transferred to the application to perform a drive firmware read operation using the I2C communication mode,
OIS device.
13. The method of claim 12, wherein the flashless controller is
an OIS controller that is reset for a booting operation by the flashless controller when the main power is turned on, and starts an OIS (Optical Image Stabilization) operation after the booting operation; and
a pin selector for selecting a pin connection with one of the gyro sensor unit and the external memory; further comprising,
The flashless controller is
When the download completion of the driving firmware is confirmed, the state values of the flashless busy signal (FLS_BUSY) and the re-download prevention signal (DO_NOT_REDOWNLOAD) are changed, and the gyro is connected to the external memory by using the pin selector. Changed by pin connection with the sensor unit
OIS device.

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