KR20220033637A - Display device - Google Patents

Abstract

The present invention relates to a display device. A display device according to an embodiment includes: a substrate; a transistor positioned on the substrate; an interlayer insulating film positioned on the transistor; a driving voltage line and a data line located on the interlayer insulating film and connected to the transistor; a passivation layer positioned on the driving voltage line and the data line; a pixel electrode positioned on the passivation layer and overlapping at least a portion of the driving voltage line and the data line; a pixel defining layer disposed on the pixel electrode and including a pixel opening; a light emitting element layer positioned on the pixel electrode; and a common electrode positioned on the light emitting element layer and the pixel defining layer. The interlayer insulating film includes a groove, and the driving voltage line and the data line are located in the groove. The present invention can prevent a decrease in transmittance while preventing a decrease in contrast.

Description

display device {DISPLAY DEVICE}

The present disclosure relates to a display device.

A display device is a device that displays a screen, and includes a liquid crystal display (LCD), an organic light emitting diode (OLED), and the like. Such a display device is used in various electronic devices such as a mobile phone, a navigation system, a digital camera, an electronic book, a portable game machine, or various terminals.

The organic light emitting diode display has a self-luminance characteristic, and unlike the liquid crystal display, it does not require a separate light source, so that the thickness and weight can be reduced. In addition, the organic light emitting diode display has high quality characteristics such as low power consumption, high luminance, and fast response speed.

Meanwhile, external light incident on the organic light emitting diode display may be reflected from the surface of the device, thereby reducing contrast. Accordingly, it is necessary to improve visibility by providing an antireflection unit in the organic light emitting diode display to prevent a decrease in contrast caused by external light. In order to prevent a decrease in transmittance due to the anti-reflection portion, a light blocking layer may be formed on the non-emissive portion and a color filter that transmits light in a wavelength band similar to that of light emitted from the light emitting layer of the light emitting portion overlapping the light emitting portion may be formed. As such, when the color filter is formed in the anti-reflection unit, external light is reflected and viewed due to a step caused by a wiring positioned under the light emitting layer of the display area, thereby reducing color and contrast.

SUMMARY Embodiments provide a display device capable of preventing a decrease in transmittance while preventing a decrease in contrast and preventing external light from being reflected and viewed due to a step caused by a wiring positioned under an emission layer.

It is apparent that the object of the present invention is not limited to the above-mentioned purpose, and can be variously expanded without departing from the spirit and scope of the present invention.

A display device according to an exemplary embodiment includes a substrate, a transistor disposed on the substrate, an interlayer insulating layer disposed over the transistor, a driving voltage line and a data line disposed on the interlayer insulating layer and connected to the transistor, the driving voltage line, and the data line a passivation layer positioned on the passivation layer, a pixel electrode positioned on the passivation layer and overlapping at least a portion of the driving voltage line and the data line, a pixel defining layer positioned over the pixel electrode and including a pixel opening, and a light emitting element layer positioned over the pixel electrode , and a common electrode disposed on the light emitting device layer and the pixel defining layer, wherein the interlayer insulating layer includes a groove, and the driving voltage line and the data line are located in the groove.

The interlayer insulating layer may include a first groove and a second groove, the driving voltage line may be located in the first groove, and the data line may be located in the second groove.

A depth of the first groove may be equal to a thickness of the driving voltage line, and a depth of the second groove may be equal to a thickness of the data line.

A width of the first groove may be greater than or equal to a width of the driving voltage line, and a width of the second groove may be greater than or equal to a width of the data line.

The display device may include a plurality of data lines spaced apart from each other, and at least two data lines among the plurality of data lines may be positioned in the second groove.

One data line may be positioned in the second groove.

The interlayer insulating film may include a lower interlayer insulating film and an upper interlayer insulating film positioned on the lower interlayer insulating film, the lower interlayer insulating film being entirely positioned on the substrate, and a portion from which the upper interlayer insulating film is removed may become the groove.

A bottom surface of the groove may be in contact with a top surface of the lower interlayer insulating layer, and a side surface of the groove may be in contact with a side surface of the upper interlayer insulating layer.

The display device may include a plurality of driving voltage lines spaced apart from each other, and at least two driving voltage lines among the plurality of driving voltage lines may be positioned in the groove.

The display device according to an embodiment further includes an encapsulation layer positioned on the common electrode, a touch unit positioned on the encapsulation layer, and an anti-reflection part positioned on the touch part, wherein the anti-reflection part overlaps the pixel defining layer a light blocking layer, and a color filter overlapping the pixel electrode.

Each pixel of the display device may include a plurality of transistors, and the plurality of transistors may include an oxide transistor including an oxide semiconductor and a polycrystalline transistor including a polycrystalline semiconductor.

A display device according to an exemplary embodiment includes a substrate, a transistor disposed on the substrate, an interlayer insulating layer disposed over the transistor, a driving voltage line and a data line disposed on the interlayer insulating layer and connected to the transistor, the driving voltage line, and the data line a passivation layer positioned on the passivation layer, a pixel electrode positioned on the passivation layer and overlapping at least a portion of the driving voltage line and the data line, a pixel defining layer positioned over the pixel electrode and including a pixel opening, and a light emitting element layer positioned over the pixel electrode , and a common electrode disposed on the light emitting device layer and the pixel defining layer, wherein the passivation layer includes a first passivation layer and a second passivation layer over the first passivation layer, and the second passivation layer is disposed on the substrate. It may be located in a partial region and overlap the driving voltage line and the data line.

The first passivation layer is entirely disposed on the substrate, the second passivation layer overlaps the pixel electrode, the pixel electrode is disposed on the second passivation layer, the second passivation layer overlaps an edge of the pixel defining layer, and the pixel It may not overlap with the center of the defining film.

The first passivation layer and the second passivation layer may include an organic insulating material.

In the display device according to an embodiment, the passivation layer may further include a third passivation layer positioned under the first passivation layer, and the third passivation layer may include an inorganic insulating material.

The first passivation layer and the third passivation layer may be entirely disposed on the substrate.

The third passivation layer may be entirely disposed on the substrate, and the first passivation layer may be positioned on a partial region of the substrate and overlap the driving voltage line and the data line.

A display device according to an exemplary embodiment includes a substrate, a transistor disposed on the substrate, an interlayer insulating layer disposed over the transistor, a driving voltage line and a data line disposed on the interlayer insulating layer and connected to the transistor, the driving voltage line, and the data line a passivation layer positioned on the passivation layer, a pixel electrode positioned on the passivation layer and overlapping at least a portion of the driving voltage line and the data line, a pixel defining layer positioned over the pixel electrode and including a pixel opening, and a light emitting element layer positioned over the pixel electrode and a common electrode positioned on the light emitting device layer and the pixel defining layer, wherein the passivation layer includes a first portion overlapping the driving voltage line and the data line, and a second portion excluding the first portion, wherein A thickness of the first portion may be greater than a thickness of the second portion.

A first portion of the passivation layer may overlap the pixel electrode, overlap an edge of the pixel defining layer, and not overlap a central portion of the pixel defining layer.

The passivation layer may include an organic insulating material.

According to the display device according to the exemplary embodiment, it is possible to prevent a decrease in transmittance while preventing a decrease in contrast by including an anti-reflection unit including a color filter, and external light is reflected and recognized due to a step difference due to a wiring located under the emission layer can be prevented from becoming

It is apparent that the effect of the present invention is not limited to the above-described effect, and can be variously expanded without departing from the spirit and scope of the present invention.

1 is a cross-sectional view of a display device according to an exemplary embodiment.
2 is a layout view illustrating a part of a display device according to an exemplary embodiment.
3 is a cross-sectional view of a display device according to an exemplary embodiment taken along line III-III of FIG. 2 .
4 is a circuit diagram of a display device according to an exemplary embodiment.
5 is a plan view illustrating a display device according to an exemplary embodiment.
6 is a cross-sectional view of a display device according to an exemplary embodiment taken along line VI-VI of FIG. 5 .
7 to 13 are plan views sequentially illustrating a manufacturing sequence of a display device according to an exemplary embodiment.
14 is a cross-sectional view of a display device according to an exemplary embodiment.
15 is a cross-sectional view of a display device according to an exemplary embodiment.
16 is a cross-sectional view of a display device according to an exemplary embodiment.
17 is a diagram illustrating a third interlayer insulating layer of the display device according to the exemplary embodiment of FIG. 16 .
18 is a diagram illustrating a third interlayer insulating layer of the display device according to the exemplary embodiment of FIG. 3 .
19 is a plan view of a display device according to an exemplary embodiment.
20 is a cross-sectional view of a display device according to an exemplary embodiment taken along line XX-XX of FIG. 19 .
21 is a cross-sectional view of a display device according to an exemplary embodiment.
22 is a diagram illustrating a part of a display device according to an exemplary embodiment.
23 is a cross-sectional view of a display device according to an exemplary embodiment.
24 is a cross-sectional view of a display device according to an exemplary embodiment.
25 is a cross-sectional view of a display device according to an exemplary embodiment.

Hereinafter, with reference to the accompanying drawings, various embodiments of the present invention will be described in detail so that those of ordinary skill in the art to which the present invention pertains can easily implement them. The present invention may be embodied in several different forms and is not limited to the embodiments described herein.

In order to clearly explain the present invention, parts irrelevant to the description are omitted, and the same reference numerals are assigned to the same or similar components throughout the specification.

In addition, since the size and thickness of each component shown in the drawings are arbitrarily indicated for convenience of description, the present invention is not necessarily limited to the illustrated bar. In order to clearly express various layers and regions in the drawings, the thicknesses are enlarged. And in the drawings, for convenience of description, the thickness of some layers and regions are exaggerated.

Further, when a part of a layer, film, region, plate, etc. is said to be “on” or “on” another part, it includes not only cases where it is “directly on” another part, but also cases where another part is in between. . Conversely, when we say that a part is "just above" another part, we mean that there is no other part in the middle. In addition, to be "on" or "on" the reference part is located above or below the reference part, and does not necessarily mean to be located "on" or "on" the opposite direction of gravity. .

In addition, throughout the specification, when a part "includes" a certain component, this means that other components may be further included, rather than excluding other components, unless otherwise stated.

In addition, throughout the specification, when referring to "planar", it means when the target part is viewed from above, and "cross-sectional" means when viewed from the side when a cross-section of the target part is vertically cut.

First, a display device according to an exemplary embodiment will be briefly described with reference to FIG. 1 . 1 is a cross-sectional view of a display device according to an exemplary embodiment.

Referring to FIG. 1 , the display device 10 according to the embodiment includes a display unit 1000 , a touch unit 2000 , and an anti-reflection unit 3000 . The touch unit 2000 may be positioned between the display unit 1000 and the anti-reflection unit 3000 . The display device 10 may include a display area DA and a non-display area PA.

The display unit 1000 includes a substrate 110 , and a buffer layer 111 may be positioned on the substrate 110 .

The substrate 110 is polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, polyetherimide, polyethylene Naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetate cellulose , and may include at least one of cellulose acetate propionate. The substrate 110 may be a rigid substrate or a flexible substrate capable of bending, folding, rolling, or the like. The substrate 110 may be a single layer or a multilayer. The substrate 110 may be alternately stacked with at least one base layer and at least one inorganic layer including the sequentially stacked polymer resin.

The buffer layer 111 is positioned between the substrate 110 and the second semiconductor 130 to block impurities from the substrate 110 during the crystallization process for forming polysilicon, thereby improving the characteristics of the polysilicon, and improving the properties of the substrate 110 . Stress of the second semiconductor 130 formed on the buffer layer 111 may be relieved by planarizing the .

The buffer layer 111 may include an inorganic insulating material such as silicon oxide (SiO _x ), silicon nitride (SiN _x ), and silicon nitroxide (SiO _x N _y ). The buffer layer 111 may include amorphous silicon (a-Si).

Although not shown, a barrier layer may be further positioned between the substrate 110 and the buffer layer 111 . The barrier layer may have a single-layer or multi-layer structure. The barrier layer may include an inorganic insulating material such as silicon oxide, silicon nitride, and silicon nitride oxide.

The second semiconductor 130 may be positioned on the buffer layer 111 . The second semiconductor 130 may include a polycrystalline silicon material. That is, the second semiconductor 130 may be formed of a polycrystalline semiconductor. The second semiconductor 130 may include a source region 131 , a channel region 132 , and a drain region 133 .

The source region 131 of the second semiconductor 130 may be connected to the second source electrode SE2 , and the drain region 133 of the second semiconductor 130 may be connected to the second drain electrode DE2 .

A first gate insulating layer 141 may be positioned on the second semiconductor 130 . The first gate insulating layer 141 may have a single-layer or multi-layer structure including silicon nitride, silicon oxide, silicon nitroxide, and the like.

A second gate lower electrode GE2_L may be positioned on the first gate insulating layer 141 . The second gate lower electrode GE2_L may include molybdenum (Mo), aluminum (Al), copper (Cu), and/or titanium (Ti), and may have a single-layer or multi-layer structure including the same.

A second gate insulating layer 142 may be positioned on the second gate lower electrode GE2_L. The second gate insulating layer 142 may include silicon nitride, silicon oxide, silicon nitroxide, or the like. The second gate insulating layer 142 may have a single-layer or multi-layer structure including silicon nitride, silicon oxide, or silicon nitroxide.

A second gate upper electrode GE2_U may be positioned on the second gate insulating layer 142 . The second gate lower electrode GE2_L and the second gate upper electrode GE2_U may overlap with the second gate insulating layer 142 interposed therebetween. The second gate upper electrode GE2_U and the second gate lower electrode GE2_L constitute the second gate electrode GE2. The second gate electrode GE2 may overlap the channel region 132 of the second semiconductor 130 in a direction perpendicular to the substrate 110 .

The second gate upper electrode GE2_U and the gate line GL are made of molybdenum (Mo), aluminum (Al), copper (Cu) silver (Ag), chromium (Cr), tantalum (Ta), titanium (Ti), etc. It may include, and may have a single-layer or multi-layer structure including the same.

Although not shown, a metal blocking layer BML made of the same layer as the second gate upper electrode GE2_U and the gate line GL may be positioned on the second gate insulating layer 142 , and the metal blocking layer BML is It may overlap with the oxide transistor To, which will be described later.

The second semiconductor 130 , the second gate electrode GE2 , the second source electrode SE2 , and the second drain electrode DE2 constitute the polycrystalline transistor Tp. The polycrystalline transistor Tp may be a driving transistor connected to the light emitting diode LED, and may include a transistor including a polycrystalline semiconductor.

A first interlayer insulating layer 161 may be positioned on the second gate electrode GE2 . The first interlayer insulating layer 161 may include silicon nitride, silicon oxide, silicon nitroxide, or the like. The first interlayer insulating layer 161 may be formed of a multilayer in which a layer including silicon oxide and a layer including silicon nitride are stacked. In this case, the layer including silicon nitride in the first interlayer insulating layer 161 may be located closer to the substrate 110 than the layer including silicon oxide.

A first semiconductor 135 may be positioned on the first interlayer insulating layer 161 . The first semiconductor 135 may overlap the metal blocking layer BML.

The first semiconductor 135 may include an oxide semiconductor. For example, the first semiconductor 135 may include Indium-Gallium-Zinc Oxide (IGZO).

The first semiconductor 135 may include a channel region 137 and a source region 136 and a drain region 138 positioned on both sides of the channel region 137 . The source region 136 of the first semiconductor 135 may be connected to the first source electrode SE1 , and the drain region 138 of the first semiconductor 135 may be connected to the first drain electrode DE1 .

A third gate insulating layer 143 may be positioned on the first semiconductor 135 . The third gate insulating layer 143 may include silicon nitride, silicon oxide, silicon nitroxide, or the like.

In the illustrated embodiment, the third gate insulating layer 143 may be positioned on the entire surface of the first semiconductor 135 and the first interlayer insulating layer 161 . Accordingly, the third gate insulating layer 143 covers top surfaces and side surfaces of the source region 136 , the channel region 137 , and the drain region 138 of the first semiconductor 135 .

In the process of realizing the high resolution, the size of each pixel is reduced, and accordingly, the length of the channel of the semiconductor is reduced. In this case, if the third gate insulating layer 143 does not cover the upper surfaces of the source region 136 and the drain region 138 , a part of the material of the first semiconductor 135 moves to the side surface of the third gate insulating layer 143 . may be In the present embodiment, since the third gate insulating layer 143 is positioned on the entire surface of the first semiconductor 135 and the first interlayer insulating layer 161 , the first semiconductor 135 and the first gate electrode are caused by diffusion of metal particles. A short circuit in (GE1) can be prevented.

However, embodiments are not limited thereto, and the third gate insulating layer 143 may not be positioned on the entire surface of the first semiconductor 135 and the first interlayer insulating layer 161 . For example, the third gate insulating layer 143 may be positioned only between the first gate electrode GE1 and the first semiconductor 135 . That is, the third gate insulating layer 143 may overlap the channel region 137 of the first semiconductor 135 and may not overlap the source region 136 and the drain region 138 .

A first gate electrode GE1 may be positioned on the third gate insulating layer 143 .

The first gate electrode GE1 may overlap the channel region 137 of the first semiconductor 135 in a direction perpendicular to the substrate 110 . The first gate electrode GE1 may include molybdenum (Mo), aluminum (Al), copper (Cu), and/or titanium (Ti), and may have a single-layer or multi-layer structure including the same. For example, the first gate electrode GE1 may include a lower layer including titanium and an upper layer including molybdenum. In the lower layer including titanium, fluorine (F), an etching gas, is diffused during dry etching of the upper layer. can be prevented from becoming

The first semiconductor 135 , the first gate electrode GE1 , the first source electrode SE1 , and the first drain electrode DE1 constitute the oxide transistor To. The oxide transistor To may be a switching transistor for switching the polycrystalline transistor Tp, and may include a transistor including an oxide semiconductor.

A second interlayer insulating layer 162 may be positioned on the first gate electrode GE1 . The second interlayer insulating layer 162 may include silicon nitride, silicon oxide, silicon nitroxide, or the like. The second interlayer insulating layer 162 may be formed of a multilayer in which a layer including silicon nitride and a layer including silicon oxide are stacked.

A first source electrode SE1 and a first drain electrode DE1 , and a second source electrode SE2 and a second drain electrode DE2 may be positioned on the second interlayer insulating layer 162 . The first source electrode SE1 , the first drain electrode DE1 , the second source electrode SE2 , and the second drain electrode DE2 may include molybdenum (Mo), chromium (Cr), tantalum (Ta), and aluminum. (Al), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), calcium (Ca), titanium (Ti), tungsten (W) and/or copper (Cu), etc. and may have a single-layer or multi-layer structure including the same. For example, the first source electrode SE1 , the first drain electrode DE1 , the second source electrode SE2 , and the second drain electrode DE2 may be formed of a refractory metal such as molybdenum, chromium, tantalum, and titanium. Or it may have a triple film structure of a lower film including an alloy thereof, an intermediate film including an aluminum-based metal having low specific resistance, a silver-based metal, and a copper-based metal, and an upper film including a refractory metal such as molybdenum, chromium, tantalum and titanium. .

The first source electrode SE1 may be connected to the source region 136 of the first semiconductor 135 , and the first drain electrode DE1 may be connected to the drain region 138 of the first semiconductor 135 .

The second source electrode SE2 may be connected to the source region 131 of the second semiconductor 130 , and the second drain electrode DE2 may be connected to the drain region 133 of the second semiconductor 130 .

A third interlayer insulating layer 163 may be positioned on the first source electrode SE1 , the first drain electrode DE1 , the second source electrode SE2 , and the second drain electrode DE2 . The third interlayer insulating layer 163 may be an organic layer. For example, the third interlayer insulating film 163 may be a general general-purpose polymer such as polymethylmethacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenol-based group, an acrylic polymer, an imide-based polymer, a polyimide, an acrylic polymer, or a siloxane-based polymer. It may include an organic insulating material such as a polymer.

A connection electrode CE, a data line 171 , and a driving voltage line 172 may be positioned on the third interlayer insulating layer 163 . The connection electrode CE and the data line DL are formed of aluminum (Al), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), chromium (Cr), calcium (Ca), and molybdenum. It may include (Mo), titanium (Ti), tungsten (W), and/or copper (Cu), and may have a single-layer or multi-layer structure including the same.

The connection electrode CE is connected to the second drain electrode DE2 .

A passivation layer 180 may be positioned on the third interlayer insulating layer 163 , the connection electrode CE, and the data line DL. The passivation layer 180 may serve to planarize and eliminate a step difference in order to increase the luminous efficiency of a light emitting device to be formed thereon. The protective film 180 is made of an organic insulating material such as a general general-purpose polymer such as polymethylmethacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer, an imide-based polymer, a polyimide, an acrylic polymer, or a siloxane-based polymer. may include

A pixel electrode 191 may be positioned on the passivation layer 180 . The pixel electrode 191 may be connected to the second drain electrode DE2 through a contact hole of the passivation layer 180 .

The pixel electrode 191 may be provided individually for each pixel PX. The pixel electrode 191 may include a metal such as silver (Ag), lithium (Li), calcium (Ca), aluminum (Al), magnesium (Mg), or gold (Au), indium tin oxide (ITO), It may include a transparent conductive oxide (TCO) such as indium zinc oxide (IZO). The pixel electrode 191 may be formed of a single layer including a metal material or a transparent conductive oxide or a multi-layer including the same. For example, the pixel electrode 191 may have a triple layer structure of indium tin oxide (ITO)/silver (Ag)/indium tin oxide (ITO).

A pixel defining layer 360 may be positioned on the pixel electrode 191 . The pixel defining layer 360 is a general-purpose polymer such as polymethylmethacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenol-based group, an acrylic polymer, an imide-based polymer, a polyimide, an acrylic polymer, or an organic insulating material such as a siloxane-based polymer. material may be included. The pixel defining layer 360 may include black dye and may not transmit light.

A pixel opening 365 is formed in the pixel defining layer 360 , and the pixel opening 365 of the pixel defining layer 360 may overlap the pixel electrode 191 . A light emitting device layer 370 may be positioned in the pixel opening 365 of the pixel defining layer 360 .

The light emitting device layer 370 may include a material layer that uniquely emits light of primary colors such as red, green, and blue. The light emitting device layer 370 may have a structure in which a plurality of material layers emitting light of different colors are stacked.

A common electrode 270 may be positioned on the light emitting device layer 370 and the pixel defining layer 360 . The common electrode 270 may be provided in common to all the pixels PX, and the common voltage ELVSS may be applied through the common voltage transfer unit 27 of the non-display area PA.

The common electrode 270 includes calcium (Ca), barium (Ba), magnesium (Mg), aluminum (Al), silver (Ag), platinum (Pt), palladium (Pd), gold (Au), and nickel (Ni). , reflective metals containing neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), etc. or transparent conductive oxides such as indium tin oxide (ITO) and indium zinc oxide (IZO) ( TCO) may be included.

The pixel electrode 191 , the light emitting device layer 370 , and the common electrode 270 form a light emitting diode (LED). Here, the pixel electrode 191 may be an anode that is a hole injection electrode, and the common electrode 270 may be a cathode that is an electron injection electrode. However, the embodiment is not necessarily limited thereto, and the pixel electrode 191 may be a cathode and the common electrode 270 may be an anode depending on a driving method of the organic light emitting diode display.

When holes and electrons are injected into the light emitting device layer 370 from the pixel electrode 191 and the common electrode 270, respectively, and excitons in which the injected holes and electrons are combined fall from the excited state to the ground state, light emission is emitted. is done

The oxide transistor To, which is a part of the switching transistor of the display device according to the embodiment, may include an oxide semiconductor, and the polycrystalline transistor Tp, which is the driving transistor, may include a polycrystalline semiconductor. By raising the existing frequency of about 60Hz to about 120Hz for high-speed operation, the motion of a video can be expressed more naturally, but power consumption increases. In order to compensate for the increased power consumption, the frequency when driving a still image may be lowered. For example, when driving a still image, it may be driven at about 1 Hz. When the frequency is lowered in this way, leakage current may occur. In the display device according to an exemplary embodiment, the oxide transistor To, which is a switching transistor, includes an oxide semiconductor, thereby minimizing leakage current. In addition, since the polycrystalline transistor Tp, which is the driving transistor, includes the polycrystalline semiconductor, high electron mobility may be achieved. That is, the switching transistor and the driving transistor may be driven more stably and have high reliability by including different semiconductor materials.

An encapsulation layer 390 is positioned on the common electrode 270 . The encapsulation layer 390 may cover not only the upper surface of the display unit 1000 but also the side surfaces of the display unit 1000 to seal the display unit 1000 . The encapsulation layer 390 may be positioned on the front surface of the display area DA, extend from the display area DA, and the end of the encapsulation layer 390 may be positioned in the non-display area PA.

Since the organic light emitting diode is very vulnerable to moisture and oxygen, the encapsulation layer 390 seals the display unit 1000 to block the inflow of external moisture and oxygen. The encapsulation layer 390 may include a plurality of layers, and among them, may be formed as a composite film including both an inorganic film and an organic film. For example, the encapsulation layer 390 may be formed of a triple layer in which the first inorganic layer 390a, the organic layer 390b, and the second inorganic layer 390c are sequentially formed.

The touch unit 2000 is positioned on the encapsulation layer 390 .

The touch unit 2000 will be briefly described. A first insulating layer 410 is positioned on the encapsulation layer 390 . The first insulating layer 410 may be formed of an inorganic layer or an organic layer such as metal oxide, metal oxynitride, silicon oxide, silicon nitride, and silicon oxynitride. The first insulating layer 410 may cover the encapsulation layer 390 to protect the encapsulation layer 390 and prevent moisture permeation. Also, the first insulating layer 410 may serve to reduce parasitic capacitance between the common electrode 270 and the touch electrode.

The first touch cell connection part 452 is positioned on the first insulating layer 410 , and the second insulating layer 420 is positioned on the first touch cell connection part 452 . The second insulating layer 420 may be formed of an inorganic layer or an organic layer such as metal oxide, metal oxynitride, silicon oxide, silicon nitride, and silicon oxynitride.

A first touch cell 451 is positioned on the second insulating layer 420 . In addition, although not shown, the second touch cell and the second touch cell connection part may also be positioned on the second insulating layer 420 . In this case, one of the first touch cell 451 and the second touch cell may be a sensing input electrode, and the other may be a sensing output electrode. The first touch cell 451 and the second touch cell may be electrically separated from each other, and may be distributed so as not to overlap each other and disposed in a mesh shape. The first touch cells 451 may be connected to each other by a first touch cell connection part 452 , and the second touch cells may be connected to each other by a second touch cell connection part.

A touch cell passivation layer 430 may be positioned on the first touch cell 451 and the second touch cell (not shown). The touch cell passivation layer 430 protects the first touch cell 451 and the second touch cell (not shown) by covering the first touch cell 451 and the second touch cell (not shown) from being exposed to the outside. can do. The touch cell passivation layer 430 may include an inorganic material such as silicon nitride (SiN _x ) or silicon oxide (SiO ₂ ) or an organic material such as polyacrylates resin and polyimides resin.

The anti-reflection unit 3000 is positioned on the touch unit 2000 .

The anti-reflection unit 3000 includes a light blocking layer 520 and color filters 530A, 530B, and 530C.

The light blocking layer 520 may overlap the pixel defining layer 360 of the display unit 1000 and may be narrower than the pixel defining layer 360 . The light blocking layer 520 may be positioned throughout the non-display area PA.

The light blocking layer 520 has a plurality of openings 521 overlapping the pixel openings 365 of the pixel defining layer 360 , and each opening 521 overlaps the pixel openings 365 . The width of the opening 521 of the light blocking layer 520 may be wider than the width of the pixel opening 365 overlapping each other.

The color filters 530A, 530B, and 530C are positioned on the light blocking layer 520 . Most of the color filters 530A, 530B, and 530C are located in the opening 521 of the light blocking layer 520 . A planarization layer 540 may be positioned on the plurality of color filters 530A, 530B, and 530C.

The anti-reflection unit 3000 prevents external light incident from the outside from being visually recognized by being reflected by a wiring or the like. The light blocking layer 520 of the anti-reflection unit 3000 is positioned to overlap the edges of the light emitting areas of the non-display area PA and the display area DA, and absorbs incident external light to reduce the amount of light incident on the light emitting area. Accordingly, it is possible to reduce the degree to which external light is reflected and visually recognized.

The color filters 530A, 530B, and 530C of the anti-reflection unit 3000 reduce external light incident from the outside is reflected and viewed after being incident on the pixel defining layer 360 . Since the color filters 530A, 530B, and 530C do not completely block light, it is possible to prevent the reflected light of external light from being recognized without reducing the efficiency of the light emitted from the light emitting device layer 370 .

In general, a polarization layer may be used in order to prevent recognition of reflected light of external light, but this lowers the efficiency of light emitted from the light emitting device layer. However, according to the embodiment, it is possible to prevent the reflection of external light from being viewed without reducing the efficiency of the light emitted from the light emitting device layer 370 through the antireflection unit 3000 .

Next, with reference to FIGS. 2 and 3 , the data line 171 , the driving voltage line 172 of the display unit 1000 , and the third interlayer insulating layer 163 positioned thereunder will be further described.

FIG. 2 is a layout view illustrating a portion of a display device according to an exemplary embodiment, and FIG. 3 is a cross-sectional view of the display device according to an exemplary embodiment taken along line III-III of FIG. 2 . 2 and 3 illustrate some layers of the display device according to the exemplary embodiment of FIG. 1 , and the remaining partial layers are omitted. In FIG. 3 , the third interlayer insulating layer 163 is positioned on the substrate 110 , and the buffer layer 111 and the first gate insulating layer 141 positioned between the substrate 110 and the third interlayer insulating layer 163 are shown. ), the second gate insulating layer 142 , the first interlayer insulating layer 161 , the third gate insulating layer 143 , and the second interlayer insulating layer 162 are omitted.

2 and 3 , in the display device according to an exemplary embodiment, a plurality of first pixels PXA, a plurality of second pixels PXB, and a plurality of third pixels PXC display different colors. ) may be included.

In one row of the display device, the first pixel PXA and the third pixel PXC may be positioned to be spaced apart from each other by a predetermined distance, and the second pixel PXB may be positioned to be spaced apart from each other by a predetermined distance in the other adjacent row. . A row in which the first pixel PXA and the third pixel PXC are alternately arranged and a row in which the second pixel PXB is repeatedly arranged may be alternately repeated. Such a pixel arrangement structure is called a PenTile matrix, and by sharing adjacent pixels to express colors, high resolution can be realized with a small number of pixels.

For example, the first pixel PXA may be a blue pixel displaying blue, the second pixel PXB may be a green pixel displaying green, and the third pixel PXC may be a red pixel displaying red. can be However, this is only an example, and the color displayed by each pixel may be variously changed.

A pixel electrode 191 , a light emitting device layer 370 , and a common electrode 270 are stacked in each pixel, which may form a light emitting diode (LED). In the display device according to an exemplary embodiment, most external light incident from the outside may be blocked by the anti-reflection unit 3000 . Such external light is reflected by the pixel electrode 191 and the like, and when the pixel electrode 191 has a flat shape, the reflectance of external light may be lowered to further lower the reflection blocking ratio of external light.

The display device according to an embodiment may include a third interlayer insulating layer 163 , a data line 171 , a driving voltage line 172 , and a passivation layer 180 positioned between the substrate 110 and the pixel electrode 191 . there is. The data line 171 and the driving voltage line 172 may be positioned between the third interlayer insulating layer 163 and the passivation layer 180 . The passivation layer 180 may be positioned on the data line 171 and the driving voltage line 172 , and the pixel electrode 191 may be positioned on the passivation layer 180 . The pixel electrode 191 may overlap at least a portion of the data line 171 and the driving voltage line 172 . For example, in the first pixel PXA and the third pixel PXC, the pixel electrode 191 may overlap the driving voltage line 172 , and in the second pixel PXB, the pixel electrode 191 is a data line It can overlap with (171). Although the pixel electrode 191 is illustrated as overlapping a wide portion of the driving voltage line 172 in the first pixel PXA and the third pixel PXC, the position of the pixel electrode 191 may be variously changed. . For example, about half the area of the pixel electrode 191 may overlap the driving voltage line 172 . A step may be generated by the data line 171 and the driving voltage line 172 that are positioned under the pixel electrode 191 and overlap the pixel electrode 191 . When the upper surface of the passivation layer 180 is flattened by reducing the step difference, the pixel electrode 191 may have a flat shape. Hereinafter, the relationship between the third interlayer insulating layer 163 , the data line 171 , and the driving voltage line 172 to make the top surface of the passivation layer 180 flat will be described.

The third interlayer insulating layer 163 may include a first groove 163g1 and a second groove 163g2 . The third interlayer insulating layer 163 includes a third portion positioned in the first portion 163a in which the first groove 163g1 is formed, the second portion 163b in which the second groove 163g2 is formed, and the remaining region. It may include a portion 163c. A thickness THa of the first portion 163a of the third interlayer insulating layer 163 may be thinner than a thickness THc of the third portion 163c. A thickness THb of the second portion 163b of the third interlayer insulating layer 163 may be thinner than a thickness THc of the third portion 163c. The thickness THa of the first portion 163a of the third interlayer insulating layer 163 may be substantially the same as the thickness THb of the second portion 163b of the third interlayer insulating layer 163 .

A driving voltage line 172 may be positioned on the third interlayer insulating layer 163 . The driving voltage line 172 may be positioned in the first groove 163g1 of the third interlayer insulating layer 163 . Accordingly, the driving voltage line 172 may overlap the first portion 163a of the third interlayer insulating layer 163 . A depth Dg1 of the first groove 163g1 of the third interlayer insulating layer 163 may correspond to a thickness THe of the driving voltage line 172 . For example, the depth Dg1 of the first groove 163g1 of the third interlayer insulating layer 163 may be substantially equal to the thickness THe of the driving voltage line 172 . The sum of the thickness THe of the driving voltage line 172 and the thickness THa of the first portion 163a of the third interlayer insulating layer 163 is the thickness of the third portion 163c of the third interlayer insulating layer 163 ( THc). Accordingly, the top surface of the third portion 163c of the third interlayer insulating layer 163 may coincide with the top surface of the driving voltage line 172 . That is, the upper surface of the third portion 163c of the third interlayer insulating layer 163 and the upper surface of the driving voltage line 172 may be formed to be flat. Accordingly, an upper surface of the passivation layer 180 positioned on the third interlayer insulating layer 163 and the driving voltage line 172 may be formed to be flat. The width Wg1 of the first groove 163g1 of the third interlayer insulating layer 163 may be greater than the width We of the driving voltage line 172 . However, the present invention is not limited thereto, and the width Wg1 of the first groove 163g1 of the third interlayer insulating layer 163 may be substantially the same as the width We of the driving voltage line 172 .

A data line 171 may be positioned on the third interlayer insulating layer 163 . The data line 171 may be positioned in the second groove 163g2 of the third interlayer insulating layer 163 . Accordingly, the data line 171 may overlap the second portion 163b of the third interlayer insulating layer 163 . A depth Dg2 of the second groove 163g2 of the third interlayer insulating layer 163 may correspond to a thickness THd of the data line 171 . For example, the depth Dg2 of the second groove 163g2 of the third interlayer insulating layer 163 may be substantially equal to the thickness THd of the data line 171 . The sum of the thickness THd of the data line 171 and the thickness THb of the second portion 163b of the third interlayer insulating layer 163 is the thickness of the third portion 163c of the third interlayer insulating layer 163 ( THc). Accordingly, the upper surface of the third portion 163c of the third interlayer insulating layer 163 may coincide with the upper surface of the data line 171 . That is, the upper surface of the third portion 163c of the third interlayer insulating layer 163 and the upper surface of the data line 171 may be formed to be flat. Accordingly, the third interlayer insulating layer 163 and the upper surface of the passivation layer 180 positioned on the data line 171 may be formed to be flat. The width Wg2 of the second groove 163g2 of the third interlayer insulating layer 163 may be greater than the width Wd of the data line 171 . However, the present invention is not limited thereto, and the width Wg2 of the second groove 163g2 of the third interlayer insulating layer 163 may be substantially the same as the width Wd of the data line 171 . Two data lines 171 may be positioned in the second groove 163g2 of the third interlayer insulating layer 163 . In this case, the width Wg2 of the second groove 163g2 of the third interlayer insulating layer 163 may be at least twice the width Wd of the data line 171 .

As such, the driving voltage line 172 is positioned in the first groove 163g1 of the third interlayer insulating layer 163 and the data line 171 is positioned in the second groove 163g2 of the third interlayer insulating layer 163 , so that the passivation layer The upper surface of 180 may be made flat. That is, it is possible to prevent a step difference due to the driving voltage line 172 and the data line 171 . A pixel electrode 191 is positioned on the passivation layer 180 , and an upper surface of the pixel electrode 191 may be formed to be flat. When light incident from the outside is reflected by the pixel electrode 191 in which the step is formed, color bleeding may occur. In the display device according to the exemplary embodiment, the pixel electrode 191 has a flat top surface, thereby reducing the reflectance of external light and preventing such color bleeding.

In this case, when the passivation layer 180 positioned under the pixel electrode 191 has a large thickness, the step along the signal lines such as the data line 171 and the driving voltage line 172 positioned under the passivation layer 180 is a pixel Although it may not affect the electrode 191 , the internal gas generated in the baking process for forming the passivation layer 180 and the insulating layers positioned thereunder may not be discharged to the outside, and thereby, the light emitting device layer This deterioration or the discoloration of the electrode layer of the organic device may deteriorate the light emitting characteristic of the light emitting device layer.

In addition, when the passivation layer 180 is formed to be thin in order to discharge internal gas that may be generated in the process of forming the insulating layer including the organic material, the data line 171 positioned below the passivation layer 180 . and a step difference according to a signal line such as the driving voltage line 172 may also cause a step difference on the surface of the pixel electrode 191 .

In the display device according to the exemplary embodiment, the driving voltage line is formed by forming the grooves 163g1 and 163g2 in the third interlayer insulating layer 163 and locating the driving voltage line 172 and the data line 171 in the grooves 163g1 and 163g2. It is possible to prevent a step difference due to the 172 and the data line 171 . Accordingly, while the passivation layer 180 is thinly formed, the upper surface of the passivation layer 180 may be flat. For example, in order to form the passivation layer 180 flat in a structure in which the grooves 163g1 and 163g2 are not formed in the third interlayer insulating layer 163 , the thickness of the passivation layer 180 may be about 3.1 μm. In the display device according to an exemplary embodiment, the thickness of the passivation layer 180 may be reduced to about 2.4 μm while being formed flat. Due to this, internal gas that may be generated in the process of forming the insulating layer including the organic material may be smoothly discharged.

Although it has been described above that the third interlayer insulating layer 163 includes the first groove 163g1 and the second groove 163g2, the present invention is not limited thereto, and various modifications are possible. For example, the third interlayer insulating layer 163 may include the first groove 163g1 and may not include the second groove 163g2 . Also, the third interlayer insulating layer 163 may include the second groove 163g2 and may not include the first groove 163g1 .

Next, any one pixel of the display unit 1000 of the display device according to an exemplary embodiment will be further described with reference to FIGS. 4 to 13 .

4 is a circuit diagram of a display device according to an embodiment; It is a cross section. 7 to 13 are plan views sequentially illustrating a manufacturing sequence of a display device according to an exemplary embodiment.

First, a circuit diagram of one pixel of the display unit 1000 of a display device according to an exemplary embodiment will be described with reference to FIG. 4 .

As shown in FIG. 4 , one pixel PX of the display device according to an exemplary embodiment is connected to several wirings 127 , 128 , 151 , 152 , 153 , 154 , 155 , 171 , 172 , and 741 . a plurality of transistors T1, T2, T3, T4, T5, T6, T7, a holding capacitor Cst, a boost capacitor Cbt, and a light emitting diode (LED).

A plurality of wires 127 , 128 , 151 , 152 , 153 , 154 , 155 , 171 , 172 , and 741 are connected to one pixel PX. The plurality of wirings includes a first initialization voltage line 127 , a second initialization voltage line 128 , a first scan line 151 , a second scan line 152 , an initialization control line 153 , and a bypass control line 154 . , a light emission control line 155 , a data line 171 , a driving voltage line 172 , and a common voltage line 741 .

The first scan line 151 is connected to a gate driver (not shown) to transmit the first scan signal GW to the second transistor T2 . A voltage having a polarity opposite to that of the voltage applied to the first scan line 151 may be applied to the second scan line 152 at the same timing as the signal of the first scan line 151 . For example, when a negative voltage is applied to the first scan line 151 , a positive voltage may be applied to the second scan line 152 . The second scan line 152 transfers the second scan signal GC to the third transistor T3 .

The initialization control line 153 transfers the initialization control signal GI to the fourth transistor T4 . The bypass control line 154 transfers the bypass signal GB to the seventh transistor T7 . The bypass control line 154 may be formed of the first scan line 151 of the previous stage. The emission control line 155 transfers the emission control signal EM to the fifth transistor T5 and the sixth transistor T6 .

The data line 171 is a wire that transmits the data voltage DATA generated by the data driver (not shown), and the luminance of the light emitting diode LED according to the data voltage DATA applied to the pixel PX is increased. change

The driving voltage line 172 applies the driving voltage ELVDD. The first initialization voltage line 127 transmits the first initialization voltage VINT, and the second initialization voltage line 128 transmits the second initialization voltage AINT. The common voltage line 741 applies the common voltage ELVSS to the cathode electrode of the light emitting diode LED. In the present embodiment, voltages applied to the driving voltage line 172 , the first and second initialization voltage lines 127 and 128 , and the common voltage line 741 may each be a constant voltage.

The plurality of transistors include a driving transistor T1 , a second transistor T2 , a third transistor T3 , a fourth transistor T4 , a fifth transistor T5 , a sixth transistor T6 , and a seventh transistor T7 . ) may be included. The plurality of transistors may include an oxide transistor including an oxide semiconductor and a polycrystalline transistor including a polycrystalline semiconductor. For example, the third transistor T3 and the fourth transistor T4 may be formed of an oxide transistor, and the driving transistor T1 , the second transistor T2 , the fifth transistor T5 , and the sixth transistor T6 . ) and the seventh transistor T7 may be formed of a polycrystalline transistor. However, the present invention is not limited thereto, and all of the plurality of transistors may be formed of polycrystalline transistors.

Although it has been described above that one pixel PX includes seven transistors T1 to T7, one storage capacitor Cst, and one boost capacitor Cbt, the present invention is not limited thereto, and the number of transistors and capacitors is not limited thereto. The number of , and their connection relationship may be variously changed.

Next, an interlayer structure of one pixel of the display unit 1000 of a display device according to an exemplary embodiment will be described in more detail with reference to FIGS. 5 to 13 .

A buffer layer 111 is positioned on the substrate 110 , and a polycrystalline semiconductor layer including a channel 1132 , a first region 1131 , and a second region 1133 of the driving transistor T1 is positioned on the buffer layer 111 . can 7 shows a polycrystalline semiconductor layer. The polycrystalline semiconductor layer forms the channel, the first region, and the second region of each of the driving transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7, respectively. may include more.

The channel 1132 of the driving transistor T1 may have a curved shape on a plane. However, the shape of the channel 1132 of the driving transistor T1 is not limited thereto, and may be variously changed. For example, the channel 1132 of the driving transistor T1 may be bent in another shape or may be formed in a bar shape. A first region 1131 and a second region 1133 of the driving transistor T1 may be positioned on both sides of the channel 1132 of the driving transistor T1 . The first region 1131 of the driving transistor T1 may extend upward and downward on a plane, a downwardly extending portion may be connected to the second region of the second transistor T2 , and an upwardly extending portion may be a fifth transistor It may be connected to the second region of (T5). The second region 1133 of the driving transistor T1 may extend upward on a plane to be connected to the first region of the sixth transistor T6 .

A first gate insulating layer 141 may be positioned on the polycrystalline semiconductor layer including the channel 1132 , the first region 1131 , and the second region 1133 of the driving transistor T1 .

A first gate conductor including the gate electrode 1151 of the driving transistor T1 may be positioned on the first gate insulating layer 141 . 8 shows the polycrystalline semiconductor layer and the first gate conductor together. The first gate conductor may further include gate electrodes of each of the second transistor T2 , the fifth transistor T5 , the sixth transistor T6 , and the seventh transistor T7 as well as the driving transistor T1 . .

The gate electrode 1151 of the driving transistor T1 may overlap the channel 1132 of the driving transistor T1 . The channel 1132 of the driving transistor T1 is covered by the gate electrode 1151 of the driving transistor T1 .

The first gate conductor may further include a first scan line 151 and a light emission control line 155 . The first scan line 151 and the emission control line 155 may extend in a substantially horizontal direction. The first scan line 151 may be formed integrally with the gate electrode of the second transistor T2 . The bypass control line connected to the seventh transistor T7 may be formed of the first scan line 151 of the previous stage. The gate electrode of the fifth transistor T5 and the gate electrode of the sixth transistor T6 may be formed integrally with the emission control line 155 .

After the first gate conductor including the gate electrode 1151 of the driving transistor T1 is formed, a doping process may be performed. The polycrystalline semiconductor layer covered by the first gate conductor may be undoped, and a portion of the polycrystalline semiconductor layer not covered by the first gate conductor may be doped to have the same characteristics as the conductor. In this case, the doping process may be performed with a p-type dopant, and the driving transistor T1, the second transistor T2, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 including a polycrystalline semiconductor layer. ) may have a p-type transistor characteristic.

A second gate insulating layer 142 may be positioned on the first gate conductor including the gate electrode 1151 of the driving transistor T1 and the first gate insulating layer 141 .

The first storage electrode 1153 of the storage capacitor Cst, the lower gate electrode 3155 of the third transistor T3, and the lower gate electrode 4155 of the fourth transistor T4 are formed on the second gate insulating layer 142 . The included second gate conductor may be positioned. 9 shows a polycrystalline semiconductor together with a first gate conductor and a second gate conductor.

The first storage electrode 1153 overlaps the gate electrode 1151 of the driving transistor T1 to form the storage capacitor Cst. An opening 1152 is formed in the first storage electrode 1153 of the storage capacitor Cst. The opening 1152 of the first storage electrode 1153 of the storage capacitor Cst may overlap the gate electrode 1151 of the driving transistor T1 . The lower gate electrode 3155 of the third transistor T3 may overlap the channel 3137 and the upper gate electrode 3151 of the third transistor T3 . The lower gate electrode 4155 of the fourth transistor T4 may overlap the channel 4137 and the upper gate electrode 4151 of the fourth transistor T4 .

The second gate conductor may further include a lower second scan line 152a , a lower initialization control line 153a , and a first initialization voltage line 127 . The lower second scan line 152a, the lower initialization control line 153a, and the first initialization voltage line 127 may extend in a substantially horizontal direction. The lower second scan line 152a may be formed integrally with the lower gate electrode 3155 of the third transistor T3 . The lower initialization control line 153a may be formed integrally with the lower gate electrode 4155 of the fourth transistor T4 .

On the second gate conductor including the first storage electrode 1153 of the storage capacitor Cst, the lower gate electrode 3155 of the third transistor T3, and the lower gate electrode 4155 of the fourth transistor T4, A first interlayer insulating layer 161 may be positioned.

On the first interlayer insulating layer 161 , the channel 3137 of the third transistor T3 , the first region 3136 and the second region 3138 , and the channel 4137 of the fourth transistor T4 , the first region ( An oxide semiconductor layer including 4136 and a second region 4138 may be positioned. 10 shows a polycrystalline semiconductor layer, a first gate conductor, a second gate conductor, and an oxide semiconductor layer together.

The channel 3137 , the first region 3136 and the second region 3138 of the third transistor T3 , and the channel 4137 , the first region 4136 , and the second region 4138 of the fourth transistor T4 ) may be connected to each other and formed integrally. A first region 3136 and a second region 3138 of the third transistor T3 may be positioned on both sides of the channel 3137 of the third transistor T3 . A first region 4136 and a second region 4138 of the fourth transistor T4 may be positioned on both sides of the channel 4137 of the fourth transistor T4 . The second region 3138 of the third transistor T3 may be connected to the second region 4138 of the fourth transistor T4 . The channel 3137 of the third transistor T3 may overlap the lower gate electrode 3155 . The channel 4137 of the fourth transistor T4 may overlap the lower gate electrode 4155 .

The channel 3137 , the first region 3136 and the second region 3138 of the third transistor T3 , and the channel 4137 , the first region 4136 , and the second region 4138 of the fourth transistor T4 ), a third gate insulating layer 143 may be positioned on the oxide semiconductor layer. The third gate insulating layer 143 may be disposed over the oxide semiconductor layer and the first interlayer insulating layer 161 . Accordingly, the third gate insulating layer 143 includes the channel 3137 of the third transistor T3 , the first region 3136 and the second region 3138 , and the channel 4137 of the fourth transistor T4 , the first Top surfaces and side surfaces of the region 4136 and the second region 4138 may be covered. However, the present exemplary embodiment is not limited thereto, and the third gate insulating layer 143 may not be positioned on the entire surface of the oxide semiconductor layer and the first interlayer insulating layer 161 . For example, the third gate insulating layer 143 may overlap the channel 3137 of the third transistor T3 and not overlap the first region 3136 and the second region 3138 . Also, the third gate insulating layer 143 may overlap the channel 4137 of the fourth transistor T4 and not overlap the first region 4136 and the second region 4138 .

A third gate conductor including an upper gate electrode 3151 of the third transistor T3 and an upper gate electrode 4151 of the fourth transistor T4 may be positioned on the third gate insulating layer 143 . 11 shows a polycrystalline semiconductor layer, a first gate conductor, a second gate conductor, an oxide semiconductor layer and a third gate conductor together.

The upper gate electrode 3151 of the third transistor T3 may overlap the channel 3137 of the third transistor T3 . The upper gate electrode 3151 of the third transistor T3 may overlap the lower gate electrode 3155 of the third transistor T3 .

The upper gate electrode 4151 of the fourth transistor T4 may overlap the channel 4137 of the fourth transistor T4 . The upper gate electrode 4151 of the fourth transistor T4 may overlap the lower gate electrode 4155 of the fourth transistor T4 .

The third gate conductor may further include an upper second scan line 152b and an upper initialization control line 153b.

The upper second scan line 152b and the upper initialization control line 153b may extend in a substantially horizontal direction. The upper second scan line 152b forms the second scan line 152 together with the lower second scan line 152a. The upper second scan line 152b may be formed integrally with the upper gate electrode 3151 of the third transistor T3 . The upper initialization control line 153b forms the initialization control line 153 together with the lower initialization control line 153a. The upper initialization control line 153b may be formed integrally with the upper gate electrode 4151 of the fourth transistor T4 .

A doping process may be performed after the third gate conductor including the upper gate electrode 3151 of the third transistor T3 and the upper gate electrode 4151 of the fourth transistor T4 is formed. A portion of the oxide semiconductor layer covered by the third gate conductor may be undoped, and a portion of the oxide semiconductor layer not covered by the third gate conductor may be doped to have the same characteristics as the conductor. The channel 3137 of the third transistor T3 may be positioned under the upper gate electrode 3151 to overlap the upper gate electrode 3151 . The first region 3136 and the second region 3138 of the third transistor T3 may not overlap the upper gate electrode 3151 . The channel 4137 of the fourth transistor T4 may be positioned under the upper gate electrode 4151 to overlap the upper gate electrode 4151 . The first region 4136 and the second region 4138 of the fourth transistor T4 may not overlap the upper gate electrode 4151 . The upper boost electrode 3138t may not overlap the third gate conductor. The doping process of the oxide semiconductor layer may be performed with an n-type dopant, and the third transistor T3 and the fourth transistor T4 including the oxide semiconductor layer may have n-type transistor characteristics.

A second interlayer insulating layer 162 may be positioned on the third gate conductor including the upper gate electrode 3151 of the third transistor T3 and the upper gate electrode 4151 of the fourth transistor T4 . The second interlayer insulating layer 162 may have a single-layer or multi-layer structure. The second interlayer insulating layer 162 may include an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiOxNy). The second interlayer insulating layer 162 may include a first opening 1165 , a second opening 1166 , a third opening 3165 , and a fourth opening 3166 .

The first opening 1165 may overlap at least a portion of the gate electrode 1151 of the driving transistor T1 . The first opening 1165 may be further formed in the third gate insulating layer 143 , the first interlayer insulating layer 161 , and the second gate insulating layer 142 . The first opening 1165 may overlap the opening 1152 of the first storage electrode 1153 . The first opening 1165 may be located inside the opening 1152 of the first storage electrode 1153 . The second opening 1166 may at least partially overlap the boost capacitor Cbt. The second opening 1166 may be further formed in the third gate insulating layer 143 .

The third opening 3165 may overlap at least a portion of the second region 1133 of the driving transistor T1 . The third opening 3165 may be further formed in the third gate insulating layer 143 , the first interlayer insulating layer 161 , the second gate insulating layer 142 , and the first gate insulating layer 141 . The fourth opening 3166 may overlap at least a portion of the first region 3136 of the third transistor T3 . The fourth opening 3166 may be further formed in the third gate insulating layer 143 .

A first data conductor including a first connection electrode 1175 and a second connection electrode 3175 may be positioned on the second interlayer insulating layer 162 . 12 shows a polycrystalline semiconductor layer, a first gate conductor, a second gate conductor, an oxide semiconductor layer, a third gate conductor and a first data conductor together.

The first connection electrode 1175 may overlap the gate electrode 1151 of the driving transistor T1 . The first connection electrode 1175 may be connected to the gate electrode 1151 of the driving transistor T1 through the opening 1152 of the first opening 1165 and the first storage electrode 1153 . The first connection electrode 1175 may overlap the boost capacitor Cbt. The first connection electrode 1175 may be connected to the upper boost electrode 3138t of the boost capacitor Cbt through the second opening 1166 . Accordingly, the gate electrode 1151 of the driving transistor T1 and the upper boost electrode 3138t of the boost capacitor Cbt may be connected by the first connection electrode 1175 . In this case, the gate electrode 1151 of the driving transistor T1 is connected to the second region 3138 of the third transistor T3 and the second region 4138 of the fourth transistor T4 by the first connection electrode 1175 . It can also be connected to

The second connection electrode 3175 may overlap the second region 1133 of the driving transistor T1 . The second connection electrode 3175 may be connected to the second region 1133 of the driving transistor T1 through the third opening 3165 . The second connection electrode 3175 may overlap the first region 3136 of the third transistor T3 . The second connection electrode 3175 may be connected to the first region 3136 of the third transistor T3 through the fourth opening 3166 . Accordingly, the second region 1133 of the driving transistor T1 and the first region 3136 of the third transistor T3 may be connected by the second connection electrode 3175 .

The first data conductor may further include a second initialization voltage line 128 . The second initialization voltage line 128 may extend in an approximately horizontal direction.

A third interlayer insulating layer 163 may be positioned on the first data conductor including the first connection electrode 1175 and the second connection electrode 3175 .

A second data conductor including a data line 171 and a driving voltage line 172 may be positioned on the third interlayer insulating layer 163 . 13 shows a polycrystalline semiconductor layer, a first gate conductor, a second gate conductor, an oxide semiconductor layer, a third gate conductor, a first data conductor and a second data conductor together.

The data line 171 and the driving voltage line 172 may extend in an approximately vertical direction. The data line 171 may be connected to the second transistor T2 . The driving voltage line 172 may be connected to the fifth transistor T5 . Also, the driving voltage line 172 may be connected to the first storage electrode 1153 . As described above, the third interlayer insulating layer 163 may include a first groove 163g1 and a second groove 163g2 . The driving voltage line 172 may be positioned in the first groove 163g1 of the third interlayer insulating layer 163 , and the data line 171 may be positioned in the second groove 163g2 of the third interlayer insulating layer 163 . there is.

A passivation layer 180 may be positioned on the data line 171 and the driving voltage line 172 . Although not shown in FIGS. 5 and 6 , a pixel electrode may be positioned on the passivation layer 180 . A pixel defining layer may be disposed on the pixel electrode, a light emitting device layer may be disposed in a pixel opening of the pixel defining layer, and a common electrode may be disposed on the pixel defining layer and the light emitting device layer.

Next, a display device according to an exemplary embodiment will be described with reference to FIG. 14 .

The display device according to the embodiment shown in FIG. 14 has substantially the same parts as the display device according to the embodiment shown in FIGS. 1 to 6 , and thus descriptions of the same parts will be omitted. This embodiment is different from the previous embodiment in that one data line is positioned in one second groove, and will be described further below.

14 is a cross-sectional view of a display device according to an exemplary embodiment.

As shown in FIG. 14 , the display device according to an exemplary embodiment includes a substrate 110 , a pixel electrode 191 positioned on the substrate 110 , and a third device positioned between the substrate 110 and the pixel electrode 191 . It may include an interlayer insulating layer 163 , a data line 171 , a driving voltage line 172 , and a passivation layer 180 . The data line 171 and the driving voltage line 172 may be positioned on the third interlayer insulating layer 163 , and the passivation layer 180 may be positioned on the data line 171 and the driving voltage line 172 .

The third interlayer insulating layer 163 may include a first groove 163g1 and a second groove 163g2 . The driving voltage line 172 may be positioned in the first groove 163g1 of the third interlayer insulating layer 163 . The data line 171 may be positioned in the second groove 163g2 of the third interlayer insulating layer 163 .

In the previous embodiment, two data lines 171 may be positioned in the second groove 163g2 of the third interlayer insulating film 163 , and in the present embodiment, the second groove 163g2 of the third interlayer insulating film 163 in the present embodiment. ), one data line 171 may be located. However, the present invention is not limited thereto, and the number of data lines 171 positioned in the second groove 163g2 of the third interlayer insulating layer 163 may be variously changed. The width Wg2 of the second groove 163g2 of the third interlayer insulating layer 163 may be greater than the width Wd of the data line 171 . However, the present invention is not limited thereto, and the width Wg2 of the second groove 163g2 of the third interlayer insulating layer 163 may be substantially the same as the width Wd of the data line 171 .

Next, a display device according to an exemplary embodiment will be described with reference to FIG. 15 .

The display device according to the embodiment shown in FIG. 15 has substantially the same parts as the display device according to the embodiment shown in FIGS. 1 to 6 , and thus descriptions of the same parts will be omitted. This embodiment is different from the previous embodiment in that the driving voltage line and the data line are formed to fill the groove of the third interlayer insulating layer, and will be described further below.

15 is a cross-sectional view of a display device according to an exemplary embodiment.

15 , the display device according to an exemplary embodiment includes a substrate 110 , a pixel electrode 191 positioned on the substrate 110 , and a third positioned between the substrate 110 and the pixel electrode 191 . It may include an interlayer insulating layer 163 , a data line 171 , a driving voltage line 172 , and a passivation layer 180 . The data line 171 and the driving voltage line 172 may be positioned on the third interlayer insulating layer 163 , and the passivation layer 180 may be positioned on the data line 171 and the driving voltage line 172 .

The third interlayer insulating layer 163 may include a first groove 163g1 and a second groove 163g2 . The driving voltage line 172 may be positioned in the first groove 163g1 of the third interlayer insulating layer 163 . The data line 171 may be positioned in the second groove 163g2 of the third interlayer insulating layer 163 .

In the previous embodiment, the width Wg1 of the first groove 163g1 of the third interlayer insulating film 163 may be greater than the width We of the driving voltage line 172, and in the present embodiment, the third interlayer insulating film 163 The width Wg1 of the first groove 163g1 may be substantially the same as the width We of the driving voltage line 172 . The driving voltage line 172 may be formed to fill the first groove 163g1 of the third interlayer insulating layer 163 .

In the previous embodiment, the width Wg2 of the second groove 163g2 of the third interlayer insulating film 163 may be greater than the width Wd of the data line 171 , and in the present embodiment, the third interlayer insulating film 163 . The width Wg2 of the second groove 163g2 may be substantially the same as the width Wd of the data line 171 . The data line 171 may be formed to fill the second groove 163g2 of the third interlayer insulating layer 163 .

The second data conductor including the driving voltage line 172 and the data line 171 may be formed by a photo and etching process. However, the present invention is not limited thereto, and the second data conductor including the driving voltage line 172 and the data line 171 may be formed by a chemical mechanical polishing (CMP) process. If the chemical mechanical polishing process is used, the driving voltage line 172 and the data line 171 may be easily formed to fill the groove of the third interlayer insulating layer 163 .

Next, a display device according to an exemplary embodiment will be described with reference to FIG. 16 .

The display device according to the embodiment shown in FIG. 16 has substantially the same parts as the display device according to the embodiment shown in FIGS. 1 to 6 , and thus a description of the same parts will be omitted. This embodiment is different from the previous embodiment in that the third interlayer insulating film has a double layer, which will be further described below.

16 is a cross-sectional view of a display device according to an exemplary embodiment.

As shown in FIG. 16 , the display device according to an exemplary embodiment includes a substrate 110 , a pixel electrode 191 positioned on the substrate 110 , and a third device positioned between the substrate 110 and the pixel electrode 191 . It may include an interlayer insulating layer 163 , a data line 171 , a driving voltage line 172 , and a passivation layer 180 . The data line 171 and the driving voltage line 172 may be positioned on the third interlayer insulating layer 163 , and the passivation layer 180 may be positioned on the data line 171 and the driving voltage line 172 .

The third interlayer insulating layer 163 may include a first groove 163g1 and a second groove 163g2 . The driving voltage line 172 may be positioned in the first groove 163g1 of the third interlayer insulating layer 163 . The data line 171 may be positioned in the second groove 163g2 of the third interlayer insulating layer 163 .

In the previous embodiment, the third interlayer insulating film 163 may be formed of a single layer, and in the present embodiment, the third interlayer insulating film 163 may be formed of a double layer. The third interlayer insulating layer 163 may include a third lower interlayer insulating layer 163p and a third upper interlayer insulating layer 163q. The third upper interlayer insulating layer 163q may be positioned on the third lower interlayer insulating layer 163p. The third lower interlayer insulating layer 163p and the third upper interlayer insulating layer 163q may include the same material or different materials. Bottom surfaces of the first and second grooves 163g1 and 163g2 may be in contact with the top surface of the third lower interlayer insulating layer 163p. Sides of the first and second grooves 163g1 and 163g2 may be in contact with side surfaces of the third upper interlayer insulating layer 163q.

As in the previous embodiment, when the third interlayer insulating layer 163 is formed of a single layer, a halftone exposure process may be used to form the grooves 163g1 and 163g2 in the third interlayer insulating layer 163 . In this case, the ratio of elements in the third interlayer insulating layer 163 may be different depending on the location. The content of element sulfur (S) in the first portion 163a and the second portion 163b of the third interlayer insulating film 163 positioned under the grooves 163g1 and 163g2 is the third of the third interlayer insulating film 163 . It may be less than the content of elemental sulfur (S) in the portion 163c. The first portion 163a and the second portion 163b of the third interlayer insulating layer 163 are portions subjected to halftone exposure, because sulfur (S) element is partially decomposed.

As in the present embodiment, when the third interlayer insulating film 163 includes the third lower interlayer insulating film 163p and the third upper interlayer insulating film 163q, the third lower interlayer insulating film 163p and the third upper interlayer insulating film ( 163q) may be formed through separate processes. In this case, the ratio of elements in the third interlayer insulating layer 163 may be constant regardless of the position. After the third lower interlayer insulating layer 163p is first formed to be flat, the third upper interlayer insulating layer 163q is formed on the third lower interlayer insulating layer 163p and patterned to form the grooves 163g1 and 163g2 . That is, a portion from which the third upper interlayer insulating layer 163q is removed may become the grooves 163g1 and 163g2 .

Hereinafter, a structural difference between the case in which the third interlayer insulating film 163 is formed of a double layer and the case where the third interlayer insulating film 163 is formed of a single layer will be described with reference to FIGS. 17 and 18 .

17 is a diagram illustrating a third interlayer insulating layer of the display device according to the embodiment of FIG. 16 , and FIG. 18 is a diagram illustrating a third interlayer insulating layer of the display device according to the embodiment of FIG. 3 .

17 , when the third interlayer insulating layer 163 is formed of a double layer, the third lower interlayer insulating layer 163p and the third upper interlayer insulating layer 163q may be formed through separate processes. In this case, the inclined surface of the portion in which the groove is formed may have a taper angle of about 40 to 50 degrees.

18 , when the third interlayer insulating layer 163 is formed of a single layer, the third interlayer insulating layer 163 may be formed through a halftone process. In this case, the inclined surface of the portion where the groove is formed may have a taper angle of about 25 to 30 degrees. During the halftone process, since a portion of the fulltone area is exposed by light diffracted from the halftone area, the taper angle of the inclined surface may be relatively low.

Next, a display device according to an exemplary embodiment will be described with reference to FIGS. 19 and 20 .

The display device according to the exemplary embodiment illustrated in FIGS. 19 and 20 has substantially the same parts as the display device according to the exemplary embodiment illustrated in FIGS. 1 to 6 , and thus descriptions of the same portions will be omitted. The present embodiment is different from the previous embodiment in that adjacent driving voltage lines are spaced apart from each other, which will be further described below.

19 is a plan view of a display device according to an exemplary embodiment, and FIG. 20 is a cross-sectional view of the display device according to an exemplary embodiment taken along line XX-XX of FIG. 19 .

19 and 20 , the display device according to an exemplary embodiment includes a substrate 110 , a pixel electrode 191 positioned on the substrate 110 , and a position between the substrate 110 and the pixel electrode 191 . and a third interlayer insulating layer 163 , a data line 171 , a driving voltage line 172 , and a passivation layer 180 . The data line 171 and the driving voltage line 172 may be positioned on the third interlayer insulating layer 163 , and the passivation layer 180 may be positioned on the data line 171 and the driving voltage line 172 .

The third interlayer insulating layer 163 may include a first groove 163g1 and a second groove 163g2 . The driving voltage line 172 may be positioned in the first groove 163g1 of the third interlayer insulating layer 163 . The data line 171 may be positioned in the second groove 163g2 of the third interlayer insulating layer 163 .

In the previous embodiment, two adjacent driving voltage lines 172 may be connected to each other to form an integral body, and in the present embodiment, two adjacent driving voltage lines 172 may be separated from each other. An opening pattern 72a may be positioned between two adjacent driving voltage lines 172 , and driving voltage lines 172 on both sides may be spaced apart from each other by the opening pattern 72a.

The driving voltage line 172 may include an extension portion 72 , and the extension portions 72 of two adjacent driving voltage lines 172 may be separated from each other by an opening pattern 72a. Since the driving voltage line 172 includes the extension part 72 , it is possible to prevent a signal delay of the driving voltage. The extended portion 72 may have a relatively large area, so that the internal gas generated in the baking process for forming the insulating layers located under the driving voltage line 172 and including the organic material cannot be discharged to the outside. In this case, the light emitting device layer may be deteriorated or the electrode layer of the organic device may be discolored, and thus the light emitting characteristics of the light emitting device layer may be deteriorated. In the display device according to the exemplary embodiment, since the extension portions 72 of the adjacent driving voltage lines 172 are separated from each other by the opening pattern 72a, when the extension portions 72 of the adjacent driving voltage lines 172 are connected to each other, Compared to that, it may be a passage through which internal gas that may be generated when the insulating layer is formed can be discharged to the outside.

When the extension portions 72 of the adjacent driving voltage lines 172 are separated from each other by the opening pattern 72a, a step may occur. In the display device according to an exemplary embodiment, since the driving voltage line 172 is positioned in the first groove 163g1 of the third interlayer insulating layer 163 , it is possible to prevent such a step difference from occurring. Accordingly, the passivation layer 180 positioned on the third interlayer insulating layer 163 and the driving voltage line 172 can be formed thinly and flatly.

In FIG. 20 , two driving voltage lines 172 adjacent to each other in one first groove 163g1 are illustrated, but the present invention is not limited thereto. One driving voltage line 172 may be positioned in one first groove 163g1 . In this case, the upper surface of the portion of the third interlayer insulating layer 163 overlapping the opening pattern 72a may coincide with the upper surface of the driving voltage line 172 . That is, the upper surface of the portion of the third interlayer insulating layer 163 overlapping the opening pattern 72a and the upper surface of the driving voltage line 172 may be formed to be flat. Accordingly, the upper surface of the passivation layer 180 positioned on the third interlayer insulating layer 163 and the driving voltage line 172 may be further flattened.

Next, a display device according to an exemplary embodiment will be described with reference to FIG. 21 .

The display device according to the embodiment shown in FIG. 21 has substantially the same parts as the display device according to the embodiment shown in FIGS. 1 to 6 , and thus descriptions of the same parts will be omitted. This embodiment is different from the previous embodiment in that the passivation layer includes a first passivation layer and a second passivation layer, which will be further described below.

21 is a cross-sectional view of a display device according to an exemplary embodiment.

As shown in FIG. 21 , the display device according to an exemplary embodiment includes a substrate 110 , a pixel electrode 191 positioned on the substrate 110 , and a third device positioned between the substrate 110 and the pixel electrode 191 . It may include an interlayer insulating layer 163 , a data line 171 , a driving voltage line 172 , and a passivation layer 180 . The data line 171 and the driving voltage line 172 may be positioned on the third interlayer insulating layer 163 , and the passivation layer 180 may be positioned on the data line 171 and the driving voltage line 172 .

In the previous embodiment, the passivation layer 180 may be formed of a single layer, and in this embodiment, the passivation layer 180 may include a first passivation layer 180p and a second passivation layer 180q.

The first passivation layer 180p may be positioned on the data line 171 and the driving voltage line 172 . The first passivation layer 180p may be entirely formed on the substrate 110 . The second passivation layer 180q may be positioned on the first passivation layer 180p. The second passivation layer 180q may be formed only in a partial region. The second passivation layer 180q may overlap the data line 171 and the driving voltage line 172 . The second passivation layer 180q may overlap the pixel electrode 191 . The second passivation layer 180q may overlap an edge of the pixel defining layer 360 . The second passivation layer 180q may not overlap the central portion of the pixel defining layer 360 . A portion of the second passivation layer 180q that does not overlap the data line 171 and the driving voltage line 172 may be patterned to be removed.

The first passivation layer 180p and the second passivation layer 180q may include an organic insulating material. The first passivation layer 180p and the second passivation layer 180q may include the same material or different materials.

In the previous embodiment, the third interlayer insulating layer 163 includes a groove, and the data line 171 and the driving voltage line 172 may be positioned in the groove. In this embodiment, the third interlayer insulating layer 163 forms the groove. may not be included. The third interlayer insulating layer 163 is formed to be flat, and since the data line 171 and the driving voltage line 172 are positioned on the third interlayer insulating layer 163 , a step may occur. Accordingly, the upper surface of the first passivation layer 180p positioned on the data line 171 and the driving voltage line 172 may not be flat. In the display device according to an embodiment, the second passivation layer 180q may be positioned on the first passivation layer 180p, and the upper surface of the second passivation layer 180q may be formed to be flat. Accordingly, the pixel electrode 191 positioned on the passivation layer 180 may have a flat upper surface, reduce the reflectance of external light, and prevent color bleeding.

In addition, the first passivation layer 180p is formed to have a thin thickness and the second passivation layer 180q is patterned to be positioned only in a partial region, so that internal gas that may be generated in the process of forming the insulating layer can be smoothly discharged.

Although it has been described above that the third interlayer insulating layer 163 does not include a groove, the present invention is not limited thereto. The third interlayer insulating layer 163 may include a groove, and the data line 171 and the driving voltage line 172 may be positioned in the groove. Accordingly, the passivation layer 180 positioned on the data line 171 and the driving voltage line 172 may be formed flat. At this time, the first passivation layer 180p is formed entirely on the data line 171 and the driving voltage line 172 , and the second passivation layer 180q is additionally formed on the first passivation layer 180p, thereby forming the upper surface of the passivation layer 180 . can further improve the flatness of

21 illustrates a structure in which adjacent driving voltage lines 172 are separated from each other, but is not limited thereto. As in the previous embodiment, adjacent driving voltage lines 172 may be connected to each other and formed integrally.

Hereinafter, a cross-sectional shape of the passivation layer of the display device according to an exemplary embodiment will be further described with reference to FIG. 22 .

22 is a diagram illustrating a part of a display device according to an exemplary embodiment. FIG. 22 is a view illustrating a protective film and its periphery of the display device according to the embodiment of FIG. 21 .

22 , the passivation layer 180 of the display device according to an embodiment may include a first passivation layer 180p and a second passivation layer 180q. As described above, in the display device according to an exemplary embodiment, the passivation layer 180 may be formed to be flat while being thin. The second passivation layer 180q is patterned to be positioned only in a partial region, and in this case, an inclined surface of the second passivation layer 180q may be formed gently.

Next, a display device according to an exemplary embodiment will be described with reference to FIG. 23 .

Since the display device according to the embodiment shown in FIG. 23 has substantially the same parts as the display device according to the embodiment shown in FIGS. 1 to 6 , descriptions of the same parts will be omitted. This embodiment is different from the previous embodiment in that the protective film includes a first protective film, a second protective film, and a third protective film, which will be further described below.

23 is a cross-sectional view of a display device according to an exemplary embodiment.

23 , the display device according to an exemplary embodiment includes a substrate 110 , a pixel electrode 191 positioned on the substrate 110 , and a third positioned between the substrate 110 and the pixel electrode 191 . It may include an interlayer insulating layer 163 , a data line 171 , a driving voltage line 172 , and a passivation layer 180 . The data line 171 and the driving voltage line 172 may be positioned on the third interlayer insulating layer 163 , and the passivation layer 180 may be positioned on the data line 171 and the driving voltage line 172 .

In the previous embodiment, the passivation layer 180 may be formed of a single layer, and in this embodiment, the passivation layer 180 may include a first passivation layer 180p, a second passivation layer 180q, and a third passivation layer 180r. .

The first passivation layer 180p may be positioned on the data line 171 and the driving voltage line 172 . The first passivation layer 180p may be entirely formed on the substrate 110 . The first passivation layer 180p may include an inorganic insulating material such as silicon oxide (SiO _x ), silicon nitride (SiN _x ), and silicon nitride oxide (SiO _x N _y ). The second passivation layer 180q may be positioned on the first passivation layer 180p. The second passivation layer 180q may be entirely formed on the substrate 110 . The second passivation layer 180q may include an organic insulating material. The third passivation layer 180r may be positioned on the second passivation layer 180q. The third passivation layer 180r may be formed in a partial region. The third passivation layer 180r may overlap the data line 171 and the driving voltage line 172 . The third passivation layer 180r may overlap an edge of the pixel defining layer 360 . The third passivation layer 180r may not overlap the central portion of the pixel defining layer 360 . A portion of the third passivation layer 180r that does not overlap the data line 171 and the driving voltage line 172 may be patterned to be removed. The third passivation layer 180r may include an organic insulating material.

In the previous embodiment, the third interlayer insulating layer 163 includes a groove, and the data line 171 and the driving voltage line 172 may be positioned in the groove. In this embodiment, the third interlayer insulating layer 163 forms the groove. may not be included. The third interlayer insulating layer 163 is formed to be flat, and since the data line 171 and the driving voltage line 172 are positioned on the third interlayer insulating layer 163 , a step may occur. Accordingly, the upper surface of the first passivation layer 180p positioned on the data line 171 and the driving voltage line 172 may not be flat. In the display device according to an exemplary embodiment, a second passivation layer 180q is positioned on the first passivation layer 180p, a third passivation layer 180r is positioned on the second passivation layer 180q, and an upper surface of the third passivation layer 180r. can be made flat. Accordingly, the pixel electrode 191 positioned on the passivation layer 180 may have a flat upper surface, reduce the reflectance of external light, and prevent color bleeding.

In addition, the first passivation layer 180p and the second passivation layer 180q are formed to have a thin thickness, and the third passivation layer 180r is patterned to be positioned only in a partial region, thereby discharging internal gas that may be generated in the insulating layer forming process. This can be done smoothly.

Although it has been described above that the third interlayer insulating layer 163 does not include a groove, the present invention is not limited thereto. The third interlayer insulating layer 163 may include a groove, and the data line 171 and the driving voltage line 172 may be positioned in the groove. Accordingly, the passivation layer 180 positioned on the data line 171 and the driving voltage line 172 may be formed flat. At this time, the first passivation layer 180p and the second passivation layer 180q are formed entirely on the data line 171 and the driving voltage line 172 , and the third passivation film 180r is additionally formed on the second passivation layer 180q, The flatness of the upper surface of the passivation layer 180 may be further improved.

23 illustrates a structure in which adjacent driving voltage lines 172 are separated from each other, but is not limited thereto. As in the previous embodiment, adjacent driving voltage lines 172 may be connected to each other and formed integrally.

Next, a display device according to an exemplary embodiment will be described with reference to FIG. 24 .

Since the display device according to the embodiment shown in FIG. 24 has substantially the same parts as the display device according to the embodiment shown in FIG. 23 , descriptions of the same parts will be omitted. This embodiment is different from the previous embodiment in that the second passivation layer is located only in a partial region, which will be further described below.

24 is a cross-sectional view of a display device according to an exemplary embodiment.

24 , a display device according to an exemplary embodiment includes a substrate 110 , a pixel electrode 191 positioned on the substrate 110 , and a third pixel electrode 191 positioned between the substrate 110 and the pixel electrode 191 . It may include an interlayer insulating layer 163 , a data line 171 , a driving voltage line 172 , and a passivation layer 180 . The data line 171 and the driving voltage line 172 may be positioned on the third interlayer insulating layer 163 , and the passivation layer 180 may be positioned on the data line 171 and the driving voltage line 172 . The passivation layer 180 may include a first passivation layer 180p, a second passivation layer 180q, and a third passivation layer 180r.

In the previous embodiment, the second passivation layer 180q may be entirely formed on the substrate 110 , and in the present exemplary embodiment, the second passivation layer 180q may be formed in a partial region. The second passivation layer 180q may overlap the data line 171 and the driving voltage line 172 . The second passivation layer 180q may overlap the pixel electrode 191 . The second passivation layer 180q may overlap an edge of the pixel defining layer 360 . The second passivation layer 180q may not overlap the central portion of the pixel defining layer 360 . A portion of the second passivation layer 180q that does not overlap the data line 171 and the driving voltage line 172 may be patterned to be removed. In this case, the second passivation layer 180q and the third passivation layer 180r may be patterned using the same mask, may be patterned simultaneously in the same process, and may have substantially the same planar shape.

Next, a display device according to an exemplary embodiment will be described with reference to FIG. 25 .

The display device according to the embodiment shown in FIG. 25 has substantially the same parts as the display device according to the embodiment shown in FIGS. 1 to 6 , and thus descriptions of the same parts will be omitted. This embodiment is different from the previous embodiment in that the thickness of the passivation layer is different depending on the position, which will be further described below.

25 is a cross-sectional view of a display device according to an exemplary embodiment.

25 , the display device according to an exemplary embodiment includes a substrate 110 , a pixel electrode 191 positioned on the substrate 110 , and a third positioned between the substrate 110 and the pixel electrode 191 . It may include an interlayer insulating layer 163 , a data line 171 , a driving voltage line 172 , and a passivation layer 180 . The data line 171 and the driving voltage line 172 may be positioned on the third interlayer insulating layer 163 , and the passivation layer 180 may be positioned on the data line 171 and the driving voltage line 172 .

In the previous embodiment, the passivation layer 180 may have a substantially constant thickness, and in the present exemplary embodiment, the passivation layer 180 may have different thicknesses according to positions.

The passivation layer 180 may include a first portion 180i having a first thickness THi and a second portion 180j having a second thickness THj. In this case, the first thickness THi of the first portion 180i of the passivation layer 180 may be thicker than the second thickness THj of the second portion 180j of the passivation layer 180 . The first portion 180i of the passivation layer 180 may overlap the data line 171 and the driving voltage line 172 . The first portion 180i of the passivation layer 180 may overlap an edge of the pixel defining layer 360 . The first portion 180i of the passivation layer 180 may not overlap the central portion of the pixel defining layer 360 . The second portion 180j of the passivation layer 180 may overlap the central portion of the pixel defining layer 360 . The second portion 180j of the passivation layer 180 may not overlap the data line 171 and the driving voltage line 172 . The passivation layer 180 may be formed using a halftone exposure process, and in this case, the second portion 180j of the passivation layer 180 may be patterned to have a thinner thickness than the first portion 180i.

In the previous embodiment, the third interlayer insulating layer 163 includes a groove, and the data line 171 and the driving voltage line 172 may be positioned in the groove. In this embodiment, the third interlayer insulating layer 163 forms the groove. may not be included. The third interlayer insulating layer 163 is formed to be flat, and since the data line 171 and the driving voltage line 172 are positioned on the third interlayer insulating layer 163 , a step may occur. Accordingly, the upper surface of the passivation layer 180 positioned on the data line 171 and the driving voltage line 172 may not be flat. In the display device according to an exemplary embodiment, the first portion 180i of the passivation layer 180 overlapping the data line 171 and the driving voltage line 172 has a relatively large thickness, so that the first portion of the passivation layer 180 is relatively thick. The upper surface of 180i may be made flat. Since the pixel electrode 191 is positioned on the first portion 180i of the passivation layer 180 , it may have a flat upper surface, may lower the reflectance of external light, and may prevent color bleeding.

In addition, since the second portion 180j of the passivation layer 180 has a relatively thin thickness, internal gas that may be generated in the process of forming the insulating layer may be smoothly discharged.

Although it has been described above that the third interlayer insulating layer 163 does not include a groove, the present invention is not limited thereto. The third interlayer insulating layer 163 may include a groove, and the data line 171 and the driving voltage line 172 may be positioned in the groove. Accordingly, the passivation layer 180 positioned on the data line 171 and the driving voltage line 172 may be formed flat. In this case, by forming the first portion 180i of the passivation layer 180 overlapping the data line 171 and the driving voltage line 172 to be relatively thick, the flatness of the upper surface of the passivation layer 180 may be further improved. .

Although FIG. 25 illustrates a structure in which adjacent driving voltage lines 172 are separated from each other, the present invention is not limited thereto. As in the previous embodiment, adjacent driving voltage lines 172 may be connected to each other and formed integrally.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements by those skilled in the art using the basic concept of the present invention as defined in the following claims are also provided. is within the scope of the right.

110: substrate 111: buffer layer
161: first interlayer insulating film 162: second interlayer insulating film
163: third interlayer insulating film 163a: first portion of third interlayer insulating film
163b: second portion of third interlayer insulating film 163c: third portion of third interlayer insulating film
163g1: first groove 163g2: second groove
163p: third lower interlayer insulating film 163q: third upper interlayer insulating film
171: data line 172: driving voltage line
180: protective film 180i: first portion of the protective film
180j: the second portion of the passivation layer 180p: the first passivation layer
180q: second passivation layer 180r: third passivation layer
191: pixel electrode 270: common electrode
360: pixel defining layer 365: pixel opening
370: light emitting device layer

Claims (20)

Board,
a transistor positioned on the substrate;
an interlayer insulating film positioned over the transistor;
a driving voltage line and a data line positioned on the interlayer insulating layer and connected to the transistor;
a protective film positioned on the driving voltage line and the data line;
a pixel electrode positioned on the passivation layer and overlapping at least a portion of the driving voltage line and the data line;
a pixel defining layer disposed on the pixel electrode and including a pixel opening;
a light emitting element layer positioned on the pixel electrode; and
a common electrode positioned on the light emitting device layer and the pixel defining layer;
The interlayer insulating layer includes a groove, and the driving voltage line and the data line are positioned in the groove. In claim 1,
The interlayer insulating film includes a first groove and a second groove,
The driving voltage line is located in the first groove,
The data line is located in the second groove. In claim 2,
The depth of the first groove is the same as the thickness of the driving voltage line,
A depth of the second groove is the same as a thickness of the data line. In claim 2,
a width of the first groove is greater than or equal to a width of the driving voltage line;
A width of the second groove is greater than or equal to a width of the data line. In claim 2,
The display device includes a plurality of data lines spaced apart from each other;
At least two data lines among the plurality of data lines are positioned in the second groove. In claim 2,
A display device in which one data line is positioned in the second groove. In claim 1,
The interlayer insulating film includes a lower interlayer insulating film and an upper interlayer insulating film positioned on the lower interlayer insulating film,
The lower interlayer insulating film is entirely located on the substrate,
A portion from which the upper interlayer insulating layer is removed becomes the groove. In claim 7,
a bottom surface of the groove is in contact with an upper surface of the lower interlayer insulating film;
A side surface of the groove is in contact with a side surface of the upper interlayer insulating layer. In claim 1,
The display device includes a plurality of driving voltage lines spaced apart from each other;
At least two driving voltage lines among the plurality of driving voltage lines are positioned in the groove. In claim 1,
an encapsulation layer positioned on the common electrode;
a touch unit positioned on the encapsulation layer; and
Further comprising an anti-reflection unit positioned on the touch unit,
The anti-reflection part
a light blocking layer overlapping the pixel defining layer; and
and a color filter overlapping the pixel electrode. In claim 1,
Each pixel of the display device includes a plurality of transistors,
The plurality of transistors includes an oxide transistor including an oxide semiconductor and a polycrystalline transistor including a polycrystalline semiconductor. Board,
a transistor positioned on the substrate;
an interlayer insulating film positioned over the transistor;
a driving voltage line and a data line positioned on the interlayer insulating layer and connected to the transistor;
a protective film positioned on the driving voltage line and the data line;
a pixel electrode positioned on the passivation layer and overlapping at least a portion of the driving voltage line and the data line;
a pixel defining layer disposed on the pixel electrode and including a pixel opening;
a light emitting element layer positioned on the pixel electrode; and
a common electrode positioned on the light emitting device layer and the pixel defining layer;
The passivation layer includes a first passivation layer and a second passivation layer positioned on the first passivation layer,
The second passivation layer is positioned on a partial region of the substrate and overlaps the driving voltage line and the data line. In claim 12,
The first protective film is positioned entirely on the substrate,
the second passivation layer overlaps the pixel electrode, and the pixel electrode is positioned on the second passivation layer;
The second passivation layer overlaps an edge of the pixel defining layer and does not overlap a central portion of the pixel defining layer. In claim 13,
The first passivation layer and the second passivation layer include an organic insulating material. In claim 12,
The protective film further includes a third protective film positioned under the first protective film,
The third passivation layer includes an inorganic insulating material. In claim 15,
The first passivation layer and the third passivation layer are entirely disposed on the substrate. In claim 15,
The third protective film is entirely located on the substrate,
The first passivation layer is positioned on a partial region on the substrate and overlaps the driving voltage line and the data line. Board,
a transistor positioned on the substrate;
an interlayer insulating film positioned over the transistor;
a driving voltage line and a data line positioned on the interlayer insulating layer and connected to the transistor;
a protective film positioned on the driving voltage line and the data line;
a pixel electrode positioned on the passivation layer and overlapping at least a portion of the driving voltage line and the data line;
a pixel defining layer disposed on the pixel electrode and including a pixel opening;
a light emitting element layer positioned on the pixel electrode; and
a common electrode positioned on the light emitting device layer and the pixel defining layer;
the passivation layer includes a first portion overlapping the driving voltage line and the data line and a second portion excluding the first portion,
A thickness of the first portion is greater than a thickness of the second portion. In claim 18,
A first portion of the passivation layer overlaps the pixel electrode, overlaps an edge of the pixel-defining layer, and does not overlap a central portion of the pixel-defining layer. In paragraph 19,
The passivation layer includes an organic insulating material.

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