KR20220033397A - A memory device and memory system including the same for generating pulse amplitude modulation based dq signal - Google Patents

Abstract

The present invention relates to a memory device for generating a pulse amplitude modulation (PAM)-based DQ signal to output a DQ signal having good signal characteristics even at low power and a memory system including the same. According to an exemplary embodiment of the present invention the memory device comprises a memory cell array and a transmitter. The transmitter includes: a PAM encoder configured to generate a first input signal conforming to n-level PAM from data read from the memory cell array, where n is an integer greater than or equal to 4; a pre-driver configured to generate a second input signal on the basis of the first input signal and the calibration code signal and using a first power supply voltage to output the second input signal; and a driver configured to output a DQ signal based on the PAM-n by using a second power supply voltage lower than the first power supply voltage in response to the second input signal.

Description

A MEMORY DEVICE AND MEMORY SYSTEM INCLUDING THE SAME FOR GENERATING PULSE AMPLITUDE MODULATION BASED DQ SIGNAL

The present disclosure relates to a memory device, and more particularly, to a memory device generating a pulse amplitude modulation-based DQ signal and a memory system including the same.

Demand for high-capacity and high-speed data transmission is increasing day by day with the rapid supply of mobile devices and the rapid increase in the amount of Internet access. Accordingly, there is a need for a technology for storing high-capacity data in a memory system and for high-speed data transmission in response to a data request. However, it is difficult to satisfy the demand for high-capacity and high-speed data transmission using a signal modulation method based on a non-return to zero type encoding. Recently, even in a memory system, a pulse amplitude modulation (PAM) method has been actively studied as an alternative to a signal method for high-capacity and high-speed data transmission.

The problem to be solved by the technical spirit of the present disclosure is to improve data transmission performance in a high frequency band of a memory device generating a pulse amplitude modulation DQ signal and efficiently improve power consumption, and a memory system including the same is to provide

A memory device according to an exemplary embodiment of the present disclosure includes a memory cell array and a transmitter, wherein the transmitter performs n-level pulse amplitude modulation (PAM-n) from data read from the memory cell array (where n is an integer greater than or equal to 4) a PAM encoder configured to generate a first input signal, a second input signal is generated based on the first input signal and a calibration code signal, and the second input signal is generated using a first power supply voltage. a pre-driver configured to output two input signals and a driver configured to output a DQ signal based on the PAM-n using a second power supply voltage lower than the first power supply voltage in response to the second input signal. Meanwhile, hereinafter, a code signal may be used interchangeably as the same term as a code.

A memory device according to an exemplary embodiment of the present disclosure includes a memory cell array and a transmitter, wherein the transmitter includes first and second Most Significant MSBs (MSBs) conforming to PAM-4 from data read from the memory cell array. Bit) signals and a PAM encoder configured to generate first and second Least Significant Bit (LSB) signals, in a first voltage domain, to generate a third MSB signal based on the first MSB signal and the first pull-up code. generating a fourth MSB signal based on the second MSB signal and a second pull-up code, and generating a third LSB signal based on the first LSB signal and the first pull-down code; A pre-driver configured to generate a fourth LSB signal based on a second LSB signal and a second pull-down code and a first pull-up circuit activated by the third MSB signal, the first pull-up circuit configured to adjust a driving strength, the first pull-up circuit configured to be adjusted; A first pull-down circuit activated based on a fourth MSB signal and configured to adjust driving strength, a second pull-up circuit activated by the third LSB signal and configured to adjust driving strength, and the fourth LSB a second pull-down circuit activated by a signal and configured to adjust driving strength, using first and second pull-up circuits and first and second pull-down circuits in a second voltage domain and a driver configured to output a DQ signal based on the PAM-4.

A memory system according to an exemplary embodiment of the present disclosure includes a memory controller and a plurality of memory devices connected to the memory controller through one channel, and each of the plurality of memory devices includes data requested by the memory controller. a PAM encoder configured to generate a first input signal conforming to PAM-n from a pre-driver configured to generate a second input signal based on the first input signal and a calibration code signal, and output the second input signal using a first power supply voltage; and a transmitter including a driver configured to output the DQ signal based on the PAM-n using a second power supply voltage lower than the first power supply voltage in response to the second input signal.

The driver of the transmitter according to an exemplary embodiment of the present disclosure operates by receiving a second power supply voltage lower than the first power supply voltage provided to other logics of the transmitter, thereby reducing power consumed in the output of the DQ signal. - A DQ signal having good signal characteristics can be output even at low power by receiving the second input signal having been driven in advance from the driver and having improved signal characteristics.

Effects that can be obtained in the exemplary embodiments of the present disclosure are not limited to the above-mentioned effects, and other effects not mentioned are common knowledge in the art to which exemplary embodiments of the present disclosure pertain from the following description. It can be clearly derived and understood by those who have That is, unintended effects of carrying out the exemplary embodiments of the present disclosure may also be derived by those of ordinary skill in the art from the exemplary embodiments of the present disclosure.

1 is a block diagram illustrating a memory system according to an exemplary embodiment of the present disclosure.
2 is a diagram for describing a DQ signal according to an exemplary embodiment of the present disclosure.
3 is a block diagram illustrating a transmitter according to an exemplary embodiment of the present disclosure.
4A and 4B are circuit diagrams illustrating exemplary implementations of the driver of FIG. 3 ;
5A and 5B are diagrams illustrating exemplary implementations of the pre-driver of FIG. 3 ;
6A to 6C are block diagrams illustrating a memory system for explaining a memory device connected to a memory controller having various types of termination resistors according to exemplary embodiments of the present disclosure;
7A to 7C are diagrams for explaining first to third swing sections of the DQ signal in FIGS. 6A to 6C .
8 is a block diagram of a memory system for explaining a transmitter of a memory device that outputs a DQ signal having a swing period according to a type of a termination resistor of a memory controller according to an exemplary embodiment of the present disclosure.
9 is a block diagram of a memory system for describing a transmitter of a memory device supporting a PAM-n signaling mode and a non-return-to-zero signaling mode according to an exemplary embodiment of the present disclosure.
10A to 10C are diagrams for explaining first to third swing sections of a DQ signal in a non-zero return signaling mode.
11 is a block diagram illustrating a transmitter that outputs a PAM-n based DQ signal according to an exemplary embodiment.
12A and 12B are diagrams for explaining a characteristic change of a DQ signal according to an operating environment of a memory device.
13A and 13B are block diagrams of a transmitter illustrating an implementation of a driver that further includes additional pull-up circuits or additional pull-down circuits.
14A and 14B are block diagrams illustrating a calibration circuit according to an exemplary embodiment of the present disclosure.
15A to 15D are diagrams for explaining a calibration method different from the calibration method of FIG. 14A according to an exemplary embodiment of the present disclosure.
16A and 16B are diagrams for illustrating an embodiment of the pull-up replica circuit and the pull-down replica circuit in FIGS. 15C and 15D .
17 is a block diagram illustrating an implementation of a transmitter according to an exemplary embodiment of the present disclosure.
18A to 18F are diagrams for explaining an embodiment and an operation method of the calibration circuit of FIG. 17 .
19 is a block diagram illustrating a memory device receiving first and second setting signals according to an exemplary embodiment of the present disclosure.
20A to 20C are block diagrams illustrating a memory system including a transmitter performing a termination resistor operation according to an exemplary embodiment of the present disclosure.
21 is a block diagram illustrating a memory device according to an exemplary embodiment of the present disclosure.
22 is a block diagram illustrating a memory device according to an exemplary embodiment of the present disclosure.
23 is a block diagram illustrating systems including a transmitter according to an exemplary embodiment of the present disclosure.
24 is a block diagram illustrating a system-on-chip including a memory device according to an exemplary embodiment of the present disclosure.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a memory system 10 according to an exemplary embodiment of the present disclosure. In the following embodiments, a dynamic random access memory (DRAM) corresponding to a volatile memory is exemplified as the memory device 100 included in the memory system 10 , but embodiments of the present disclosure are not limited thereto. For example, a different type of volatile memory may be applied to the memory device 100 , or a nonvolatile memory such as a resistive memory device or a flash memory device may be applied to the memory device according to exemplary embodiments of the present disclosure. Obvious.

Referring to FIG. 1 , a memory system 10 may include a memory device 100 and a memory controller 200 . The memory device 100 may include a transmitter 120 and a memory cell array 140 . The memory controller 200 may include a receiver 220 and a command generator 240 .

개의 데이터 값을 표현할 수 있는 DQ 신호(DQ)를 생성하여 출력할 수 있다. 일 예로, 송신기(120)는 PAM-4 에 따라 2-비트 수의 심볼을 포함하여 4개의 데이터 값(00, 01, 10, 11)을 표현할 수 있는 DQ 신호(DQ)를 생성하여 출력할 수 있다. 도 1에서는 DQ 신호(DQ)는 단일(single) 신호로서 구현되어 메모리 장치(100)와 메모리 컨트롤러(200) 사이의 단일 라인을 통해 송수신될 수 있다. 일부 실시예에서, DQ 신호(DQ)는 차동(differential) 신호로 구현되어 메모리 장치(100)와 메모리 컨트롤러(200) 사이의 차동 라인들을 통해 송수신될 수 있다.The transmitter 120 according to an exemplary embodiment may include a PAM encoder 121 , a pre-driver 122 , and a driver 123 . Transmitter 120 includes a-bit number of symbols according to PAM-n (n-level Pulse Amplitude Modulation),

It is possible to generate and output a DQ signal DQ capable of expressing data values of . For example, the transmitter 120 may generate and output a DQ signal (DQ) capable of expressing four data values (00, 01, 10, 11) including a 2-bit number of symbols according to PAM-4. there is. In FIG. 1 , the DQ signal DQ is implemented as a single signal and may be transmitted/received through a single line between the memory device 100 and the memory controller 200 . In some embodiments, the DQ signal DQ may be implemented as a differential signal and may be transmitted/received through differential lines between the memory device 100 and the memory controller 200 .

On the other hand, when the memory device 100 transmits the DQ signal DQ, it is essential to sufficiently secure an eye opening height and an eye opening width of the DQ signal DQ in a high frequency band. , at the same time, it may be required that power is efficiently consumed. The driver 123 of the transmitter 120 according to the technical concept of the present disclosure has improved linearity, and a sufficient opening height and eye opening width are ensured by using a power voltage lower than the power voltage supplied to other logic of the transmitter 120 . The DQ signal DQ may be output.

The command generator 240 of the memory controller 200 may generate a command CMD for controlling a memory operation in response to a request REQ received from a host (not shown) and provide it to the memory device 100 . . In an exemplary embodiment, the memory controller 200 includes a first setting signal (not shown) indicating the type of termination resistance of the memory controller 200 and a signaling mode (or a transmission mode) of the transmitter 120 of the memory device 100 . ) may be transmitted to the memory device 100 , from among second setting signals (not shown). The memory controller 200 transmits at least one of the first and second setting signals to the memory device 100 through a pin for transmitting the command CMD, a pin for transmitting an address, or a separate pin. can be transmitted In an exemplary embodiment, when the memory device 100 is a DRAM device, the memory controller 200 generates a mode register set signal including at least one of first and second setting signals to generate a memory may be provided to the device 100 .

When the command CMD is a read command, the transmitter 120 may receive the read data DATA from the memory cell array 140 . The PAM encoder 121 may encode the read data DATA based on the PAM-n method to generate encoded data (ENCa, hereinafter referred to as a first input signal) and provide it to the pre-driver 122 . . The pre-driver 122 may generate the second input signal ENCb based on the first input signal ENCa and the calibration code signal CALI_CODE and output the generated second input signal ENCb to the driver 123 . The calibration code signal CALI_CODE may be defined as a signal including a plurality of codes for adjusting driving strength of each of the plurality of pull-up circuits and the plurality of pull-down circuits included in the driver 123 . The second input signal ENCb is generated through a predetermined operation between the first input signal ENCa and the calibration code signal CALI_CODE, and the predetermined operation may vary depending on the configuration of the driver 123 . In an exemplary embodiment, the PAM encoder 121 and the pre-driver 122 may operate by receiving the first power voltage VDD2H. The PAM encoder 121 and the pre-driver 122 may be defined to operate in the first voltage domain VDM1. In an exemplary embodiment, the driver 123 uses the second power supply voltage VDDQ lower than the first power supply voltage VDD2H in response to the second input signal ENCb to the DQ signal DQ based on the PAM-n. ) can be printed. The driver 123 may be defined to operate in the second voltage domain VDM2 . In an exemplary embodiment, the first power supply voltage (VDD2H) and the second power supply voltage (VDDQ) may follow the specifications specified in the LPDDR5 standard specification, and accordingly, the first power supply voltage (VDD2H) is 1.05 (V), The second power voltage VDDQ may be set to 0.5 (V). In some embodiments, the first power voltage may be set to 'VDD2L' defined in the LPDDR5 standard specification at a level lower than 'VDD2H'. However, this is an exemplary embodiment and is not limited thereto, and the first power supply voltage VDD2H and the second power supply voltage VDDQ may be variously set according to the standard specification of the memory to which the exemplary embodiment of the present disclosure is applied. there is.

As such, the driver 123 provides a second power supply relatively lower than the first power supply voltage VDD2H provided to other logics of the transmitter 120 (eg, the PAM encoder 121 and the pre-driver 122 ). Power consumed in the output of the DQ signal DQ can be reduced by operating by receiving the voltage VDDQ, and the second input signal ENCb having improved signal characteristics by being previously driven from the pre-driver 122 is provided. By receiving it, it is possible to output the DQ signal DQ having good signal characteristics even at low power.

In an exemplary embodiment, the transmitter 120 may output the DQ signal DQ having a different swing period according to the type of the termination resistor of the memory controller 200 . The transmitter 120 receives the first setting signal from the memory controller 200, recognizes the type of the termination resistor of the memory controller 200 based on the first setting signal, and a DQ signal (DQ) having a swing period corresponding thereto. can be printed out.

In an exemplary embodiment, the transmitter 120 may output a DQ signal based on non-zero return as well as a DQ signal based on PAM-n. That is, the transmitter 120 may support the PAM-n signaling mode and the non-zero return signaling mode. The transmitter 120 may receive a second configuration signal from the memory controller 200 and may be set to any one of a PAM-n signaling mode and a non-zero return signaling mode based on the second configuration signal. For example, in the PAM-n signaling mode, the driver 123 outputs a PAM-n based DQ signal (DQ), and in the non-return-to-zero signaling mode, the driver 123 outputs a non-return-based DQ signal (DQ). ) can be printed.

The receiver 220 of the memory controller 200 may include an amplifier 221 , a PAM decoder 222 , and a deserializer 223 . For example, the memory device 100 and the memory controller 200 may transmit and receive a DQ signal DQ in a serial interfacing manner, and the memory controller 200 may communicate with a host (not shown) in a parallel interfacing manner. there is. However, this is an exemplary embodiment and is not limited thereto, and the memory controller 200 may communicate with the host (not shown) in a serial interfacing manner, and in this case, the configuration of the deserializer 226 may be omitted. there is.

The amplifier 221 may generate the RX signal RXS by amplifying the DQ signal DQ. Meanwhile, the amplifier 221 may have an input impedance for impedance matching with the transmitter 120 . In an exemplary embodiment, a termination resistor may be connected to the amplifier 221 of the receiver 220 for impedance matching with the transmitter 120 . As described above, since the transmitter 120 can output the DQ signal DQ having a different swing period according to the type of the termination resistor of the memory controller 200 (or the receiver 220), the type of termination resistor is It can be connected to a variety of memory controllers without limitation to smoothly perform data transmission/reception operations.

The PAM decoder 222 may receive the RX signal RXS from the amplifier 221 , and decode the RX signal RXS based on PAM-n to generate the decoded signal DES. In some embodiments, the receiver 220 may further include an equalizer (not shown) to perform equalization to compensate for distortion of the DQ signal DQ. The deserializer 223 may receive the decoding signal DES and convert it into RX data RXD. For example, the decoding signal DES may include a series of symbols each having a UI (Unit Interval) of '1/baud rate', and the deserializer 226 determines the number of x-bits (where x is An integer greater than 1) of RX data (RXD) can be output at a frequency of 'baud rate/n'. The receiver 220 may provide RX data RXD to a host (not shown).

In an exemplary embodiment, the transmitter 120 may be implemented to be included in the data input/output circuit (not shown) of the memory device 100 , and also the transmitter (not shown) included in the memory controller 200 according to the present disclosure. ideas can be applied.

2 is a diagram for describing a DQ signal DQ according to an exemplary embodiment of the present disclosure. Although FIG. 2 shows a DQ signal (DQ) based on PAM-4 having four levels, this is an exemplary embodiment premised for convenience of understanding, and is not limited thereto, and PAM- having eight or more levels It will be fully understood that the technical spirit of the present disclosure may also be applied to a DQ signal (DQ) based on n.

Referring to FIG. 2 , the lowest first level V1 of the DQ signal DQ may be mapped to 2-bit data '00', and the fourth highest level V4 of the DQ signal DQ is 2 - May be mapped to bit data '11'. Middle second and third levels V2 and V3 of the DQ signal DQ may be mapped to 2-bit data '01 and 10'. The above-described mapping of the voltage levels V1 to V4 and data is a mapping according to a gray code method, which is only an exemplary embodiment, and the mapping may be changed according to various purposes. For the convenience of understanding, the present disclosure is centered on the mapping relationship between the first to fourth levels V1 to V4 of the DQ signal DQ shown in FIG. 2 and 2-bit data in the context related to PAM-4 below. It will be fully understood that the technical idea of the present disclosure is not limited thereto.

3 is a block diagram illustrating a transmitter 120a according to an exemplary embodiment of the present disclosure. 3 shows an embodiment of the transmitter 120a that outputs a DQ signal (DQ) based on PAM-4, which is only an exemplary embodiment, and the technical idea of the content to be described below is a higher-dimensional PAM- It is clear that it can also be applied to a DQ signal (DQ) based on n. 2 may be further referred to for better understanding in FIG. 3 .

Referring to FIG. 3 , the transmitter 120a may include a PAM encoder 121a , a pre-driver 122a , a driver 123a , and a calibration circuit 124a . The driver 123a may include first and second driving circuits 123a_1 and 123a_2 . The first driving circuit 123a_1 includes a first pull-up circuit 123a_11 directly provided with the second power voltage VDDQ and a grounded first pull-down circuit 123a_12 , and a second driving circuit 123a_2 ) may include a second pull-up circuit 123a_21 to which the second power voltage VDDQ is directly provided and a grounded second pull-down circuit 123a_22 . In an exemplary embodiment, the PAM encoder 121a and the pre-driver 122a receive a first power supply voltage VDD2H, and the first and second driving circuits 123a_1 and 123a_2 have a first power supply voltage VDD2H. A second power voltage VDDQ different from that of VDDQ may be supplied. In an exemplary embodiment, the second power voltage VDDQ may be lower than the first power voltage VDD2H.

The PAM encoder 121a receives the read data DATA from the memory cell array 140 ( FIG. 1 ), and maps between four voltage levels of the DQ signal DQ based on PAM-4 and 2-bit data. A first input signal including first and second Most Significant Bit (MSB) signals (S1_MSBa, S2_MSBa) and first and second Least Significant Bit (LSB) signals (S1_LSBa, S2_LSBa) is generated based on the relationship. 1 can be generated using the power supply voltage (VDD2H). Specifically, the first MSB signal S1_MSBa is a signal for activating the first pull-up circuit 123a_11 , and the second MSB signal S2_MSBa is a signal for activating the first pull-down circuit 123_21 , and , the first LSB signal S1_LSBa may be a signal for activating the second pull-up circuit 123a_21 , and the second LSB signal S2_LSBa may be a signal for activating the second pull-down circuit 123a_22 . Hereinafter, activation of a circuit may refer to a state in which at least one of transistors included in a corresponding circuit is turned on. In addition, the deactivation of the circuit may mean that all transistors included in the circuit are turned off.

For example, the PAM encoder 121a may output first and second pull-down circuits to output the DQ signal DQ having the first level V1 when the read data DATA is bit data of '00'. The DQ generates the first input signals S1_MSBa, S2_MSBa, S1_LSBa, and S2_LSBa for activating the 123a_12 and 123a_22 and has the second level V2 when the read data DATA is bit data of '01'. Generates and reads first input signals S1_MSBa, S2_MSBa, S1_LSBa, and S2_LSBa for activating the first pull-down circuit 123a_12 and the second pull-up circuit 123a_21 to output the signal DQ The first pull-up circuit 123a_11 and the second pull-down circuit 123a_22 to output the DQ signal DQ having the third level V3 when the data DATA is bit data of '10' Generates first input signals S1_MSBa, S2_MSBa, S1_LSBa, and S2_LSBa for activating Thus, first input signals S1_MSBa, S2_MSBa, S1_LSBa, and S2_LSBa for activating the first and second pull-up circuits 123a_11 and 123a_21 may be generated.

The calibration circuit 124a includes a pull-up code for adjusting the driving strength of each of the first and second pull-up circuits 123a_11 and 123a_21 and the first and second pull-down circuits 123a_12 and 123a_22. A calibration code signal including CODE_PUa) and a pull-down code (CODE_PDa) may be generated. The calibration circuit 124a includes a replica circuit having the same configuration as the driver 123a, and is calibrated so that the DQ signal DQ has a target level separation mismatch ratio using the replica circuit. Code signals CODE_PUa and CODE_PDa may be generated. In an exemplary embodiment, the pull-up code CODE_PUa is a signal for determining the number of turned-on transistors among a plurality of first transistors included in the first and second pull-up circuits 123a_11 and 123a_21, respectively. , and the pull-down code CODE_PDa may be a signal for determining the number of turned-on transistors among a plurality of second transistors included in the first and second pull-down circuits 123a_12 and 123a_22, respectively. That is, the driving strength of the first and second pull-up circuits 123a_11 and 123a_21 and the first and second pull-down circuits 123a_12 and 123a_22 is adjusted by the calibration code signal so that the DQ signal DQ is It can be controlled so that the target level is precisely reached. The calibration circuit 124a may determine in advance the calibration code signals CODE_PUa and CODE_PDa by performing a predetermined calibration operation, such as when the memory device is powered on or in an idle period of the memory device.

The pre-driver 122a mutually calculates the first input signals S1_MSBa, S2_MSBa, S1_LSBa, and S1_LSBb received from the PAM encoder 121a using the first power voltage VDD2H and the calibration code signals CODE_PUa and CODE_PDa. and output the second input signal including the third and fourth MSB signals S1_MSBb and S2_MSBb and the third and fourth LSB signals S1_LSBb and S2_LSBb generated as a result of the operation to the driver 123a. there is. A calculation method for generating the second input signals S1_MSBb, S2_MSBb, S1_LSBb, and S2_LSBb of the pre-driver 122a may vary depending on the configuration of the driver 123a, and a specific embodiment thereof will be described later.

The first pull-up circuit 123a_11 may receive the third MSB signal S1_MSBb and be activated in response thereto, and the driving strength may be determined. The second pull-up circuit 123a_21 may receive the third LSB signal S1_LSBb and be activated in response thereto, and the driving strength may be determined. The first pull-down circuit 123a_12 may receive the fourth MSB signal S2_MSBb and be activated in response thereto, and the driving strength may be determined. The second pull-down circuit 123a_22 may receive the fourth LSB signal S2_LSBb and be activated in response thereto, and the driving strength may be determined.

The driver 123a uses the second power supply voltage VDDQ through the configuration of the first and second pull-up circuits 123a_11 and 123a_21 and the first and second pull-down circuits 123a_12 and 123a_22. A DQ signal DQ may be output.

4A and 4B are circuit diagrams illustrating exemplary implementations of the driver 123a of FIG. 3 .

Referring to FIG. 4A , the driver 123aa may include first and second pull-up circuits 123aa_11 and 123aa_21 , and first and second pull-down circuits 123aa_12 and 123aa_22 . The first pull-up circuit 123aa_11 includes 'o (where o is an integer greater than or equal to 2)' pMOS transistors pTR_a1 to pTR_ao, and the first pull-down circuit 123aa_12 includes 'o' nMOS transistors. It may include transistors nTR_a1 to nTR_ao. The second pull-up circuit 123aa_21 includes 'p' (where p is an integer greater than or equal to 2) pMOS transistors pTR_b1 to pTR_bp, and the second pull-down circuit 123aa_22 includes 'p' nMOS transistors. It may include transistors nTR_b1 to nTR_bp.

In an exemplary embodiment, the pMOS transistors pTR_a1 to pTR_ao of the first pull-up circuit 123aa_11 may receive the third MSB signal S1_MSBba through a gate terminal. The third MSB signal S1_MSBba may include 'o' signals S1_MSBba1 to S1_MSBbao respectively input to the pMOS transistors pTR_a1 to pTR_ao.

In an exemplary embodiment, the nMOS transistors nTR_a1 to nTR_ao of the first pull-down circuit 123aa_12 may receive the fourth MSB signal S2_MSBba through a gate terminal. The fourth MSB signal S2_MSBba may include 'o' signals S2_MSBba1 to S2_MSBbao respectively input to the nMOS transistors nTR_a1 to nTR_ao.

In an exemplary embodiment, the pMOS transistors pTR_b1 to pTR_bp of the second pull-up circuit 123aa_21 may receive the third LSB signal S1_LSBba through a gate terminal. The third LSB signal S1_LSBba may include 'p' signals S1_LSBba1 to S1_LSBbap respectively input to the pMOS transistors pTR_b1 to pTR_bp.

In an exemplary embodiment, the nMOS transistors nTR_b1 to nTR_bp of the second pull-down circuit 123aa_22 may receive the fourth LSB signal S2_LSBba through a gate terminal. The fourth LSB signal S2_LSBba may include 'p' signals S2_LSBba1 to S2_LSBbap respectively input to the nMOS transistors nTR_b1 to nTR_bp.

Meanwhile, the first pull-up circuit 123aa_11 and the first pull-down circuit 123aa_12 are implemented to have greater driving strength than the second pull-up circuit 123aa_21 and the second pull-down circuit 123aa_22, respectively. can be For example, the number of transistors included in the first pull-up circuit 123aa_11 and the first pull-down circuit 123aa_12 is included in the second pull-up circuit 123aa_21 and the second pull-down circuit 123aa_22 There may be more than the number of transistors. In some embodiments, the number of transistors included in the first pull-up circuit 123aa_11 and the first pull-down circuit 123aa_12 and the second pull-up circuit 123aa_21 and the second pull-down circuit 123aa_22 Although the number of transistors included is the same, the transistors included in the first pull-up circuit 123aa_11 and the first pull-down circuit 123aa_12 include the second pull-up circuit 123aa_21 and the second pull-down circuit ( 123aa_22) may be implemented to have a characteristic that more current can flow under the same condition than the transistors included in the transistor.

Some of the first and second pull-up circuits 123aa_11 and 123aa_21 and the first and second pull-down circuits 123aa_12 and 123aa_22 of the driver 123aa include second input signals S1_MSBba, S2_MSBba, S1_LSBba, S2_LSBba), the number of transistors activated in response to and turned on for each of the activated circuits is determined, so that the PAM-4 based DQ signal DQ may be output.

Referring further to FIG. 4B , the configuration of the first and second pull-up circuits 123ab_11 and 123ab_21 of the driver 123ab may be different from that of the driver 123aa of FIG. 4A . In an exemplary embodiment, the first pull-up circuit 123ab_11 includes 'o' nMOS transistors nTR_a11 to nTR_ao1 , and the second pull-up circuit 123ab_21 includes 'p' nMOS transistors ( nTR_b11 to nTR_bp1) may be included. The nMOS transistors nTR_a11 to nTR_ao1 of the first pull-up circuit 123ab_22 receive the third MSB signal S1_MSBbb through a gate terminal, and the nMOS transistors nTR_b11 to nTR_b11 of the second pull-up circuit 123ab_21 nTR_bp1) may receive the third LSB signal S1_LSBbb through the gate terminal. The third MSB signal S1_MSBbb includes 'o' signals S1_MSBbb1 to S1_MSBbbo respectively input to the nMOS transistors nTR_a11 to nTR_ao1 of the first pull-up circuit 123ab_11, and the third LSB signal ( S1_LSBbb may include 'p' signals S1_LSBbb1 to S1_LSBbbp respectively input to the nMOS transistors nTR_b11 to nTR_bp1 of the second pull-up circuit 123ab_21 .

In the technical idea of the present disclosure, since the driver 123ab outputs the DQ signal DQ based on the second input signals S1_MSBbb, S2_MSBba, S1_LSBbb, and S2_LSBba having good signal characteristics driven through the pre-driver, the first and The second pull-up circuits 123ab_11 and 123ab_21 may be configured with an nMOS transistor (or an n-channel MOSFET (Metal-Oxide Semiconductor Field Effect Transistor)). The driver 123ab through the configuration shown in FIG. 4B . can be reduced, which may be advantageous in terms of designing a memory device.

5A and 5B are diagrams illustrating example implementations of the pre-driver 122a of FIG. 3 . FIG. 5A shows an implementation example of the pre-driver 122aa connected to the driver 123aa illustrated in FIG. 4A , and FIG. 5B is an implementation example of the pre-driver 122ab connected with the driver 123ab illustrated in FIG. 4B . shows an example.

Referring to FIG. 5A , the pre-driver 122aa may include a plurality of NAND circuits. In an exemplary embodiment, the plurality of NAND circuits includes a plurality of transistors included in the driver 123aa (eg, the plurality of transistors pTR_a1 to pTR_ao, pTR_b1 to pTR_bp, nTR_a1 to nTR_ao, nTR_b1 to nTR_bp of FIG. 4A ). )) respectively, and an output terminal of the NAND circuit may be connected to a gate terminal of a corresponding transistor. For example, the plurality of NAND circuits may include a first NAND circuit 122aa_1 . Specifically, the first NAND circuit 122aa_1 may correspond to the first pMOS transistor pTR_a1 included in the first pull-up circuit 123aa_11 of the driver 122aa ( FIG. 4A ). The first NAND circuit 122aa_1 receives the first MSB signal S1_MSBa and the pull-up code CODE_PUa<1>, and performs a NAND operation to generate the first signal S1_MSBba1 included in the third MSB signal. 1 It can output to the gate terminal of the pMOS transistor pTR_a1. In an exemplary embodiment, when the first pMOS transistor pTR_a1 is turned on by the first signal S1_MSBba1 , the gate-source voltage of the first pMOS transistor pTR_a1 may be greater than the drain-source voltage. Through this, the linearity of the first pMOS transistor pTR_a1 is improved, so that the driver 123aa may output a DQ signal having good characteristics.

Referring to FIG. 5B , the pre-driver 122ab may include a plurality of NOR circuits. In an exemplary embodiment, the plurality of NOR circuits includes a plurality of transistors included in the driver 123ab (eg, the plurality of transistors nTR_a11 to nTR_ao1, nTR_b11 to nTR_bp1, nTR_a1 to nTR_ao, nTR_b1 to nTR_bp of FIG. 4B ). )) respectively, and an output terminal of the NOR circuit may be connected to a gate terminal of a corresponding transistor. For example, the plurality of NOR circuits may include a first NOR circuit 122ab_1 . Specifically, the first NOR circuit 122ab_1 may correspond to the first nMOS transistor nTR_a11 included in the first pull-up circuit 123ab_11 of the driver 122ab ( FIG. 4B ). The first NOR circuit 122ab_1 receives the first MSB signal S1_MSBa and the pull-up code CODE_PUa<1>, and performs a NOR operation to generate the first signal S1_MSBbb1 included in the third MSB signal. 1 It can output to the gate terminal of the nMOS transistor nTR_a11. In an exemplary embodiment, when the first pMOS transistor pTR_a1 is turned on by the first signal S1_MSBba1 , the gate-source voltage of the first nMOS transistor nTR_a11 may be greater than the drain-source voltage. Through this, the linearity of the first nMOS transistor nTR_a11 is improved, so that the driver 123ab may output a DQ signal having good characteristics.

6A to 6C are memory systems 10a to 10c for explaining the memory devices 100a to 100c according to exemplary embodiments of the present disclosure connected to the memory controllers 200a to 200c having various types of termination resistors. It is a block diagram showing

Referring to FIG. 6A , the memory system 10a may include a memory device 100a and a memory controller 200a. The receiver 220a may include an amplifier 221a and a first type of termination resistor Ra connected to an input terminal of the amplifier 221a. The first type may be referred to as a grounding type because one end of the termination resistor Ra is grounded. The memory device 100a includes a transmitter 120a according to an exemplary embodiment of the present disclosure, the pre-driver 122a operates using the first power supply voltage VDD2H, and the driver 123a operates the second power supply voltage VDD2H. By operating using the power supply voltage VDDQ, the DQ signal having the first swing period may be output to the memory controller 200a.

Referring to FIG. 6B , the memory system 10b may include a memory device 100b and a memory controller 200b. The receiver 220b may include an amplifier 221b and a second type of termination resistor Rb connected to an input terminal of the amplifier 221b. The second type may be referred to as a pseudo open drain type because one end of the termination resistor Rb is connected to the second power voltage VDDQ. The memory device 100b includes a transmitter 120b according to an exemplary embodiment of the present disclosure, the pre-driver 122b operates using the first power supply voltage VDD2H, and the driver 123b operates the second By operating using the power supply voltage VDDQ, the DQ signal having the second swing period may be output to the memory controller 200b.

Referring to FIG. 6C , the memory system 10c may include a memory device 100c and a memory controller 200c. The receiver 220c may include an amplifier 221c and third-type termination resistors Rc connected to an input terminal of the amplifier 221c. The third type may be referred to as a center tab termination type because one end of one of the termination resistors Rc is connected to the second power voltage VDDQ and the other end is grounded. The memory device 100c includes a transmitter 120c according to an exemplary embodiment of the present disclosure, the pre-driver 122c operates using the first power supply voltage VDD2H, and the driver 123c operates the second power supply voltage VDD2H. By operating using the power voltage VDDQ, the DQ signal having the third swing period may be output to the memory controller 200c.

7A to 7C are diagrams for explaining first to third swing sections of the DQ signal in FIGS. 6A to 6C .

In FIG. 7A , the DQ signal output from the transmitter 120a of FIG. 6A is shown, the lowest first level (V1a) of the DQ signal corresponds to the ground voltage (VSS), and the fourth highest level (V4a) of the DQ signal is shown. ) may correspond to '1/2' of the second power voltage VDDQ. The intermediate second and third levels V2a and V3a of the DQ signal may correspond to '1/6' and '1/3' of the second power voltage VDDQ, respectively. That is, the DQ signal may swing to any one of the first to fourth levels V1a to V4a in the first swing period between '1/2' of the ground voltage VSS and the second power voltage VDDQ. . Meanwhile, the levels Vaa to Vca used in the calibration circuit 124a ( FIG. 3 ) to distinguish the first to fourth levels V1a to V4a will be described later.

In FIG. 7B , the DQ signal output from the transmitter 120b of FIG. 6B is shown, and the lowest first level V1b of the DQ signal corresponds to '1/2' of the second power supply voltage VDDQ, and the DQ signal The highest fourth level V4b may correspond to the second power voltage VDDQ. The intermediate second and third levels V2b and V3b of the DQ signal may correspond to '2/3' and '5/6' of the second power voltage VDDQ, respectively. That is, the DQ signal may swing to any one of the first to fourth levels V1b to V4b in the second swing period between '1/2' of the second power supply voltage VDDQ and the second power supply voltage VDDQ. can Meanwhile, the levels Vab to Vcb used in the calibration circuit 124b ( FIG. 3 ) to distinguish the first to fourth levels V1b to V4b will be described later.

In FIG. 7C , the DQ signal output from the transmitter 120c of FIG. 6C is shown, and the lowest first level V1c of the DQ signal corresponds to '1/4' of the second power supply voltage VDDQ, and the DQ signal The highest fourth level V4c may correspond to '3/4' of the second power voltage VDDQ. The intermediate second and third levels V2c and V3c of the DQ signal may correspond to '5/12' and '7/12' of the second power voltage VDDQ, respectively. That is, the DQ signal is applied to the first to fourth levels V1c to V4c in the third swing period between '1/4' of the second power supply voltage VDDQ and '3/4' of the second power supply voltage VDDQ. ) can be swung to any one of the Meanwhile, the levels Vac to Vcc used in the calibration circuit 124b ( FIG. 3 ) to distinguish the first to fourth levels V1c to V4c will be described later.

8 is a diagram for explaining the transmitter 120d of the memory device 100d that outputs a DQ signal having a swing period according to the type of the termination resistor 224d of the memory controller 200d according to an exemplary embodiment of the present disclosure; It is a block diagram of the memory system 10d.

Referring to FIG. 8 , a memory system 10d may include a memory device 100d and a memory controller 200d. The memory device 100d may include a transmitter 120d, and the transmitter 120d may include a pre-driver 122d, a driver 123d, and a calibration circuit 124d. The memory controller 200d may include a receiver 220d, and the receiver 220d may include an amplifier 221d and a termination resistor 224d. The memory controller 200d may provide the first set signal TE_Type indicating the type of the termination resistor 224d to the memory device 100d in various ways. For example, the memory controller 200d may provide the first setting signal TE_Type to the memory device 100d through a pin for transmitting a command, a pin for transmitting an address, or a separate pin.

The calibration circuit 124d according to an exemplary embodiment may receive the first setting signal TE_Type and perform an operation to generate the calibration code signal CALI_CODE based thereon. That is, the calibration circuit 124d may generate the calibration code signal CALI_CODE to generate a DQ signal matching the type of the termination resistor 224d of the memory controller 200d to which the memory device 100d is connected. . 7A to 7C , the DQ signal may have a different swing period depending on the type of the termination resistor 224d of the memory controller 200d. When the calibration circuit 124d generates the calibration code signal CALI_CODE, it is terminated. The levels Vaa to Vca, Vab to Vcb, Vac to Vcc, and FIGS. 7A to 7C ) used may vary according to the type of the resistor 224d. The calibration circuit 124d may include a voltage regulator 124d_7 , and the voltage regulator 124d_7 may adjust levels based on the first setting signal TE_Type, and use the adjusted levels to the calibration code signal CALI_CODE ) can be created. The pre-driver 122d and the driver 123d receive the first and second power voltages VDD2H and VDDQ, respectively, and generate and output a DQ signal based on the calibration code signal CALI_CODE. there is.

9 is a block diagram of a memory system 10e for illustrating a transmitter 120e of a memory device 100e supporting a PAM-n signaling mode and a non-return-to-zero signaling mode according to an exemplary embodiment of the present disclosure; 10A to 10C are diagrams for explaining first to third swing sections of a DQ signal in a non-zero return signaling mode.

Referring to FIG. 9 , a memory system 10e may include a memory device 100e and a memory controller 200e. The memory device 100e may include a transmitter 120e, and the transmitter 120e may include a pre-driver 122e and a driver 123e. The memory controller 200e may include a receiver 220e, and the receiver 220e may include an amplifier 221e and a termination resistor 224e. The transmitter 120e may support the PAM-n signaling mode and the non-zero return signaling mode, and the memory controller 200e sends a second setting signal MODE_SEL for setting the signaling mode of the transmitter 120e to the transmitter 120e. can be provided to The transmitter 120e may be set to operate in any one of the PAM-n signaling mode and the non-zero return signaling mode in response to the second setting signal MODE_SEL. Transmitter 120e shown in FIG. 9 is an exemplary embodiment, but is not limited thereto, and transmitter 120e further includes a calibration circuit, wherein the calibration circuit is a calibration code for generating a DQ signal based on non-return to zero. signal can be generated.

Also, in an exemplary embodiment, the transmitter 120e may output a non-zero return-based DQ signal having a different swing period according to the type of the termination resistor 224e of the memory controller 200e.

Referring further to FIG. 10A , when the type of the termination resistor 224e of the memory controller 200e is the ground type described in FIG. 6A , the DQ signal output from the transmitter 120e is the ground voltage VSS and the second power supply. The swing may be performed in the first swing period between '1/2' of the voltage VDDQ.

Referring further to FIG. 10B , when the type of the termination resistor 224e of the memory controller 200e is the pseudo open-drain type described in FIG. 6B , the DQ signal output from the transmitter 120e is the second power supply voltage VDDQ. The swing may be performed in a second swing period between '1/2' and the second power voltage VDDQ.

Referring further to FIG. 10C , when the type of the termination resistor 224e of the memory controller 200e is the center tap termination type described in FIG. 6C , the DQ signal output from the transmitter 120e is the second power voltage (VDDQ) The swing may be performed in a third swing period between '1/4' of '1/4' and '3/4' of the second power voltage VDDQ.

Returning to FIG. 9 , the transmitter 120e may additionally receive a first setting signal indicating the type of the termination resistor 224e from the memory controller 200e for the operation of FIGS. 10A to 10C .

11 is a block diagram illustrating a transmitter 120f that outputs a PAM-n based DQ signal according to an exemplary embodiment.

Referring to FIG. 11 , the transmitter 120f may include a PAM encoder 121f, a pre-driver 122f, a driver 123f, and a calibration circuit 124f. The driver 123f may include first to kth (f is an integer greater than or equal to 2) driving circuits 123f_1 to 123f_k. In some embodiments, the number of driving circuits of the driver 123f varies depending on the PAM order 'n', or has a fixed number of driving circuits, and the number of driving circuits activated according to the PAM order 'n' is different. It can be implemented so that

The first driving circuit 123f_1 includes a first pull-up circuit 123f_11 directly provided with the second power voltage VDDQ and a grounded first pull-down circuit 123f_12 , and a k-th driving circuit 123f_k ) may include a k-th pull-up circuit 123f_k1 to which the second power voltage VDDQ is directly provided and a grounded k-th pull-down circuit 123f_k2 . The second to k-th driving circuits 123f_2 to 123f_k-1 may be implemented in the same configuration as the first and k-th driving circuits 123f_1 and 123f_k.

The PAM encoder 121f may encode the read data DATA using the first power supply voltage VDD2H to generate the first input signals S1_PU1a to S1_PUka and S2_PD1a to S2_PDka, and provide it to the pre-driver 122f. there is. The calibration circuit 124f performs a calibration operation in advance so that the DQ signal DQ has a level separation mismatch ratio corresponding to the order 'n' of the PAM, and provides the determined calibration code signals CODE_PUb and CODE_PDb to the pre-driver 122f. can provide The pre-driver 122f generates second input signals S1_PU1b to S1_PUkb, S2_PD1b to S2_PDkb based on the first input signals S1_PU1a to S1_PUka, S2_PD1a to S2_PDka and the calibration code signals CODE_PUb and CODE_PDb. One power supply voltage VDD2H may be used and provided to the driver 123f. The driver 123f may output the PAM-n-based DQ signal DQ using the second power voltage VDDQ in response to the second input signals S1_PU1b to S1_PUkb and S2_PD1b to S2_PDkb.

12A and 12B are diagrams for explaining a characteristic change of a DQ signal according to an operating environment of a memory device.

Referring to FIG. 12A , the second and third levels V2' and V3', which are intermediate levels, of the DQ signal may be lower than ideal levels V2 and V3 according to the operating environment of the memory device. Accordingly, when the second and third levels V2' and V3' of the DQ signal are higher than before, the DQ signal has a target level separation mismatch ratio, so that it is possible to sufficiently secure the eye opening height. However, since this is only an exemplary embodiment, the present invention is not limited thereto, and various situations in which the level of the DQ signal needs to be increased or decreased may occur.

12B , the DQ signal may transition from the first level V1 to the fourth level V4 and from the fourth level V4 to the first level V1 depending on the operating environment of the memory device. When the slope is low, the width W1 maintaining the fourth level V4 may be too narrow. Accordingly, the eye opening width of the DQ signal can be sufficiently secured by increasing the slope of the DQ signal to have a sufficient width W2 for the DQ signal.

In order to compensate for the degradation of the characteristics of the DQ signal generated in FIGS. 12A and 12B , the driver according to an exemplary embodiment of the present disclosure may include additional pull-up circuits or additional pull-down circuits.

13A and 13B are block diagrams of transmitters 120ga and 120gb illustrating implementations of drivers 123ga and 123gb that further include additional pull-up circuits or additional pull-down circuits.

Referring to FIG. 13A , the transmitter 120ga may include a PAM encoder 121g, a pre-driver 122ga, and a driver 123ga. The driver 123ga may include first and second driving circuits 123g_1 and 123g_2 and an additional driving circuit 123g_3a. The additional driving circuit 123g_3a may include first and second additional pull-up circuits 123g_31 and 123g_32 to which the second power voltage VDDQ is directly provided. The pre-driver 122ga generates second input signals S1_MSBb, S2_MSBb, S1_LSBb, S2_LSBb, S1_LSBc, S1 based on the first input signals S1_MSBa, S2_MSBb, S1_LSBa, S2_LSBb and the calibration code signal CODE_ga. can The first and second additional pull-up circuits 123g_31 and 123g_32 respectively receive the fifth MSB signal S1_MSBc and the fifth LSB signal S1_LSBc, and in response thereto, the DQ signal DQ has a sufficient eye opening height. In addition, the first and second pull-up circuits 123g_11 and 123g_21 may be supplemented by adjusting intermediate levels and a transition slope of the DQ signal DQ to secure a width.

Referring further to FIG. 13B , the driver 123gb may include grounded first and second additional pull-down circuits 123g_33 and 123g_34 as compared to the driver 123ga of FIG. 13A , the additional driving circuit 123g_3b is grounded. can The pre-driver 122gb generates second input signals S1_MSBb, S2_MSBb, S1_LSBb, S2_LSBb, S2_LSBc, S2_LSBc based on the first input signals S1_MSBa, S2_MSBb, S1_LSBa, S2_LSBb and the calibration code signal CODE_gb. can The first and second additional pull-down circuits 123g_32 and 123g_34 receive the sixth MSB signal S2_MSBc and the sixth LSB signal S2_LSBc, respectively, and in response thereto, the DQ signal DQ has a sufficient eye opening height. In addition, the first and second pull-down circuits 123g_12 and 123g_22 may be supplemented by adjusting intermediate levels and a transition slope of the DQ signal DQ to secure a width.

The additional driving circuits 123g_3a and 123g_3b shown in FIGS. 13A and 13B are merely exemplary embodiments, and are not limited thereto. The DQ signal ( DQ) can be implemented in various ways to improve the characteristics.

14A and 14B are block diagrams illustrating calibration circuits 124a and 124b according to an exemplary embodiment of the present disclosure. 14A and 14 illustrate implementations of the calibration circuits 124a and 124b corresponding to the configuration of the driver 120ga of FIG. 13A , which are only exemplary embodiments, and are not limited thereto, depending on the configuration of the driver. The calibration circuits 124a and 124b may be implemented in various ways.

Referring to FIG. 14A , the calibration circuit 124a includes first to fourth pull-up replica circuits 124a_11 , 124a_12 , 124a_21 , 124a_22 , and first to fourth pull-down replica circuits 124a_13 , 124a_14 , 124a_23 . , 124a_24 , first and second additional pull-up replica circuits 124a_31 , 124a_32 , multiplexer 124a_4 , first and second comparators 124a_51 , 124a_52 , pull-up code generator 124a_61 , pull - It may include a down code generator (124a_62).

The first and third pull-up replica circuits 124a_11 and 124a_21 are circuits replicated from the first pull-up circuit 123g_11 of FIG. 13A , and the second and fourth pull-up replica circuits 124a_12 and 124a_22 ) may be a circuit duplicated from the second pull-up circuit 123g_21 of FIG. 13A . The first and third pull-down replica circuits 124a_13 and 124a_23 are circuits cloned from the first pull-down circuit 123g_12 of FIG. 13A , and the second and fourth pull-down replica circuits 124a_14 and 124a_24 ) may be a circuit duplicated from the second pull-down circuit 123g_22 of FIG. 13A . The first and second additional pull-up replica circuits 124a_31 and 124a_32 may be circuits replicated from the first and second additional pull-up circuits 123g_31 and 123g_32 of FIG. 13A . The duplicated circuit refers to a circuit that includes transistors having the same characteristics as transistors included in the target circuit or has a connection configuration in which the transistors of the target circuit have the same connection relationship.

The pull-up code generator 124a_61 generates a pull-up code PU_CODE<n:1> and provides it to the first to fourth pull-up replica circuits 124a_11 , 124a_12 , 124a_21 , 124a_22 , and provides an additional pull The -up code ADD_PU_CODE<k:1> may be generated and provided to the first and second additional pull-up replica circuits 124a_31 and 124a_32. The pull-down code generator 124a_62 may generate the pull-down code PD_CODE<m:1> and provide it to the first to fourth pull-down replica circuits 124a_13 , 124a_14 , 124a_23 , and 124a_24 .

The first comparator 124a_51 may compare the signal generated in the first part PART1 and the first reference voltage, and provide the comparison result to the pull-up code generator 124a_61 . A resistance RZQ for calibration may be connected to an input terminal of the first comparator 124a_51 through an external pin (eg, a ZQ pin). For example, the resistor RZQ may have a resistance value of 40 [ohm]. The second comparator 124a_52 may compare the signal generated in the second part PART2 and the second reference voltage, and provide the comparison result to the pull-down code generator 124a_62 . The first part PART1 includes first and second pull-up replica circuits 124a_11 and 124a_12 , first and second pull-down replica circuits 124a_13 and 124a_14 , first and second additional pull-ups It is a concept including replica circuits 124a_31 and 124a_32, and the second part PART2 includes third and fourth pull-up replica circuits 124a_21 and 124a_22, and third and fourth pull-down replica circuits ( It may be a concept including 124a_23 and 124a_24).

The multiplexer 124a_4 may select any one of the first to third voltages Va, Vb, and Vc and provide it to the first comparator 124a_51 as the first reference voltage VREF1. The first to third voltages Va, Vb, and Vc may have levels necessary to check the level of the DQ signal. For example, in the case of FIG. 7A , the first voltage Va corresponds to a level Vaa for distinguishing the second level V2a from the third level V3a, and the second voltage Vb is Corresponds to the level Vba for distinguishing the first level V1a from the second level V2a, and the third voltage Vc is the level for distinguishing the third level V3a and the fourth level V4a. Vca). Meanwhile, the second reference voltage VREF2 may correspond to the first voltage Va. In some embodiments, the calibration circuit 124a may further include a reference voltage generator (not shown) that generates at least one of the first to third voltages Va, Vab, and Vc.

The pull-up code generator 124a_61 and the pull-down code generator 124a_62 generate a pull-up code (PU_CODE<n:1>) according to the levels of signals output from the first and second parts PART1 and PART2. , by changing the values of the pull-down code (PD_CODE<m:1>) and the additional pull-up code (ADD_PU_CODE<k:1>) so that the DQ signal has a target level separation mismatch ratio. can decide In some embodiments, each bit of the pull-up code (PU_CODE<n:1>), the pull-down code (PD_CODE<m:1>) and the additional pull-up code (ADD_PU_CODE<k:1>) is the same or different. Meanwhile, the pull-up code (PU_CODE<n:1>), the pull-down code (PD_CODE<m:1>), and the additional pull-up code (ADD_PU_CODE<k:1>)) are 'n' and 'm, respectively. Although it has been described as a code composed of ' and 'k' bits, this is only an exemplary embodiment, and may be set to have a various number of bits according to the configuration of the calibration circuit 124a.

Referring further to FIG. 14B , the calibration circuit 124b may further include a voltage regulator 124a_7 as compared to FIG. 14A . As shown in FIGS. 7A to 7C , when the type of the termination resistor of the memory controller is changed, the swing period of the DQ signal is different, so the level of the first and second reference voltages VREF1 and VREF2 used by the calibration circuit 124b is also a memory It may depend on the type of termination resistor of the controller.

As described above in FIG. 8 , in an exemplary embodiment, the voltage regulator 124a_7 changes the levels of the first to third voltages Va, Vb, and Vc based on the first setting signal TE_type to obtain a multiplexer. (124a_4) can be provided. For example, assuming that the levels of the first to third voltages Va, Vb, and Vc correspond to 'Vaa', 'Vba', and 'Vca' of FIG. 7A , respectively, the voltage regulator 124a_7 is shown in FIG. In 7b, the levels of the first to third voltages Va, Vb, and Vc may be adjusted to 'Vab', 'Vbb', and 'Vcb', respectively, and in FIG. 7C , the first to third voltages Va , Vb, Vc) can be adjusted to 'Vac', 'Vbc', and 'Vcc', respectively.

The transmitter according to an exemplary embodiment of the present disclosure may output a DQ signal having various swing sections according to the type of the termination resistor of the memory controller through the calibration circuit 124b as shown in FIG. 14B .

15A to 15D are diagrams for explaining a calibration method different from the calibration method of FIG. 14A according to an exemplary embodiment of the present disclosure. Hereinafter, for convenience of understanding, it is assumed that the calibration is for generating the DQ signal of FIG. 7A . Hereinafter, an embodiment using the first and second calibration circuits 124c_1 and 124c_2 having a configuration different from that of FIGS. 14A and 14B and a resistance RZQ' of 240 (ohm) will be mainly described. However, this is only an exemplary embodiment, and a resistor having a resistance value (eg, 120 (ohm)) defined in various memory standard specifications may be connected to the first calibration circuit 124c_1, and even in this case, It is clear that technical ideas can be applied.

Referring to FIG. 15A , the first calibration circuit 124c_1 is connected to a resistance RZQ' of 240 (ohm) through a ZQ pin, and the first comparator 124c_31 corresponds to half of the second power voltage VDDQ. voltage can be received. The first calibration circuit 124c_1 may use the first comparator 124c_31 to calibrate the first pull-down code PD_CODE_1 so that the pull-down replica circuit 124c_11 is set to 240 (ohm). The first pull-down code PD_CODE_1 may correspond to a reference code for generating other pull-down codes.

15B , the first calibration circuit 124c_1 and the resistor RZQ' are disconnected, and the first calibration circuit 124c_1 uses the first comparator 124c_31 to pull-up the replica circuit 124c_21. ) may be calibrated so that the first pull-up code PU_CODE1 is set to 240 (ohm). The first pull-up code PU_CODE1 may correspond to a reference code for generating other pull-up codes.

Referring further to FIG. 15C , the second comparator 124c_62 receives the third voltage Vc, and the second calibration circuit 124c_2 provides a first pull-down code PD_CODE1 and a first pull-up code PD_CODE1. ) based on the second pull-down code PD_CODE2 for setting the first pull-down replica circuit 124c_12 to 120 (ohm), the second pull-down replica circuit 124c_22 to 40 (ohm) A third pull-down code PD_CODE3 to be set and a second pull-up code PU_CODE2 to set the pull-up replica circuit 124c_32 to 60 (ohm) may be generated. Thereafter, the second calibration circuit 124c_2 performs the second comparator 124c_62 to adjust a predetermined level (eg, the third level V3a of FIG. 7A ) so that the DQ signal has a target level separation mismatch ratio. may be used to calibrate the first additional pull-up code ADD_PU_CODE1 provided to the first additional pull-up replica circuit 124c_42 . Meanwhile, the second additional pull-up replica circuit 124a_32 may be in a deactivated state.

15D , the second comparator 124c_62 receives the second voltage Vb, and the calibration circuit 124c_2 receives the first pull-down code PD_CODE1 and the first pull-up code PD_CODE1. Based on the fourth pull-down code PD_CODE4 for setting the first pull-down replica circuit 124c_12 to 60 (ohm), the second pull-down replica circuit 124c_22 to set it to 40 (ohm) It is possible to generate a third pull-down code PD_CODE3 for this purpose and a third pull-up code PU_CODE3 for setting the pull-up replica circuit 124c_32 to 120 (ohm). Thereafter, the second calibration circuit 124c_2 adjusts a predetermined level (eg, the second level V2a of FIG. 7A ) so that the DQ signal has a target level separation mismatch ratio. may be used to calibrate the second additional pull-up code ADD_PU_CODE2 provided to the second additional pull-up replica circuit 124c_52 . Meanwhile, the first additional pull-up replica circuit 124c_42 may be in a deactivated state.

16A and 16B are diagrams illustrating an embodiment of the pull-up replica circuit and the pull-down replica circuit in FIGS. 15C and 15D . Fig. 16A corresponds to the embodiment of Fig. 15C, and Fig. 16B corresponds to the embodiment of Fig. 15D.

Referring to FIG. 16A , the first pull-down replica circuit pull-up replica circuit 124c_12 ( FIG. 15C ) may include a plurality of first sub-pull-down replica circuits connected in parallel with each other, among which two second A first pull-down code PD_CODE1 may be provided to one sub pull-down replica circuits 124c_12G1 . The two first sub-pull-down replica circuits 124c_12G1 are respectively activated and set to 240 (ohm). As a result, the first pull-down replica circuit pull-up replica circuit 124c_12 (FIG. 15c) is 120 (ohm). ) can be set. Second Pull-Down Replica Circuit The pull-up replica circuit 124c_22 ( FIG. 15C ) may include a plurality of second sub-pull-down replica circuits connected in parallel with each other, among which six second sub-pull-down replicas A first pull-down code PD_CODE1 may be provided to the circuits 124c_22G. The six second sub-pull-down replica circuits 124c_22G are each activated and set to 240 (ohm). As a result, the second pull-down replica circuit 124c_22 (FIG. 15c) can be set to 40 (ohm). there is. The pull-up replica circuit 124c_32 ( FIG. 15C ) may include a plurality of sub pull-up replica circuits connected in parallel to each other, among which the first pull-up is provided to four sub pull-up replica circuits 124c_32G1 . A code (PU_CODE1) may be provided. Each of the four sub pull-up replica circuits 124c_32G1 is activated and is set to 240 (ohm). As a result, the pull-up replica circuit 124c_32 ( FIG. 15C ) may be set to 60 (ohm).

Referring to FIG. 16B , the first pull-down replica circuit 124c_21 ( FIG. 15D ) includes four first sub pull-down replica circuits 124c_12G2 among a plurality of first sub pull-down replica circuits connected in parallel to each other. A first pull-down code PD_CODE1 may be provided to . The four first sub pull-down replica circuits 124c_12G2 are each activated and set to 240 (ohm). As a result, the first pull-down replica circuit 124c_21 ( FIG. 15D ) can be set to 60 (ohm). there is. Six second sub-pull-down replica circuits 123c_22G of the second pull-down replica circuit 124c_22 ( FIG. 15D ) receive the first pull-down code PD_CODE1 and are activated respectively to 240 (ohm) As a result, the second pull-down replica circuit 124c_22 ( FIG. 15D ) may be set to 40 (ohm). The pull-up replica circuit 124c_32 ( FIG. 15D ) may include a plurality of sub pull-up replica circuits connected in parallel to each other, and two sub pull-up replica circuits 124c_32G2 are connected to the first pull-up circuit 124c_32G2 . A code (PU_CODE1) may be provided. Each of the two sub pull-up replica circuits 124c_32G2 is activated and is set to 240 (ohm). As a result, the pull-up replica circuit 124c_32 ( FIG. 15D ) may be set to 120 (ohm).

However, the embodiments shown in FIGS. 16A and 16B are only exemplary embodiments, and are not limited thereto, and various implementations are calibrated to calibrate the first and second additional pull-up codes ADD_PU_CODE1 and ADD_PU_CODE2. can be applied to the circuit.

17 is a block diagram for explaining an implementation of the transmitter 120h according to an exemplary embodiment of the present disclosure.

Referring to FIG. 17 , the transmitter 120h may include a pre-driver 122h, a driver 123h, and a calibration circuit 124h. The driver 123h includes a first pull-up driver circuit 123h_1 for exclusively outputting the DQ signal DQ having a level corresponding to the '11' data value, the DQ having a level corresponding to the '00' data value. A first pull-down driver circuit 123h_2 for exclusively outputting the signal DQ, and a second pull-up driver circuit for exclusively outputting the DQ signal DQ having a level corresponding to the '10' data value (123h_3) and the second pull-down driver circuit 123h_4, the third pull-up driver 123h_5 and the third pull for exclusively outputting the DQ signal DQ having a level corresponding to the '01' data value -Down driver (123h_6) may be included.

The calibration circuit 124h has first to fourth codes (CODE_11, CODE_10, CODE_01, CODE_00) for controlling the driver 123h individually configured to output the DQ signal DQ having a level corresponding to each data value. may be provided to the pre-driver 122h. The first code CODE_11 includes a first pull-up code PU_CODE_11, and the second code CODE_10 includes a second pull-up code PU_CODE_10 and a second pull-down code PD_CODE_10, The third code CODE_01 may include a third pull-up code PU_CODE_01 and a third pull-down code PD_CODE_01, and the fourth code CODE_00 may include a first pull-down code PD_CODE_00. there is. The fourth code CODE_00 may be generated using a pull-up code generated when the DQ signal DQ is calibrated to have a level corresponding to the '11' data value. As for the first pull-down code PD_CODE_00, the pre-driver 122h provides the first pull-up code PU_CODE_11 to the first pull-up driver circuit 123h_1, and the first pull-down code PD_CODE_00 to the first pull-down driver circuit 123h_2, provide a second pull-up code PU_CODE_10 to the second pull-up driver circuit 123h_3, and generate a second pull-down code PD_CODE_10 2 is provided to the pull-down driver circuit 123h_4, the third pull-up code PU_CODE_01 is provided to the third pull-up driver circuit 123h_5, and the third pull-down code PD_CODE_01 is provided to the third pull - Can be provided to the down driver circuit (123h_6).

18A to 18F are diagrams for explaining an embodiment and an operation method of the calibration circuit 124h of FIG. 17 .

Referring to FIG. 18A , at the input terminal of the comparator 124h_2 of the calibration circuit 124h, a resistor RZQ'' for calibration through an external pin (eg, a ZQ pin) and a pull-down replica circuit 124h_1 and can be connected The comparator 124h_2 may receive a voltage corresponding to half of the second power voltage VDDQ. The calibration circuit 124h uses the comparator 124h_2 to set the pull-down replica circuit 124h_1 to a predetermined resistance value (eg, the same resistance as the connected resistor RZQ'') using the fourth pull-down code. (PD_CODE_11) can be calibrated.

Referring further to FIG. 18B , the calibration circuit 124h uses the comparator 124h_2 so that the resistance value of the pull-down replica circuit 124h_1 and the resistance value of the pull-up replica circuit 124h_3 have the same value. The up code PD_CODE_11 may be calibrated.

Referring further to FIG. 18C , the calibration circuit 124h uses the comparator 124h_2 to determine the ratio between the resistance value of the pull-down replica circuit 124h_1 and the resistance value of the resistor RZQ'' connected through the ZQ pin and the third voltage. The second pull-down code PD_CODE_10 may be calibrated to match the ratio between Vc and the second power voltage VDDQ.

Referring further to FIG. 18D , the calibration circuit 124h uses the comparator 124_2 to determine the ratio between the resistance value of the pull-down replica circuit 124h_1 and the resistance value of the pull-up replica circuit 124h_3 and the third voltage Vc. The second pull-up code PU_CODE_10 may be calibrated to match the ratio between the voltage and the second power voltage VDDQ.

Referring further to FIG. 18E , the calibration circuit 124h uses the comparator 124h_2 to calculate the ratio between the resistance value of the pull-down replica circuit 124h_1 and the resistance value of the resistor RZQ'' connected through the ZQ pin and the second voltage. The third pull-down code PD_CODE_01 may be calibrated to match the ratio between (Vb) and the second power voltage VDDQ.

Referring further to FIG. 18F , the calibration circuit 124h uses the comparator 124_2 to determine the ratio between the resistance value of the pull-down replica circuit 124h_1 and the resistance value of the pull-up replica circuit 124h_3 and the second voltage Vb. The third pull-up code PU_CODE_01 may be calibrated to match the ratio between the voltage and the second power voltage VDDQ.

19 is a block diagram illustrating a memory device 300 receiving first and second setting signals according to an exemplary embodiment of the present disclosure.

Referring to FIG. 19 , the memory device 300 may include a transmitter 320 , a control logic circuit 340 , and an address register 350 . The control logic circuit 340 may include a mode register 342 . The control logic circuit 340 may include command related signals applied from the memory controller, for example, a chip select signal (/CS), a row address strobe signal (/RAS), and a column address strobe signal (Column Address). A strobe (/CAS), a write enable signal (/WE) and a clock enable signal (/CKE) may be received and decoded to internally generate a decoded command.

The address register 350 receives the address signal ADDR through a plurality of address pads of the memory device 300 , and synchronizes the received address signal ADDR with the main clock CK or the inverted clock signal to a control logic circuit (340) can be provided. Meanwhile, as an example, the address register 350 may receive the MRS signal MRS through address pads, and may provide the received MRS signal MRS to the mode register 342 . The MRS signal MRS may be a signal for designating an operation mode of the mode register, and as described above, includes first and second setting signals SS for operation according to exemplary embodiments of the present disclosure. can do.

In an exemplary embodiment, the transmitter 320 may set a signaling mode based on the first and second setting signals SS, check the type of the termination resistor of the memory controller, and set the swing period of the DQ signal. . A detailed operation of the transmitter 320 has been described above, and thus will be omitted below.

On the other hand, the implementation of FIG. 15 is only an exemplary embodiment, it is not limited thereto, and various implementations are possible, and the address register 350 directly transmits the first and second setting signals SS to the transmitter 300 . Implementations provided in may also be possible.

20A to 20C are block diagrams illustrating memory systems MSa to MSc including a transmitter performing a termination resistor operation according to an exemplary embodiment of the present disclosure.

Referring to FIG. 20A , the memory system MSa may include a memory controller MC and a memory device 400a. The memory controller MC and the memory device 400a may be connected through a channel CHa. The memory device 400a may include a transmitter 420a and a receiver 460a , and the transmitter 420a and the receiver 460a may be connected to a channel CHa through one port 480 . The transmitter 420a may include a pre-driver 422a and a driver 423a to which the spirit of the present disclosure is applied.

In an exemplary embodiment, when the receiver 460a receives a signal from the memory controller MC through the channel CHa, the driver 423a operates as the termination resistor R _T1 of the memory device 400a. can Also, the driver 423a may be controlled to have a resistance value for impedance matching with the memory controller MC.

Referring to FIG. 20B , the memory system MSb may include a memory controller MC and first and second memory devices 400b_1 and 400b_2 . The memory controller MC and the first and second memory devices 400b_1 and 400b_2 may be connected through one channel CHb. When the first memory device 400b_1 provides the DQ signal DQ to the memory controller MC, the driver 423b_2 included in the second memory device 400b_2 may operate as a termination resistor R _T2 . . Also, the driver 423b_2 may be controlled to have a resistance value for impedance matching with the memory controller MC.

Referring to FIG. 20C , the memory system MSc may include a memory controller MC and first and second memory groups G1 and G2. The memory controller MC and the first and second memory groups G1 and G2 may be connected through one channel CHc. The first memory group G1 may include first and second memory devices 400c_1 and 400c_2, and the second memory group G2 may include third and fourth memory devices 400c_3 and 400c_4. there is.

A driver included in each of the third and fourth memory devices 400c_3 and 400c_4 of the second memory group G2 when the first memory group G1 provides the DQ signal DQ to the memory controller MC The ones 423c_3 and 423c_4 may operate as termination resistors R _T3a and R _T3b . Also, the drivers 423c_3 and 423c_4 may be controlled to have resistance values for impedance matching with the memory controller MC.

21 is a block diagram illustrating a memory device 500 according to an exemplary embodiment of the present disclosure. In FIG. 21 , an embodiment in which the memory device 500 is implemented as a DRAM device is illustrated.

Referring to FIG. 21 , the memory device 500 includes a memory cell array 510 , a row decoder 520 , a column decoder 530 , a control logic circuit 540 , an input/output sense amplifier 550 , and an input/output gating circuit 560 . ) and a data input/output circuit 570 .

The memory cell array 510 may include memory cells connected to a plurality of word lines and a plurality of bit lines, and the row decoder 520 performs a selection operation on the word lines in response to an external row address. can be done Also, the column decoder 530 may perform a selection operation on bit lines in response to an external column address.

The control logic circuit 540 may control overall operations inside the memory device 500 . As an example, the control logic circuit 540 may control various circuit blocks in the memory device 500 in response to a command from the memory controller.

The control logic circuit 540 may sequentially receive the command CMD and the address signal ADDR through command/address (CA) pads (or pins). The control logic circuit 540 may generate an internal command for controlling the memory operation by decoding the received command CMD, and may provide it to the input/output sense amplifier 550 and the input/output gating circuit 560 .

The data input/output circuit 570 according to an exemplary embodiment may include a transmitter 572 to which exemplary embodiments of the present disclosure are applied. The transmitter 572 may be configured and operable according to the exemplary embodiments of the present disclosure described above to output a DQ signal DQ.

22 is a block diagram illustrating a memory device 600 according to an exemplary embodiment of the present disclosure. 22 , an embodiment in which the memory device 600 is implemented as a flash device is illustrated.

Referring to FIG. 22 , the memory device 600 includes a memory cell array 610 , a page buffer circuit 620 , a control logic 630 , a voltage generator 640 , an address decoder 650 , and a data input/output circuit 660 . may include

The memory cell array 610 may include a plurality of strings (or cell strings) disposed on a substrate in row and column directions. Each of the strings may include a plurality of memory cells stacked in a direction perpendicular to the substrate. That is, the memory cells may be stacked in a direction perpendicular to the substrate to form a three-dimensional structure. Each of the memory cells may be used as a cell type such as a single-level cell or a multi-level cell or a triple-level cell or a quadruple-level cell. The technical spirit of the present disclosure may be flexibly applied according to various cell types of a memory cell.

Memory cells of the memory cell array 610 may be connected to word lines WL, string select lines, ground select lines GSL, and bit lines BL. The memory cell array 610 is connected to the address decoder 650 through word lines WL, string select lines SSL, and ground select lines GSL, and a page buffer through bit lines BL. It may be connected to circuit 620 .

The page buffer circuit 620 may temporarily store data to be programmed into the memory cell array 610 and data read from the memory cell array 610 . The page buffer circuit 620 may include a plurality of page buffers (or a plurality of latch units). As an example, each of the page buffers may include a plurality of latches corresponding to the plurality of bit lines BL, and may store data in units of pages. In some embodiments, the page buffer circuit 620 may include a sensing latch unit, and the sensing latch unit may include a plurality of sensing latches corresponding to the plurality of bit lines BL. In addition, each of the sensing latches may be connected to a sensing node through which data is sensed through a corresponding bit line.

The control logic 630 controls the overall operation of the memory device 600 , for example, based on a command CMD, an address ADDR, and a control signal CTRL received from a memory controller (not shown), a memory cell Various internal control signals for programming data into the array 610 , reading data from the memory cell array 610 , or erasing data stored in the memory cell array 610 may be output.

Various internal control signals output from the control logic 630 may be provided to the page buffer circuit 620 , the voltage generator 640 , and the address decoder 650 . Specifically, the control logic 630 may provide the voltage control signal CS_vol to the voltage generator 640 . The voltage generator 640 may include one or more pumps (not shown), and according to a pumping operation based on the voltage control signal CS_vol, the voltage generator 640 may generate voltages VWL having various levels. there is. Meanwhile, the control logic 630 may provide the row address X_ADD to the address decoder 650 , and page the column address Y_ADD and the page buffer control signal PB_CS for controlling the page buffer circuit 620 . It may be provided to the buffer circuit 620 .

The data input/output circuit 660 may include a transmitter 662 to which exemplary embodiments of the present disclosure are applied. The transmitter 662 may be configured and operated according to the above-described exemplary embodiments of the present disclosure to output a data signal (Data) (or a DQ signal).

23 is a block diagram illustrating systems including a transmitter according to an exemplary embodiment of the present disclosure. 19 , the memory system 1000 and the host system 1600 may communicate through the interface 1800 , and the memory system 1000 may communicate with the memory controller 1200 and the memory devices 1400 . may include

The interface 1800 may use an electrical signal and/or an optical signal, and as non-limiting examples, a serial advanced technology attachment (SATA) interface, a SATA express (SATAe) interface, a serial attached small computer system interface (SAS); serial attached SCSI), a Universal Serial Bus (USB) interface, or a combination thereof. The host system 1600 and the memory controller 1200 may include SerDes for serial communication.

In some embodiments, the memory system 1000 may communicate with the host system 1600 by being removably coupled with the host system 1600 . The memory device 1400 may be a volatile memory or a nonvolatile memory, and the memory system 1000 may be referred to as a storage system. For example, the memory system 1000 is a non-limiting example of a solid-state drive or solid-state disk (SSD), an embedded SSD (eSSD), a multimedia card (MMC), an embedded multimedia card ( embedded multimedia card (eMMC) or the like. The memory controller 1200 may control the memory devices 1400 in response to a request received from the host system 1600 through the interface 1800 .

Meanwhile, the transmitters 1220 and 1420 to which the exemplary embodiments of the present disclosure are applied may be implemented to be included in the memory controller 1200 and the memory devices 1400 , respectively.

24 is a block diagram illustrating a system-on-chip 2000 including a memory device according to an exemplary embodiment of the present disclosure. The System on Chip (SoC) 2000 may refer to an integrated circuit in which components of a computing system or other electronic system are integrated. For example, an application processor (AP) as one of the system-on-chip 2000 may include a processor and components for other functions.

24, the system-on-chip 2000 includes a core 2100, a digital signal processor (DSP) 2200, a graphic processing unit (GPU) 2300, a built-in memory 2400, and a communication interface. 2500 and a memory interface 2600 . Components of system-on-chip 2000 may communicate with each other via bus 2700 .

The core 2100 may process instructions and may control operations of components included in the system-on-chip 2000 . For example, the core 2000 may drive an operating system and execute applications on the operating system by processing a series of instructions. The DSP 2200 may generate useful data by processing a digital signal, such as a digital signal provided from the communication interface 2500 . The GPU 2300 may generate data for an image output through the display device from image data provided from the built-in memory 2400 or the memory interface 2600 , or may encode the image data. The built-in memory 2400 may store data necessary for the core 2100 , the DSP 2200 , and the GPU 2300 to operate. The memory interface 2600 may provide an interface to an external memory of the system-on-chip 2000 , for example, a dynamic random access memory (DRAM), a flash memory, or the like.

The communication interface 2500 may provide serial communication with the outside of the system-on-chip 2000 . For example, the communication interface 2500 may be connected to Ethernet and may include SerDes for serial communication.

Meanwhile, the configuration of the transmitter to which the exemplary embodiments of the present disclosure are applied may be applied to the communication interface 2500 or the memory interface 2600 .

Exemplary embodiments have been disclosed in the drawings and specification as described above. Although the embodiments have been described using specific terms in the present specification, these are used only for the purpose of explaining the technical spirit of the present disclosure, and are not used to limit the meaning or the scope of the present disclosure described in the claims. . Therefore, it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the true technical protection scope of the present disclosure should be defined by the technical spirit of the appended claims.

Claims (20)

memory cell array; and
includes a transmitter;
The transmitter is
a PAM encoder configured to generate a first input signal conforming to n-level pulse amplitude modulation (PAM-n) (where n is an integer greater than or equal to 4) from the data read from the memory cell array;
a pre-driver configured to generate a second input signal based on the first input signal and a calibration code signal, and output the second input signal using a first power supply voltage; and
and a driver configured to output the DQ signal based on the PAM-n using a second power supply voltage lower than the first power supply voltage in response to the second input signal. According to claim 1,
The calibration code signal includes a plurality of codes for adjusting driving strength of each of a plurality of pull-up circuits and a plurality of pull-down circuits included in the driver. According to claim 1,
The driver may include a plurality of pull-up circuits each having a plurality of first transistors; and a plurality of pull-down circuits each having a plurality of second transistors,
At least two first circuits of the plurality of pull-up circuits and the plurality of pull-down circuits are selected based on the second input signal applied to gate terminals of the plurality of first and second transistors; , the number of the first or second transistors to be turned on for each of the selected first circuits is determined. 4. The method of claim 3,
The plurality of first and second transistors are configured as nMOS transistors. 4. The method of claim 3,
The driver further comprises a plurality of additional pull-up circuits each having a plurality of third transistors,
The pre-driver is configured to generate a third input signal based on the first input signal and an additional calibration code signal, and to output the fourth input signal using the first power supply voltage,
Any one of the plurality of additional pull-up circuits is selected based on the fourth input signal applied to the gate terminals of the plurality of third transistors, and the second circuit is turned on for the selected second circuit A memory device, characterized in that the number of third transistors is determined. 4. The method of claim 3,
The driver further comprises a plurality of additional pull-down circuits each having a plurality of third transistors,
The pre-driver is configured to generate a third input signal based on the first input signal and an additional calibration code signal, and to output the fourth input signal using the first power supply voltage,
Any one of the plurality of additional pull-down circuits is selected based on the fourth input signal applied to the gate terminals of the plurality of third transistors, and the second circuit is turned on for the selected second circuit A memory device, characterized in that the number of third transistors is determined. According to claim 1,
and the driver is configured to output the DQ signal having a different swing period according to a type of a termination resistor of a memory controller that receives the DQ signal through a channel. According to claim 1,
a calibration circuit comprising a replica circuit having the same configuration as that of the driver, and using the replica circuit to generate the calibration code signal so that the DQ signal has a predetermined level separation mismatch ratio; A memory device, characterized in that it further comprises. 9. The method of claim 8,
The calibration circuit is configured to generate the calibration code signal using voltages whose level is adjusted according to a type of a termination resistor of a memory controller that receives the DQ signal through a channel. According to claim 1,
The memory device further comprises a receiver,
and the driver is configured to operate as a termination resistor of the memory device when the receiver receives a signal from the memory controller through a channel. According to claim 1,
The transmitter can support the PAM-n signaling mode and the Non-Return Zero signaling mode, and any one of the PAM-n signaling and the non-return zero signaling based on the signaling mode of the memory device A memory device, characterized in that configured to select and provide. According to claim 1,
The memory device receives a mode register set signal including at least one of a first setting signal indicating a type of termination resistor of the memory controller and a second setting signal for setting a signaling mode of the memory device, , configured to output the DQ signal based on the mode register set signal. memory cell array; and
includes a transmitter;
The transmitter is
a PAM encoder configured to generate first and second Most Significant Bit (MSB) signals and first and second Least Significant Bit (LSB) signals conforming to PAM-4 from the data read from the memory cell array;
In the first voltage domain, a third MSB signal is generated based on the first MSB signal and a first pull-up code, and a fourth MSB signal is generated based on the second MSB signal and a second pull-up code. and generating a third LSB signal based on the first LSB signal and a first pull-down code, and generating a fourth LSB signal based on the second LSB signal and a second pull-down code. driver; and
a first pull-up circuit activated by the third MSB signal and configured to adjust driving strength; a first pull-down circuit activated based on the fourth MSB signal and configured to adjust driving strength; a second pull-up circuit activated by the LSB signal and configured to adjust driving strength; and a second pull-down circuit activated by the fourth LSB signal and configured to adjust driving strength; and a driver configured to output a DQ signal based on the PAM-4 using first and second pull-up circuits and first and second pull-down circuits in 14. The method of claim 13,
The second voltage domain is lower than the first voltage domain. 14. The method of claim 13,
The driver is
and first and second additional circuits for adjusting the magnitude of intermediate levels between the maximum and minimum levels of the DQ signal. 14. The method of claim 13,
and the driver is configured to output the DQ signal having a different swing period according to a type of a termination resistor of a memory controller that receives the DQ signal through a channel. 14. The method of claim 13,
The driver is configured to output a DQ signal based on the PAM-4 based on a signaling mode set by the memory controller or output a DQ signal based on a non-return zero . 14. The method of claim 13,
The memory device further comprises a receiver,
and the driver is configured to operate as a termination resistor of the memory device when the receiver receives a signal from the memory controller through a channel. memory controller; and
a plurality of memory devices connected to the memory controller through one channel;
Each of the plurality of memory devices,
a PAM encoder configured to generate a first input signal conforming to PAM-n from the data requested by the memory controller; a pre-driver configured to generate a second input signal based on the first input signal and a calibration code signal, and output the second input signal using a first power supply voltage; and a transmitter including a driver configured to output the DQ signal based on the PAM-n using a second power supply voltage lower than the first power supply voltage in response to the second input signal. 20. The method of claim 19,
In the plurality of memory devices, the driver included in at least one of the remaining memory devices other than the target memory device communicating with the memory controller is configured to operate as a termination resistor.

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