KR20220019588A - Etchant compositions and methods of manufacturing semiconductor device using the same - Google Patents

Abstract

The present invention relates to an etching composition and a method for manufacturing a semiconductor element using the same, wherein the etching composition comprises inorganic acid and a silane-based compound represented by chemical formula 1. According to the present invention, reliability of the semiconductor element can be improved.

Description

Etchant compositions and methods of manufacturing semiconductor device using the same}

The technical idea of the present invention relates to an etching composition and a method of manufacturing a semiconductor device using the same, and more particularly, to an etching composition for etching a nitride layer and a method of manufacturing a semiconductor device using the same.

In an integrated circuit (semiconductor) device, an oxide film such as a silicon oxide film (SiO2) and a nitride film such as a silicon nitride film (SiNx) are typical insulating films, respectively, or have a structure in which one or more layers are alternately stacked. These oxide films and nitride films are also used as hard masks for forming conductive patterns such as metal wiring.

In a wet etching process for removing the nitride layer, an etching composition in which phosphoric acid and deionized water are mixed is generally used. At this time, the deionized water is added to reduce the etch rate and to prevent the change of the etch selectivity for the oxide film, but when the nitride film is removed through the wet etching process, a defect occurs due to a slight change in the amount of deionized water, and the nitride film for the oxide film There was a problem in that there was a limitation in etching the nitride film to a required level due to the decrease in the etch selectivity of the etchant.

Recently, with the multifunctionalization of information and communication devices, there is a demand for high capacity and high integration of semiconductor devices including memory devices. As the size of a memory cell for high integration is reduced, operation circuits and wiring structures included in the memory device for operation and electrical connection of the memory device are also becoming more complex. In the manufacturing process of a highly downscaled semiconductor device, oxide and nitride layers, which are typical insulating layers, may be used alone or alternately stacked. In order to construct it, a selective etching process of the nitride film having a pattern of various shapes may be required. In particular, there is a need for an etching composition capable of securing a sufficient etching selectivity of the nitride film to the oxide film without causing problems such as unnecessary particle generation or unwanted abnormal growth of by-products on the surface of the oxide film during the etching process of the nitride film.

Accordingly, the present invention does not cause problems such as unnecessary particle generation or unwanted abnormal growth of by-products on the surface of the oxide film during the etching process of the nitride film. do.

In addition, the present invention provides an oxide film without causing problems such as unnecessary particle generation or unwanted abnormal growth of by-products on the surface of the oxide film during etching of nitride films of various shapes for realizing electronic devices having complex and miniaturized structures. An object of the present invention is to provide a method of manufacturing a semiconductor device capable of securing a sufficient etching selectivity of the nitride layer to ensure stability and reliability of the nitride layer etching process and improving the productivity of the semiconductor device manufacturing process.

The technical problems to be achieved by the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned can be clearly understood by those of ordinary skill in the art to which the present invention belongs from the description below. There will be.

As a technical means for achieving the above-described technical problem, one aspect of the present invention is,

inorganic acids; And it provides an etching composition comprising a silane-based compound of Formula 1:

[Formula 1]

In Formula 1, R ₁ to R ₁₀ are each independently a substituted or unsubstituted alkyl group having 1 to 10 carbon atoms, a substituted or unsubstituted cycloalkyl group having 3 to 10 carbon atoms, or a substituted or unsubstituted alkene group having 1 to 10 carbon atoms. It is selected from the group consisting of a nyl group, a substituted or unsubstituted aryl group having 5 to 20 carbon atoms, a substituted or unsubstituted heteroaryl group having 5 to 20 carbon atoms, X ₁ to X ₃ is a halogen element, and n is 0 to 10 Integer, m ₁ to m ₄ are each an integer from 0 to 2, m ₁ +m ₂ and m ₃ +m ₄ are integers from 0 to 2

In Formula 1, R ₁ to R ₁₀ are each independently a substituted or unsubstituted alkyl group having 1 to 5 carbon atoms, a substituted or unsubstituted alkenyl group having 1 to 5 carbon atoms, or a substituted or unsubstituted aryl group having 5 to 10 carbon atoms. selected from the group consisting of, X ₁ to X ₃ is a halogen element, n is an integer from 0 to 10, m ₁ to m ₄ are each an integer from 0 to 2, m ₁ +m ₂ and m ₃ +m ₄ may be an integer of 0 to 2.

The inorganic acid may include at least one selected from the group consisting of sulfuric acid, nitric acid, phosphoric acid, silicic acid, hydrofluoric acid, boric acid, hydrochloric acid and perchloric acid.

The etching composition may include 70 to 99 parts by weight of the inorganic acid and 0.01 to 15 parts by weight of the silane-based compound.

The etching composition may further include an ammonium-based compound.

The ammonium-based compound may include at least one of ammonium chloride, ammonium phosphate, ammonium acetate, ammonium sulfate, ammonium formate, and a metal amine complex salt.

The etching composition may be used to etch the nitride layer.

The silicon nitride layer/oxide layer etching selectivity of the etching composition may be 50 or more.

In another aspect of the present invention, an insulating film and a sacrificial film are stacked on a substrate to form a structure; It provides a method of manufacturing a semiconductor device including; performing an etching process using the etching composition to remove the sacrificial layer to form a spatial region.

The sacrificial layer may include silicon nitride, and the insulating layer may include silicon oxide.

In the etching process, the sacrificial layer may have a higher etch rate than the insulating layer.

In the step of performing the etching process to remove the sacrificial layer to form a spatial region, the spatial region may include a gate region formed between the insulating layer and a trench connected to the gate region.

forming openings passing through the stacked structure; and forming a semiconductor pattern spaced apart from the trench in the openings, wherein the forming of the semiconductor pattern may be performed before forming the trench.

Another aspect of the present invention provides a structure in which an insulating film and a sacrificial film are stacked; a space portion formed by etching the sacrificial layer with an etching composition in the structure; and a deposition portion formed by depositing a conductive material or an insulating material in the space portion, wherein the etching composition includes: an inorganic acid; And it provides a semiconductor device comprising a silane-based compound of the formula (1):

[Formula 1]

In Formula 1, R ₁ to R ₁₀ are each independently a substituted or unsubstituted alkyl group having 1 to 10 carbon atoms, a substituted or unsubstituted cycloalkyl group having 3 to 10 carbon atoms, or a substituted or unsubstituted alkene group having 1 to 10 carbon atoms. It is selected from the group consisting of a nyl group, a substituted or unsubstituted aryl group having 5 to 20 carbon atoms, a substituted or unsubstituted heteroaryl group having 5 to 20 carbon atoms, X ₁ to X ₃ is a halogen element, and n is 0 to 10 The integers m ₁ to m ₄ are each an integer from 0 to 2, and m ₁ +m ₂ and m ₃ +m ₄ are integers from 0 to 2.

The silicon nitride layer/oxide layer etching selectivity of the etching composition may be 50 or more.

According to an embodiment of the present invention, the effective oxide film height (EFH) can be easily adjusted as the etching rate of the oxide film is adjusted because the etch selectivity of the nitride film is high. In addition, the etching composition of the present invention can improve the reliability of the semiconductor device by preventing damage to the film quality of the oxide film, deterioration of electrical properties due to the etching of the oxide film, and generation of particles when the nitride film is removed.

In addition, when etching the nitride layer, even when the nitride layer and the oxide layer are alternately stacked or mixed, the nitride layer has a relatively high etch selectivity of about 50:1 to about 800:1, and only the nitride layer is selectively etched. can do. Accordingly, while etching a nitride film having various shapes of patterns in order to construct an electronic device having a complex and refined structure, it does not cause problems such as unnecessary particle generation or unwanted abnormal growth on the surface of the oxide film. By securing a sufficient etching selectivity, stability and reliability of the nitride film etching process can be secured, and damage to the oxide film exposed to the etching composition together with the nitride film or deterioration of the electrical properties of the oxide film is prevented, thereby improving the productivity of the semiconductor device manufacturing process and , it is possible to improve the reliability of the semiconductor device.

Accordingly, the etching composition of the present invention may include a semiconductor device manufacturing process requiring selective removal of a nitride layer with respect to an oxide layer (eg, a device isolation process of a flash memory device, a pipe channel forming process of a 3D flash memory device, It is usefully used in a diode formation process of a phase change memory, etc.) and can contribute to improving the efficiency of a semiconductor device manufacturing process.

It should be understood that the effects of the present invention are not limited to the above-described effects, and include all effects that can be inferred from the configuration of the invention described in the detailed description or claims of the present invention.

1 is a plan view of a semiconductor device according to embodiments of the present invention.
2 to 8 are views for explaining a method of manufacturing a semiconductor device according to embodiments of the present invention.
FIG. 9 is an enlarged view of area A of FIG. 8 .

Hereinafter, the present invention will be described in more detail. However, the present invention may be embodied in various different forms, and the present invention is not limited by the embodiments described herein, and the present invention is only defined by the claims to be described later.

In addition, the terms used in the present invention are only used to describe specific embodiments, and are not intended to limit the present invention. The singular expression includes the plural expression unless the context clearly dictates otherwise. In the entire specification of the present invention, 'including' any component means that other components may be further included, rather than excluding other components, unless otherwise stated.

As used herein, “silicon nitride film,” “silicon nitride,” and “Si _x N _y ” refer to pure silicon nitride as well as impure silicon nitride containing hydrogen, carbon and/or oxygen impurities in its crystal structure. (wherein x and y are each independently positive integers).

As used herein, “silicon oxide film” and “silicon oxide” refer to a thin film made of silicon oxide (SiO _x ), for example, SiO2, “thermal oxide” (ThOx), or the like. Silicon oxide may be deposited on the substrate by any method, such as thermal evaporation or deposition via chemical vapor deposition from TEOS or other sources. Silicon oxide may contain generally commercially useful low levels of other substances or impurities. Silicon oxide may be present as part of the microelectronic device, for example as an insulating layer, as a feature of the microelectronic device.

As used herein, “at least partial removal of the silicon nitride material” corresponds to removal of at least a portion of the exposed silicon nitride layer. For example, partial removal of the silicon nitride film includes anisotropic removal of the silicon nitride film covering/protecting the gate electrode to form Si ₃ N ₄ . It is contemplated that the compositions of the present invention may be used more generally to substantially remove silicon nitride compared to polysilicon and/or silicon oxide films. In this context, “substantial removal” is defined as at least 90% in one embodiment of the present invention, at least 95% in another embodiment, and in another embodiment at least 99% of the silicon nitride material from the composition of the present invention. It may mean to be removed using

As used herein, "substituted or unsubstituted" is a hydrogen atom, a deuterium atom, a halogen atom, a cyano group, a nitro group, an amino group, a silyl group, a boron group, a phosphine oxide group, a phosphine sulfide group, a carboxy group, an alkyl group, an alke group It may mean unsubstituted or substituted with one or more substituents selected from the group consisting of a nyl group, an aryl group, and a heterocyclic group. Specifically, “substituted or unsubstituted” may mean unsubstituted or substituted with one or more substituents selected from the group consisting of a hydrogen atom, a deuterium atom, an alkyl group, an amino group, a silyl group, and an alkoxy group. In addition, each of the substituents exemplified above may be substituted or unsubstituted. For example, a methyl amino group can be interpreted as an amino group.

In the present specification, examples of the halogen atom include a fluorine atom, a chlorine atom, a bromine atom or an iodine atom.

In the present specification, the alkyl group may be a linear alkyl group, a branched alkyl group, or a cyclic alkyl group. The alkyl group may be a linear alkyl group, a branched alkyl group, or a cyclic alkyl group. Examples of the alkyl group include methyl group, ethyl group, n-propyl group, isopropyl group, n-butyl group, t-butyl group, i-butyl group, 2-ethylbutyl group, 3,3-dimethylbutyl group, n-pentyl group , i-pentyl group, neopentyl group, t-pentyl group, cyclopentyl group, 1-methylpentyl group, 3-methylpentyl group, 2-ethylpentyl group, 4-methyl-2-pentyl group, n-hexyl group , 1-methylhexyl group, 2-ethylhexyl group, 2-butylhexyl group, cyclohexyl group, 4-methylcyclohexyl group, 4-t-butylcyclohexyl group, n-heptyl group, 1-methylheptyl group, 2,2-dimethylheptyl group, 2-ethylheptyl group, 2-butylheptyl group, n-octyl group, t-octyl group, 2-ethyloctyl group, 2-butyloctyl group, 2-hexyloctyl group, 3, 7-dimethyloctyl group, cyclooctyl group, n-nonyl group, and n-decyl group may be mentioned, but are not limited thereto.

In the present specification, the amino group may include an alkyl amino group and an aryl amino group. Examples of the amino group include, but are not limited to, a methylamino group, an ethylamino group, a dimethylamino group, a diethylamino group, and/or an ethylmethylamino group.

In the present specification, the alkoxy group may include an alkyl alkoxy group and an aryl alkoxy group. Examples of the alkoxy group include a methyl alkoxy group, an ethyl alkoxy group, a propyl alkoxy group, a butyl alkoxy group, a pentyl alkoxy group, a hexyl alkoxy group, a heptyl alkoxy group, an octyl alkoxy group, a nonyl alkoxy group, and a decyl alkoxy group, but these is not limited to

Hereinafter, before describing the first aspect of the present invention, the concept of the etching composition will be described.

The etching composition may be used to etch the silicon-containing material. For example, the etching composition may be used to etch a silicon nitride layer or a silicon oxide layer that is an insulating layer. The etching of the silicon oxide layer using the etching composition may be performed as shown in Scheme 1 below. The etching of the silicon oxide film using the silicone composition may proceed as shown in Reaction Equation 2 below. However, in the etching process using the etching composition, the etch rate of the silicon nitride layer as the first insulating layer may be greater than the etch rate of the silicon oxide layer as the second insulating layer. In this specification, the etching of the silicon nitride layer may mean that the silicon nitride is removed, and the etching of the silicon oxide layer may mean that the silicon oxide is removed. Silicon nitride may be represented by Si _x N _y . Silicon oxide may include Si _x O _y . (wherein x and y are each independently positive integers)

[Scheme 1]

3Si ₃ N ₄ + 4H ₃ PO ₄ + 27H ₂ O → 4(NH ₄ )3PO ₄ + 9SiO ₂ H ₂ O

[Scheme 2]

SiO ₂ +4H ⁺ + 4e ^- → Si + 2H ₂ O

Referring to Scheme 1, phosphoric acid may react with silicon nitride to remove silicon nitride. In this case, the composition ratio of phosphoric acid as an inorganic acid may be 70 to 99 parts by weight. In the present specification, the composition ratio means a composition ratio with respect to the composition. When phosphoric acid is less than 70 parts by weight of the etching composition, it may be difficult to easily remove the silicon nitride layer. Alternatively, in the etching process, etching byproducts may be formed. In one embodiment of the present invention, the composition ratio of phosphoric acid may mean the composition ratio of 85% phosphoric acid aqueous solution. That is, when the composition ratio of phosphoric acid is 65%, it may mean that 85% phosphoric acid aqueous solution is 65% of the etching composition.

Referring to Scheme 2, phosphoric acid may provide hydrogen ions to react with silicon oxide. When the phosphoric acid is greater than 99 parts by weight of the etching composition, the reaction rate between the phosphoric acid and the silicon oxide may increase. Accordingly, in the etching process, it may be difficult for the silicon nitride layer to have a sufficiently high etch selectivity with respect to the silicon oxide layer.

etching composition

Hereinafter, the etching composition according to the first aspect of the present invention will be described in detail.

One aspect of the present invention is

inorganic acids; And it provides an etching composition comprising a silane-based compound of Formula 1:

[Formula 1]

In Formula 1, R ₁ to R ₁₀ are each independently a substituted or unsubstituted alkyl group having 1 to 10 carbon atoms, a substituted or unsubstituted cycloalkyl group having 3 to 10 carbon atoms, or a substituted or unsubstituted alkene group having 1 to 10 carbon atoms. It is selected from the group consisting of a nyl group, a substituted or unsubstituted aryl group having 5 to 20 carbon atoms, a substituted or unsubstituted heteroaryl group having 5 to 20 carbon atoms, X ₁ to X ₃ is a halogen element, and n is 0 to 10 The integers m ₁ to m ₄ are each an integer from 0 to 2, and m ₁ +m ₂ and m ₃ +m ₄ are integers from 0 to 2.

In one embodiment of the present invention, preferably, in Formula 1, R ₁ to R ₁₀ are each independently a substituted or unsubstituted alkyl group having 1 to 5 carbon atoms, a substituted or unsubstituted alkyl group having 1 to 5 carbon atoms It is selected from the group consisting of a nyl group, a substituted or unsubstituted aryl group having 5 to 10 carbon atoms, X ₁ to X ₃ is a halogen element, n is an integer from 0 to 10, m ₁ to m ₄ are each an integer from 0 to 2 , and m ₁ +m ₂ and m ₃ +m ₄ may be integers from 0 to 2.

In one embodiment of the present invention, the silane-based compound may be represented by the following Chemical Formula 2 or Chemical Formula 3, but is not limited thereto.

[Formula 2]

[Formula 3]

In one embodiment of the present invention, the inorganic acid included in the etching composition allows the etching composition to have an acidic pH (eg, pH 2 to 6) to etch the object to be etched (eg, an insulating film). do.

The inorganic acid is not particularly limited, but may be at least one selected from the group consisting of sulfuric acid, nitric acid, phosphoric acid, silicic acid, hydrofluoric acid, boric acid, hydrochloric acid, and perchloric acid. Specifically, the inorganic acid may be phosphoric acid. When phosphoric acid is used as the inorganic acid and the etching target is an oxide film and a nitride film, the etching selectivity of the nitride film to the oxide film may be increased. In addition, when phosphoric acid is used as the inorganic acid, hydrogen ions may be provided in the etching composition to promote etching.

In addition, when the inorganic acid is phosphoric acid, the etching composition of the present invention may further include sulfuric acid as an additive. The sulfuric acid may increase the boiling point of the etching composition including the phosphoric acid as an inorganic acid, thereby helping to etch the nitride layer.

The content of the inorganic acid and the silane compound is not particularly limited, but the etching composition may include 70 to 99 parts by weight of the inorganic acid and 0.01 to 20 parts by weight of the silane compound. Specifically, the etching composition may include 70 to 90 parts by weight of the inorganic acid and 0.5 to 18 parts by weight of the silane-based compound. More specifically, the etching composition may include 75 to 85 parts by weight of the inorganic acid and 1 to 15 parts by weight of the silane-based compound. If the content of the inorganic acid is less than 70 parts by weight, etching (removal) of the nitride film may not be easy or particle generation may be induced. In terms of securing a high etch selectivity of the nitride layer, preferably, the silane-based compound may include 2 to 15 parts by weight, more preferably 3 to 15 parts by weight, even more preferably 5 to 13 parts by weight. there is.

In addition, when the content of the silane-based compound is less than 0.01 parts by weight, it is difficult to obtain a high etch selectivity with respect to the nitride layer, and when it exceeds 10 parts by weight, it is difficult to increase the effect due to an increase in the content, so economic efficiency may be deteriorated.

In one embodiment of the present invention, the etching composition may further include an ammonium-based compound. The ammonium-based compound may refer to a compound that forms ammonium (NH ⁴⁺ ) in aqueous solution conditions. The ammonium-based compound may include, for example, at least one of ammonia, ammonium chloride, ammonium phosphate, ammonium acetate, ammonium sulfate, ammonium formate, and a metal amine complex salt. The metal amine complex salt may be a metal complex salt including at least one ammonia (NH ₃ ) ligand. When the etching process of the silicon nitride layer is performed for a long time, the concentration of silicon ions may increase. For example, the silicon ion may be formed by SiO ₂ H ₂ O, which is the product of Reaction Formula 1 above. Abnormal growth of the silicon oxide film may occur due to silicon ions. According to embodiments, in the etching process, the ammonium-based compound may be dissociated to form ammonium (NH ⁴⁺ ). Ammonium may react with a precursor of silicon ions (eg, SiO ₂ ) to remove the precursor of silicon ions. Accordingly, abnormal growth of the silicon oxide film can be prevented. The ammonium-based compound may maintain an etching rate according to an etching time constant.

If the ammonium-based compound is less than 0.01 wt% of the etching composition, it may be difficult to prevent abnormal growth of the silicon oxide layer or the etch selectivity of the silicon nitride layer to the silicon oxide layer may change with time. When the ammonium-based compound exceeds 10 wt% of the etching composition, the etching rates of the silicon nitride layer and the silicon oxide layer may change with time. According to an embodiment, the composition ratio of the ammonium-based compound may be 0.01 wt% to 10 wt%.

Also, in one embodiment of the present invention, the etching composition may further include a solvent. Specifically, the solvent may be water or deionized water (DIW). The content of the solvent may be the remaining parts by weight (residual amount) excluding the components based on 70 to 99 parts by weight of the first inorganic acid and 0.01 to 10 parts by weight of the first additive.

In addition, the etching composition of the present invention may further include any commonly known additives to improve etching performance. The additive may be a surfactant, a sequestering agent, or a corrosion inhibitor.

As the etching composition of the present invention as described above selectively further includes an additive and an ammonium-based compound in addition to the inorganic acid and the silane-based compound, the etching selectivity of the nitride layer to the oxide layer may be significantly high. In addition, the etching composition can prevent damage to the film quality of the oxide film or deterioration of electrical properties due to etching of the oxide film during the etching process of the nitride film, and minimize the generation of particles. Accordingly, the etching composition of the present invention may be usefully used in an etching process when manufacturing a semiconductor device.

Manufacturing method of semiconductor device

The second aspect of the present application is

forming a structure by stacking an insulating film and a sacrificial film on a substrate; and forming a spatial region by removing the sacrificial layer by performing an etching process using the etching composition.

Although detailed descriptions of parts overlapping with the first aspect of the present application are omitted, the contents described with respect to the first aspect of the present application may be equally applied even if the description thereof is omitted in the second aspect.

Hereinafter, a method of manufacturing a semiconductor device according to the second aspect of the present application will be described in detail.

As used herein, the “space” in “space region” and “space portion” refers to a space formed by removing a sacrificial layer in an etching process of a semiconductor device, and as a non-limiting example, a trench, a channel, a gate, and a spacer etc. may be included.

In addition, as used herein, the term “deposited portion” means including a portion in which a conductive material or an insulating material is deposited and formed in the aforementioned spatial region or space, and may be patterned and configured.

1 is a plan view of a semiconductor device according to example embodiments. 2 to 8 are views for explaining a method of manufacturing a semiconductor device according to embodiments, and correspond to cross-sections taken along line II′ of FIG. 1 . Hereinafter, content that overlaps with those described above will be omitted.

1 and 2 of the present application, the stacked structure 200 may be formed on the substrate 100 . The substrate 100 is a bulk silicon substrate, a silicon on insulator (SOI) substrate, a germanium substrate, a germanium on insulator (GOI) substrate, a silicon-germanium substrate, or optional It may be a substrate of an epitaxial thin film obtained by performing selective epitaxial growth (SEG). The first direction D1 and the second direction D2 may be parallel to the upper surface 100a of the substrate 100 . The second direction D2 may intersect the first direction D1 . The third direction D3 may be perpendicular to the upper surface 100a of the substrate 100 .

In one embodiment of the present invention, the stacked structure 200 may include sacrificial layers SC and insulating layers IL. The formation of the stacked structure 200 may include alternately and repeatedly forming the sacrificial layers SC and the insulating layers IL on the substrate 100 . The sacrificial layers SC may be formed between the insulating layers IL. The sacrificial layers SC may have etch selectivity with respect to the insulating layers IL. The sacrificial layers SC may include, for example, silicon nitride (eg, Si _x N _y ). The insulating layers IL may include silicon oxide (eg, Si _x O _y ). The insulating layers IL may be formed using tetraethoxysilane (TEOS), and tetraethoxysilane may be represented by (C ₂ H ₅ O) ₄ Si.

In embodiments of the present invention, the sacrificial layers SC may have substantially the same thickness as each other. Alternatively, the lowermost sacrificial film SC and the uppermost sacrificial film SC among the sacrificial films SC may be formed to be thicker than the sacrificial films SC positioned therebetween. Also, the insulating layers IL may have the same thickness, or at least two of the insulating layers IL may have different thicknesses. The lowermost layer among the insulating layers IL may have a thickness thinner than that of the sacrificial layers SC and the insulating layers IL formed thereon. The lowermost layer among the insulating layers IL may be a silicon oxide layer formed through a thermal oxidation process. In this specification, the thickness of a component may mean a distance in the third direction D3 of the component.

1 and 3 of the present application, openings 210 and vertical structures 300 may be formed in the stacked structure 200 . Forming the openings 210 includes forming a mask pattern (not shown) defining the planar positions of the openings 210 on the laminate structure 200 and using the mask pattern as an etch mask to form the laminate structure ( 200) may include etching. The etching of the stacked structure 200 may be performed by an anisotropic etching process.

In one embodiment of the present invention, the openings 210 may pass through the stacked structure 200 . Sidewalls of the openings 210 may expose the sacrificial layers SC and the insulating layers IL. The openings 210 may expose the substrate 100 . While forming the openings 210 , the upper surface 100a of the substrate 100 may be over-etched. In this case, the upper surface 100a of the substrate 100 exposed through the openings 210 may be recessed to a predetermined depth.

In one embodiment of the present invention, each of the openings 210 may be formed in the form of a cylindrical or rectangular parallelepiped hole. The lower portions of the openings 210 may have smaller widths than their upper portions. 1 , the openings 210 may form columns parallel to the second direction D2 in a plan view. The openings 210 between two adjacent columns may be arranged in a zigzag shape in the second direction D2 . Unlike FIG. 1 , the openings 210 may form an array aligned along the first direction D1 and the second direction D2 . For example, the openings 210 of two adjacent columns may be aligned in the first direction D1 to form an array.

In one embodiment of the present invention, the first dielectric patterns 310 may be formed in the openings 210 . The first dielectric patterns 310 may cover sidewalls of the openings 210 . The first dielectric patterns 310 may expose the upper surface 100a of the substrate 100 . The first dielectric pattern 310 may include a single insulating layer or multiple insulating layers. The first dielectric pattern 310 may function as a part of the data storage layer of the charge trap type flash memory transistor. Exemplary embodiments of the first dielectric pattern 310 will be described later with reference to FIG. 9 .

In one embodiment of the present invention, semiconductor patterns 320 may be formed in the openings 210 . The semiconductor patterns 320 may include, for example, silicon (Si), germanium (Ge), or a mixture thereof. The semiconductor patterns 320 may have a crystal structure including at least one of single crystal, amorphous, and polycrystalline. The semiconductor patterns 320 may further include doped impurities. As another example, the semiconductor patterns 320 may be intrinsic semiconductors in an undoped state. The semiconductor patterns 320 may be formed using a thermal chemical vapor deposition (CVD), plasma enhanced CVD, or atomic layer deposition (ALD) technique.

In one embodiment of the present invention, the semiconductor patterns 320 may be formed on sidewalls of the openings 210 to cover the first dielectric patterns 310 . The semiconductor patterns 320 may extend onto the substrate 100 and contact a portion of the upper surface 100a of the substrate 100 exposed by the openings 210 . Each of the semiconductor patterns 320 may have a pipe-shaped shape, a hollow cylindrical shape, or a cup shape in each of the corresponding openings 210 . The semiconductor patterns 320 may define empty regions 321 in central portions of the openings 210 .

In one embodiment of the present invention, the filling insulation patterns 330 may be filled in the empty regions 321 , respectively. The buried insulating patterns 330 may be formed of an insulating material having excellent gap fill characteristics. The buried insulating patterns 330 may be formed of, for example, a high-density plasma oxide film, a spin on glass layer (SOG), an ALD oxide film, and/or a CVD oxide film.

In one embodiment of the present invention, the pads 340 may be formed on the vertical structures 300 . The pads 340 may be formed of a semiconductor material doped with impurities or a conductive material such as metal. Lower surfaces of the pads 340 may be disposed at a level higher than the upper surface of the uppermost sacrificial layer SC. A lower capping layer 510 may be formed on the upper surfaces of the vertical structures 300 and the stack structure 200 . The lower capping layer 510 may include an insulating material such as silicon oxide, silicon nitride, and/or silicon oxynitride.

Referring to FIG. 4 of the present application, trenches 600 may be formed to pass through the stack structure 200 and the lower capping layer 510 . Forming the trenches 600 includes forming a mask pattern (not shown) defining planar positions of the trenches 600 on the lower capping layer 510 and using the mask pattern as an etch mask to form a stacked structure. and etching (200). Etching the stacked structure 200 may be performed by an anisotropic etching process.

In one embodiment of the present invention, trenches 600 may be formed between adjacent vertical structures 300 . The trenches 600 may be spaced apart from the vertical structures 300 to expose sidewalls of the sacrificial layers SC and sidewalls of the insulating layers IL. The tops of the trenches 600 may have greater widths than their bottoms. The trenches 600 may expose the upper surface 100a of the substrate 100 . During the formation of the trenches 600 , the upper surface 100a of the substrate 100 exposed to the trenches 600 by over-etching may be recessed to a predetermined depth. 1 , the trenches 600 may have long axes parallel to the second direction D2 in a plan view. The trenches 600 may be spaced apart from each other in the first direction D1 .

Referring to FIG. 5 , the sacrificial layers SC may be etched to form gate regions 250 . The gate regions 250 may be voids, and may be regions in which the gate electrode patterns 450 are formed in FIG. 7 . The gate regions 250 are formed between the insulating layers IL and may be connected to the trenches 600 . The gate regions 250 may expose portions of the sidewalls 300c of the vertical structures 300 . The thicknesses of the gate regions 250 may be substantially the same as the thicknesses of the removed sacrificial layers SC. The sacrificial layers SC may be etched by an etching process using an etching composition. The etching process may be a wet etching process.

In one embodiment of the present invention, the etching composition may include an inorganic acid such as phosphoric acid, an ammonium-based compound, and a silane-based compound. Since the sacrificial layers SC include silicon nitride, they may be etched by phosphoric acid as shown in Scheme 1.

In one embodiment of the present invention, for example, an etching composition at 150° C. to 200° C., specifically 155° C. to 170° C. may be supplied on the substrate 100 . Under the temperature condition, phosphoric acid may further etch silicon oxide as well as the sacrificial layers SC. The insulating layers IL may include silicon oxide. In some embodiments, the etching composition may include a silicon-containing compound to prevent/reduce etching of the insulating layers IL by phosphoric acid. For example, in the etching process, oxygen of the silicon-containing compound may be coupled to surfaces of the insulating layers IL to protect the insulating layers IL. Accordingly, during the etching process, the insulating layers IL may exhibit a low etch rate. The oxygen atom of the silicon-containing compound may not interact (eg, hydrogen bond) with the surfaces of the sacrificial layers SC. Accordingly, the etch selectivity of the sacrificial layers SC with respect to the insulating layers IL may be increased. When the silicon-containing compound is unstable, by-products are formed, which can form particles. The by-products and/or particles may cause defects in the manufacturing process of the semiconductor device. For example, byproducts and/or particles may be adsorbed to the insulating layers IL. Since the bonding of the silicon atom and the oxygen atom of the silicon-containing compound is stable, formation of byproducts in the etching process can be prevented. The sacrificial layers SC may be etched to form silicon ions (eg, SiO 2 H 2 O). The ammonium-based compound may remove silicon ions generated while the sacrificial layers SC are etched. Accordingly, abnormal growth of the insulating layers IL by the silicon ions may be prevented/reduced.

In one embodiment of the present invention, in the etching process, the etching composition may be applied on the substrate 100 by coating, dipping, spraying, or spraying. When the etching composition is applied by an immersion method, in the etching process, a batch type apparatus may be used. When the etching composition is sprayed onto the substrate 100 , in the etching process, a single wafer type device may be used. After the etching process, a cleaning process and a drying process using ultrapure water or the like may be performed on the substrate 100 . Ultrapure water may mean water having an impurity of 100 ppb or less.

Referring to FIG. 6 of the present application, a second dielectric pattern 410 and a gate conductive layer 451 may be formed on the stack structure 200 and in the trenches 600 . The second dielectric pattern 410 may be substantially conformally formed on the stack structure 200 and in the trenches 600 . The second dielectric pattern 410 may extend into the trenches 600 and the gate regions 250 . The second dielectric pattern 410 is exposed by the top surface of the uppermost insulating layer IL among the insulating layers IL, sidewalls of the insulating layers IL exposed by the trenches 600 , and gate regions 250 . The upper and lower surfaces of the insulating layers IL, the sidewalls 300c of the vertical structures 300 exposed by the gate regions 250 , and the upper surface 100a of the substrate 100 are substantially It can be covered conformally. The second dielectric pattern 410 may be formed by a deposition process. By adjusting the deposition method and deposition conditions, the second dielectric pattern 410 may be formed to have good step coverage. For example, the deposition process of the second dielectric pattern 410 may be performed by chemical vapor deposition or atomic layer deposition. The second dielectric pattern 410 may include a single layer or a plurality of layers. The second dielectric pattern 410 may be a part of the data storage layer DS of the charge trap type flash memory transistor. Exemplary embodiments of the second dielectric pattern 410 will be described later with reference to FIG. 9 . A gate conductive layer 451 may be formed on the second dielectric pattern 410 . The gate conductive layer 451 may fill at least a portion of each of the trenches 600 and the gate regions 250 . Unlike the drawings, the gate conductive layer 451 may completely fill each of the trenches 600 . Although not shown, a barrier metal layer and a metal layer may be sequentially deposited to form a gate conductive layer 451 . The barrier metal layer may include, for example, a metal nitride such as titanium nitride (TiN), tantalum nitride (TaN), or tungsten nitride (WN). The metal layer may include, for example, tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), cobalt (Co), or copper (Cu).

1 and 7 , the gate conductive layer 451 is patterned to form gate electrode patterns 450 in the gate regions 250 , respectively. The patterning of the gate conductive layer 451 may be performed by an etching process. In this case, the second dielectric pattern 410 may be further etched. In the etching process of the gate conductive layer 451 , the gate conductive layer 451 on the substrate 100 may be removed. The etching of the gate conductive layer 451 may be performed until the insulating layers IL on the sidewalls of the insulating layers IL are removed and the sidewalls of the insulating layers IL are exposed. Accordingly, the gate electrode patterns 450 and the second dielectric pattern 410 may be localized in the gate regions 250 , and gate structures 400 may be formed. Each of the gate structures 400 may be formed between two trenches 600 adjacent to each other. Sidewalls of the gate structures 400 may be exposed to the trenches 600 . The gate structures 400 may expose the upper surface 100a of the substrate 100 in the trenches 600 . The exposed upper surface 100a of the substrate 100 may be further etched. 1 , the gate structures 400 may have long axes parallel to the second direction D2 in a plan view. The gate structures 400 may be spaced apart from each other in the first direction D1 .

In one embodiment of the present invention, each of the gate structures 400 may include stacked gate electrode patterns 450 , a second dielectric pattern 410 , and insulating layers IL. In each of the gate structures 400 , the gate electrode patterns 450 may be interposed between the insulating layers IL. The gate electrode patterns 450 may be used as string selection lines, ground selection lines, and word lines. For example, an uppermost one and a lowermost one of the stacked gate electrode patterns 450 may be used as a string select line and a ground select line, respectively. The gate electrode patterns 450 between the uppermost and lowermost gate electrode patterns 450 may be used as word lines.

In one embodiment of the present invention, in the gate structures 400 , the second dielectric pattern 410 is formed between the gate electrode patterns 450 and the insulating layers IL and between the vertical structure 300 and the insulating layers IL. ) can be interposed between

In an embodiment of the present invention, common source regions CSR may be formed in the substrate 100 exposed to the trenches 600 . The common source regions CSR may be spaced apart from each other in the second direction D2 . The common source regions CSR may be formed through an ion implantation process using the gate structures 400 as ion masks. The common source regions CSR may overlap a portion of the lower portions of the gate structures 400 in a plan view due to diffusion of impurities. The common source regions CSR may have a conductivity type different from that of the substrate 100 . As another example, the common source regions CSR may be performed after the formation of the trenches 600 of FIG. 4 .

1 and 8 , spacers 550 and common source plugs CSP may be respectively formed in the trenches 600 . The spacers 550 may cover sidewalls of the gate structures 400 . The spacers 550 may include an insulating material. The spacers 550 may be formed of, for example, silicon oxide, silicon nitride, silicon oxynitride, or a low-k material. Forming the spacers 550 is common by depositing a spacer layer (not shown) on the substrate 100 to a uniform thickness, covering the gate structures 400 , and performing an etch-back process on the spacer layer. It may include exposing the source regions CSR.

In an embodiment of the present invention, common source plugs CSP may be formed on the spacers 550 to fill the trenches 600 . The common source plugs CSP may be respectively connected to the common source regions CSR. Forming the common source plug CSP may include depositing a barrier metal layer (not shown) covering sidewalls of the spacers 550 and depositing a metal layer (not shown) on the barrier metal layer. . The barrier metal film may include, for example, at least one of tantalum (Ta), tantalum nitride (TaN), titanium (Ti), titanium nitride (TiN), tungsten (W), tungsten nitride (WN), and combinations thereof. can The metal layer may include tungsten (W), aluminum (Al), titanium (Ti), tantalum (Ta), cobalt (Co), or copper (Cu). In a plan view as shown in FIG. 1 , long axes of the common source plugs CSP may extend in parallel with the second direction D2 .

In one embodiment of the present invention, an upper capping layer 520 may be formed on the lower capping layer 510 to cover top surfaces of the common source plug CSP. The upper capping layer 520 may include an insulating material.

In one embodiment of the present invention, bit line contact plugs 530 may be formed in the upper capping layer 520 . The bit line contact plugs 530 may pass through the upper capping layer 520 and the lower capping layer 510 and may be respectively connected to the pads 340 . The bit line contact plugs 530 may be electrically connected to the vertical structures 300 (eg, the semiconductor patterns 320 ) through the pads 340 , respectively. The bit lines BL may be formed on the upper capping layer 520 to connect to the bit line contact plugs 530 . As shown in FIG. 1 , the bit lines BL may extend in the first direction D1 in a plan view. The bit line contact plugs 530 and the bit lines BL may include a conductive material such as metal. Accordingly, the manufacturing of the semiconductor device 1 can be completed. The semiconductor device 1 may be a 3D memory device.

FIG. 9 of the present application is a view for explaining insulating patterns of semiconductor devices according to embodiments, and is an enlarged view of region A of FIG. 8 . Hereinafter, in the description of FIG. 9 , a single insulating film, a single gate electrode pattern, and a single vertical structure will be described for simplicity of explanation.

8 and 9 , the first dielectric pattern 310 may include a tunnel insulating layer 311 , a charge storage layer 312 , and a first blocking insulating layer 313 . The tunnel insulating layer 311 may extend along the vertical structure. The charge storage layer 312 and the first blocking insulating layer 313 may be stacked on the tunnel insulating layer 311 . The tunnel insulating layer 311 may be formed of a material having a lower dielectric constant than that of the first blocking insulating layer 313 . The tunnel insulating layer 311 may include, for example, at least one selected from oxide, nitride, or oxynitride. Alternatively, the tunnel insulating layer 311 may include a high-k material. The high-k material refers to an insulating material having a higher dielectric constant than silicon oxide, and may include zirconium oxide, aluminum oxide, and/or hafnium oxide. The charge storage layer 312 may be interposed between the tunnel insulating layer 311 and the first blocking insulating layer 313 . The charge storage layer 312 may include at least one of a charge trap insulating layer, a floating gate electrode, and conductive nano dots. The first blocking insulating layer 313 may include a high-k material.

In one embodiment of the present invention, the second dielectric pattern 410 may include a second blocking insulating layer. The second blocking insulating layer may be interposed between the gate electrode pattern 450 and the first dielectric pattern 310 and between the gate electrode pattern 450 and the insulating layer IL. The second blocking insulating layer may include a high-k material. For example, the first blocking insulating layer 313 may include a high-k material, and the second blocking insulating layer may be made of a material having a smaller dielectric constant than that of the first blocking insulating layer 313 . As another example, the second blocking insulating layer may be one of high-k materials, and the first blocking insulating layer 313 may be a material having a smaller dielectric constant than that of the second blocking insulating layer.

In one embodiment of the present invention, the first dielectric pattern 310 and the second dielectric pattern 410 may function as a data storage layer. Data stored in the data storage layer may be changed using Fowler-Northernheim tunneling, and the Fowler-Northernheim tunneling may be caused by a voltage difference between the vertical structure 300 and the gate electrode pattern 450 . .

In one embodiment of the present invention, unlike illustrated, the second dielectric pattern 410 may not be formed. As another example, the first blocking insulating layer 313 may not be formed.

semiconductor device

The third aspect of the present application is

a structure formed by stacking an insulating film and a sacrificial film; a space portion formed by etching the sacrificial layer with an etching composition in the structure; and a deposition portion formed by depositing a conductive material or an insulating material in the space portion, wherein the etching composition includes: an inorganic acid; And it provides a semiconductor device comprising the silane-based compound of the formula (1).

Although detailed descriptions of parts overlapping with the first and second aspects of the present application are omitted, the descriptions of the first and second aspects of the present application may be equally applied even if the descriptions thereof are omitted in the third aspect.

Hereinafter, embodiments of the present invention will be described in detail so that those of ordinary skill in the art can easily carry out the present invention. However, the present invention may be embodied in several different forms and is not limited to the embodiments described herein.

manufacturing example. Preparation of etching composition

As a silane-based compound, CAS No. 18727-65-6 compound or CAS No. 133902-90-6 compound was used, phosphoric acid was used as an inorganic acid, and ammonium chloride (AC) or ammonium phosphate dibasic acid (AP2) was mixed as an ammonium-based compound to prepare an etching composition. In this case, 85% phosphoric acid aqueous solution was used.

As a comparative example, a composition containing only phosphoric acid as an inorganic acid without including a silane-based compound and an ammonium-based compound was used. The compositions of Examples and Comparative Examples according to the composition are shown in Table 1 below.

experimental example. Etching rate and selectivity measurement

The nitride film and the oxide film were etched at a process temperature of 165 ° C. using the etching compositions prepared in Examples and Comparative Examples, respectively, and the nitride film was etched using an ellipsometer (NANO VIEW, SEMG-1000), which is a thin film thickness measuring device. And the etching rate of the oxide film was measured and shown in Table 2 below. Specifically, the etch rate in Table 2 below is a numerical value calculated by dividing the difference between the film thickness before the etching treatment and the film thickness after the etching treatment of each film by the etching time (minutes) after each film is etched for 300 seconds.

According to Table 2, it can be seen that the etching rate of the nitride layer is significantly higher than the etching rate of the oxide layer in the etching composition of Examples corresponding to the etching composition of the present invention compared to the etching composition of Comparative Example. This point can be seen as supporting that the etching composition of the present invention selectively etches the nitride layer.

In addition, the solution from the silicon oxide film is collected, and when the concentration of silicon ions in the solution becomes 100 ppm, the etching rate before and after filtering is measured (hereinafter referred to as a dummy etching rate), and the results are shown in Table 3 indicated.

According to Table 3 above, looking at the etching rate and etching selectivity of the silicon oxide film before and after the filter in Comparative Examples and Examples, the difference in the etching rate of the silicon oxide film before and after the filter in Comparative Examples and Examples 4 and 11 and There was a difference in the etching selectivity. However, in Examples 5, 6, 12 and 13, the etch rate and etch selectivity of the silicon oxide film before and after the filter were maintained at the same level. That is, the silicon-oxygen bond of TEOS is broken in the etching composition to generate a large amount of reaction byproducts, and the thickness is increased by adsorption of the generated byproducts to the silicon oxide layer. After that, when the reaction by-products are removed by the filter process, the actual thickness of the etched silicon oxide layer can be measured, so that the etching rate is increased compared to before the filter.

On the other hand, in Examples 5, 6, 12, and 13 containing an ammonium compound, it can be seen that the etching rate of the oxide film is maintained without increasing even after the filter, and it can be seen that the nitride film selectivity is still higher than that of Comparative Example. This means that reaction by-products generated during the etching of the silicon nitride layer are converted into water-soluble compounds by combining with ammonium ions included in the etching composition, and thus the phenomenon of precipitation of reaction by-products is minimized.

Claims (15)

inorganic acids; and
Etching composition comprising a silane-based compound of Formula 1 below:
[Formula 1]

(In Formula 1, R ₁ to R ₁₀ are each independently a substituted or unsubstituted alkyl group having 1 to 10 carbon atoms, a substituted or unsubstituted cycloalkyl group having 3 to 10 carbon atoms, or a substituted or unsubstituted C 1 to C10 substituted or unsubstituted alkyl group. It is selected from the group consisting of an alkenyl group, a substituted or unsubstituted aryl group having 5 to 20 carbon atoms, a substituted or unsubstituted heteroaryl group having 5 to 20 carbon atoms, X ₁ to X ₃ is a halogen element, and n is 0 to 10 of integers, m ₁ to m ₄ are each an integer from 0 to 2, and m ₁ +m ₂ and m ₃ +m ₄ are integers from 0 to 2)
According to claim 1,
In Formula 1, R ₁ to R ₁₀ are each independently a substituted or unsubstituted alkyl group having 1 to 5 carbon atoms, a substituted or unsubstituted alkenyl group having 1 to 5 carbon atoms, or a substituted or unsubstituted aryl group having 5 to 10 carbon atoms. selected from the group consisting of, X ₁ to X ₃ is a halogen element, n is an integer from 0 to 10, m ₁ to m ₄ are each an integer from 0 to 2, m ₁ +m ₂ and m ₃ +m ₄ is an integer from 0 to 2;
The method of claim 1,
The inorganic acid is an etching composition comprising at least one selected from the group consisting of sulfuric acid, nitric acid, phosphoric acid, silicic acid, hydrofluoric acid, boric acid, hydrochloric acid and perchloric acid.
The method of claim 1,
The etching composition comprises 70 to 99 parts by weight of the inorganic acid and 0.01 to 15 parts by weight of the silane-based compound.
According to claim 1,
The etching composition further comprises an ammonium-based compound.
6. The method of claim 5,
The ammonium-based compound is an etching composition comprising at least one of ammonium chloride, ammonium phosphate, ammonium acetate, ammonium sulfate, ammonium formate, and a metal amine complex salt.
According to claim 1,
The etching composition is an etching composition, characterized in that used for etching the silicon nitride layer.
According to claim 1,
The etching composition, characterized in that the silicon nitride film / oxide film etching selectivity of the etching composition is 50 or more.
forming a structure by stacking an insulating film and a sacrificial film on a substrate; and
A method of manufacturing a semiconductor device comprising: performing an etching process using the etching composition according to any one of claims 1 to 7 to remove the sacrificial layer to form a spatial region.
10. The method of claim 9,
The sacrificial layer includes silicon nitride, and the insulating layer includes silicon oxide.
11. The method of claim 10,
In the etching process, the sacrificial layer has an etch rate higher than that of the insulating layer.
10. The method of claim 9,
forming a spatial region by removing the sacrificial layer by performing the etching process; wherein the spatial region includes a gate region formed between the insulating layer and a trench connected to the gate region manufacturing method.
10. The method of claim 9,
forming openings passing through the stacked structure; and
Further comprising forming a semiconductor pattern spaced apart from the trench in the openings,
The forming of the semiconductor pattern is performed before forming the trench.
a structure formed by stacking an insulating film and a sacrificial film;
a space portion formed by etching the sacrificial layer with an etching composition in the structure; and
and a deposition unit formed by depositing a conductive material or an insulating material in the space portion;
The etching composition is
inorganic acids; and
A semiconductor device comprising a silane-based compound of Formula 1 below:
[Formula 1]

(In Formula 1, R ₁ to R ₁₀ are each independently a substituted or unsubstituted alkyl group having 1 to 10 carbon atoms, a substituted or unsubstituted cycloalkyl group having 3 to 10 carbon atoms, or a substituted or unsubstituted C 1 to C10 substituted or unsubstituted alkyl group. It is selected from the group consisting of an alkenyl group, a substituted or unsubstituted aryl group having 5 to 20 carbon atoms, a substituted or unsubstituted heteroaryl group having 5 to 20 carbon atoms, X ₁ to X ₃ is a halogen element, and n is 0 to 10 of integers, m ₁ to m ₄ are each an integer from 0 to 2, and m ₁ +m ₂ and m ₃ +m ₄ are integers from 0 to 2)
15. The method of claim 14,
The semiconductor device, characterized in that the silicon nitride layer / oxide layer etch selectivity of the etching composition is 50 or more.

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