KR20220011558A - Semiconductor device, and semiconductor package comprising the same device - Google Patents

Abstract

The present invention provides a semiconductor device including a cell region and a ferry region having a bank structure suitable for a limited size of a package and a pad structure easy to test and package, and a semiconductor package comprising the same. The semiconductor device comprises: a cell region including a plurality of memory cells arranged to have an array structure; and at least two ferry regions arranged therein with circuits to drive the memory cells and disposed around the cell region. The cell region is divided into a plurality of banks. The banks include a first bank having a basic size and a second bank having 1/(2*n) (n is an integer than 0) size of the basic size. The at least two ferry regions extend in a first direction and are disposed adjacent to the plurality of banks. Chip pads are disposed at an outer wall of the chip to have an L shape, and has a long rectangular shape in a second direction perpendicular to the first direction.

Description

A semiconductor device, and a semiconductor package comprising the semiconductor device TECHNICAL FIELD

The technical idea of the present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a cell region of a plurality of banks and a semiconductor package including the semiconductor device.

BACKGROUND Semiconductor devices such as memory devices are widely used to store information in various electronic devices such as computers, wireless communication devices, cameras, and digital displays. Information may be stored by programming the various states of the memory element. For example, information may be stored in two states, denoted by a logical “1” or a logical “0”. To store information, a component of the electronic device may write or program a state to the memory element, and may also read or sense the state stored in the memory element to access the stored information. Memory devices can be broadly classified into volatile and non-volatile memory devices. In relation to memory devices, research and development are steadily being conducted to increase the density of memory cells, increase read/write speed, increase reliability, increase data retention, decrease power consumption, or decrease manufacturing cost.

The problem to be solved by the technical idea of the present invention is to provide a semiconductor device including a cell region and a peripheral region of a bank structure suitable for a limited package size, and including a pad structure that is easy for testing and packaging, and the semiconductor device It is to provide a semiconductor package equipped with.

In order to solve the above problems, a technical idea of the present invention is to provide a cell region in which a plurality of memory cells are arranged in an array structure; and at least two peripheral regions in which circuits for driving the memory cells are disposed and disposed around the cell region, wherein the cell region is divided into a plurality of banks, wherein the banks have a basic size. a first bank and a second bank having a size of 1/(2*n) (n being an integer greater than or equal to 1) of the basic size, wherein the at least two peripheral regions extend in a first direction, and the plurality of Provided is a semiconductor device, which is disposed immediately adjacent to the banks, wherein chip pads are disposed in an “L” shape at an outer portion of the chip, and has the shape of a rectangular chip elongated in a second direction perpendicular to the first direction do.

In addition, the technical idea of the present invention, in order to solve the above problems, a cell region in which a plurality of memory cells are arranged in an array structure; and a peripheral region in which circuits for driving the memory cells are disposed and disposed around the cell region, wherein the cell region is divided into a plurality of banks, wherein the banks are arranged in a first direction and the first direction A first bank disposed along a second direction perpendicular to the direction and comprising a first bank having a basic size and a second bank having a size of 1/(2*n) (n is an integer greater than or equal to 1) of the basic size, wherein A semiconductor device having a shape of a rectangular chip elongated in a second direction perpendicular to one direction is provided.

Further, the technical idea of the present invention, in order to solve the above problems, a package substrate; a first stacked structure mounted on the package substrate and stacked with a plurality of chips; a second stacked structure mounted on the package substrate and disposed adjacent to the first stacked structure, in which the same number of chips as the first stacked structure are stacked; and a sealing material sealing the first stacked structure and the second stacked structure on the package substrate, wherein each of the chips includes a cell region in which a plurality of memory cells are disposed in an array structure, and the memory Circuits for driving cells are disposed, and include a peripheral region disposed around the cell region, wherein the cell region is divided into a plurality of banks, wherein the banks are in a first direction and perpendicular to the first direction. disposed along a second direction, comprising a first bank having a basic size and a second bank having a size of 1/(2*n) (n being an integer greater than or equal to 1) of the basic size, the second bank being perpendicular to the first direction A semiconductor package having a rectangular shape elongated in the second direction is provided.

According to the inventive concept, in a semiconductor device, as the second bank has various sizes, various bank structures can be implemented in a cell region by combining the first bank and the second bank. For example, when the semiconductor device includes only the first bank of the basic size, the structure of the bank in the cell region is inevitably limited. The bank structure in the second bank may be changed more variously based on the second bank.

In addition, the semiconductor device according to the technical idea of the present invention has the shape of a rectangular chip elongated in the second direction (y-direction), and can constitute a stacked structure. In addition, two stacked structures may be disposed adjacent to each other on a package substrate to constitute a semiconductor package, and such a semiconductor package may have a significantly increased memory capacity while satisfying the standard standard for package size of JEDEC.

1A to 1D are plan views and conceptual views of a semiconductor device including a cell region and a peripheral region according to an embodiment of the present invention.
2A to 3B are plan views of semiconductor devices including a cell region and a peripheral region according to embodiments of the present invention.
4 is a plan view of a semiconductor device including a pad structure according to an embodiment of the present invention.
5A to 7B are plan views of semiconductor devices including a structure of a pad and a structure of a wiring connected to the pad according to an exemplary embodiment of the present invention.
8A and 8B are a plan view and a cross-sectional view of a semiconductor package according to an embodiment of the present invention.
9A to 10B are plan views illustrating a structure in which semiconductor chips are variously stacked in the semiconductor package of FIG. 8A .

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and duplicate descriptions thereof are omitted.

1A to 1D are plan views and conceptual views of a semiconductor device including a cell region and a peripheral region according to an embodiment of the present invention. FIG. 1B is a plan view of one bank portion in the semiconductor device of FIG. 1A, and FIG. 1C FIG. 1B is a conceptual diagram illustrating a connection relationship between memory cells in a bank and peripheral circuits and/or core circuits, and FIG. 1D is a conceptual diagram illustrating a wiring structure for input/output of data in the semiconductor device of FIG. 1A.

1A to 1D , the semiconductor device 100 according to the present embodiment may include a cell area 110 and a peripheral area 120 .

A plurality of memory cells may be arranged in a two-dimensional array structure in the cell region 110 . As shown in FIG. 1A , the cell region 110 may be divided into a plurality of banks (banks, B1, and B2), and a plurality of memory cells are provided in each of the banks (B1, B2) in a two-dimensional array structure. can be placed. Meanwhile, the semiconductor device 100 may be classified into various memory devices according to the types of memory cells disposed in the cell region 110 . For example, in the cell region 110 , a planar FET (Field Effect Transistor) or FET such as a FinFET, a flash memory, a dynamic random access memory (DRAM), a static random access memory (SRAM), an electrically erasable programmable read (EEPROM), etc. -Only Memory), PRAM (Phase-change Random Access Memory), MRAM (Magnetoresistive Random Access Memory), FeRAM (Ferroelectric Random Access Memory), RRAM (Resistive Random Access Memory), such as memory cells may be disposed, and accordingly , the semiconductor device 100 may be divided into FET memory, flash memory, DRAM, SRAM, EEPROM, PRAM, MRAM, FeRAM, RRAM device, and the like. The semiconductor device 100 of the present embodiment may be a DRAM device, and accordingly, DRAM cells may be disposed in the cell region 110 . Of course, the semiconductor device 100 of the present embodiment is not limited to the DRAM device. Hereinafter, for convenience of description, a DRAM device will be mainly described for the semiconductor device 100 of the present embodiment.

In the semiconductor device 100 of the present embodiment, the cell region 110 may include 17 banks B1 and B2. Also, the banks B1 and B2 may include a first bank B1 having a basic size and a second bank B2 having a size of 1/2 of the basic size. Here, the size may mean a physical area. Also, the size may mean the number of memory cells included in the bank, that is, the memory capacity of the bank. For example, in the semiconductor device 100 of the present embodiment, the first bank B1 and the second bank B2 have the same size in the second direction (y-direction), and the first bank B1 and the second bank B2 have the same size in the first direction (x-direction). When (B1) has a size of '1', the second bank B2 may have a size of '1/2'. On the other hand, in terms of memory capacity, assuming that the semiconductor device 100 of this embodiment has a memory capacity of 16 Gb (Gigabit) or 2 GB (GigaByte), the first bank B1 has a memory capacity of 1 Gb, The second bank B2 may have a memory capacity of 0.5 Gb.

In the semiconductor device 100 of the present embodiment, the size of the second bank B2 is not limited to 1/2 the size of the first bank B1. For example, according to an embodiment, the second bank B2 may have a size of 1/4, 1/8, etc. of the first bank B1. That is, the second bank B2 may have a size of 1/(2*n) (n is an integer greater than or equal to 1) of the first bank B1. Also, according to an embodiment, the second bank B2 may include banks of different sizes. For example, the second bank B2 may include a bank having a size of 1/2 of the first bank B1 and a bank having a size of 1/4 of the first bank B1 . However, the overall size of the second bank B2 may be an integer multiple of the size of the first bank B1 . For example, the second bank B2 includes one bank of the size of 1/2 of the first bank B1 and two banks of the size of 1/4, and the total size is that of one first bank B1. It can be the same size.

In the semiconductor device 100 of the present embodiment, as shown in FIG. 1A , 15 first banks B1 and two second banks B2 may be disposed in the cell region 110 . . Five first banks B1 may be disposed along the first direction (x-direction) and three may be disposed along the second direction (y-direction). Also, two second banks B2 may be disposed along the second direction (y-direction). More specifically, the second bank B2 may be disposed adjacent to the right side of the first bank B1 at a second position in the first direction (x-direction). Also, the second bank B2 may be disposed at first and second positions from the bottom in the second direction (y-direction).

In the semiconductor device 100 of the present embodiment, the arrangement structure of the first bank B1 and the second bank B2 is not limited to the arrangement structure of FIG. 1A . For example, according to an embodiment, the second bank B2 may be disposed at first and third positions from the bottom in the second direction (y-direction), or may be disposed at second and third positions. Also, when the width of the first core region 122 in the first direction (x-direction) is secured to a certain extent, the second bank B2 may be disposed at any position in the first direction (x-direction).

The peripheral region 120 may be disposed around the cell region 110 . More specifically, the peripheral region 120 is disposed between the banks B1 and B2 at the first position and the banks B1 and B2 at the second position from the bottom in the second direction (y direction), and in the first direction. (x direction) can be extended. Peripheral circuits for operation of memory cells and/or core circuits for operation and the like may be disposed in the peripheral region 120 . In the semiconductor device 100 of the present embodiment, the peripheral region 120 may include one peripheral region, for example, the first peripheral region P1 .

Meanwhile, the core regions 122 and 124 may be disposed adjacent to the banks B1 and B2 of the cell region 110 . Peripheral circuits for input/output of data or commands or input of power/ground may be disposed in the peripheral region 120 , and core circuits performing operations such as decoders may be disposed in the core regions 122 and 124 . According to an embodiment, the entire region other than the cell region 110 may be referred to as a peripheral region or a core-periphery region. In the semiconductor device 100 of the present embodiment, the peripheral region 120 and the core regions 122 and 124 may be used separately. Peripheral circuits and core circuits disposed in the peripheral region 120 and the core regions 122 and 124 will be described in more detail in the descriptions of FIGS. 1B and 1C .

In the semiconductor device 100 of the present embodiment, an additional peripheral region 125 may be further disposed around the cell region 110 . The additional peripheral region 125 is disposed between the second bank B2 and the first bank B1 at a third position from the left in the first direction (x-direction), and may extend in the second direction (y-direction). have. Peripheral circuits, core circuits, wirings, etc. may be disposed in the additional peripheral region 125 . For example, core circuits for the banks B1 and B2 may be disposed in the additional peripheral region 125 . Meanwhile, in the second direction (y-direction), the additional ferry region 125 includes a first additional peripheral region AP1 disposed above the ferry region 120 and a second additional peripheral region AP2 disposed below it in the second direction (y-direction). can do. According to an embodiment, a redistribution connecting the wirings on the peripheral region 120 to the pads (see 140 of FIG. 4 ) outside the chip may be disposed on the second additional peripheral region AP2 .

A similar bank area SB may be disposed at a third location from the bottom in the second direction (y direction) at a location where the second bank B2 is disposed in the first direction (x-direction). The physical size of the similar bank area SB may be substantially the same as that of the second bank B2. However, devices other than memory cells may be disposed in the similar bank area SB. For example, a device such as an anti-fuse or a DC generator may be disposed in the similar bank region SB. Of course, the devices disposed in the similar bank region SB are not limited to the aforementioned devices.

As can be seen from FIG. 1B , the core regions 122 and 124 may be disposed around the banks B1 and B2 . The core regions 122 and 124 may be divided into a first core region 122 extending in a second direction (y-direction) and a second core region 124 extending in a first direction (x-direction). A row decoder (R/D) may be disposed in the first core area 122 , and a column decoder (C/D) may be disposed in the second core area 124 . The row decoder (R/D) is sometimes referred to as an X-decoder. Meanwhile, in the second core region 124 , a sense amplifier (S/A) may be disposed along with the column decoder (C/D).

Referring to FIG. 1C , the connection relationship and operations between the memory cells of the bank B1 or B2 and the peripheral circuits and/or core circuits disposed in the peripheral circuits and/or core circuits will be described in more detail. Operations such as reading and writing of memory cells A word line 132 and a bit line 134 for . may be disposed to be connected to the memory cells 112 . The word line 132 may extend in, for example, a first direction (x-direction), and the bit line 134 may extend in a second direction (y-direction). The word line 132 and the bit line 134 may be formed of, for example, a metal such as copper (Cu), aluminum (Al), gold (Au), or tungsten (W). However, the material of the word line 132 and the bit line 134 is not limited to metal. For example, the word line 132 and the bit line 134 may be formed of a conductive material such as a metal alloy, carbon, a semiconductor doped with an impurity, a compound of another conductivity, or the like.

Each row of memory cells 112 may be connected to a word line 132 . Also, each column of the memory cells 112 may be connected to a bit line 134 . By activating one word line 132 and one bit line 134, for example, by applying a voltage to the corresponding word line 132 and the corresponding bit line 134, one memory cell ( 112) can be accessed. Accessing the memory cell 112 may include reading from or writing to the memory cell 112 . The intersection of the word line 132 and the bit line 134 may be referred to as the address of the memory cell 112 .

Briefly describing the access of the memory cell 112 with a DRAM device, the logical storage element of the memory cell 112, eg, a capacitor, may be electrically isolated from the bit line 134 via a transistor. On the other hand, the word line 132 may be connected to the transistor and may control the transistor. For example, word line 132 may be connected to the gate of a transistor. With this connection structure, when the word line 132 is activated, an electrical connection circuit or a closed circuit is formed between the capacitor of the memory cell 112 and its corresponding bit line 134 , and then through the bit line 134 . The memory cell 112 may be accessed to read or write to the memory cell 112 .

Accessing the memory cell 112 may be controlled through a row decoder R/D and a column decoder C/D. For example, the row decoder R/D may receive a row address from a memory controller (M/C) and activate an appropriate word line 132 based on the received row address. Similarly, the column decoder C/D may receive a column address from the memory controller M/C and activate an appropriate bit line 134 . The memory controller M/C may be disposed, for example, in the peripheral region 120 .

As described above, the row decoder R/D and the column decoder C/D may be disposed in the core regions 122 and 124 adjacent to the bank B1 or B2. Accordingly, the row decoder R/D and the column decoder C/D may receive a row address and a column address for the memory cell 112 located in the bank B1 or B2, respectively. For example, bank B1 or B2 may include a plurality of word lines 132 denoted as WL_1 through WL_M, and a plurality of bit lines 134 denoted as DL_1 through DL_N, where M and N represent banks B1 or may depend on the array size of B2). Thus, by activating word line 132 and bit line 134, eg, WL_2 and DL_3, the memory cell 112 at its intersection can be accessed.

On the other hand, when the memory cell 112 is accessed, it may be read or sensed by the sense amplifier S/A to determine the stored state of the memory cell 112 . For example, after accessing the memory cell 112 , the capacitor of the memory cell 112 may be discharged to the corresponding bit line 134 . When discharged, the voltage of the bit line 134 may be changed, and the sense amplifier S/A may determine the stored state of the memory cell 112 by comparing it with a reference voltage.

As described above, the sense amplifier S/A may be disposed together with the column decoder C/D in the second core region 124 . The sense amplifier S/A may include various transistors or amplifiers for detecting and amplifying a signal difference. The detected logic state of the memory cell 112 may be output through a column decoder C/D and an input-output unit (I/O). According to an embodiment, the sense amplifier S/A may be treated as a part of the column decoder C/D. Meanwhile, the input/output unit I/O may include pads (see 140 and 150 of FIG. 4 ) for input/output of data and commands, power/ground input, and the like.

The memory controller M/C may control the operation of the memory cell 112 through various components, for example, a row decoder (R/D), a column decoder (C/D), a sense amplifier (S/A), and the like. can Operations of the memory cell 112 may include, for example, reading, writing, rewriting, refreshing, discharging, and the like. The memory controller M/C may generate a row address signal and a column address signal to activate the word line 132 and the bit line 134 . Also, the memory controller M/C may generate and control various voltages or currents used for the operation of the memory cell 112 . The memory controller M/C may communicate commands, data, and other information with the host device.

In the semiconductor device 100 according to the present embodiment, data input/output to the memory cell 112 in the bank B1 or B2 may be performed through the following process. Data from the memory cell 112 is transferred to the peripheral region 120 through the second core region 124 of the corresponding bank, and input/output pads disposed outside the chip through redistribution in the peripheral region 120 . (Refer to 140 of FIG. 4 ) and may be output in a way that is transmitted. Conversely, data from the input/output pads 140 may be input in such a way that it is transferred to the memory cell 112 of the corresponding bank through the redistribution, the peripheral region 120 , and the second core region 124 of the corresponding bank. can Here, the output of data may mean reading data, and the input of data may mean writing or storing data.

Meanwhile, as can be seen from FIG. 1D , the wiring 130 may include a first wiring 130 - 1 , a second wiring 130 - 2 , and a third wiring 130 - 3 . The first interconnection 130 - 1 may be disposed on the peripheral region 120 . The second wiring 130 - 2 connects the circuits in the second core region 124 of the banks B1 and B2 at first and second positions in the second direction (y direction) to the first wiring in the peripheral region 120 . (130-1) can be connected. The third wiring 130 - 3 connects circuits in the second core region 124 of the first bank B1 at a third position in the second direction (y direction) to the first wiring 130 - in the peripheral region 120 . 1) can be connected. The second core region 124 of the first bank B1 at the third position in the second direction (y direction) is the second core region 124 of the banks B1 and B2 at the first and second positions in the second direction (y direction). Compared to the second core region 124 , it is relatively far from the peripheral region 120 , and accordingly, the second interconnection 130 - 2 may be shorter than the third interconnection 130 - 3 .

Based on the structure of the wiring 130 , data into the memory cells 112 of the first bank B1 in the third position in the second direction (y direction) using the relatively long third wiring 130 - 3 is I/O may be slower than input/output of data to the memory cells 112 of the banks B1 and B2 at first and second positions in the second direction (y-direction) using the short second wiring 130 - 2 . Also, the third wiring 130 - 3 may be disposed to pass through the banks B1 and B2 at a second position in the second direction (y direction). In addition, in the case of the second bank B2 , the first and second directions in the second direction (y-direction) are taken into consideration when the distance between the second core region 124 and the peripheral region 120 and the corresponding wiring length are considered. may be placed in position. Also, the peripheral region 120 may be disposed between the second bank B2 at the first position in the second direction (y-direction) and the second bank B2 at the second position.

As shown in FIG. 1A , the semiconductor device 100 of the present embodiment may have a shape of a rectangular chip elongated in the second direction (y-direction). The rectangular chip may have a first width W1 in a first direction (x-direction) and a second width W2 in a second direction (y-direction). For example, the first width W1 may be 5.7 mm or less, and the second width W2 may be 10.92 mm or less. Of course, the first width W1 and the second width W2 are not limited to the above numerical values. When a semiconductor package is implemented using the semiconductor device 100 of the present embodiment, the semiconductor device 100 is adjacent to the package substrate (see 200 of FIG. 8A ) in the first direction (x-direction) based on the size of the above-described chip. Thus, two can be mounted. In addition, a plurality of semiconductor devices 100 may be stacked in a third direction perpendicular to the x-y plane to form a stacked structure (refer to 100S1 and 100S2 of FIG. 8A ). Similar to the semiconductor device 100 , two stacked structures 100S1 and 100S2 may be mounted adjacent to each other in the first direction (x-direction) on the package substrate 200 . The semiconductor package including the semiconductor device 100 of the present embodiment will be described in more detail in the description of FIGS. 8A to 10B .

In the semiconductor device 100 of the present embodiment, as the second bank B2 has various sizes, the first bank B1 and the second bank B2 are combined to form various bank structures in the cell region 110 . can be implemented. For reference, when the semiconductor device includes only the first bank B1 of the basic size, the bank structure in the cell region 110 is inevitably limited. For example, when the 16 Gb semiconductor device 100 includes only the first bank B1 having a basic size of 1 Gb, 16 first banks B1 are included in the cell region 110, and 1*16, 2*8 , and only 4*4 arrangement structures may be possible. On the other hand, when the 16 Gb semiconductor device 100 includes the first bank B1 having a basic size of 1 Gb and the second bank B2 having a size of 1/2 of 0.5 Gb together, the cell region 110 has With 15 first banks B1 and two second banks B2, an arrangement structure such as 3*5 + 0.5*2 may be possible. Of course, the bank structure in the cell region 110 may be more variously changed based on various sizes of the second bank B2 .

The semiconductor device 100 of the present embodiment may have a rectangular chip shape elongated in the second direction (y-direction), and may constitute a stacked structure in which a plurality of semiconductor devices are stacked. In addition, based on the shape of a rectangular chip, two stacked structures may be disposed adjacent to each other on the package substrate 200 to constitute a semiconductor package, and such a semiconductor package is a package size of the Joint Electron Device Engineering Council (JEDEC) It is possible to have a significantly increased memory capacity while satisfying the standard specification of

2A to 3B are plan views of semiconductor devices including a cell region and a peripheral region according to embodiments of the present invention. Contents already described in the description part of FIGS. 1A to 1D will be briefly described or omitted.

Referring to FIGS. 2A and 2B , the semiconductor device 100a of this embodiment has the structure of the peripheral region 120a and the structure of the first bank B1 of the cell region 110a according to the structure of the semiconductor device 100a of FIG. 1A . (100) may be different. Specifically, in the semiconductor device 100a of the present exemplary embodiment, the peripheral region 120a may include a first peripheral region P1 and a second peripheral region P2 . The first peripheral region P1 may be substantially the same as the first peripheral region P1 of the semiconductor device 100 of FIG. 1A . Accordingly, the first peripheral region P1 is disposed between the banks B1 and B2 at the first position in the second direction (y direction) and the banks B1 and B2 at the second position, and in the first direction (x). direction) can be extended.

The second peripheral region P2 may be disposed on the outermost side of the semiconductor device 100a in the second direction (y-direction) and may extend in the first direction (x-direction). For example, the second peripheral region P2 may be disposed outside the first bank B1 at a third position in the second direction (y-direction). Also, the banks B1 and B2 at the second position in the second direction (y-direction) and the first bank B1 at the third position are disposed between the first and second peripheral regions P1 and P2. can be

As the second peripheral region P2 is disposed at the outer portion of the semiconductor device 100a in the second direction (y-direction), the second core region of the first bank B1 at a third position in the cell region 110a 124 may be disposed on the upper side in the second direction (y-direction). For example, the second core area 124 of the first bank B1 at the third location may be disposed between the first bank B1 at the third location and the second peripheral area P2 .

Meanwhile, as can be seen from FIG. 2B , the wiring 130a may include a first wiring 130-1, a second wiring 130-2, and a fourth wiring 130-4. The first wiring 130 - 1 may be disposed on the peripheral region 120a. The second wiring 130 - 2 connects the circuits in the second core region 124 of the banks B1 and B2 at first to third positions in the second direction (y direction) to the first wiring in the peripheral region 120a. (130-1) can be connected. More specifically, the second wiring 130 - 2 connects the circuits of the second core region 124 of the banks B1 and B2 at first and second positions in the second direction (y direction) to the first peripheral region ( The circuits in the second core region 124 of the first bank B1 at the third position in the second direction (y-direction) are connected to the first wiring 130-1 of P1) and are connected to the second peripheral region. It may be connected to the first wiring 130-1 of (P2). The fourth interconnection 130 - 4 may connect the first interconnection 130 - 1 of the first peripheral region P1 to the first interconnection 130 - 1 of the second peripheral region P2 . The fourth wiring 130 - 4 may be disposed on the first additional peripheral area AP1 .

In the semiconductor device 100a of the present embodiment, data input/output to the memory cells 112 in the banks B1 and B2 may be performed through the following process. Data from the memory cells 112 of the banks B1 and B2 in the first and second positions in the second direction (y direction) passes through the second core region 124 of the corresponding bank to the first peripheral region P1 . is transmitted from the first peripheral region P1 to the input/output pads (see 140 of FIG. 4 ) disposed on the second peripheral region P2 through the fourth wiring 130-4. can be In addition, data from the memory cell 112 of the first bank B1 at the third position in the second direction (y-direction) goes to the second peripheral region P2 through the second core region 124 of the bank. After being transferred, the output may be directly transferred to the input/output pads 140 disposed on the second peripheral region P2 . Conversely, data from the input/output pads 140 passes through the second peripheral region P2 , the first peripheral region P1 , and the second core region 124 of the corresponding bank to the memory cells 112 of the corresponding bank. ) or through the second peripheral region P2 and the second core region 124 of the corresponding bank to the memory cell 112 of the corresponding bank.

In the semiconductor device 100a of the present embodiment, the second peripheral region P2 is additionally disposed outside the first bank B1 at the third position in the second direction (y-direction), and the first bank at the third position The second core region 124 of (B1) may be disposed immediately adjacent to the second peripheral region P2. Accordingly, as in the semiconductor device 100 of FIG. 1A , the third wiring 130 - 3 extending long through the banks B1 and B2 may not exist. Also, since the fourth wiring 130 - 4 is disposed on the first additional peripheral area AP1 , a problem such as a need for a separate wiring area or a wiring having to pass through a bank may not occur. Furthermore, in the semiconductor device 100a of the present exemplary embodiment, input/output pads 140 are disposed in the second peripheral region P2 , and accordingly, the first wiring 130 - 1 of the second peripheral region P2 . ) may be directly connected to the pads 140 , so rewiring as in the semiconductor device 100 of FIG. 1A may not be necessary. As a result, in the semiconductor device 100a of this embodiment, based on the structure of the peripheral region 120a and the structure of the banks B1 and B2 of the cell region 110a, data input/output to and from the memory cell 112 is very easy. and can be done quickly.

Meanwhile, the semiconductor device 100a of the present embodiment may also have the shape of a rectangular chip elongated in the second direction (y-direction). The rectangular chip may have a first width W1 of 5.7 mm or less in the first direction (x-direction) and a second width W2 of 10.92 mm or less in the second direction (y-direction). Of course, the first width W1 and the second width W2 are not limited to the above numerical values. However, in the case of the semiconductor device 100a of the present embodiment, since the second peripheral region P2 is further included, the banks B1 and B2 and the second core region ( 124) may have a small width in the second direction (y-direction).

Referring to FIGS. 3A and 3B , the semiconductor device 100b of this embodiment has the structure of the peripheral region 120a and the structure of the first bank B1 of the cell region 110b according to the structure of the semiconductor device 100b of FIG. 2A . (100a) may be different. Specifically, in the semiconductor device 100b of the present embodiment, the peripheral region 120b may include a first peripheral region P1 and a second peripheral region P2, similarly to the semiconductor device 100a of FIG. 2A . can The first peripheral region P1 may be substantially the same as the first peripheral region P1 of the semiconductor device 100a of FIG. 2A . Accordingly, the first peripheral region P1 is disposed between the banks B1 and B2 at the first position in the second direction (y direction) and the banks B1 and B2 at the second position, and in the first direction (x). direction) can be extended.

However, unlike the semiconductor device 100a of FIG. 2A , the second peripheral region P2 includes the second banks B1 and B2 in the second direction (y-direction) and the first bank B1 in the third position. It is disposed between and may extend in the first direction (x-direction). Also, the banks B1 and B2 at a second position in the second direction (y-direction) may be disposed between the first and second peripheral regions P1 and P2 .

As the second peripheral region P2 is disposed between the second banks B1 and B2 in the second direction (y-direction) and the first bank B1 in the third position, in the cell region 110a, three The second core region 124 of the first bank B1 at the second position may be disposed on the lower side in the second direction (y-direction). For example, the second core area 124 of the first bank B1 at the third location may be disposed between the first bank B1 at the third location and the second peripheral area P2 .

Meanwhile, as can be seen from FIG. 3B , the wiring 130b may include a first wiring 130 - 1 , a second wiring 130 - 2 , and a fourth wiring 130 - 4 ′. The first interconnection 130 - 1 may be disposed on the peripheral region 120b. The second wiring 130 - 2 connects the circuits in the second core region 124 of the banks B1 and B2 in the first to third positions in the second direction (y direction) to the first wiring in the peripheral region 120b. (130-1) can be connected. More specifically, the second wiring 130 - 2 connects the circuits of the second core region 124 of the banks B1 and B2 at first and second positions in the second direction (y direction) to the first peripheral region ( The circuits in the second core region 124 of the first bank B1 at the third position in the second direction (y-direction) are connected to the first wiring 130-1 of P1) and are connected to the second peripheral region. It may be connected to the first wiring 130-1 of (P2). The fourth wiring 130 - 4 ′ may connect the first wiring 130 - 1 of the first peripheral region P1 to the first wiring 130 - 1 of the second peripheral region P2 . The fourth interconnection 130 - 4 ′ may be disposed on the first additional peripheral region AP1 .

Meanwhile, in the semiconductor device 100b of the present embodiment, the additional peripheral region 125a may include first to third additional peripheral regions AP1 , AP2 , and AP3 . The first additional peripheral area AP1 is disposed between the second bank B2 and the first bank B1 at a third position from the left in the first direction (x direction), and is disposed between the second bank B2 and the first bank B1 in the second direction (y direction). It is disposed at a portion corresponding to the banks B1 and B2 at the second position, and may extend in the second direction (y-direction). The second additional peripheral area AP2 is disposed between the second bank B2 and the first bank B1 at a third position from the left in the first direction (x-direction), and the first in the second direction (y-direction) It is disposed at a portion corresponding to the banks B1 and B2 at the second position, and may extend in the second direction (y-direction). The third additional peripheral area AP3 is disposed between the second bank B2 and the first bank B1 at a third position from the left in the first direction (x-direction), and is arranged in three directions in the second direction (y-direction). It is disposed in a portion corresponding to the first bank B1 at the second position, and may extend in the second direction (y-direction).

In the semiconductor device 100b of the present embodiment, data input/output to the memory cells 112 in the banks B1 and B2 may be performed through the following process. Data from the memory cells 112 of the banks B1 and B2 in the first and second positions in the second direction (y direction) passes through the second core region 124 of the corresponding bank to the first peripheral region P1 . is transmitted to, and may be output in such a way that it is transmitted to the input/output pads 140 disposed outside the chip through redistribution in the first peripheral region P1 . In addition, data from the memory cell 112 of the first bank B1 at the third position in the second direction (y-direction) goes to the second peripheral region P2 through the second core region 124 of the bank. is transmitted to the first peripheral region P1 through the fourth wiring 130 - 4 ′, and is transmitted from the first peripheral region P1 to the input/output pads 140 through the redistribution. can be Conversely, data from the input/output pads 140 is transferred to the memory cell 112 of the corresponding bank through the redistribution, the first peripheral region P1, and the second core region 124 of the corresponding bank, or Alternatively, the input may be transmitted to the memory cell 112 of the corresponding bank through the redistribution, the first peripheral region P1 , the second peripheral region P2 , and the second core region 124 of the corresponding bank. .

In the semiconductor device 100b of the present embodiment, the second peripheral region P2 is additionally disposed between the second banks B1 and B2 in the second direction (y-direction) and the first bank B1 in the third position. and the second core region 124 of the first bank B1 at the third position may be disposed immediately adjacent to the second peripheral region P2 . Accordingly, as in the semiconductor device 100 of FIG. 1A , the third wiring 130 - 3 extending long through the banks B1 and B2 may not exist. In addition, since the fourth wiring 130 - 4 ′ is disposed on the first additional peripheral area AP1 , a problem such as a need for a separate wiring area or a wiring having to pass through a bank may not occur. . As a result, in the semiconductor device 100b of this embodiment, based on the structure of the peripheral region 120b and the structure of the banks B1 and B2 of the cell region 110b, data input/output to and from the memory cell 112 is very easy. and can be done quickly.

Meanwhile, the semiconductor device 100b of this embodiment has a second peripheral region P2 in the second direction (y-direction) and a first bank B1 at a third position, compared to the semiconductor device 100a of FIG. 2A . Since only the position of the second core region 124 of , is changed, the first width W1 in the first direction (x-direction) and the second width W2 in the second direction (y-direction) are the semiconductor device ( 100a) may be substantially the same as the first width W1 and the second width W2.

4 is a plan view of a semiconductor device including a pad structure according to an embodiment of the present invention. The content already described in the description part of FIGS. 1A to 3B will be briefly described or omitted.

Referring to FIG. 4 , the semiconductor device 100a according to the present exemplary embodiment may include an “L”-shaped chip pad CP. The chip pad CP may include a first pad 140 for a package and a second pad 150 for a test. The first pad 140 may correspond to a pad connected to a wire when the semiconductor device 100a is mounted on a package substrate (see 200 of FIG. 8A ) through wire bonding. The second pad 150 may be a pad used to test whether the semiconductor device 100a is normal, or a pad not used after the test.

The first pad 140 may be disposed on the second peripheral area AP2 and may be disposed along the first direction (x-direction). In FIG. 4 , the first pads 140 are arranged in one row along the first direction (x-direction), but according to an embodiment, the first pads 140 may be arranged in two or more rows. Meanwhile, although not clearly distinguished, the first pad 140 may be divided into a data pad, a command pad, and a power/ground pad. Here, data may be transmitted through the data pad, a command may be transmitted through the command pad, and power and ground voltage may be applied through the power/ground pad. In general, the data pad and the power/ground pad may be disposed at both outer sides, and the command pad may be disposed at the center portion. However, the positions of the data pad, the command pad, and the power/ground pad are not limited to the above-described positions.

The second pad 150 may be disposed on a side portion adjacent to the second peripheral area AP2 . For example, the second pad 150 may be disposed on a right side portion adjacent to the second peripheral area AP2 and may be disposed along the second direction (y-direction). However, the present invention is not limited thereto, and the second pad 150 may be disposed on the left side adjacent to the second peripheral area AP2 . Meanwhile, due to the function of the second pad 150 , the second pad 150 may be disposed on a side portion facing the second peripheral area AP2 . However, in the case of such a pad structure, it may deviate from the "L" shape.

Meanwhile, the semiconductor device 100a of the present embodiment may be the semiconductor device 100a of FIG. 2A . Accordingly, in the semiconductor device 100a of the present embodiment, the peripheral region 120a includes a first peripheral region P1 and a second peripheral region P2, and the second peripheral region P2 is formed in the second direction ( y-direction), and may be disposed at the outermost portion of the semiconductor device 100a. In addition, the second core region 124 of the third first bank B1 in the second direction (y-direction) is disposed on the upper side of the third first bank B1 and is in the second peripheral region P2. can be directly adjacent. However, the semiconductor device 100a of the present embodiment is not limited to the semiconductor device 100a of FIG. 2A . For example, the semiconductor device 100a of the present embodiment may be the first semiconductor device 100 or the semiconductor device 100b of FIG. 3A .

The semiconductor device 100a of the present embodiment includes the "L"-shaped chip pads CP, thereby increasing the number of pads available for chip testing, and easily packaging according to the required size of the semiconductor package. can make this happen. For example, in the semiconductor device 100a of the present embodiment, the first pad 140 required for packaging is disposed on the short side portion where the second peripheral region P2 is disposed, and the second pad 140 required for testing is disposed on the adjacent long side portion. By disposing the pads 150, the number of pads that can be used during chip testing can be increased, and since the pads are arranged on one side during packaging, the semiconductor device 100a can be used according to the required size of the semiconductor package. may be easily disposed on the package substrate 200 . A connection structure between the first pad 140 and the package substrate 200 will be described in more detail with reference to FIGS. 8A to 10B .

5A to 7B are plan views of semiconductor devices including a pad structure and a structure of a wiring connected to the pad according to an embodiment of the present invention, wherein FIGS. 5A and 5B correspond to the semiconductor device of FIG. 1A, and , FIGS. 6A and 6B may correspond to the semiconductor device of FIG. 2A . Contents already described in the description part of FIGS. 1A to 4 will be briefly described or omitted.

5A and 5B , the semiconductor device 100 according to the present embodiment may include a first pad 140a for a package. The first pad 140a may include a first partial pad 142 disposed on a short side of the semiconductor device 100 and a second partial pad 144 disposed on a long side of the semiconductor device 100 . For example, the first partial pad 142 may be a command pad, and the second partial pad 144 may be a data pad. Meanwhile, the power/ground pad may be included in at least one of the first partial pad 142 and the second partial pad 144 . In addition, the semiconductor device 100 of FIGS. 5A and 5B may correspond to a shape in which the semiconductor device 100 of FIG. 1A is rotated by 180°.

As shown in FIG. 5B , the semiconductor device 100 according to the present embodiment has a structure of a first pad 140a and a wiring 130 of the peripheral region 120 , for example, a first wiring 130 - 1 . may include a redistribution 160 for connecting to the first pad 140a. The redistribution 160 may include a first redistribution 162 and a second redistribution 164 . The first redistribution 162 connects the wiring 130 of the peripheral region 120 to the first partial pad 142 , and the second redistribution 164 forms the wiring 130 of the peripheral region 120 . It can be connected by a two-part pad 144 .

6A and 6B , the semiconductor device 100a of the present embodiment may include a first pad 140 for a package. The first pad 140 may be disposed in the second peripheral region P2 of the semiconductor device 100a and may be disposed in a first direction (x-direction). Although not separately illustrated, the first pad 140 may include a data pad, a command pad, and a power/ground pad. For example, the data pad and the power/drown pad may be disposed at both outer sides, and the command pad may be disposed at the center portion.

As shown in FIG. 6B , the semiconductor device 100a of the present embodiment may have a structure of the first pad 140 and may not include a separate redistribution. In other words, the first wiring 130 - 1 of the second peripheral region P2 may be directly connected to the first pad 140 without a separate redistribution. In addition, the first wiring 130 - 1 of the first peripheral region P1 is connected to the first wiring 130 - 1 of the first peripheral region P1 through a fourth wiring 130 - 4 , The first wiring 130 - 1 of the first peripheral region P1 may be directly connected to the first pad 140 without a separate redistribution.

7A and 7B , the semiconductor device 100c of the present embodiment may include a first pad 140b for a package. The first pad 140b may include a first partial pad 142a disposed on a short side of the semiconductor device 100c and a second partial pad 144a disposed on a long side of the semiconductor device 100c. For example, the first partial pad 142a may include a data pad and a command pad, and the second partial pad 144a may include a power/ground pad. However, the types of the first partial pad 142a and the second partial pad 144a are not limited to the aforementioned pads.

As shown in FIG. 7B , the semiconductor device 100c according to the present exemplary embodiment has a structure of a first pad 140b, and a part of the first wiring 130 - 1 of the second peripheral region P2 is formed as a second A redistribution line 160a connected to the partial pad 144a may be included. Meanwhile, a portion of the first wiring 130 - 1 of the second peripheral region P2 may be directly connected to the first partial pad 142a without redistribution. Also, the first wiring 130 - 1 of the first peripheral region P1 is connected to the first wiring 130 - 1 of the second peripheral region P2 through the fourth wiring 130 - 4 , and again , a portion of the first wiring 130 - 1 of the second peripheral region P2 is connected to the second partial pad 144a through the redistribution 160a, and the other portion is connected to the first partial pad 142a without redistribution. ) can be directly connected to

Meanwhile, in the semiconductor device 100c of the present embodiment, except for the arrangement structure of the first pad 140b, the structures of the banks B1 and B2 and the peripheral region 120a of the cell region 110a are shown in FIG. 2A . It may be substantially the same as the semiconductor device 100a. Accordingly, in the semiconductor device 100c of the present embodiment, the peripheral region 120a includes a first peripheral region P1 and a second peripheral region P2, and the second peripheral region P2 is formed in the second direction ( y-direction) in the outermost portion of the semiconductor device 100c. In addition, the second core region 124 of the third first bank B1 in the second direction (y-direction) is disposed on the upper side of the third first bank B1 and is in the second peripheral region P2. can be directly adjacent.

8A and 8B are a plan view and a cross-sectional view of a semiconductor package according to an embodiment of the present invention, and FIG. 8A shows only the first semiconductor chip 100-1 at the bottom of each of the stacked structures without the sealing material; FIG. 8B is a cutaway view of part II′ of FIG. 8A . The content already described in the description part of FIGS. 1A to 7B will be briefly described or omitted.

8A and 8B , the semiconductor package 1000 according to the present embodiment may include a package substrate 200 , stacked structures 100S1 and 100S2 , an adhesive layer 300 , and a sealing material 400 .

The package substrate 200 is a support substrate on which the stack structures 100S1 and 100S2 are mounted, and may include at least one layer of wiring therein. In the case where the wirings are formed in multiple layers, wirings of different layers may be connected to each other through vertical contacts. According to an embodiment, the package substrate 200 may include a through electrode directly connecting the pads on the upper surface and the lower surface. Although not shown, protective layers such as solder resist may be formed on the upper and lower surfaces of the package substrate 200 . The pads are connected to the wirings of the wiring layer and may be exposed from the protective layer. The package substrate 200 may be formed based on, for example, a ceramic substrate, a PCB, an organic substrate, an interposer substrate, or the like. According to an embodiment, the package substrate 200 may be formed of an active wafer such as a silicon wafer.

As shown in FIG. 8B , an external connection member 250 such as a bump or a solder ball may be disposed on the lower surface of the package substrate 200 . The external connection member 250 may function to mount the semiconductor package 1000 on an external system board or main board. The external connection member 250 may be formed as a multi-layer or a single layer. For example, when formed in multiple layers, the external connection member 250 may include a copper pillar and solder. In the case of being formed as a single layer, the connection member 330 may include tin-silver solder or copper.

Meanwhile, the semiconductor package 1000 of the present embodiment may satisfy the JEDEC standard for a semiconductor package including a DRAM device. Accordingly, the package substrate 200 may have a third width W3 in the first direction (x-direction) and a fourth width W4 in the second direction (y-direction). For example, the third width W3 may be 12.4 mm, and the fourth width W4 may be 14 mm.

The stacked structures 100S1 and 100S2 may include a first stacked structure 100S1 and a second stacked structure 100S2 . The first stacked structure 100S1 and the second stacked structure 100S2 may be disposed adjacent to each other in the first direction (x-direction) on the package substrate 200 . Since the structures of the first stacked structure 100S1 and the second stacked structure 100S2 are substantially the same, hereinafter, the first stacked structure 100S1 will be mainly described.

The first stacked structure 100S1 may include first to fourth semiconductor chips 100-1 to 100-4 sequentially stacked. Each of the first to fourth semiconductor chips 100-1 to 100-4 may be, for example, the semiconductor device 100a of FIG. 2A . However, the present invention is not limited thereto, and each of the first to fourth semiconductor chips 100 - 1 to 100 - 4 may be the semiconductor devices 100 , 100b and 100c of FIGS. 1A , 3A and 7A .

Each of the first to fourth semiconductor chips 100 - 1 to 100 - 4 may be laminated by being adhered to the package substrate 200 through the adhesive layer 300 or on the corresponding semiconductor chip underneath. The adhesive layer 300 may be, for example, a die attach film (DAF). However, the material of the adhesive layer 300 is not limited to the DAF. Meanwhile, the first stacked structure 100S1 may have various shapes according to the stacked structures of the first to fourth semiconductor chips 100-1 to 100-4. The stacked structure of the first stacked structure 100S1 will be described in more detail in the description part of FIGS. 9A to 10B .

The sealing material 400 may cover and seal the stacked structures 100S1 and 100S2 on the package substrate 200 . The sealing material 400 may seal the stacked structures 100S1 and 100S2 to protect them from external physical and chemical damage. The sealing material 400 may be formed of, for example, an epoxy-based material, a thermosetting material, a thermoplastic material, a UV curable material, or the like. In addition, the sealing material 400 is formed of resin, and may contain a filler. As shown in FIG. 8B , the sealing material 400 may have a structure covering the upper surfaces of the stack structures 100S1 and 100S2 . However, the present invention is not limited thereto, and the sealing material 400 may have a structure that does not cover the upper surfaces of the stacked structures 100S1 and 100S2 . For example, the upper surface of the fourth semiconductor chip 100 - 4 may be exposed from the sealing material 400 .

In the semiconductor package 1000 of the present embodiment, the number of semiconductor chips constituting each of the stack structures 100S1 and 100S2 is not limited to four. For example, each of the stack structures 100S1 and 100S2 may include 1 to 3 or 5 or more semiconductor chips. For reference, in the semiconductor package 1000 of the present embodiment, each of the first to fourth semiconductor chips 100-1 to 100-4 of the stacked structures 100S1 and 100S2 is the semiconductor device 100a of FIG. 2A , and a semiconductor When the device 100a has a memory capacity of 16 Gb and the semiconductor package 1000 has a memory capacity of 8 GB, that is, 64 Gb, four semiconductor chips may be disposed on the package substrate 200 , and the stack structure 100S1 , 100S2) may each include two semiconductor chips. In addition, when the semiconductor package 1000 has a capacity of 16 GB, that is, 128 Gb, eight semiconductor chips may be disposed on the package substrate 200 , and each of the stack structures 100S1 and 100S2 includes four semiconductor chips. can do.

In the semiconductor package 1000 of the present embodiment, the semiconductor chips 100 - 1 to 100 - 4 of each of the stack structures 100S1 and 100S2 may be stacked so that pads are exposed. Accordingly, the thickness of the adhesive layer 300 for bonding the semiconductor chips 100 - 1 to 100 - 4 to the package substrate 200 or the corresponding semiconductor chip underneath can be minimized. Accordingly, the overall thickness of the semiconductor package 1000 may be minimized. For example, the total thickness of the semiconductor package 1000 may be 0.7 mm or less, and the thickness of the adhesive layer 300 may be 0.01 mm or less. Meanwhile, according to an embodiment, the semiconductor package 1000 may have a thickness of 0.67 mm or less by adjusting the thickness of at least one of the semiconductor chips 100 - 1 to 100 - 4 , the package substrate 200 , and the sealing material 400 . It may have a thickness.

9A to 10B are plan views illustrating a structure in which semiconductor chips are stacked in various ways in the semiconductor package of FIG. 8A. In FIGS. 9A to 10B, only the semiconductor chips are shown, and the package substrate and sealing material are omitted. have. It will be described with reference to FIGS. 8A and 8B , and the content already described in the description part of FIGS. 1A to 8B will be briefly described or omitted.

Referring to FIG. 9A , the semiconductor package 1000 of this embodiment may be the semiconductor package 1000 of FIG. 8A . In the semiconductor package 1000 of the present embodiment, the first stack structure 100S1 may have a structure in which the semiconductor chips 100 - 1 to 1004 are stacked in a zigzag shape in the second direction (y-direction). Also, the first pads 140 of the semiconductor chips 100 - 1 to 1004 may be alternately disposed upward and downward in the second direction (y-direction). More specifically, the first semiconductor chip 100 - 1 may protrude downward in the second direction (y direction), and the first pad 140 may be disposed on a short side portion below the second direction (y direction). The second semiconductor chip 100 - 2 may protrude upward in the second direction (y-direction), and the first pad 140 may be disposed on a short side portion upwardly in the second direction (y-direction). Subsequently, the third semiconductor chip 100 - 3 protrudes downward in the second direction (y direction), the first pad 140 is disposed on a short side portion below the second direction (y direction), and the fourth semiconductor chip 100 - 3 The chip 100 - 4 may protrude upward in the second direction (y-direction), and the first pad 140 may be disposed on a short side portion upwardly in the second direction (y-direction). For reference, in the case of FIG. 9A , only the third semiconductor chip 100 - 3 and the fourth semiconductor chip 100 - 4 are shown due to the zigzag stacked structure of the first stacked structure 100S1 .

Referring to FIG. 9B , the first stacked structure 100S1a of the semiconductor package 1000a of the present embodiment may include the semiconductor chips 100-1 to 100-4 of the semiconductor device 100a of FIG. 2A or 6A. have. In the semiconductor package 1000a of the present embodiment, the first stacked structure 100S1a may have a structure in which the semiconductor chips 100 - 1 to 1004 are stacked in a step shape in the second direction (y-direction). In addition, the first pad 140 of the semiconductor chips 100 - 1 to 1004 may be disposed only downward in the second direction (y-direction). More specifically, the semiconductor chips 100-1 to 1004 have a step shape sequentially protruding downward in the second direction (y-direction), and the first pad 140 of each of the semiconductor chips 100-1 to 1004 is All of them may be disposed on the short side portion below the second direction (y-direction).

Referring to FIG. 10A , the first stacked structure 100S1b of the semiconductor package 1000b according to the present exemplary embodiment may include the semiconductor chips 100-1 to 100-4 of the semiconductor device 100c of FIG. 7A . In the semiconductor package 1000b of the present embodiment, the first stack structure 100S1b may have a structure in which the semiconductor chips 100 - 1 to 1004 are stacked in a zigzag shape in a diagonal direction. Also, the first pads 140 of the semiconductor chips 100 - 1 to 1004 may be alternately disposed upward and downward in a diagonal direction. More specifically, the first semiconductor chip 100 - 1 may protrude upward in a diagonal direction, and the first pad 140 may be disposed on a portion of a short side and a long side of an upper side in the diagonal direction. The second semiconductor chip 100 - 2 may protrude downward in a diagonal direction, and the first pad 140 may be disposed on a portion of a short side and a long side of the diagonally downward direction. Subsequently, the third semiconductor chip 100 - 3 protrudes upward in the diagonal direction, the first pad 140 is disposed on a part of the short side and the long side in the upper diagonal direction, and the fourth semiconductor chip 100 - 4 may protrude downward in a diagonal direction, and the first pad 140 may be disposed on a portion of a short side and a long side of the diagonally downward direction. For reference, in the case of FIG. 10A , only the third semiconductor chip 100 - 3 and the fourth semiconductor chip 100 - 4 are shown due to the zigzag stacked structure of the first stacked structure 100S1b.

Referring to FIG. 10B , the first stacked structure 100S1c of the semiconductor package 1000c according to the present embodiment may include the semiconductor chips 100-1 to 100-4 of the semiconductor device 100c of FIG. 7A . In the semiconductor package 1000c of the present embodiment, the first stacked structure 100S1c may have a structure in which the semiconductor chips 100 - 1 to 1004 are stacked in a diagonal direction in a step shape. In addition, the first pads 140 of the semiconductor chips 100 - 1 to 1004 may be disposed only diagonally upward. More specifically, the semiconductor chips 100-1 to 1004 have a step shape sequentially protruding upward in a diagonal direction, and the first pads 140 of each of the semiconductor chips 100-1 to 1004 are all diagonally formed. It may be disposed on a part of the short side and the long side of the upper side.

Up to now, the present invention has been described with reference to the embodiment shown in the drawings, but this is only exemplary, and it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible therefrom. will be. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

100, 100a to 100c: semiconductor device, 100-1 to 100-4: semiconductor chip, 100S1, 100S1a, 100S1b, 100S1c, 100S2: stacked structure, 110, 110a, 100b: cell region, 112: memory cell, 120, 120a , 120b: peripheral region, 122, 124: core region, 130, 130a, 130b: wiring, 132: word line, 134: bit line, 140, 140a, 140b: first pad, 150: second pad, 160, 160a : rewiring, 200: package substrate, 250: external connection member, 300: adhesive layer, 400: sealing material, 1000, 1000a to 1000c: semiconductor package

Claims (20)

a cell region in which a plurality of memory cells are arranged in an array structure; and
circuits for driving the memory cells are disposed, and at least two peripheral regions disposed around the cell region;
The cell area is divided into a plurality of banks,
The banks include a first bank having a basic size and a second bank having a size of 1/(2*n) (n is an integer greater than or equal to 1) of the basic size,
the at least two of the peripheral regions extend in a first direction and are disposed immediately adjacent to the plurality of banks;
Chip pads are arranged in an "L" shape on the outer part of the chip,
A semiconductor device having a shape of a rectangular chip elongated in a second direction perpendicular to the first direction. According to claim 1,
The second bank has a size of 1/2 of the basic size,
The cell region includes 15 of the first banks and two of the second banks,
Five of the first banks are arranged along the first direction, and three are arranged along the second direction,
The second bank is disposed between the first banks at second and third positions in the first direction. 3. The method of claim 2,
wherein the at least two peripheral regions include a first peripheral region and a second peripheral region;
The first peripheral region is disposed between the banks at first and second positions in the second direction,
the second peripheral region is disposed outside the first bank at a third position in the second direction;
and the banks at second and third positions are disposed between the first and second peripheral regions in the second direction. 4. The method of claim 3,
An additional peripheral region extending in the second direction is disposed between the second bank in the first direction and the first bank. 3. The method of claim 2,
The two second banks are disposed adjacent to each other in the second direction, or disposed spaced apart from each other,
A similar bank region is disposed outside the second bank or between the two second banks along the second direction. According to claim 1,
The chip pads include first pads for a package and second pads for a test,
The semiconductor device of claim 1, wherein the first pads are disposed on a short side of the chip, and the second pads are disposed on a long side of the chip. 7. The method of claim 6,
Some of the first pads are disposed on the long side. According to claim 1,
The chip has a size of 5.7 mm or less in the first direction and 10.92 mm or less in the second direction,
The semiconductor device, characterized in that it has a memory capacity of 16 Gb (Gigabit). a cell region in which a plurality of memory cells are arranged in an array structure; and
a peripheral region in which circuits for driving the memory cells are disposed and disposed around the cell region;
The cell area is divided into a plurality of banks,
The banks are arranged along a first direction and a second direction perpendicular to the first direction, and the size of a first bank having a basic size and 1/(2*n) (n is an integer greater than or equal to 1) of the basic size Including a second bank having,
A semiconductor device having a shape of a rectangular chip elongated in a second direction perpendicular to the first direction. 10. The method of claim 9,
The second bank has a size of 1/2 of the basic size,
The cell region includes 15 of the first banks and two of the second banks,
Five of the first banks are arranged along the first direction, and three are arranged along the second direction,
The second bank is disposed between the first banks at second and third positions in the first direction. 10. The method of claim 9,
The peripheral region includes the first peripheral region and the second peripheral region;
the first and second peripheral regions extend along the first direction, respectively;
the first peripheral region is disposed between the banks at first and second positions in the second direction;
The second peripheral region is disposed at an outer portion of the chip in the second direction. 10. The method of claim 9,
A semiconductor device, characterized in that the chip pads are arranged in an "L" shape on the outer portion of the chip. 13. The method of claim 12,
The chip pads include first pads for a package and second pads for a test,
The first pads are disposed on a short side or a short side and a long side of the chip, and the second pads are disposed on a long side of the chip. package substrate;
a first stacked structure mounted on the package substrate and stacked with a plurality of chips;
a second stacked structure mounted on the package substrate and disposed adjacent to the first stacked structure, in which the same number of chips as the first stacked structure are stacked; and
a sealing material sealing the first laminated structure and the second laminated structure on the package substrate;
Each of the chips,
a cell region in which a plurality of memory cells are arranged in an array structure; and a peripheral region in which circuits for driving the memory cells are arranged, and arranged around the cell region;
The cell area is divided into a plurality of banks,
The banks are arranged along a first direction and a second direction perpendicular to the first direction, and the size of a first bank having a basic size and 1/(2*n) (n is an integer greater than or equal to 1) of the basic size Including a second bank having,
A semiconductor package having a rectangular shape elongated in a second direction perpendicular to the first direction. 15. The method of claim 14,
The package substrate is 12.4 mm or less in the first direction and 14 mm or less in the second direction,
The semiconductor package, characterized in that each of the chips has a capacity of 16 Gb. 15. The method of claim 14,
The second bank has a size of 1/2 of the basic size,
The cell region includes 15 of the first banks and two of the second banks,
Five of the first banks are arranged along the first direction, and three are arranged along the second direction,
The second bank is disposed between the first banks at second and third positions in the first direction. 15. The method of claim 14,
The peripheral region includes the first peripheral region and the second peripheral region;
the first and second peripheral regions extend along the first direction, respectively;
the first peripheral region is disposed between the banks at first and second positions in the second direction;
The second peripheral region is disposed at an outer portion of each of the chips in the second direction. 15. The method of claim 14,
Chip pads are arranged in an "L" shape on the outer portion of each of the chips,
wherein the chip pads include first pads for a package and second pads for a test. 19. The method of claim 18,
The first pads are disposed on a short side or a short side and a long side of each of the chips,
The second pads are disposed on a long side of the chip. 20. The method of claim 19,
When the first pads are disposed only on the end surfaces of each of the chips, the chips are also stacked in a zigzag shape in the second direction,
When the first pads are disposed on the end face and the long side of each of the chips, the chips are stacked in a zigzag shape in a diagonal direction with the first pads exposed.

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