KR20220010453A - Deep uv light emitting diode - Google Patents

Abstract

A deep ultraviolet light emitting diode is provided. A deep ultraviolet light emitting diode according to an embodiment comprises: a substrate; an n-type semiconductor layer positioned on the substrate; a mesa which is disposed on the n-type semiconductor layer, comprises an active layer and a p-type semiconductor layer, and has a plurality of via-holes exposing the n-type semiconductor layer; n-ohmic contact layers coming in contact with the n-type semiconductor layer in the via-holes; a p-ohmic contact layer coming in contact with the p-type semiconductor layer; an n-pad metal layer electrically connected to the n-ohmic contact layers; a p-pad metal layer electrically connected to the p-ohmic contact layer; an n-bump electrically connected to the n-pad metal layer; and a p-bump electrically connected to the p-pad metal layer, wherein the p-pad metal layer is formed so as to surround the n-pad metal layer. According to the present invention, light extraction efficiency is improved.

Description

Deep UV light emitting diode {DEEP UV LIGHT EMITTING DIODE}

The present invention relates to an inorganic semiconductor light emitting diode, and more particularly, to a light emitting diode emitting deep ultraviolet light of 300 nm or less.

In general, light emitting diodes emitting ultraviolet light within the range of 200 to 300 nm can be used in various applications, including as an excitation source for sterilization devices, water or air purification devices, high-density optical recording devices, and bio-aerosol fluorescence detection systems.

Unlike near-ultraviolet or blue light-emitting diodes, light-emitting diodes that emit relatively deep ultraviolet light include a well layer containing Al, such as AlGaN. Due to the composition of the gallium nitride-based semiconductor layer, the deep ultraviolet light emitting diode has a structure significantly different from that of a blue light emitting diode or a near ultraviolet light emitting diode.

In particular, the deep ultraviolet light emitting diode according to the prior art has a structure different from that of a general blue light emitting diode or near ultraviolet light emitting diode in the shape and position of the mesa disposed on the n-type semiconductor layer. That is, the mesa is formed to be biased toward one side from the center of the n-type semiconductor layer, and the p-bump is disposed on the mesa, and the n-bump is disposed near the other side opposite to the one side and spaced apart from the mesa.

These conventional ultraviolet light emitting diodes generally have disadvantages of low light output and high forward voltage. In particular, the deep ultraviolet light emitting diode achieves good internal quantum efficiency with the improvement of the crystal quality of the semiconductor layer, but the light extraction efficiency is very low. Light extraction efficiency is reduced by total internal or internal light loss. For example, the p-type GaN layer included for the ohmic contact absorbs ultraviolet rays generated by the active layer, and the n-ohmic contact layer bonded to the n-type semiconductor layer also absorbs ultraviolet rays.

Furthermore, since it is difficult to utilize the light emitted from the side of the mesa, the conventional UV light emitting diode tends to reduce the total area of the side of the mesa as much as possible. That is, the mesa is formed to have a relatively wide width. However, as the mesa width increases, the distance from the n-ohmic contact layer to the mesa central region increases, which is not good for current distribution, and thus the forward voltage increases. Moreover, poor current dissipation performance limits the increase in current density, thereby limiting the luminous intensity that can be achieved with individual light emitting diodes.

An object of the present invention is to provide a deep ultraviolet light emitting diode having a novel structure capable of improving electrical characteristics and/or light output.

Another problem to be solved by the present invention is to provide a deep ultraviolet light emitting diode capable of improving current dissipation performance.

A deep ultraviolet light emitting diode according to an embodiment of the present invention, the deep ultraviolet light emitting diode according to an embodiment, a substrate; an n-type semiconductor layer positioned on the substrate; a mesa disposed on the n-type semiconductor layer, including an active layer and a p-type semiconductor layer, and having a plurality of via holes exposing the n-type semiconductor layer; n-ohmic contact layers contacting the n-type semiconductor layer in the via holes; a p-ohmic contact layer in contact with the p-type semiconductor layer; an n pad metal layer electrically connected to the n ohmic contact layers; a p pad metal layer electrically connected to the p ohmic contact layer; an n bump electrically connected to the n pad metal layer; and a p-bump electrically connected to the p-pad metal layer, wherein the p-pad metal layer is formed to surround the n-pad metal layer.

A light emitting diode according to another embodiment of the present invention includes: a substrate; an n-type semiconductor layer positioned on the substrate; a mesa disposed on the n-type semiconductor layer, including an active layer and a p-type semiconductor layer, and having a plurality of via holes exposing the n-type semiconductor layer; n-ohmic contact layers contacting the n-type semiconductor layer in the via holes; a p-ohmic contact layer in contact with the p-type semiconductor layer; an n bump electrically connected to the n ohmic contact layers; and a p-bump electrically connected to the p-ohmic contact layer, wherein the p-ohmic contact layer includes Ni/Rh.

A deep ultraviolet light emitting diode according to another embodiment of the present invention, a substrate; an n-type semiconductor layer positioned on the substrate; a mesa disposed on the n-type semiconductor layer, including an active layer and a p-type semiconductor layer, and including a groove exposing the n-type semiconductor layer; n-ohmic contact layers contacting the n-type semiconductor layer in the groove; a p-ohmic contact layer in contact with the p-type semiconductor layer; an n pad metal layer electrically connected to the n ohmic contact layers; a p pad metal layer electrically connected to the p ohmic contact layer; an n bump electrically connected to the n pad metal layer; and a p-bump electrically connected to the p-pad metal layer.

According to embodiments of the present invention, it is possible to provide a deep ultraviolet light emitting diode capable of evenly distributing current in a mesa by employing a plurality of via holes. Furthermore, by adopting Ni/Rh as the p-type ohmic contact layer, a deep ultraviolet light emitting diode having improved light extraction efficiency can be provided. In addition, since the luminous intensity of individual light emitting diodes can be increased by increasing the current density injected into the light emitting diodes, in particular, the number of light emitting diodes required to sterilize bacteria or viruses can be reduced, and the sterilization time can be reduced. .

Advantages and features of the present invention will be discussed in detail or will become apparent from the detailed description.

1A is a schematic plan view illustrating an ultraviolet light emitting diode according to an embodiment of the present invention.
Fig. 1B is a schematic cross-sectional view taken along line A-A' of Fig. 1A;
2A, 3A, 4A, 5A, 6A, 7A, and 8A are schematic plan views for explaining a method of manufacturing an ultraviolet light emitting diode according to an embodiment of the present invention.
2B, 3B, 4B, 5B, 6B, 7B, and 8B are the cut-away lines A-A' of FIGS. 2A, 3A, 4A, 5A, 6A, 7A, and 8A, respectively. Schematic cross-sectional views taken along
9 is a diagram illustrating a light output distribution of an ultraviolet light emitting diode manufactured according to an embodiment of the present invention.
10A is a cross-sectional SEM photograph showing an interface after Ni/Au is deposited on a p-type contact layer and heat-treated.
10B is a cross-sectional SEM photograph showing an interface after Ni/Rh is deposited on a p-type contact layer and heat-treated.
11A, 11B, and 11C are schematic plan views for explaining modifications of the via hole shape of the ultraviolet light emitting diode according to embodiments of the present invention.
12A is a schematic plan view for explaining an ultraviolet light emitting diode according to an embodiment of the present invention.
12B is a schematic cross-sectional view taken along line B-B' of FIG. 12A.
13A, 14A, 15A, 16A, 17A, 18A, 19A, and 20A are schematic plan views for explaining a method of manufacturing an ultraviolet light emitting diode according to an embodiment of the present invention.
13B, 14B, 15B, 16B, 17B, 18B, 19B, and 20B are respectively FIGS. 13A, 14A, 15A, 16A, 17A, 18A, 19A, and 20A. Schematic cross-sectional views taken along the perforated line B-B' of
21 is a schematic plan view for explaining a modified example of a mesa of an ultraviolet light emitting diode according to an embodiment of the present invention.
22 is a schematic plan view for explaining another modified example of a mesa of an ultraviolet light emitting diode according to an embodiment of the present invention.
23A is a schematic plan view illustrating an ultraviolet light emitting diode according to an embodiment of the present invention.
23B is a schematic cross-sectional view taken along line C-C' of FIG. 23A.
24A, 25A, 26A, 27A, 28A, 29A, 30A, and 31A are schematic plan views for explaining a method of manufacturing an ultraviolet light emitting diode according to an embodiment of the present invention.
24B, 25B, 26B, 27B, 28B, 29B, 30B, and 31B are respectively FIGS. 24A, 25A, 26A, 27A, 28A, 29A, 30A, and 31A respectively. Schematic cross-sectional views taken along the perforated line C-C'.
32 is a schematic plan view for explaining a modified example of a mesa of an ultraviolet light emitting diode according to an embodiment of the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. The embodiments introduced below are provided as examples so that the spirit of the present invention can be sufficiently conveyed to those skilled in the art to which the present invention pertains. Accordingly, the present invention is not limited to the embodiments described below and may be embodied in other forms. And, in the drawings, the width, length, thickness, etc. of the components may be exaggerated for convenience. In addition, when one component is described as being “on” or “on” another component, each component is different from each component as well as when each component is “immediately above” or “directly on” the other component. It includes the case where another component is interposed between them. Like reference numerals refer to like elements throughout.

The nitride-based semiconductor layers described below may be grown using a variety of generally known methods, for example, metal organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), or hydration vapor phase epitaxy (HVPE). It can be grown using technology. However, in the embodiments described below, it is described that the semiconductor layers are grown in a growth chamber using MOCVD. In the process of growing the nitride-based semiconductor layers, a generally known source may be used as the sources introduced into the growth chamber. For example, TMGa, TEGa, etc. may be used as a Ga source, and TMAl, TEAl, etc. may be used as an Al source. , TMIn, TEIn, etc. may be used as the In source, and NH ₃ may be used as the N source. However, the present invention is not limited thereto.

A deep ultraviolet light emitting diode according to an embodiment of the present invention, the deep ultraviolet light emitting diode according to an embodiment, a substrate; an n-type semiconductor layer positioned on the substrate; a mesa disposed on the n-type semiconductor layer, including an active layer and a p-type semiconductor layer, and having a plurality of via holes exposing the n-type semiconductor layer; n-ohmic contact layers contacting the n-type semiconductor layer in the via holes; a p-ohmic contact layer in contact with the p-type semiconductor layer; an n pad metal layer electrically connected to the n ohmic contact layers; a p pad metal layer electrically connected to the p ohmic contact layer; an n bump electrically connected to the n pad metal layer; and a p-bump electrically connected to the p-pad metal layer, wherein the p-pad metal layer is formed to surround the n-pad metal layer.

By forming a plurality of via holes in the mesa, the current can be uniformly distributed, and further, it is possible to prevent a non-emission area from being formed in the mesa. Conventionally, when the width of the mesa is wide, the distance from the n-ohmic contact layer to the inside of the mesa is increased to form a non-emission area. On the other hand, in the present application, by disposing a plurality of via-holes in the mesa and forming an n-ohmic contact layer in the via-holes, current can be evenly distributed in the mesa.

In an embodiment, the via holes may be arranged in a honeycomb shape. Accordingly, the via-holes may be spaced apart from each other at the same distance to evenly distribute the current.

Meanwhile, the via holes may be spaced apart from the edge of the mesa by more than a distance between the via holes.

The n-pad metal layer may cover the via holes.

The p pad metal layer may be positioned between the via holes and an edge of the mesa.

The n-bump and the p-bump may be located in an upper region of the mesa. Accordingly, light may be emitted through the side surface of the mesa.

The deep UV light emitting diode may further include a lower insulating layer covering the p ohmic contact layer and the n ohmic contact layer, the lower insulating layer having openings exposing the p ohmic contact layer and the n ohmic contact layer , the n-pad metal layer and the p-pad metal layer may be electrically connected to the n-ohmic contact layer and the p-ohmic contact layer through openings of the lower insulating layer, respectively.

An upper insulating layer may further include an upper insulating layer covering the n and p pad metal layers, wherein the upper insulating layer has openings exposing the n pad metal layer and the p pad metal layer, and the n and p bumps are on the upper insulating layer. may be electrically connected to the n-pad metal layer and the p-pad metal layer through the openings of the upper insulating layer.

In an embodiment, the opening exposing the n-pad metal layer is disposed near one edge of the mesa, and the opening exposing the p-pad metal layer is disposed near the opposite edge of the mesa.

In an embodiment, the p-type semiconductor layer may include a p-type GaN layer, and the p-type GaN layer may have a thickness of 200 nm or less. Furthermore, the p-ohmic contact layer may include Ni/Rh.

In an embodiment, the n-pad metal layer may include an Al layer.

A light emitting diode according to another embodiment of the present invention includes: a substrate; an n-type semiconductor layer positioned on the substrate; a mesa disposed on the n-type semiconductor layer, including an active layer and a p-type semiconductor layer, and having a plurality of via holes exposing the n-type semiconductor layer; n-ohmic contact layers contacting the n-type semiconductor layer in the via holes; a p-ohmic contact layer in contact with the p-type semiconductor layer; an n bump electrically connected to the n ohmic contact layers; and a p-bump electrically connected to the p-ohmic contact layer, wherein the p-ohmic contact layer includes Ni/Rh.

The plurality of via holes may be spaced apart from each other at the same distance, and may be arranged in a honeycomb shape.

Furthermore, the deep ultraviolet light emitting diode may include: a lower insulating layer covering the n-ohmic contact layers and the p-ohmic contact layer; and an n-pad metal layer and a p-pad metal layer disposed on the lower insulating layer, wherein the lower insulating layer has openings exposing the n-ohmic contact layers and the p-ohmic contact layer, respectively, and the n-pad The metal layer and the p-pad metal layer may be electrically connected to the n-ohmic contact layers and the p-ohmic contact layer through the openings, respectively, and the n-bump and the p-bump may be electrically connected to the n-pad metal layer and the p-pad metal layer, respectively. .

The p-pad metal layer may surround the n-pad metal layer.

Also, the opening exposing the p-ohmic contact layer may have a ring shape surrounding the via holes.

In an embodiment, the p pad metal layer may be located in an upper portion of a region between the via holes and an edge of the mesa. Accordingly, the p pad metal layer does not cover the side surface of the mesa.

The deep UV light emitting diode may further include an upper insulating layer including the n-pad metal layer and the p-pad metal layer, the upper insulating layer having openings exposing the n-pad metal layer and the p-pad metal layer; The n-bump and the p-bump may be electrically connected to the n-pad metal layer and the p-pad metal layer through the openings of the upper insulating layer, respectively.

The lower insulating layer and the upper insulating layer may cover side surfaces of the mesa.

Meanwhile, the opening exposing the n-pad metal layer may be disposed near one edge of the mesa, and the opening exposing the p-pad metal layer may be disposed near the opposite edge of the mesa.

The p-type semiconductor layer may include a p-type GaN layer, the p-type GaN layer may have a thickness of 200 nm or less, and the Ni/Rh may be in ohmic contact with the p-type GaN layer.

A deep ultraviolet light emitting diode according to another embodiment of the present invention, a substrate; an n-type semiconductor layer positioned on the substrate; a mesa disposed on the n-type semiconductor layer, including an active layer and a p-type semiconductor layer, and including a groove exposing the n-type semiconductor layer; n-ohmic contact layers contacting the n-type semiconductor layer in the groove; a p-ohmic contact layer in contact with the p-type semiconductor layer; an n pad metal layer electrically connected to the n ohmic contact layers; a p pad metal layer electrically connected to the p ohmic contact layer; an n bump electrically connected to the n pad metal layer; and a p-bump electrically connected to the p-pad metal layer.

The deep ultraviolet light emitting diode may include an n capping layer covering the n ohmic contact layers; and a p capping layer covering the p ohmic contact layer.

The groove may extend in the longitudinal direction of the mesa, and a difference between the length of the mesa in the longitudinal direction and the length of the groove may be less than or equal to the width of each of the mesa regions positioned on both sides of the groove.

The sum of the areas of the mesa regions positioned on both sides of the groove may exceed 1/2 of the total area of the mesa.

Corners of one end of the mesa region positioned on both sides of the groove may have a curved shape.

Concave portions may be respectively formed at outer corners among corners of one end of the mesa region positioned on both sides of the groove.

The groove may include a main groove extending in a longitudinal direction of the mesa; and a plurality of sub grooves extending in a direction perpendicular to the main groove.

The plurality of sub grooves may include grooves having different lengths and widths.

The deep ultraviolet light emitting diode may have a symmetrical structure with respect to a straight line passing through the center and parallel to the sub-groove.

The deep ultraviolet light emitting diode may have an asymmetric structure with respect to a straight line passing through the center and parallel to the main groove.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

1A is a schematic plan view for explaining an ultraviolet light emitting diode according to an embodiment of the present invention, and FIG. 1B is a schematic cross-sectional view taken along the cut-out line A-A' of FIG. 1 .

1A and 1B, the ultraviolet light emitting diode according to this embodiment includes a substrate 21, an n-type semiconductor layer 23, an active layer 25, a p-type semiconductor layer 27, and an n-ohmic contact layer ( 31), p ohmic contact layer 33, lower insulating layer 35, n pad metal layer 37a, p pad metal layer 37b, upper insulating layer 39, n bump 41a, and p bump 41b ) may be included.

The substrate 21 is not particularly limited as long as it is a substrate capable of growing a nitride-based semiconductor, and may include, for example, a heterogeneous substrate such as a sapphire substrate, a silicon substrate, a silicon carbide substrate, or a spinel substrate. It may include a homogeneous substrate such as a gallium substrate, an aluminum nitride substrate, or the like.

The n-type semiconductor layer 23 is positioned on the substrate 21 . The n-type semiconductor layer 23 may include, for example, an AlN buffer layer (about 3.79 μm) and an n-type AlGaN layer. The n-type AlGaN layer may include a lower n-type AlGaN layer (about 2.15 μm) with an Al molar ratio of 0.8 or more, an intermediate AlGaN layer (1.7 nm) with an Al molar ratio of 0.7 to 0.8, and an upper n-type AlGaN layer with a thickness of about 66.5 nm. have. The n-type semiconductor layer 23 is formed of a nitride-based semiconductor having a bandgap higher than that of the active layer so that light generated in the active layer can pass therethrough. When the gallium nitride-based semiconductor layer is grown on the sapphire substrate 21 , the n-type semiconductor layer 23 may generally include a plurality of layers to improve crystal quality.

The mesa M is disposed on a partial region of the n-type semiconductor layer 23 . The mesa M includes an active layer 25 and a p-type semiconductor layer 27 . In general, the mesa ( M) is formed.

The active layer 25 may have a single quantum well structure or a multi-quantum well structure including a well layer and a barrier layer. The well layer may be formed of AlGaN or AlInGaN, and the barrier layer may be formed of AlGaN or AlInGaN having a wider bandgap than the well layer. For example, each well layer may be formed of AlGaN having an Al molar ratio of about 0.5 to a thickness of about 3.1 nm, and each barrier layer may be formed of AlGaN having an Al molar ratio of 0.7 or more and a thickness of about 9 nm or more. In particular, the first barrier layer may be formed to be thicker than the other barrier layers with a thickness of 12 nm or more. Meanwhile, AlGaN layers having an Al molar ratio of 0.7 to 0.8 in contact with the upper and lower portions of each well layer may be disposed to have a thickness of about 1 nm, respectively. However, the Al molar ratio of the AlGaN layer in contact with the last well layer may be 0.8 or more in consideration of the contact with the electron block layer.

Meanwhile, the p-type semiconductor layer 27 may include an electron block layer and a p-type GaN contact layer. The electron blocking layer prevents electrons from overflowing from the active layer to the p-type semiconductor layer, thereby improving the recombination rate of electrons and holes. The electron blocking layer may be formed of, for example, p-type AlGaN having an Al molar ratio of about 0.8, and may have a thickness of, for example, 55 nm. Meanwhile, the p-type GaN contact layer may be formed to a thickness of about 300 nm. The electron block layer may be omitted.

Meanwhile, the p-type GaN contact layer is used for the ohmic contact. The p-type GaN contact layer may absorb light generated in the active layer 25 . The prior art does not address ultraviolet absorption by the p-type GaN contact layer. The present invention reduces light absorption by the p-type GaN contact layer by reducing the thickness of the p-type GaN contact layer. The conventional p-type GaN contact layer is generally formed to have a thickness exceeding 300 nm, but in this embodiment, it is formed to a thickness of 200 nm or less, further 150 nm or less. Accordingly, light absorption by the p-type GaN contact layer may be reduced to improve light extraction efficiency.

The mesa M may have a rectangular shape elongated in one direction, and includes a plurality of via holes 30h exposing the n-type semiconductor layer 23 . The via holes 30h may each have an e concentric circle shape, and may be arranged at substantially equal intervals to each other in the mesa M region. As well shown in FIG. 2A , the via holes 30h may be arranged in a honeycomb shape, thus making it possible to make the spacing between the via holes 30h uniform.

The via holes 30h may have a mirror-symmetric structure with respect to a surface passing in the short axis direction of the mesa M. This mirror plane symmetrical structure helps to spread the current in the mesa (M) to improve the luminous efficiency.

Meanwhile, an n-ohmic contact layer 31 is disposed on the n-type semiconductor layer 23 exposed to the via holes 27a. The n-ohmic contact layer 31 may be formed by depositing a plurality of metal layers and then alloying the metal layers through a rapid thermal alloy (RTA) process. For example, after sequentially depositing Cr/Ti/Al/Ti/Au, the n-ohmic contact layer 31 may be alloyed through an RTA process. Accordingly, the n-ohmic contact layer 31 becomes an alloy layer containing Cr, Ti, Al, and Au.

The n-ohmic contact layer 31 is disposed in the via holes 27a. The n-ohmic contact layer 31 is spaced apart from the active layer 25 and the p-type semiconductor layer 27 in the via holes 30h. A conventional deep ultraviolet light emitting diode generally forms an n-ohmic contact layer surrounding the mesa M along the perimeter of the mesa M, but this embodiment does not dispose the n-ohmic contact layer around the mesa M. Accordingly, it is possible to prevent light emitted through the side surface of the mesa M from being blocked by the n-ohmic contact layer 31 or the like.

The p-ohmic contact layer 33 is disposed on the p-type semiconductor layer 27 to make ohmic contact with the p-type semiconductor layer 27 . The p-ohmic contact layer 33 may be formed through, for example, an RTA process after depositing Ni/Rh. The p-ohmic contact layer 33 is in ohmic contact with the p-type semiconductor layer 27 and covers most of the upper region of the mesa M, for example, 80% or more. Rh has a higher reflectivity to ultraviolet rays than Au, which is advantageous for improving light extraction efficiency. In this specification, since light absorption by the p-type GaN contact layer is reduced by reducing the thickness of the p-type GaN contact layer, the p-ohmic contact layer 33 is formed to reflect the light passing through the p-type semiconductor layer 27 . Good reflection performance is required.

The lower insulating layer 35 covers the mesa M and covers the p-ohmic contact layer 33 and the n-ohmic contact layer 31 . The lower insulating layer 35 also covers the exposed n-type semiconductor layer 23 around the mesa M and in the via holes 27a. Meanwhile, the lower insulating layer 35 has openings 35a for allowing electrical connection to the n-ohmic contact layer 31 and openings 35b for allowing electrical connection to the p-ohmic contact layer 33 . The opening 35b may be formed to surround all of the via holes 30h in a ring shape.

The lower insulating layer 35 _{may be formed of, for example, SiO 2} , but is not limited thereto, and may be formed of a distributed Bragg reflector.

Meanwhile, an n-pad metal layer 37a and a p-pad metal layer 37b are disposed on the lower insulating layer 35 . The n-pad metal layer 37a and the p-pad metal layer 37b may be formed together in the same process as the same metal layer and disposed on the same level, that is, on the lower insulating layer 35 . The n and p pad metal layers 37a and 37b may include, for example, an Al layer.

The n-pad metal layer 37a is electrically connected to the n-ohmic contact layers 31 through the openings 35a of the lower insulating layer 35 . The n-ohmic contact layers 31 are electrically connected to each other by the n-pad metal layer 37a. The n-pad metal layer 37a may be limitedly disposed in the mesa (M) region. The n-pad metal layer 37a may function as a reflective layer (second reflective layer) that reflects light emitted through the side surface of the mesa M within the via hole 30h, thereby improving the light efficiency of the light emitting diode. .

Meanwhile, the p pad metal layer 37b may be electrically connected to the p ohmic contact layer 33 through the opening 35b of the lower insulating layer 35 . The p-pad metal layer 37b may cover the opening 35b, and may surround the n-pad metal layer 37a in a ring shape. The p pad metal layer 37b may be defined in the upper region of the mesa M so that the mesa M does not have a side surface.

The upper insulating layer 39 covers the n-pad metal layer 37a and the p-pad metal layer 37b. However, the upper insulating layer 39 has openings 39a exposing the n-pad metal layer 37a and openings 39b exposing the p-pad metal layer 37b on the mesa M. The opening 39a may expose the n-pad metal layer 37a near one edge of the mesa M, and the opening 39b may expose the p-pad metal layer 37b near the opposite edge of the mesa M.

A plurality of openings 39a may be arranged, but the present invention is not limited thereto, and one opening 39a may be arranged. In addition, although it is shown that the opening 39b is continuously formed in a C shape in the drawing, a plurality of openings 39b may be disposed to be spaced apart from each other. The upper insulating layer 39 may be formed of, for example, silicon nitride or silicon oxide.

The n-bump 41a and the p-bump 41b are positioned on the upper insulating layer 39 . The n-bump 41a covers the openings 39a and connects to the exposed n-pad metal layer 37a through the openings 39a. The n-bump 41a is electrically connected to the n-type semiconductor layer 23 through the n-pad metal layer 37a and the n-ohmic contact layer 31 . The outer edges of the n-bump 41a and the p-bump 41b may be disposed on the mesa M so as not to cover the side surface of the mesa M.

The p-bump 41b covers the opening 39b and connects to the exposed p-pad metal layer 37b through the opening 39b. The p-bump 41b is electrically connected to the p-type semiconductor layer 27 through the p-pad metal layer 37b and the p-ohmic contact layer 33 .

The n-bump 41a and the p-bump 41b may be formed of, for example, Ti/Au/Cr/Au. As shown in FIG. 1 , the n-bumps 41a and the p-bumps 41b may be disposed to face each other, and may each occupy about 1/3 of the area of the mesa M. By making the area of the n-bump 41a and the p-bump 41b relatively wide, heat generated in the light emitting diode can be easily dissipated, thereby improving the performance of the light emitting diode.

Furthermore, the openings 39a and 39b are covered by the n-bumps 41a and p-bumps 41b, so that moisture or solder from the outside can be prevented from penetrating through the openings 39a and 39b. Reliability is improved.

Meanwhile, although not shown, an anti-reflection layer may be disposed on the light emitting surface side of the substrate 21 . The antireflection layer may be formed of a transparent insulating layer such as SiO2, for example, to have a thickness that is an integer multiple of 1/4 of the wavelength of ultraviolet rays. Alternatively, a bandpass filter in which layers having different refractive indices are repeatedly stacked may be used as the antireflection layer.

2a, 3a, 4a, 5a, 6a, 7a, and 8a are schematic plan views for explaining a method of manufacturing an ultraviolet light emitting diode according to an embodiment of the present invention, FIGS. 2b, 3b, 4B, 5B, 6B, 7B, and 8B are schematic cross-sectional views taken along line A-A' of FIGS. 2A, 3A, 4A, 5A, 6A, 7A, and 8A, respectively; admit.

2A and 2B , first, an n-type semiconductor layer 23 , an active layer 25 , and a p-type semiconductor layer 27 are grown on a substrate 21 .

Since the substrate 21 , the n-type semiconductor layer 23 , the active layer 25 , and the p-type semiconductor layer 27 are the same as described above, detailed descriptions thereof will be omitted to avoid duplication. However, the p-type semiconductor layer 27 may include a semiconductor layer having a smaller bandgap than the well layer of the active layer 25 , for example, a GaN layer. In particular, a p-type GaN layer can be used for an ohmic contact. The semiconductor layer having a smaller bandgap than the well layer is controlled to have a thickness of 200 nm or less, and furthermore, 150 nm or less.

Meanwhile, the mesa M is formed by patterning the p-type semiconductor layer 27 and the active layer 25 . The mesa M may have a generally elongated rectangular shape, but is not limited to a specific shape. As the mesa M is formed, the n-type semiconductor layer 23 may be exposed along the periphery of the mesa M. Also, a plurality of via holes 30h are formed in the mesa M region. The via holes 30h expose the n-type semiconductor layer 23 . The via holes 30h may be spaced apart from each other at substantially equal intervals, and may be arranged, for example, in a honeycomb structure. Furthermore, the via-holes 30h may be spaced apart from the edge of the mesa M by more than a distance between the via-holes 30h.

3A and 3B , n-ohmic contact layers 31 are formed on the bottom surfaces of the via holes 30h. The n-ohmic contact layers 31 may be formed by sequentially depositing Cr/Ti/Al/Ti/Au, for example, and then alloying with an RTA process. For example, the n-ohmic contact layer 31 may be alloyed by an RTA process at about 965° C. for 30 seconds.

4A and 4B , after the n-ohmic contact layer 31 is formed, the p-ohmic contact layer 33 is formed on the mesa M. The p-ohmic contact layer 33 is in ohmic contact with the p-type semiconductor layer 27 . In particular, the p-ohmic contact layer 33 may be in ohmic contact with the p-type GaN layer.

The p-ohmic contact layer 33 may include a reflective metal layer such as Au or Rh. For example, after depositing Ni/Au or Ni/Rh, it may be alloyed through an RTA process. Ni/Au may be heat treated, for example, at 590° C. for 80 seconds. In contrast, Ni/Rh may be heat treated at a relatively lower temperature for a long time, for example, may be heat treated at 500° C. for 5 minutes. Rh has a higher reflectance to UV rays than Au, so that light extraction efficiency can be further increased.

Furthermore, Ni/Rh is advantageous compared to Ni/Au because the interface between the p-type contact layer 27 and the p-ohmic contact layer 33 is formed smoothly to exhibit stable ohmic resistance characteristics. In addition, since the present invention reduces light absorption by the p-type contact layer 27 by reducing the thickness of the p-type GaN contact layer, the amount of light reflected by the p-ohmic contact layer 33 increases. Accordingly, light extraction efficiency can be improved by using Rh having a relatively high reflectance.

5A and 5B , a lower insulating layer 35 is formed on the mesa M. The lower insulating layer 35 covers the side and upper surfaces of the mesa M. The lower insulating layer 35 covers the n-ohmic contact layer 31 and the p-ohmic contact layer 33 . Meanwhile, the lower insulating layer 35 has openings 35a exposing the n-ohmic contact layers 31 and openings 35b exposing the p-ohmic contact layer 33 .

The opening 35b of the lower insulating layer 35 may be formed in a ring shape along the entire circumference of the via holes 30h. However, the present invention is not limited thereto, and a plurality of openings may be formed to expose the p-ohmic contact layer 33 . For example, a portion of the ring-shaped opening 35b close to the via hole 30h may be covered with the lower insulating layer 35 , and openings may be formed in portions relatively far from the via hole 30h.

6A and 6B , an n-pad metal layer 37a and a p-pad metal layer 37b are formed on the lower insulating layer 35 . The n-pad metal layer 37a is formed to cover the via-holes 30h, and may be electrically connected to the n-concave contact layers 31 in the via-holes 30h. The n-pad metal layer 37a may also cover inner walls of the via holes 30h.

The p-pad metal layer 37b may cover the opening 35b and may be electrically connected to the p-ohmic contact layer 33 exposed through the opening 35b. The p-pad metal layer 37b may be formed in a ring shape to surround the n-pad metal layer 37a. The p pad metal layer 37b may be formed to cover the side surface of the mesa M, or may be formed to be limited to the upper portion of the mesa M so as not to block light emitted to the side surface of the mesa M.

7A and 7B , an upper insulating layer 39 is formed on the n-pad metal layer 37a and the p-pad metal layer 37b. The upper insulating layer 39 may cover the n-pad metal layer 37a and the p-pad metal layer 37b and also cover the side surface of the mesa M.

Meanwhile, the upper insulating layer 39 has openings 39a and 39b exposing the n-pad metal layer 37a and the p-pad metal layer 37b. The openings 39a expose the n-pad metal layer 37a, and the opening 39b exposes the p-pad metal layer 37b. The openings 39a may be formed near one edge of the mesa M, and the opening 39b may be formed near the opposite edge of the mesa M to face the openings 39a.

8A and 8B , n bumps 41a and p bumps 41b are formed on the upper insulating layer 39 . The n-bump 41a is electrically connected to the n-pad metal layer 37a through the openings 39a, and the p-bump 41b is electrically connected to the p-pad metal layer 37b through the opening 39b.

The n-bumps 41a and p-bumps 41b may each partially cover the side surface of the mesa M, but may be formed to be limited to an upper region of the mesa M.

According to the present embodiment, by forming the via holes 30h in the mesa M region and forming the n-ohmic contact layers 31 , the current can be uniformly distributed over the entire region of the mesa M. In addition, the light extraction efficiency can be improved by reducing the thickness of the p-type GaN contact layer that absorbs the light generated by the active layer 25 and using Ni/Rh as the p-ohmic contact layer 33 .

9 is a diagram illustrating a light output distribution of an ultraviolet light emitting diode manufactured according to an embodiment of the present invention. Here, the closer to red, the stronger the ultraviolet radiation, and the closer to blue, the weaker the light. Here, the area of the light emitting diode was about 950 μm×600 μm, and a current of 100 mA was applied.

Referring to FIG. 9 , it can be seen that light is emitted over almost the entire area of the mesa M except for areas in which the via holes 30h are disposed. Since the current distribution is good, the luminous intensity of the light emitting diode can be further improved by increasing the current density.

10A and 10B are cross-sectional SEM photographs showing the interface after depositing Ni/Au and Ni/Rh on the p-type contact layer and heat treatment, respectively.

As shown in FIG. 10A , when Ni/Au was used, many voids were observed after the annealing process, and the thickness of the Ni/Au layer was non-uniform. In contrast, as shown in FIG. 10B , when Ni/Rh is used, the thickness of the ohmic contact layer is substantially uniform even after the annealing process, and voids are not observed.

In addition, as a result of comparing a light emitting diode using Ni/Rh as a p-ohmic contact layer and a light emitting diode using Ni/Au in a light emitting diode having the same structure, the light emitting diode using Ni/Rh has a relatively small forward voltage (Vf). and showed an improvement in light output of about 6%.

11A, 11B, and 11C are schematic plan views for explaining modifications of the via hole shape of the ultraviolet light emitting diode according to embodiments of the present invention.

Although the via hole 30h has been illustrated and described as having a circular shape in the previous embodiments, the shape of the via hole is not limited to a circular shape. As shown in FIG. 11A , the via hole 30h ′ may have a deformed cross shape by forming recesses 30hc in a circular shape. The depressions 30hc may be formed in four portions at equal intervals, but is not limited thereto. Via-holes 30h' may be disposed such that a convex portion of one via-hole 30h' faces between depressions of two adjacent via-holes 30h'. Furthermore, the three via holes 30h' may be disposed at vertex positions of an equilateral triangle.

Meanwhile, as shown in FIG. 11B , the via hole 30h″ located near the edge of the mesa M may have a shape that is deformed from a cross shape. That is, the via hole 30h″ may include a straight portion parallel to the edge of the mesa M. The via hole 30h″ may be an area corresponding to 1/2 of the via hole 30h′ illustrated in FIG. 11A . Accordingly, the via hole 30h″ may have only two depressions.

Meanwhile, as shown in FIG. 11C , the via hole 30h'” may have a polygonal shape. The via hole 30h′″ may include a planar sidewall, and adjacent via holes 30h′″ may face the planar sidewall as indicated by a dotted line.

Although via holes of various shapes are illustrated and described in this embodiment, the present invention is not limited to the shapes of these via holes 30h, 30h', 30h”, 30h'”, and may have other various shapes. The shape and size of the via hole 30h affect the size of the ohmic contact area or the size of the light emitting area. Accordingly, the shape of the via hole 30h may be variously modified in order to adjust the size of the light emission intensity.

12A is a schematic plan view for explaining an ultraviolet light emitting diode according to an embodiment of the present invention, and FIG. 12B is a schematic cross-sectional view taken along the cut line B-B' of FIG. 12A.

12A and 12B, the ultraviolet light emitting diode according to the present embodiment includes a substrate 121, an n-type semiconductor layer 123, an active layer 125, a p-type semiconductor layer 127, and an n-ohmic contact layer ( 131a and 131b), p ohmic contact layer 133, n capping layer 134a, p capping layer 134b, lower insulating layer 135, n pad metal layer 137a, p pad metal layer 137b, upper insulation layer 139 , n bumps 141a , and p bumps 141b .

Since the substrate 121 is similar to the substrate 21 described with reference to FIGS. 1A and 1B , a detailed description thereof will be omitted to avoid redundancy. The n-type semiconductor layer 123 is positioned on the substrate 121 . The n-type semiconductor layer 123 is substantially similar to the n-type semiconductor layer 23 described with reference to FIGS. 1A and 1B . However, the edges of the n-type semiconductor layer 123 may be located inside a region surrounded by the edges of the substrate 121 , and thus the top surface of the substrate 121 is exposed along the edges of the n-type semiconductor layer 123 . can

The mesa M is disposed on a partial region of the n-type semiconductor layer 123 . The mesa M includes an active layer 125 and a p-type semiconductor layer 127 . In general, the n-type semiconductor layer 123, the active layer 125, and the p-type semiconductor layer 127 are sequentially grown, and then the p-type semiconductor layer 127 and the active layer 125 are patterned through a mesa etching process to form a mesa ( M) is formed.

Since the stacked structure of the active layer 125 and the p-type semiconductor layer 127 is similar to that described with reference to FIGS. 1A and 1B , a detailed description thereof will be omitted to avoid redundancy.

The mesa M may have a rectangular shape elongated in one direction, and includes a groove 130g exposing the n-type semiconductor layer 123 . The groove 130g may extend along the longitudinal direction of the mesa M. As shown in FIG. 12A , the groove 130g may extend from one edge of the mesa M toward the other edge along the lengthwise direction of the mesa M. Mesa regions are disposed on both sides of the groove 130g by the groove 130g. The length of the groove 130g exceeds 1/2 of the length of the mesa M. In other words, the length of the groove 130g is greater than the distance between the inner end of the groove 130g and the other edge of the mesa M. Furthermore, the distance between the inner end of the groove 130g and the other edge of the mesa M may be smaller than the width of the mesa region disposed on both sides of the groove 130g.

The groove 130g may have a linear shape, and the mesa M may have a symmetrical structure with respect to a straight line passing through the center of the light emitting diode and parallel to the groove 130g.

Meanwhile, the corners of the mesa M may have a curved shape. The edge of the mesa M may include a straight region and curved regions located on both sides thereof. By forming the corner portion of the mesa (M) to be curved, it is possible to prevent light from being condensed from the corner portion and from being lost due to light absorption.

Meanwhile, the n-ohmic contact layer 131a is disposed on the n-type semiconductor layer 123 exposed by the groove 130g. The n-ohmic contact layer 131b is disposed on the n-type semiconductor layer 123 exposed along the periphery of the mesa M. The n-ohmic contact layer 131a may be connected to the n-ohmic contact layer 131b, but the present invention is not limited thereto. The n-ohmic contact layers 131a and 131b may be spaced apart from the mesa M to surround the mesa M.

Materials and methods of forming the n-ohmic contact layers 131a and 131b are similar to those of the n-ohmic contact layers 31 described with reference to FIGS. 1A and 1 , and thus detailed descriptions thereof will be omitted to avoid redundancy.

The p-ohmic contact layer 133 is disposed on the p-type semiconductor layer 127 to make an ohmic contact with the p-type semiconductor layer 127 . The p-ohmic contact layer 133 may be formed using, for example, Ni/Rh or Ni/Au. The p-ohmic contact layer 133 is in ohmic contact with the p-type semiconductor layer 127 and covers most of the upper region of the mesa M, for example, 80% or more.

The n-capping layer 134a may cover top surfaces and side surfaces of the n-ohmic contact layers 131a and 131b. The p capping layer 134b may cover the top and side surfaces of the p ohmic contact layer 133 . The n capping layer 134a and the p capping layer 134b prevent the n-ohmic contact layers 131a and 131b and the p-ohmic contact layer 133 from being damaged by etching or oxidation, respectively. The n capping layer 134a and the p capping layer 134b may be formed of the same metal in the same process. For example, the n capping layer 134a and the p capping layer 134b may be formed of Ti/Au/Ti.

The lower insulating layer 135 covers the mesa M and covers the n capping layer 134a and the p capping layer 134b. The lower insulating layer 135 also covers the exposed n-type semiconductor layer 123 around the mesa M and in the groove 130g. Furthermore, the lower insulating layer 135 may cover a portion of the substrate 121 exposed around the n-type semiconductor layer 123 . On the other hand, the lower insulating layer 135 has openings 135a for allowing electrical connection to the n-ohmic contact layers 131a and 131b and openings 135b for allowing electrical connection to the p-ohmic contact layer 133 . have The opening 135a may have a shape similar to that of the n-ohmic contact layers 131a and 131b or the n-capping layer 134a. That is, the opening 135a surrounds the mesa M and also extends into the groove 130g. The width of the opening 135a may be smaller than the width of the n-type capping layer 134a, and thus the n-type semiconductor layer 123 may not be exposed through the opening 135a. Meanwhile, the opening 135b is located in the upper region of the mesa M and exposes the p capping layer 134b. A plurality of openings 135b may be disposed on the p capping layer 134b. In particular, the openings may be symmetrically disposed on both sides of the groove 130g.

The lower insulating layer 135 _{may be formed of, for example, SiO 2} , but is not limited thereto, and may be formed of a distributed Bragg reflector. In particular, the lower insulating layer 135 may be formed to constitute an omni-directional reflector (ODR). For example, the lower insulating layer 135 may be formed _{of about 10,000 Å of SiO 2 .}

Meanwhile, an n-pad metal layer 137a and a p-pad metal layer 137b are disposed on the lower insulating layer 135 . The n-pad metal layer 137a and the p-pad metal layer 137b may be formed together in the same process as the same metal layer and disposed on the same level, that is, on the lower insulating layer 135 . The n and p pad metal layers 137a and 137b may include, for example, an Al layer.

The n-pad metal layer 137a is electrically connected to the n-ohmic contact layers 131a and 131b through the opening 135a of the lower insulating layer 135 . The n-pad metal layer 137a may directly contact the n-capping layer 134a through the opening 135a of the lower insulating layer 135 . The n-pad metal layer 137a covers most of the area of the mesa M, and may also cover the area around the mesa M. The n-pad metal layer 137a may form an ODR together with the lower insulating layer 135 .

Meanwhile, the p pad metal layer 137b may be electrically connected to the p ohmic contact layer 133 through the opening 135b of the lower insulating layer 135 . The p pad metal layers 137b may cover each of the openings 135b. Each of the p-pad metal layers 137b may be surrounded by the n-pad metal layer 137a. The p pad metal layers 37b may be defined in the upper region of the mesa M. In this embodiment, all sides of the mesa M are covered with the n-pad metal layer 137a. Accordingly, it is possible to prevent light loss from occurring in the mesa (M) side.

The upper insulating layer 139 covers the n-pad metal layer 137a and the p-pad metal layer 137b. However, the upper insulating layer 139 may have openings 139a exposing the n-pad metal layer 137a and openings 139b exposing the p-pad metal layer 137b. The opening 139a exposes the n-pad metal layer 137a near one edge of the mesa M, and the openings 139b expose the p-pad metal layer 137b near the opposite edge of the mesa M. . The openings 139a and 139b may be symmetrically disposed with respect to a line passing through the groove 130g, but the present invention is not limited thereto.

The upper insulating layer 139 may be formed of, for example, silicon nitride or silicon oxide.

The n-bump 141a and the p-bump 141b are positioned on the upper insulating layer 139 . The n-bump 141a covers the openings 139a and connects to the n-pad metal layer 137a exposed through the openings 139a. The n-bump 141a is electrically connected to the n-type semiconductor layer 123 through the n-pad metal layer 137a and the n-ohmic contact layers 131a and 131b. The n-bump 141a and the p-bump 141b may partially cover the side surface of the mesa M.

The p-bump 141b covers the openings 139b and connects to the exposed p-pad metal layer 137b through the openings 139b. The p-bump 141b is electrically connected to the p-type semiconductor layer 127 through the p-pad metal layer 137b and the p-ohmic contact layer 133 .

The n-bumps 141a and p-bumps 141b may include Ti/Au, and may be formed of, for example, Ti/Au/Cr/Au, or Ti/Ni/Ti/Ni/TiNi/Ti/Au. can 12A , the n-bump 141a and the p-bump 141b may be disposed to face each other, and may each occupy about 1/3 of the area of the mesa M. By making the areas of the n-bump 141a and the p-bump 141b relatively wide, heat generated in the light emitting diode can be easily dissipated, thereby improving the performance of the light emitting diode.

Furthermore, the openings 139a and 139b are covered by the n-bump 141a and the p-bump 141b, so that moisture or solder from the outside can be prevented from penetrating through the openings 139a and 139b. Reliability is improved.

Meanwhile, although not shown, an anti-reflection layer may be disposed on the light emitting surface of the substrate 121 . The antireflection layer may be formed of a transparent insulating layer such as SiO2, for example, to have a thickness that is an integer multiple of 1/4 of the wavelength of ultraviolet rays. Alternatively, a bandpass filter in which layers having different refractive indices are repeatedly stacked may be used as the antireflection layer.

13A, 14A, 15A, 16A, 17A, 18A, 19A, and 20A are schematic plan views for explaining a method of manufacturing an ultraviolet light emitting diode according to an embodiment of the present invention, FIG. 13B, 14B, 15B, 16B, 17B, 18B, 19B, and 20B are cut-off line B in FIGS. 13A, 14A, 15A, 16A, 17A, 18A, 19A, and 20A, respectively. Schematic cross-sectional views taken along -B'.

13A and 13B , first, an n-type semiconductor layer 123 , an active layer 125 , and a p-type semiconductor layer 127 are grown on a substrate 121 .

Since the substrate 121 , the n-type semiconductor layer 123 , the active layer 125 , and the p-type semiconductor layer 127 are the same as described above, detailed descriptions thereof will be omitted to avoid overlapping.

Meanwhile, the mesa M is formed by patterning the p-type semiconductor layer 127 and the active layer 125 . The mesa M may have a generally elongated rectangular shape, but is not limited to a specific shape. As the mesa M is formed, the n-type semiconductor layer 123 may be exposed along the periphery of the mesa M. Also, a groove 130g is formed in the mesa M region. The groove 130g may extend from one edge to the other edge along the longitudinal direction of the mesa M. The inner end of the groove 130g may be located near the other edge. The mesa regions disposed on both sides of the groove 130g may be identical to each other, and the width of each mesa region may be greater than or equal to a distance between the inner end of the groove 130g and the other edge of the mesa M.

14A and 14B , n-ohmic contact layers 131a and 131b are formed on the n-type semiconductor layer 123 . The n-ohmic contact layers 131a and 131b may be formed by, for example, sequentially depositing Cr/Ti/Al/Ti/Au and then alloying them through an RTA process. For example, the n-ohmic contact layer 31 may be alloyed by an RTA process at about 965° C. for 30 seconds. The n-ohmic contact layer 131a is formed on the n-type semiconductor layer 123 exposed by the groove 130g, and the n-ohmic contact layer 131b is the n-type semiconductor layer 123 exposed around the mesa M. ) is formed on The n-ohmic contact layer 131a may extend from the n-ohmic contact layer 131b. By continuously forming the n-ohmic contact layer 131a and the n-ohmic contact layer 131b, current distribution may be aided. However, the present invention is not limited thereto, and the n-ohmic contact layer 131a may be spaced apart from the n-ohmic contact layer 131b.

15A and 15B , after the n-ohmic contact layers 131a and 131b are formed, the p-ohmic contact layer 133 is formed on the mesa M. The p-ohmic contact layer 133 is in ohmic contact with the p-type semiconductor layer 127 . In particular, the p-ohmic contact layer 133 may be in ohmic contact with the p-type GaN layer.

The p-ohmic contact layer 133 may include a reflective metal layer such as Au or Rh. For example, after depositing Ni/Au or Ni/Rh, it may be alloyed through an RTA process.

16A and 16B , an isolation process for separating the n-type semiconductor layer 123 is performed. That is, the n-type semiconductor layer 123 between the adjacent light emitting diode regions is removed to expose the upper surface of the substrate 121 . By adding an isolation process, individualization of the light emitting diodes can be aided.

17A and 17B , an n capping layer 134a and a p capping layer 134b are formed. The n capping layer 134a covers the top and side surfaces of the n-type ohmic contact layers 131a and 131b , and the p capping layer 134b covers the top and side surfaces of the p-type ohmic contact layer 133 . The n capping layer 134a and the p capping layer 134b may be formed of, for example, Ti/Au/Ti.

18A and 18B , a lower insulating layer 135 covering the mesa M is formed. The lower insulating layer 135 covers the side and top surfaces of the mesa M. The lower insulating layer 135 also covers the n capping layer 134a and the p capping layer 134b. The lower insulating layer 235 may cover the side surface of the n-type semiconductor layer 223 , and may partially cover the substrate 221 exposed around the n-type semiconductor layer 223 . Meanwhile, the lower insulating layer 135 has openings 135a and 135b exposing the n capping layer 134a and the p capping layer 134b.

The opening 135a of the lower insulating layer 135 exposes the n capping layer 134a, and the opening 135b exposes the p capping layer 134b. A plurality of openings 135b may be formed on the p capping layer 134b. As illustrated, the openings 135b may be symmetrically disposed on both sides of the groove 130g.

19A and 19B , an n-pad metal layer 137a and a p-pad metal layer 137b are formed on the lower insulating layer 135 . The n pad metal layer 137a may be electrically connected to the n capping layer 134a through the opening 135a, and the p pad metal layer 137b may be electrically connected to the p capping layer 134b through the opening 135b. have. As illustrated, the n-pad metal layer 137a may surround the p-pad metal layers 137b.

The n-pad metal layer 137a may cover the opening 135a, and the p-pad metal layer 137b may cover the opening 135b. In addition, the n-pad metal layer 137a may continuously cover the side surface of the mesa M, and thus, light reflectance may be improved on the side surface of the mesa M.

20A and 20B , an upper insulating layer 139 is formed on the n-pad metal layer 137a and the p-pad metal layer 137b. The upper insulating layer 139 may cover the n-pad metal layer 137a and the p-pad metal layer 137b and also cover the edge of the n-type semiconductor layer 123 . The upper insulating layer 139 may also cover a portion of the upper surface of the substrate 121 .

The upper insulating layer 139 has openings 139a and 139b exposing the n-pad metal layer 137a and the p-pad metal layer 137b. The openings 139a expose the n-pad metal layer 137a, and the openings 139b expose the p-pad metal layer 137b. The openings 139a may be formed near one edge of the mesa M, and the openings 139b may be formed near the opposite edge of the mesa M to face the openings 139a.

Then, as shown in FIGS. 12A and 12B , an n-bump 141a and a p-bump 141b are formed on the upper insulating layer 139 . The n-bump 141a is electrically connected to the n-pad metal layer 137a through the openings 139a, and the p-bump 141b is electrically connected to the p-pad metal layer 137b through the opening 139b.

The n-bumps 141a and p-bumps 141b may each partially cover the side surface of the mesa M, but may be formed to be limited to an upper region of the mesa M.

According to the present embodiment, by forming the groove 130g in the mesa (M) region and forming the n-ohmic contact layers 131a and 131b around the mesa M and in the groove 130g in the entire region of the mesa M, The current can be evenly distributed.

21 is a schematic plan view for explaining a modified example of a mesa of an ultraviolet light emitting diode according to an embodiment of the present invention.

Referring to FIG. 21 , the groove 130g extends from one edge of the mesa M toward the other edge in the longitudinal direction. The distance between the inner end of the groove 130g and the other edge of the mesa M, that is, the difference W1 between the total length of the mesa M and the length of the groove 130g, is located on both sides of the groove 130g. It may be less than or equal to the width W2 of each of the mesa regions. In addition, the length of the groove 130g is greater than W1, and thus exceeds 1/2 of the length of the mesa M. Meanwhile, the area A1 of the mesa M between the groove 130g and the other edge of the mesa M may be smaller than the area A2 of each mesa area positioned on both sides of the mesa M. That is, the total area 2A2 of the mesa regions located on both sides of the mesa M may exceed 1/2 of the total area of the mesa.

22 is a schematic plan view for explaining another modified example of a mesa of an ultraviolet light emitting diode according to an embodiment of the present invention.

In the previous embodiments, the corners of the mesa M have been illustrated and described as having a curved shape, but in this modified example, depressions may be formed in some of the corners of the mesa M, respectively. The depressions improve the p-current dissipation near the edges of the mesa M.

23A is a schematic plan view for explaining an ultraviolet light emitting diode according to an embodiment of the present invention, and FIG. 23B is a schematic cross-sectional view taken along the cut line C-C' of FIG. 23A.

23A and 23B , the ultraviolet light emitting diode according to the present embodiment includes a substrate 221 , an n-type semiconductor layer 223 , an active layer 225 , a p-type semiconductor layer 227 , and an n-ohmic contact layer 231a. , 231b), p ohmic contact layer 233, n capping layer 234a, p capping layer 234b, lower insulating layer 235, n pad metal layer 237a, p pad metal layer 237b, upper insulating layer 239 , an n-bump 241a, and a p-bump 241b may be included.

Since the UV light emitting diode according to the present embodiment is substantially similar to the UV light emitting diode described with reference to FIGS. 12A and 12B , detailed descriptions of the same components will be omitted and differences will be described in detail to avoid duplication.

In this embodiment, the mesa M includes a main groove 230g and sub grooves 230s. The main groove 230g extends from one edge to the other edge along the longitudinal direction of the mesa M. Both ends of the mesa M may be provided by the main groove 230g. However, the present disclosure is not limited thereto, and one end of the main groove 230g may be located inside the mesa M.

Meanwhile, the sub grooves 230s extend from the main groove 230g in a direction perpendicular to the main groove 230g. The sub grooves 230s may extend from the main groove 230g to both sides. The sub grooves 230s may be symmetrically disposed with respect to the main groove 230g.

Meanwhile, the n-ohmic contact layer 231a is disposed on the n-type semiconductor layer 223 exposed by the main groove 230g and the sub grooves 230s. The n-ohmic contact layer 231b is disposed on the n-type semiconductor layer 223 exposed along the circumference of the mesa M. The n-ohmic contact layer 231a may be connected to the n-ohmic contact layer 231b, but the present invention is not limited thereto. The n-ohmic contact layers 231a and 231b may be spaced apart from the mesa M to surround the mesa M.

The p-ohmic contact layer 233 is disposed on the p-type semiconductor layer 227 to make an ohmic contact with the p-type semiconductor layer 227 . The p-ohmic contact layer 233 may be disposed in the same shape on the mesa regions that are both ends by the main groove 230g.

The n-capping layer 234a may cover top surfaces and side surfaces of the n-ohmic contact layers 231a and 231b. The p capping layer 234b may cover the top and side surfaces of the p ohmic contact layer 233 .

The lower insulating layer 235 covers the mesa M, and covers the n capping layer 234a and the p capping layer 234b. The lower insulating layer 235 also covers the exposed n-type semiconductor layer 223 around the mesa M and in the grooves 230g and 230s. Furthermore, the lower insulating layer 235 may cover a portion of the substrate 221 exposed around the n-type semiconductor layer 223 . Meanwhile, the lower insulating layer 235 includes openings 235a for allowing electrical connection to the n-ohmic contact layers 231a and 231b and openings 235b for allowing electrical connection to the p-ohmic contact layer 233 . have The opening 235a may have a shape similar to that of the n-ohmic contact layers 231a and 231b or the n-capping layer 234a. That is, the opening 235a surrounds the mesa M and also extends into the grooves 230g and 230s. The width of the opening 235a may be smaller than the width of the n-type capping layer 234a, and thus the n-type semiconductor layer 223 may not be exposed through the opening 235a. Meanwhile, the opening 235b is located in the upper region of the mesa M and exposes the p capping layer 234b. A plurality of openings 235b may be disposed on the p capping layer 234b. In particular, the openings 235b may be symmetrically disposed on both sides of the groove 230g.

Meanwhile, an n-pad metal layer 237a and a p-pad metal layer 237b are disposed on the lower insulating layer 135 . The n-pad metal layer 237a and the p-pad metal layer 237b may be formed together in the same process as the same metal layer and disposed on the same level, that is, on the lower insulating layer 235 .

The n-pad metal layer 237a is electrically connected to the n-ohmic contact layers 231a and 231b through the opening 235a of the lower insulating layer 235 . The n-pad metal layer 237a may directly contact the n-capping layer 234a through the opening 235a of the lower insulating layer 235 . The n-pad metal layer 237a may cover most of the area of the mesa M, and may also cover an area around the mesa M.

Meanwhile, the p pad metal layer 237b may be electrically connected to the p ohmic contact layer 233 through the opening 235b of the lower insulating layer 235 . The p pad metal layers 237b may cover each of the openings 235b. Each of the p-pad metal layers 237b may be surrounded by an n-pad metal layer 237a. The p pad metal layers 237b may be defined in the upper region of the mesa M. The shape of the p pad metal layers 237b may be different from that of the p pad metal layer 137b of FIG. 12A due to the sub grooves 230s. That is, the p pad metal layer 237b may have a shape in which a portion is recessed in a rectangular shape to form the sub-groove 230s. In this embodiment, all sides of the mesa M are covered with the n-pad metal layer 237a. Accordingly, it is possible to prevent light loss from occurring in the mesa (M) side.

The upper insulating layer 239 covers the n-pad metal layer 237a and the p-pad metal layer 237b, and openings 139a exposing the n-pad metal layer 137a and openings exposing the p-pad metal layer 137b (139b) may have. The opening 239a may expose the n-pad metal layer 237a near one edge of the mesa M, and the openings 239b may expose the p-pad metal layer 237b near the opposite edge of the mesa M. . The openings 239a and 239b may be disposed symmetrically with respect to a line passing through the groove 230g, but the present invention is not limited thereto.

The n-bump 241a and the p-bump 241b are positioned on the upper insulating layer 239 . The n-bump 241a covers the openings 239a and connects to the n-pad metal layer 237a exposed through the openings 239a. The p-bump 241b covers the openings 239b and connects to the exposed p-pad metal layer 237b through the openings 239b.

24A, 25A, 26A, 27A, 28A, 29A, 30A, and 31A are schematic plan views for explaining a method for manufacturing an ultraviolet light emitting diode according to an embodiment of the present invention, FIG. 24B, 25B, 26B, 27B, 28B, 29B, 30B, and 31B are cut-away line C in FIGS. 24A, 25A, 26A, 27A, 28A, 29A, 30A, and 31A, respectively. Schematic cross-sectional views taken along -C'. Since the manufacturing method of the ultraviolet light emitting diode according to the present embodiment is substantially similar to that described above with reference to FIGS. 13A to 20B , it will be briefly described.

24A and 24B , first, an n-type semiconductor layer 223 , an active layer 225 , and a p-type semiconductor layer 227 are grown on a substrate 221 .

Meanwhile, the mesa M is formed by patterning the p-type semiconductor layer 227 and the active layer 225 . The mesa M may have a generally elongated rectangular shape, but is not limited to a specific shape. As the mesa M is formed, the n-type semiconductor layer 223 may be exposed along the periphery of the mesa M. In addition, a main groove 230g and sub grooves 230s are formed in the mesa M region. The main groove 230g may extend from one edge to the other edge along the longitudinal direction of the mesa M. The mesa regions disposed on both sides of the main groove 230g may be identical to each other and may be symmetrical with respect to the main groove 230g.

25A and 25B , n-ohmic contact layers 131a and 131b are formed on the n-type semiconductor layer 123 . The n-ohmic contact layer 231a is formed on the n-type semiconductor layer 223 exposed by the main groove 230g and the sub-grooves 230s, and the n-ohmic contact layer 131b is formed around the mesa M. It is formed on the exposed n-type semiconductor layer 223 . The n-ohmic contact layer 231a may extend from the n-ohmic contact layer 231b. By continuously forming the n-ohmic contact layer 231a and the n-ohmic contact layer 231b, current distribution may be aided. However, the present invention is not limited thereto, and the n-ohmic contact layer 131a may be spaced apart from the n-ohmic contact layer 131b.

26A and 26B , after the n-ohmic contact layers 231a and 231b are formed, the p-ohmic contact layer 233 is formed on the mesa M. The p-ohmic contact layer 233 is in ohmic contact with the p-type semiconductor layer 227 .

27A and 27B , an isolation process for separating the n-type semiconductor layer 223 is performed. That is, the n-type semiconductor layer 223 between the adjacent light emitting diode regions is removed to expose the upper surface of the substrate 221 . By adding an isolation process, individualization of the light emitting diodes can be aided.

28A and 28B , an n capping layer 234a and a p capping layer 234b are formed. The n capping layer 134a covers the top and side surfaces of the n-type ohmic contact layers 131a and 131b , and the p capping layer 134b covers the top and side surfaces of the p-type ohmic contact layer 133 .

29A and 29B , a lower insulating layer 235 covering the mesa M is formed. The lower insulating layer 135 covers the side and top surfaces of the mesa M. The lower insulating layer 235 also covers the n capping layer 234a and the p capping layer 234b. The lower insulating layer 235 may cover the side surface of the n-type semiconductor layer 223 , and may partially cover the substrate 221 exposed around the n-type semiconductor layer 223 . Meanwhile, the lower insulating layer 235 has openings 235a and 235b exposing the n capping layer 234a and the p capping layer 234b.

The opening 235a of the lower insulating layer 235 exposes the n capping layer 234a, and the opening 235b exposes the p capping layer 234b. The opening 235a may be located in the main groove 230g and the sub grooves 230s. Also, a plurality of openings 235b may be formed on the p capping layer 234b. As illustrated, the openings 235b may be symmetrically disposed on both sides of the groove 130g.

30A and 30B , an n-pad metal layer 237a and a p-pad metal layer 237b are formed on the lower insulating layer 235 . The n pad metal layer 237a may be electrically connected to the n capping layer 234a through the opening 235a, and the p pad metal layer 237b may be electrically connected to the p capping layer 234b through the opening 235b. have. As illustrated, the n-pad metal layer 237a may surround the p-pad metal layers 237b.

The n-pad metal layer 237a may cover the opening 235a, and the p-pad metal layer 237b may cover the opening 235b. In addition, the n-pad metal layer 237a may continuously cover the side surface of the mesa M, and accordingly, light reflectance may be improved on the side surface of the mesa M.

31A and 31B , an upper insulating layer 239 is formed on the n-pad metal layer 237a and the p-pad metal layer 237b. The upper insulating layer 239 may cover the n-pad metal layer 237a and the p-pad metal layer 237b and also cover the edge of the n-type semiconductor layer 223 . The upper insulating layer 239 may also cover a portion of the upper surface of the substrate 221 .

The upper insulating layer 239 has openings 239a and 239b exposing the n-pad metal layer 237a and the p-pad metal layer 237b. The openings 239a expose the n-pad metal layer 237a, and the openings 239b expose the p-pad metal layer 237b. The openings 239a may be formed near one edge of the mesa M, and the openings 239b may be formed near the opposite edge of the mesa M to face the openings 239a. The openings 239a and 239b of the upper insulating layer 239 may have a rectangular shape to accommodate the sub-grooves 230s. That is, the openings 239a and 239b may have a partially recessed shape in a rectangular shape, as shown in FIG. 31A .

Then, as shown in FIGS. 23A and 23B , n-bumps 241a and p-bumps 241b are formed on the upper insulating layer 139 . The n-bump 241a is electrically connected to the n-pad metal layer 237a through the openings 239a, and the p-bump 241b is electrically connected to the p-pad metal layer 237b through the openings 239b.

The n-bumps 241a and p-bumps 241b may each partially cover the side surface of the mesa M, but may be formed to be limited to an upper region of the mesa M.

According to this embodiment, the main groove 230g and the sub grooves 230s are formed in the mesa M region, and the n-ohmic contact layer is formed around the mesa M and in the main groove 230g and the sub grooves 230s. By forming the 231a and 231b, the current can be uniformly distributed over the entire area of the mesa M.

32 is a schematic plan view for explaining a modified example of a mesa of an ultraviolet light emitting diode according to an embodiment of the present invention.

In the mesa M of the ultraviolet light emitting diode described above with reference to FIGS. 23A and 23B , the sub grooves 230s are symmetrically disposed with respect to the main groove 230g. The length and width of the sub-grooves 230s are substantially equal to each other, and accordingly, an n-ohmic contact layer 231a having the same size is formed in each sub-groove 230s. However, the present invention is not limited thereto, and the sub grooves may be variously modified. For example, as shown in FIG. 32 , mesa regions M1 and M2 that are sub-symmetric with respect to a straight line X-X passing through the center of the light emitting diode and parallel to the main groove 330g may be formed. That is, the sub grooves 330s, 330s2, and 330s3 are asymmetrically disposed with respect to the straight line X-X. Meanwhile, the sub grooves 330s1 , 330s2 , and 330s3 may be symmetrically disposed with respect to a straight line Y-Y passing through the center of the light emitting diode and perpendicular to the main groove 330g.

The sub grooves 330s1 , 330s2 , and 330s3 may be disposed on both sides of the main groove 330s , but the sub grooves 330s , 330s2 , and 330s3 may have different widths and/or lengths. For example, the sub grooves 330s2 having relatively small widths and lengths may be disposed between the sub grooves 330s1 having relatively large widths and lengths. Also, sub grooves 330s1 and 330s3 having different widths and/or lengths may be disposed to face each other with the main groove 330g interposed therebetween. By increasing the width of the sub-groove 330s1, light reflection generated from the sidewall of the mesa may be increased.

The present invention is not limited to the main groove 330g and the sub grooves 330s1, 330s2, and 330s3 described herein, and may be variously modified.

Above, various modifications and changes are possible to the above embodiments without departing from the technical spirit of the present invention, and the present invention includes all of the technical spirit of the present invention.

Claims (30)

Board;
an n-type semiconductor layer positioned on the substrate;
a mesa disposed on the n-type semiconductor layer, including an active layer and a p-type semiconductor layer, and having a plurality of via holes exposing the n-type semiconductor layer;
n-ohmic contact layers contacting the n-type semiconductor layer in the via holes;
a p-ohmic contact layer in contact with the p-type semiconductor layer;
an n pad metal layer electrically connected to the n ohmic contact layers;
a p pad metal layer electrically connected to the p ohmic contact layer;
an n bump electrically connected to the n pad metal layer; and
a p-bump electrically connected to the p-pad metal layer;
The p-pad metal layer is a deep ultraviolet light emitting diode formed to surround the n-pad metal layer. The method according to claim 1,
The via holes are a deep ultraviolet light emitting diode arranged in a honeycomb shape. The method according to claim 1,
The via-holes are spaced apart from the edge of the mesa by more than a distance between the via-holes. 4. The method according to claim 3,
The n-pad metal layer is a deep ultraviolet light emitting diode covering the via holes. 5. The method according to claim 4,
The p pad metal layer is a deep ultraviolet light emitting diode positioned between the via holes and the edge of the mesa. 6. The method of claim 5,
The n-bump and the p-bump are located in an upper region of the mesa. 5. The method according to claim 4,
Further comprising a lower insulating layer covering the p ohmic contact layer and the n ohmic contact layer,
the lower insulating layer has openings exposing the p ohmic contact layer and the n ohmic contact layer;
The n-pad metal layer and the p-pad metal layer are respectively electrically connected to the n-ohmic contact layer and the p-ohmic contact layer through the openings of the lower insulating layer. 8. The method of claim 7,
an upper insulating layer covering the n and p pad metal layers, wherein the upper insulating layer has openings exposing the n pad metal layer and the p pad metal layer;
The n-bump and the p-bump are disposed on the upper insulating layer, and are electrically connected to the n-pad metal layer and the p-pad metal layer through openings of the upper insulating layer. 9. The method of claim 8,
The opening exposing the n-pad metal layer is disposed near one edge of the mesa,
an opening exposing the p-pad metal layer is disposed near an edge opposite to the mesa. The method according to claim 1,
The p-type semiconductor layer includes a p-type GaN layer, wherein the p-type GaN layer has a thickness of 200 nm or less,
The p-ohmic contact layer is a deep ultraviolet light emitting diode comprising Ni/Rh. 11. The method of claim 10,
The n-pad metal layer is a deep ultraviolet light emitting diode comprising an Al layer. Board;
an n-type semiconductor layer positioned on the substrate;
a mesa disposed on the n-type semiconductor layer, including an active layer and a p-type semiconductor layer, and having a plurality of via holes exposing the n-type semiconductor layer;
n-ohmic contact layers contacting the n-type semiconductor layer in the via holes;
a p-ohmic contact layer in contact with the p-type semiconductor layer;
an n bump electrically connected to the n ohmic contact layers; and
a p-bump electrically connected to the p-ohmic contact layer;
The p-ohmic contact layer is a deep ultraviolet light emitting diode comprising Ni/Rh. 13. The method of claim 12,
a lower insulating layer covering the n-ohmic contact layers and the p-ohmic contact layer;
Further comprising an n-pad metal layer and a p-pad metal layer disposed on the lower insulating layer,
the lower insulating layer has openings exposing the n-ohmic contact layers and the p-ohmic contact layer, respectively;
the n-pad metal layer and the p-pad metal layer are electrically connected to the n-ohmic contact layers and the p-ohmic contact layer through the openings, respectively;
The n-bump and the p-bump are electrically connected to the n-pad metal layer and the p-pad metal layer, respectively. 14. The method of claim 13,
The p-pad metal layer is a deep ultraviolet light emitting diode surrounding the n-pad metal layer. 15. The method of claim 14,
An opening exposing the p-ohmic contact layer has a ring shape surrounding the via holes. 15. The method of claim 14,
and the p pad metal layer is located in an upper portion of a region between the via holes and an edge of the mesa. 14. The method of claim 13,
An upper insulating layer comprising the n-pad metal layer and the p-pad metal layer, wherein the upper insulating layer has openings exposing the n-pad metal layer and the p-pad metal layer;
The n-bump and the p-bump are electrically connected to the n-pad metal layer and the p-pad metal layer through the openings of the upper insulating layer, respectively. 18. The method of claim 17,
The lower insulating layer and the upper insulating layer are deep ultraviolet light emitting diodes that cover the side surface of the mesa. The method according to claim 17, wherein the opening exposing the n-pad metal layer is disposed near one edge of the mesa,
an opening exposing the p-pad metal layer is disposed near an edge opposite to the mesa. 13. The method of claim 12,
The p-type semiconductor layer includes a p-type GaN layer, wherein the p-type GaN layer has a thickness of 200 nm or less,
The Ni/Rh is a deep ultraviolet light emitting diode in ohmic contact with the p-type GaN layer. Board;
an n-type semiconductor layer positioned on the substrate;
a mesa disposed on the n-type semiconductor layer, including an active layer and a p-type semiconductor layer, and including a groove exposing the n-type semiconductor layer;
n-ohmic contact layers contacting the n-type semiconductor layer in the groove;
a p-ohmic contact layer in contact with the p-type semiconductor layer;
an n pad metal layer electrically connected to the n ohmic contact layers;
a p pad metal layer electrically connected to the p ohmic contact layer;
an n bump electrically connected to the n pad metal layer; and
and a p-bump electrically connected to the p-pad metal layer. 22. The method of claim 21,
an n capping layer covering the n ohmic contact layers; and
The deep ultraviolet light emitting diode further comprising a p capping layer covering the p ohmic contact layer. 22. The method of claim 21,
The groove extends in the longitudinal direction of the mesa,
A difference between the length of the mesa in the longitudinal direction and the length of the groove is less than or equal to the width of each of the mesa regions positioned on both sides of the groove. 24. The method of claim 23,
A deep ultraviolet light emitting diode in which the total area of the mesa region located on both sides of the groove exceeds 1/2 of the total area of the mesa. 24. The method of claim 23,
A deep ultraviolet light emitting diode having a curved shape in which corners of one end of the mesa region located on both sides of the groove have a curved shape. 24. The method of claim 23,
A deep ultraviolet light emitting diode in which depressions are formed in outer corners of one end of the corners of one end of the mesa region located on both sides of the groove. 22. The method of claim 21,
The groove may include a main groove extending in a longitudinal direction of the mesa; and
A deep ultraviolet light emitting diode having a plurality of sub grooves extending in a direction perpendicular to the main groove. 28. The method of claim 27,
The plurality of sub-grooves is a deep ultraviolet light emitting diode including grooves having different lengths and widths. 28. The method of claim 27,
A deep ultraviolet light emitting diode having a symmetrical structure with respect to a straight line passing through the center and parallel to the sub-groove. 28. The method of claim 27,
A deep ultraviolet light emitting diode having an asymmetric structure with respect to a straight line passing through the center and parallel to the main groove.

Images