KR20220003423A - Thin film transistor array substrate and display device - Google Patents

Abstract

Embodiments of the present disclosure relate to a thin film transistor array substrate and a display device. More particularly, the thin film transistor array substrate includes a first thin film transistor and a second thin film transistor. The physical properties of a channel of the semiconductor layer of the first thin film transistor is different from the physical properties of a channel of the semiconductor layer of the second thin film transistor. The gate insulating structure between the semiconductor layer and the gate electrode of the first thin film transistor is different from the gate insulating structure between the semiconductor layer and the gate electrode of the second thin film transistor. Thus, first and second thin film transistors having different transistor characteristics can be provided.

Description

Thin film transistor array substrate and display device {THIN FILM TRANSISTOR ARRAY SUBSTRATE AND DISPLAY DEVICE}

Embodiments of the present disclosure relate to a thin film transistor array substrate and a display device.

A transistor is widely used as a switching device or a driving device in the field of electronic devices. In particular, since the thin film transistor can be manufactured on a glass substrate or a plastic substrate, switching of a display device such as a liquid crystal display device or an organic light emitting display device It is widely used as an element.

A thin film transistor is an amorphous silicon thin film transistor in which amorphous silicon is used as an active layer, a polycrystalline silicon thin film transistor in which polycrystalline silicon is used as an active layer, and an oxide semiconductor as an active layer, based on a material constituting an active layer. It may be classified as an oxide semiconductor thin film transistor.

Since the active layer can be formed by depositing amorphous silicon in a short time, the amorphous silicon thin film transistor (a-Si TFT) has advantages in that the manufacturing process time is short and the production cost is low. On the other hand, since the mobility is low, the current driving ability is poor, and the threshold voltage is changed, the amorphous silicon thin film transistor has disadvantages in that its use is limited in organic light emitting display devices.

A polycrystalline silicon thin film transistor (poly-Si TFT) is made by depositing amorphous silicon and then crystallizing the amorphous silicon. Since a process in which amorphous silicon is crystallized is required in the manufacturing process of polysilicon thin film transistor, the number of processes increases and manufacturing cost increases, and since crystallization process is performed at high process temperature, polysilicon thin film transistor is applied to large area devices It is difficult to become In addition, due to polycrystalline characteristics, it is difficult to secure uniformity of the polycrystalline silicon thin film transistor.

Since the oxide constituting the active layer can be formed at a relatively low temperature, has high mobility, and has a large resistance change according to the oxygen content, an oxide semiconductor TFT has desired physical properties. It has the advantage of being easily obtained. In addition, since the oxide semiconductor is transparent due to the characteristics of the oxide, it is advantageous for realizing a transparent display. However, in order to apply the oxide semiconductor layer to the thin film transistor, a separate conductorization process is required to form a connection portion between the source electrode and the drain electrode.

On the other hand, thin film transistors need to be designed to meet various needs according to their use or function. However, in order to design thin film transistors to meet various needs, there is a problem in that the process becomes difficult or complicated. Accordingly, the design of thin film transistors satisfying various demands has not been made.

Embodiments of the present invention may provide a thin film transistor array substrate and a display device in which thin film transistors having different functions or uses are designed to have their own unique transistor characteristics.

Embodiments of the present disclosure may provide a thin film transistor array substrate and a display device including thin film transistors having different channel characteristics so that the thin film transistors may have different transistor characteristics.

Embodiments of the present disclosure may provide a thin film transistor array substrate and a display device including thin film transistors having different gate insulating structures so that the thin film transistors may have different transistor characteristics.

Embodiments of the present disclosure may implement a heterogeneous channel characteristic and a heterogeneous gate insulation structure between thin film transistors that allow the thin film transistors to have different transistor characteristics through a simple manufacturing process method.

Embodiments of the present disclosure include a substrate; a first thin film transistor disposed in a first region of the substrate and including a first semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode; a second thin film transistor disposed in a second region different from the first region of the substrate and including a second semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode; a first gate insulating layer disposed between the first semiconductor layer and the first gate electrode; and a second gate insulating layer disposed between the second semiconductor layer and the second gate electrode.

The first semiconductor layer may include a first channel part overlapping the first gate electrode, a first source connection part positioned on one side of the first channel part, and a first drain connection part positioned on the other side of the first channel part.

The second semiconductor layer may include a second channel part overlapping the second gate electrode, a second source connection part positioned on one side of the second channel part, and a second drain connection part positioned on the other side of the second channel part.

In the thin film transistor array substrate according to the embodiments of the present disclosure, the first gate insulating layer extends from the first region to the second region and is interposed between the second semiconductor layer and the second gate insulating layer, and the second gate insulating layer includes the second region may extend to the first region and be disposed on the first gate electrode.

In the thin film transistor array substrate according to embodiments of the present disclosure, the second channel portion of the second semiconductor layer may be doped with a specific dopant undoped into the first channel portion of the first semiconductor layer.

In the thin film transistor array substrate according to embodiments of the present disclosure, a distance between the second channel portion doped with a specific dopant and the second gate electrode is greater than the distance between the first channel portion undoped with a specific dopant and the first gate electrode. can

The thin film transistor array substrate according to embodiments of the present disclosure may further include an interlayer insulating layer disposed on the second gate insulating layer while covering the second gate electrode.

The first source electrode, the first drain electrode, the second source electrode, and the second drain electrode may be disposed on the interlayer insulating layer. The first source electrode may make electrical contact with the first source connection part through a first source contact hole penetrating the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer. The first drain electrode may be in electrical contact with the first drain connection part through a first drain contact hole penetrating the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer.

The second source electrode may make electrical contact with the second source connection part through a second source contact hole penetrating the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer. The second drain electrode may make electrical contact with the second drain connection part through a second drain contact hole penetrating the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer.

In the thin film transistor array substrate according to the embodiments of the present disclosure, the specific dopant doped in the second channel portion of the second semiconductor layer is doped to the second source connection portion and the second drain connection portion included in the second semiconductor layer, , the first source connection portion and the first drain connection portion included in the first semiconductor layer may be doped.

In the thin film transistor array substrate according to embodiments of the present disclosure, a thickness of the second gate insulating layer may be thinner than a thickness of the first gate insulating layer.

In the thin film transistor array substrate according to embodiments of the present disclosure, the second thin film transistor may have a larger subthreshold swing value than that of the first thin film transistor.

In the thin film transistor array substrate according to the embodiments of the present disclosure, the second thin film transistor may have a lower mobility or a lower dynamic current level than the first thin film transistor.

In the thin film transistor array substrate according to the embodiments of the present disclosure, a magnitude shifted by the threshold voltage of the second thin film transistor in the positive direction may be greater than a magnitude shifted in the positive direction by the threshold voltage of the first thin film transistor.

In the thin film transistor array substrate according to the embodiments of the present disclosure, the first thin film transistor may be a switching transistor, and the second thin film transistor may be a driving transistor.

In the thin film transistor array substrate according to embodiments of the present disclosure, the specific dopant may include one or more of fluorine, nitrogen, yttrium, and molybdenum.

Embodiments of the present disclosure include a substrate; a light emitting device disposed on a substrate; a driving transistor for supplying a driving current to the light emitting device; and a switching transistor for controlling a voltage of a gate node of the driving transistor.

The switching transistor includes a first semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode, the first semiconductor layer having a first channel portion overlapping the first gate electrode, one side of the first channel portion It may include a first source connection part positioned at , and a first drain connector positioned on the other side of the first channel part.

The driving transistor includes a second semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode, and the second semiconductor layer includes a second channel portion overlapping the second gate electrode, and one side of the second channel portion. It may include a second source connector positioned on the second drain connector positioned on the other side of the second channel part.

In the display device according to the embodiments of the present disclosure, the distance the second semiconductor layer is separated from the second gate electrode is greater than the distance that the first semiconductor layer is separated from the first gate electrode, and the second channel portion of the second semiconductor layer is An undoped specific dopant may be doped in the first channel portion of the first semiconductor layer.

The display device according to the embodiments of the present disclosure further includes a first gate insulating layer disposed between the first semiconductor layer and the first gate electrode and a second gate insulating layer disposed between the second semiconductor layer and the second gate electrode. can do.

In the display device according to the embodiments of the present disclosure, the first gate insulating layer extends from the first region in which the switching transistor is disposed to the second region in which the driving transistor is disposed and is interposed between the second semiconductor layer and the second gate insulating layer, The second gate insulating layer may extend from the second region to the first region and be disposed on the first gate electrode.

In the display device according to the embodiments of the present disclosure, the specific dopant doped in the second channel part included in the second semiconductor layer of the driving transistor may include the second source connection part and the second part included in the second semiconductor layer of the driving transistor. The drain connection part may be doped, and the first source connection part and the first drain connection part included in the first semiconductor layer of the switching transistor may be doped.

In the display device according to embodiments of the present disclosure, the driving transistor may have a larger subthreshold swing value than that of the switching transistor.

In the display device according to the embodiments of the present disclosure, the driving transistor may have lower mobility or a lower operating current level than the switching transistor.

In the display device according to the exemplary embodiments of the present disclosure, a shifted magnitude of the threshold voltage of the driving transistor in the positive direction may be greater than a shifted magnitude of the threshold voltage of the switching transistor in the positive direction.

According to embodiments of the present disclosure, it is possible to provide a thin film transistor array substrate and a display device in which thin film transistors having different functions or uses are designed to have their own unique transistor characteristics.

According to embodiments of the present disclosure, it is possible to provide a thin film transistor array substrate and a display device including thin film transistors having different channel characteristics so that the thin film transistors can have different transistor characteristics.

According to embodiments of the present disclosure, it is possible to provide a thin film transistor array substrate and a display device including thin film transistors having different gate insulating structures so that the thin film transistors have different transistor characteristics.

According to the embodiments of the present disclosure, heterogeneous channel characteristics and heterogeneous gate insulation structures between thin film transistors that allow thin film transistors to have different transistor characteristics may be implemented through a simple manufacturing process method.

1 is a view for explaining heterogeneous channel characteristics and heterogeneous gate insulation structures of a first thin film transistor and a second thin film transistor according to requirements in a thin film transistor array substrate according to embodiments of the present disclosure;
2 is a cross-sectional view of a first region and a second region in which a first thin film transistor and a second thin film transistor are formed in a thin film transistor array substrate according to embodiments of the present disclosure;
3 to 7 are views illustrating process procedures for forming heterogeneous channel characteristics and heterogeneous gate insulating structures based on the cross-sectional structure of FIG. 2 .
8 is another cross-sectional view of a first region and a second region in which a first thin film transistor and a second thin film transistor are formed in a thin film transistor array substrate according to embodiments of the present disclosure;
9 is a view for explaining a change in transistor characteristics according to a gate insulating film structure and a change in transistor characteristics according to a specific dopant type in a thin film transistor array substrate according to embodiments of the present disclosure;
10 is a diagram illustrating a display device according to embodiments of the present disclosure.
11 is a cross-sectional view illustrating a driving transistor and a switching transistor in each subpixel in a display device according to embodiments of the present disclosure.

Hereinafter, some embodiments of the present disclosure will be described in detail with reference to exemplary drawings. In adding reference numerals to components of each drawing, the same components may have the same reference numerals as much as possible even though they are indicated in different drawings. In addition, in describing the present disclosure, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present disclosure, the detailed description may be omitted. When "includes", "having", "consisting of", etc. mentioned in this specification are used, other parts may be added unless "only" is used. When a component is expressed in the singular, it may include a case in which the plural is included unless otherwise explicitly stated.

In addition, in describing the components of the present disclosure, terms such as first, second, A, B, (a), (b), etc. may be used. These terms are only for distinguishing the elements from other elements, and the essence, order, order, or number of the elements are not limited by the terms.

In the description of the positional relationship of the components, when it is described that two or more components are "connected", "coupled" or "connected", two or more components are directly "connected", "coupled" or "connected" ", but it will be understood that two or more components and other components may be further "interposed" and "connected," "coupled," or "connected." Here, other components may be included in one or more of two or more components that are “connected”, “coupled” or “connected” to each other.

In the description of the temporal flow relationship related to the components, the operation method or the production method, for example, the temporal precedence relationship such as "after", "after", "after", "before", etc. Alternatively, when a flow precedence relationship is described, it may include a case where it is not continuous unless "immediately" or "directly" is used.

On the other hand, when numerical values or corresponding information (eg, level, etc.) for a component are mentioned, even if there is no separate explicit description, the numerical value or the corresponding information is based on various factors (eg, process factors, internal or external shock, Noise, etc.) may be interpreted as including an error range that may occur.

1 is a diagram illustrating heterogeneous channel characteristics and a heterogeneous gate insulating structure of a first thin film transistor TFT1 and a second thin film transistor TFT2 according to requirements in a thin film transistor array substrate according to embodiments of the present disclosure; It is a diagram for explaining the heterogeneous gate insulation structure.

A plurality of thin film transistors disposed on the thin film transistor array substrate may be used for different purposes and may perform different functions.

The thin film transistors disposed on the thin film transistor array substrate should be designed to have different electrical characteristics (transistor characteristics) in order to have different uses and functions. To this end, the thin film transistors arranged on the thin film transistor array substrate have different structural characteristics. can have

In addition, thin film transistors disposed on different thin film transistor array substrates should be designed to have different transistor characteristics (electrical characteristics) in order to have different uses and functions. To this end, thin film transistors arranged on thin film transistor array substrates are They may have different physical properties.

For example, transistor characteristics of thin film transistors may include one or more of a subthreshold swing value (SS), threshold voltage characteristics, mobility, operating current level, and response speed. These transistor characteristics may be indices for judging the reliability of the thin film transistor.

Among the transistor characteristics mentioned above, the sub-threshold swing value SS may have the following definition. As the voltage (Vgs) between the gate electrode and the source electrode increases, the drain-source current (Ids) increases with a relationship of approximately Ids ∝ (Vgs-Vth)^2 for a voltage below the threshold voltage (Vth). The Vgs value required to increase Ids by a factor of 10 is called the sub-threshold swing value. The sub-threshold swing value is also referred to as an S-factor.

More simply, when the drain current flowing through the thin film transistor changes as the gate voltage applied to the gate electrode of the thin film transistor changes, the sub-threshold swing value becomes the inverse of the change amount of the drain current with respect to the change amount of the gate voltage. can

1, the change amount of the drain current with respect to the change amount of the gate voltage corresponds to the slope of the drain current change curve according to the change of the gate voltage, and the sub-threshold swing value becomes the inverse of the slope (that is, SS = 1/slope, slope=1/SS).

A small sub-threshold swing value (that is, a large slope of the drain current change curve according to the gate voltage change) means that the drain current increases faster as the gate voltage increases. For this reason, it can be seen that the thin film transistor having a small sub-threshold swing value has good switching characteristics (on-off characteristics).

Therefore, a thin film transistor (eg, a switching transistor) requiring good switching characteristics (on-off characteristics) needs to be designed to have a small sub-threshold swing value. The thin film transistor may include a switching transistor in each subpixel in the organic light emitting diode display. The switching transistor is turned on according to a switching operation to supply a data voltage to the gate electrode of the driving transistor.

Conversely, a large sub-threshold swing value (that is, a small slope of the drain current change curve according to the gate voltage change) means that the drain current slowly increases as the gate voltage increases. For this reason, it can be seen that the thin film transistor having a small sub-threshold swing value has better current driving ability than the switching characteristic (on-off characteristic).

Therefore, a thin film transistor requiring excellent current driving capability needs to be designed to have a large sub-threshold swing value. The thin film transistor may include a driving transistor for driving the light emitting device in each subpixel in the organic light emitting diode display.

Among the transistor characteristics mentioned above, the operating current level is the current required for driving (operation) of the thin film transistor. Thin film transistors are designed to have a desired operating current level. In addition, the operating current level, which is a unique characteristic of the thin film transistor, may correspond to the mobility of the thin film transistor. In addition, the operating current level of the thin film transistor is related to the response speed of the thin film transistor. In addition, the operating current level of the thin film transistor may mean the amount of current conducted by the thin film transistor with respect to the same gate voltage. For example, when a gate voltage of 5V is applied, a thin film transistor conducting a relatively high source-drain current is said to have a high operating current level, and a thin film transistor conducting a relatively low source-drain current is said to have a low operation It can be said to have a current level.

For example, a thin film transistor that requires a high operating current level (also referred to as a driving current level) is a thin film transistor that has high mobility and requires a fast response speed. Conversely, a thin film transistor that does not require a fast response speed may have low mobility or may have a low operating current level.

Looking at the second graph of FIG. 1, in the drain current change curve according to the gate voltage change, when the thin film transistor has a high operating current level, it may be that a relatively large drain current flows according to the gate voltage change. The thin film transistor can be considered to have high mobility (electron mobility). When the thin film transistor has a low operating current level, it may be that a relatively small drain current flows according to a change in gate voltage, and this thin film transistor can be considered to have low mobility (electron mobility).

When the thin film transistor requires a fast response speed and/or high mobility, the thin film transistor needs to be designed to operate at a high operating current level. The thin film transistor may include a switching transistor in each subpixel in the organic light emitting diode display. The switching transistor should be able to perform a faster switching operation by having high mobility, and through this, the voltage state of the gate electrode of the driving transistor should be quickly controlled.

When the thin film transistor requires not fast response speed and/or not high mobility, the thin film transistor needs to be designed to operate at a low operating current level. The thin film transistor may include a driving transistor for driving the light emitting device in each subpixel in the organic light emitting diode display. Such driving transistors do not need to operate at high operating current levels, or in some cases may need to operate at low operating current levels. The driving transistor need not have high mobility or may need to have low mobility in some cases. Instead, the mobility variation between the driving transistors needs to be minimized. On the other hand, the operating current level of the driving transistor is a unique characteristic of the driving transistor, and is a current component different from the current that the driving transistor supplies to the light emitting device and can be varied according to an image signal (the driving current for driving the light emitting device).

Among the transistor characteristics mentioned above, the threshold voltage positive shift (Vth Positive Shift) refers to a characteristic in which the threshold voltage shifts (shifts) in the positive direction (the direction in which the voltage value increases) intrinsic to the thin film transistor. Accordingly, as shown in the third graph, the drain voltage change curve according to the gate voltage change has a tendency to shift to the right.

In general, when the threshold voltage of the thin film transistor shifts in a negative direction (a direction in which the voltage value decreases), it is not preferable because the thin film transistor does not have desired performance. For example, if the threshold voltage is shifted in the negative direction, the thin film transistor may be turned on too easily and it may be difficult to properly function as a switch. In contrast, when the threshold voltage of the thin film transistor is shifted in a positive direction at an appropriate level, the thin film transistor may exhibit good performance. However, when the threshold voltage of the thin film transistor is shifted too much in the positive direction, the performance of the thin film transistor may be rather deteriorated. Accordingly, each thin film transistor needs to have a threshold voltage suitable for a desired function of the thin film transistor.

In relation to this, the deviation in the magnitude of shifting the threshold voltage of each of the thin film transistors in the positive direction may correspond to a positive bias temperature stress (PBTS). In general, in the case of a switching transistor, it may have a high PBTS characteristic. However, the switching transistor needs to have low PBTS characteristics. In relation to this, in the case of the driving transistor, since it functions to supply a driving current to the light emitting device, it may have high current stress characteristics.

As described above, since thin film transistors have different uses and functions, the transistor characteristics (eg, sub-threshold swing value (SS), threshold voltage characteristics, mobility, operating current level and response speed, etc.) are different from each other. It has TFT Requirements.

As described above, in forming the thin film transistors on the thin film transistor array substrate constituting the display panel of the display device, in order to satisfy different demands of the thin film transistors, the thin film transistors disposed on the thin film transistor array substrate have different structural characteristics. And/or it should be formed to have physical properties.

However, in forming thin film transistors on a thin film transistor array substrate, in order to satisfy different demands of thin film transistors, designing thin film transistors disposed on the thin film transistor array substrate to have different structural characteristics or physical properties is difficult. This may cause problems in making the manufacturing process of the transistor array substrate difficult or complicating the manufacturing process.

Accordingly, the thin film transistor array substrate according to the embodiments of the present disclosure does not increase the complexity or difficulty of the manufacturing process, and the thin film transistors have transistor characteristics that meet their respective needs, and structural features and physical properties of the thin film transistors provides

Below, a first thin film transistor (TFT1) and a second thin film transistor (TFT2) having different uses and functions among a plurality of thin film transistors (Thin Film Transistors) disposed on the thin film transistor array substrate according to embodiments of the present disclosure ) as an example.

For example, the first thin film transistor TFT1 and the second thin film transistor TFT2 disposed on the thin film transistor array substrate according to the embodiments of the present disclosure have different electrical characteristics (transistor characteristics) to have different uses and functions. ), and for this purpose, the first thin film transistor TFT1 and the second thin film transistor TFT2 disposed on the thin film transistor array substrate according to the embodiments of the present disclosure may have different structural characteristics. .

The first thin film transistor TFT1 and the second thin film transistor TFT2 disposed on the thin film transistor array substrate according to the embodiments of the present disclosure have different structural features, and have a heterogeneous gate insulation structure. can

The above-mentioned heterogeneous gate insulating structure may mean that the gate insulating structure of the first thin film transistor TFT1 and the gate insulating structure of the second thin film transistor TFT2 are different from each other.

The gate insulating structure of the first thin film transistor TFT1 is an insulating structure between the gate electrode (hereinafter also referred to as a first gate electrode) and a semiconductor layer (hereinafter referred to as a first semiconductor layer) of the first thin film transistor TFT1 . (gate insulating film structure).

The gate insulating structure of the second thin film transistor TFT2 is an insulating structure between the gate electrode (hereinafter also referred to as a second gate electrode) of the second thin film transistor TFT2 and a semiconductor layer (hereinafter referred to as a second semiconductor layer). (gate insulating film structure).

In addition, the first thin film transistor TFT1 and the second thin film transistor TFT2 disposed on the thin film transistor array substrate according to the embodiments of the present disclosure have different transistor characteristics (electrical characteristics) to have different uses and functions. ), and for this purpose, the first thin film transistor TFT1 and the second thin film transistor TFT2 disposed on the thin film transistor array substrate according to the embodiments of the present disclosure may have different physical properties.

The first thin film transistor TFT1 and the second thin film transistor TFT2 disposed on the thin film transistor array substrate according to the exemplary embodiments of the present disclosure may have different physical properties, and may have heterogeneous channel characteristics.

The above-mentioned heterogeneous channel characteristics may mean that the electrical characteristics of the channel of the first thin film transistor TFT1 and the electrical characteristics of the channel of the second thin film transistor TFT2 are different from each other.

The electrical characteristics of the channel of the first thin film transistor TFT1 refer to material characteristics of the channel portion (hereinafter, referred to as the first channel portion) in the first semiconductor layer of the first thin film transistor TFT1, and the second thin film transistor TFT1. The electrical characteristics of the channel of the transistor TFT2 may refer to material characteristics of a channel portion (hereinafter, referred to as a second channel portion) in the second semiconductor layer of the second thin film transistor TFT2 .

2 is a cross-sectional view of a first area A1 and a second area A2 in which a first thin film transistor TFT1 and a second thin film transistor TFT2 are formed in a thin film transistor array substrate according to embodiments of the present disclosure; to be.

Referring to FIG. 2 , a thin film transistor array substrate according to embodiments of the present disclosure may include a substrate SUB, a first thin film transistor TFT1 , a second thin film transistor TFT2 , and the like.

The first thin film transistor TFT1 is disposed in the first area A1 of the substrate SUB, and includes a first semiconductor layer ACT1 , a first gate electrode G1 , a first source electrode S1 , and a first drain electrode. An electrode D1 may be included. The first area A1 and the second area A2 may be completely different areas, may be partially overlapped areas, or may be areas that completely overlap vertically in some cases.

The second thin film transistor TFT2 is disposed in a second area A2 different from the first area A1 of the substrate SUB, the second semiconductor layer ACT2, the second gate electrode G2, and the second source An electrode S2 and a second drain electrode D2 may be included.

For example, the first semiconductor layer ACT1 and the second semiconductor layer ACT2 may be an oxide semiconductor layer, and in some cases, an amorphous silicon semiconductor layer or a polycrystalline silicon semiconductor layer.

Referring to FIG. 2 , in the thin film transistor array substrate according to embodiments of the present disclosure, a first gate insulating layer GI1 and a second semiconductor layer disposed between the first semiconductor layer ACT1 and the first gate electrode G1 are provided. A second gate insulating layer GI2 disposed between the layer ACT2 and the second gate electrode G2 may be further included.

Referring to FIG. 2 , the first semiconductor layer ACT1 includes a first channel part CH1 overlapping the first gate electrode G1 , and a first source connection part positioned at one side of the first channel part CH1 . SC1) and a first drain connection part DC1 positioned on the other side of the first channel part CH1.

The second semiconductor layer ACT2 includes a second channel part CH2 overlapping the second gate electrode G2 , a second source connection part SC2 positioned at one side of the second channel part CH2 , and a second channel A second drain connection part DC2 positioned on the other side of the part CH2 may be included.

Referring to FIG. 2 , the first gate insulating layer GI1 may extend from the first region A1 to the second region A2 and may be interposed between the second semiconductor layer ACT2 and the second gate insulating layer GI2 . . In addition, the second gate insulating layer GI2 may extend from the second area A2 to the first area A1 and be disposed on the first gate electrode G1 .

Accordingly, in the first thin film transistor TFT1, only the first gate insulating layer GI1 is disposed between the first gate electrode G1 and the first channel part CH1, and in the second thin film transistor TFT2, the second gate Both the first gate insulating layer GI1 and the second gate insulating layer GI2 may be disposed between the electrode G2 and the second channel part CH2 .

Accordingly, the distance L2 between the second channel part CH2 doped with a specific dopant and the second gate electrode G2 in the second thin film transistor TFT2 is not doped with a specific dopant in the first thin film transistor TFT1. It may be greater than the distance L1 between the first channel part CH1 and the first gate electrode G1.

Accordingly, the gate insulating structure of the first thin film transistor TFT1 and the gate insulating structure of the second thin film transistor TFT2 may be different from each other. That is, a heterogeneous gate insulating structure between the first thin film transistor TFT1 and the second thin film transistor TFT2 may be implemented.

As will be described later, in the second thin film transistor TFT2 , the distance L2 between the second channel portion CH2 doped with a specific dopant and the second gate electrode G2 is not equal to the specific dopant in the first thin film transistor TFT1 . Since the distance L1 between the doped first channel part CH1 and the first gate electrode G1 is greater than the distance L1 , the magnitude of the positive shift of the threshold voltage of the second thin film transistor TFT2 may increase. As described above, due to an increase in the threshold voltage positive shift magnitude of the second thin film transistor TFT2 , operation reliability related to the threshold voltage of the second thin film transistor TFT2 may be improved.

In addition, the distance L2 between the second channel part CH2 doped with a specific dopant and the second gate electrode G2 in the second thin film transistor TFT2 is not doped with a specific dopant in the first thin film transistor TFT1. Since the distance L1 between the first channel part CH1 and the first gate electrode G1 is greater than the distance L1 , the operating current level of the second thin film transistor TFT2 may decrease and a sub-threshold swing value may increase. This may mean that the second thin film transistor TFT2 further satisfies the requirements of the driving transistor.

Referring to FIG. 2 , in the first thin film transistor TFT1 , the distance L1 between the first channel portion CH1 undoped with a specific dopant and the first gate electrode G1 is the thickness of the first gate insulating layer GI1 . The distance L2 between the second channel portion CH2 and the second gate electrode G2, which is determined as (Ta) and is doped with a specific dopant in the second thin film transistor TFT2, is that of the first gate insulating layer GI1. It may be determined as the sum of the thickness Ta and the thickness Tb of the second gate insulating layer GI2 (Ta+Tb).

Referring to FIG. 2 , the thickness Tb of the second gate insulating layer GI2 may be similar to the thickness Ta of the first gate insulating layer GI1 . As a result, the first gate insulating layer GI1 and the second gate insulating layer GI2 can be formed using the same or similar process method, thereby making the manufacturing process easier.

Meanwhile, unlike FIG. 2 , the thickness Tb of the second gate insulating layer GI2 may be thinner than the thickness Ta of the first gate insulating layer GI1 . This will be described again with reference to FIG. 8 .

Referring to FIG. 2 , the thin film transistor array substrate according to embodiments of the present disclosure may further include an interlayer insulating layer ILD disposed on the second gate insulating layer GI2 while covering the second gate electrode G2 . can

Referring to FIG. 2 , the first source electrode S1 , the first drain electrode D1 , the second source electrode S2 , and the second drain electrode D2 may be positioned on the interlayer insulating layer ILD.

Referring to FIG. 2 , the first source electrode S1 is connected to the first source through a first source contact hole penetrating the interlayer insulating layer ILD, the second gate insulating layer GI2 and the first gate insulating layer GI1 . In electrical contact with the connection part SC1, the first drain electrode D1 is formed through a first drain contact hole penetrating the interlayer insulating layer ILD, the second gate insulating layer GI2, and the first gate insulating layer GI1. , may be in electrical contact with the first drain connection part DC1 .

Referring to FIG. 2 , the second source electrode S2 is connected to the second source through a second source contact hole penetrating the interlayer insulating layer ILD, the second gate insulating layer GI2 , and the first gate insulating layer GI1 . The second drain electrode D2 is in electrical contact with the connection part SC2 through a second drain contact hole penetrating the interlayer insulating layer ILD, the second gate insulating layer GI2, and the first gate insulating layer GI1. , may be in electrical contact with the second drain connection part DC2 .

Referring to FIG. 2 , the thin film transistor array substrate according to embodiments of the present disclosure may further include a passivation layer PAS disposed on the first thin film transistor TFT1 and the second thin film transistor TFT2 . . The passivation layer PAS may be disposed on the interlayer insulating layer ILD while covering the first source electrode S1 , the first drain electrode D1 , the second source electrode S2 , and the second drain electrode D2 . have.

Referring to FIG. 2 , in the second thin film transistor TFT2 , the second channel part CH2 of the second semiconductor layer ACT2 is the first channel part of the first semiconductor layer ACT1 in the first thin film transistor TFT1 . (CH1) may be doped with an undoped specific dopant.

That is, among the first channel part CH1 of the first semiconductor layer ACT1 in the first thin film transistor TFT1 and the second channel part CH2 of the second semiconductor layer ACT2 in the second thin film transistor TFT2 , in the second thin film transistor TFT2, only the second channel portion CH2 of the second semiconductor layer ACT2 is doped with a specific dopant.

The first channel part CH1 of the first semiconductor layer ACT1 in the first thin film transistor TFT1 and the second channel part CH2 of the second semiconductor layer ACT2 in the second thin film transistor TFT2 have the same base It is formed based on a semiconductor material. However, in the second thin film transistor TFT2, the second channel portion CH2 of the second semiconductor layer ACT2 is doped with a specific dopant in addition to the same basic semiconductor material. Here, for example, the basic semiconductor material may be an oxide semiconductor material, and in some cases may be an amorphous silicon semiconductor material or a polycrystalline silicon semiconductor material.

As a result, the first thin film transistor TFT1 and the second thin film transistor TFT2 have different channel characteristics, so that heterogeneous channel characteristics can be implemented.

The specific dopant mentioned above is selected to make the channel characteristics of the second thin film transistor TFT2 different from the channel characteristics of the first thin film transistor TFT1 . For example, the specific dopant is a dopant selected to adjust the sub-threshold swing value of the second thin film transistor TFT2 , or a dopant selected to adjust the operating current level of the second thin film transistor TFT2 , or the second thin film transistor TFT2 ) may be a dopant selected to control the mobility or a dopant selected to control the threshold voltage characteristic of the second thin film transistor TFT2.

For example, specific dopants doped in the second channel portion CH2 of the second semiconductor layer ACT2 of the second thin film transistor TFT2 include fluorine (F), nitrogen (N), yttrium (Y) and It may be one dopant selected from the group of dopants including molybdenum (Mo), or a combination of two or more dopants.

Referring to FIG. 2 , a specific dopant doped in the second channel portion CH2 of the second semiconductor layer ACT2 of the second thin film transistor TFT2 is the second semiconductor layer ACT2 of the second thin film transistor TFT2 . ) may be doped into the second source connection part SC2 and the second drain connection part DC2 included in the .

In addition, the specific dopant doped in the second channel portion CH2 of the second semiconductor layer ACT2 of the second thin film transistor TFT2 is included in the first semiconductor layer ACT1 of the first thin film transistor TFT1. The first source connection part SC1 and the first drain connection part DC1 may be doped.

As such, a specific dopant doped into the second channel portion CH2 of the second semiconductor layer ACT2 of the second thin film transistor TFT2 is applied to the first semiconductor layer ACT1 and the second semiconductor layer ACT1 of the first thin film transistor TFT1. In the second semiconductor layer ACT2 of the thin film transistor TFT2, it is confirmed in the various regions SC1, DC1, SC2, and DC2 other than the channel region, because there is a peculiarity in the manufacturing process for creating heterogeneous channel characteristics. .

3 to 7 for a unique manufacturing process related to why a specific dopant exists not only in the second channel portion CH2 of the second semiconductor layer ACT2 of the second thin film transistor TFT2 but also in various positions to be described later.

The second thin film transistor TFT2 may have a larger sub-threshold swing value than the first thin film transistor TFT1 . Such a difference in transistor characteristics may be expressed by at least one of a heterogeneous gate insulating structure and a heterogeneous channel characteristic.

Accordingly, the second thin film transistor TFT2 may be applied to a transistor requiring and requiring a relatively large sub-threshold swing value. The first thin film transistor TFT1 may be applied to a transistor requiring and requiring a relatively small sub-threshold swing value.

The second thin film transistor TFT2 may have lower mobility or a lower operating current level than the first thin film transistor TFT1 . Such a difference in transistor characteristics may be expressed by at least one of a heterogeneous gate insulating structure and a heterogeneous channel characteristic.

Accordingly, the second thin film transistor TFT2 may be applied to a transistor requiring and requiring relatively low mobility, low operating current level, or slow response speed. The first thin film transistor TFT1 may be applied to a transistor requiring and requiring relatively high mobility, high operating current level, or fast response speed.

A shift in the positive direction of the threshold voltage of the second thin film transistor TFT2 may be greater than a shift in the threshold voltage of the first thin film transistor TFT1 in the positive direction. Such a difference in transistor characteristics may be expressed by at least one of a heterogeneous gate insulating structure and a heterogeneous channel characteristic.

Accordingly, the second thin film transistor TFT2 is applied to the transistor in which the magnitude shifted in the positive direction of the threshold voltage should be large, and the first thin film transistor TFT1 is applied to the transistor in which the magnitude shifted in the positive direction of the threshold voltage is small. can be applied.

3 to 7 are views illustrating process procedures for forming heterogeneous channel characteristics and heterogeneous gate insulating structures based on the cross-sectional structure of FIG. 2 .

Referring to FIG. 3 , in step S10 , a buffer layer BUF is deposited on the substrate SUB. Thereafter, the base semiconductor material may be patterned.

Referring to FIG. 3 , when the basic semiconductor material is patterned, the basic semiconductor material serving as the basic material of the first semiconductor layer ACT1 is formed in the first region A1 where the first thin film transistor TFT1 is to be formed as the buffer layer BUF. A basic semiconductor material serving as a basic material of the second semiconductor layer ACT2 may be patterned on the buffer layer BUF in the second region A2 where the second thin film transistor TFT2 is to be formed. .

A basic semiconductor material serving as a basic material of each of the first semiconductor layer ACT1 and the second semiconductor layer ACT2 may be the same as each other.

Referring to FIG. 4 , in step S20 after step S10 , a first gate insulating layer GI1 may be deposited to cover a basic semiconductor material serving as a basic material of each of the first semiconductor layer ACT1 and the second semiconductor layer ACT2 . can

Thereafter, the first gate electrode G1 may be panned on the first gate insulating layer GI1 . Here, the first gate electrode G1 may correspond to the gate electrode of the first thin film transistor TFT1 to be formed in the first region A1 . The first gate electrode G1 may be patterned to overlap a region corresponding to the first channel portion CH1 of the first semiconductor layer ACT1 .

Referring to FIG. 5 , after step S20 , in step S30 , a second gate insulating layer GI2 may be deposited to cover the first gate electrode G1 .

Thereafter, a channel doping process may be performed using a specific dopant to be doped into the second channel portion CH2 in the second semiconductor layer ACT2 of the second thin film transistor TFT2 .

The patterned first semiconductor layer ACT1 may include a first partial region R1a, a second partial region R1b, and a third partial region R1c. Here, the first partial region R1a of the first semiconductor layer ACT1 is a region in which the first source connection part SC1 is to be formed, and the second partial region R1b of the first semiconductor layer ACT1 is the first drain A region in which the connection part DC1 is to be formed, and the third partial region R1c of the first semiconductor layer ACT1 is a region in which the first channel part CH1 is to be formed.

The patterned second semiconductor layer ACT2 may include a first partial region R2a, a second partial region R2b, and a third partial region R2c. Here, the first partial region R2a of the second semiconductor layer ACT2 is a region in which the second source connection part SC2 is to be formed, and the second partial region R2b of the second semiconductor layer ACT2 is the second drain A region in which the connection part DC2 is to be formed, and the third partial region R2c of the second semiconductor layer ACT2 is a region in which the second channel part CH2 is to be formed.

When the channel doping process using a specific dopant is performed, a first channel portion among the first partial region R1a, the second partial region R1b, and the third partial region R1c included in the first semiconductor layer ACT1 The third partial region R1c where CH1 is to be formed is covered by the first gate electrode G1 disposed thereon.

Accordingly, after the channel doping process using a specific dopant is performed, the first partial region R1a, the second partial region R1b, and the third partial region R1c included in the first semiconductor layer ACT1 . The first partial region R1a in which the source connection part SC1 is to be formed and the second partial region R1b in which the first drain connection part DC1 is to be formed are doped with a specific dopant, and the first channel part CH1 is formed. The third partial region R1c to be formed is not doped with a specific dopant.

After the channel doping process using a specific dopant is performed, in the third partial region R1c of the first semiconductor layer ACT1 , the first channel part CH1 is formed in a state in which the specific dopant is not doped into the basic semiconductor material. can

Meanwhile, after the channel doping process using a specific dopant is performed, the first partial region R2a, the second partial region R2b, and the third partial region R2c included in the second semiconductor layer ACT2 are all formed with a specific dopant. is doped with

After the channel doping process using a specific dopant is performed, in the third partial region R2c of the second semiconductor layer ACT2, the second channel part CH2 may be formed in a state in which a specific dopant is doped into a basic semiconductor material. have.

Referring to FIG. 6 , after step S30 , in step S40 , the second gate electrode G2 may be patterned. Here, the second gate electrode G2 may correspond to the gate electrode of the second thin film transistor TFT2 to be formed in the second area A2 . The second gate electrode G2 may be patterned to overlap the region R2c corresponding to the second channel portion CH2 of the second semiconductor layer ACT2 .

After the second gate electrode G2 is patterned, a conductive doping process may be performed.

When the conductive doping process is performed, among the three partial regions R1a, R1b, and R1c of the first semiconductor layer ACT1 , the first partial region R1a in which the first source connection part SC1 is to be formed and the first drain connection part The second partial region R1b in which DC1 is to be formed becomes conductive. Accordingly, the first partial region R1a of the first semiconductor layer ACT1 is formed as the first source connection part SC1 , and the second partial region R1b of the first semiconductor layer ACT1 is the first drain connection part (DC1) can be formed.

Also, when the conductive doping process is performed, among the three partial regions R2a, R2b, and R2c of the second semiconductor layer ACT2 , the first partial region R2a and the second region where the second source connection part SC2 is to be formed. The second partial region R2b in which the drain connection part DC2 is to be formed becomes a conductor. Accordingly, the first partial region R2a of the second semiconductor layer ACT2 is formed as the second source connection part SC2, and the second partial region R2b of the second semiconductor layer ACT2 is the second drain connection part. (DC2) can be formed.

Referring to FIG. 7 , after step S40 and at step S50 , an interlayer insulating layer ILD may be disposed while covering the second gate electrode G2 .

Thereafter, four contact holes passing through the interlayer insulating layer ILD, the second gate insulating layer GI2, and the first gate insulating layer GI1 are formed.

The four contact holes are contact holes for connecting the first source electrode S1 to the first source connection part SC1 of the first semiconductor layer ACT1, and the first drain electrode D1 is connected to the first semiconductor layer ACT1. a contact hole for connecting to the first drain connection part DC1 of A contact hole for connecting D2 to the second drain connection part DC2 of the second semiconductor layer ACT2 may be included.

A portion of each of the first source connection part SC1 and the first drain connection part DC1 of the first semiconductor layer ACT1 is exposed through the four contact holes, and the second source connection part ( ACT2 ) of the second semiconductor layer ACT2 is exposed. SC2) and a portion of each of the second drain connection part DC2 may be exposed.

After the four contact holes are formed, the first source electrode S1 and the first drain electrode D1 correspond to the first source connection part SC1 and the first drain connection part DC1 of the first semiconductor layer ACT1, respectively. They may be connected through contact holes. The second source electrode S2 and the second drain electrode D2 may be connected to each of the second source connection part SC2 and the second drain connection part DC2 of the second semiconductor layer ACT2 through corresponding contact holes.

After the above-described electrode connection, the passivation layer PAS may be disposed while covering the first source electrode S1 , the first drain electrode D1 , the second source electrode S2 , and the second drain electrode D2 . . Accordingly, the formation of the first thin film transistor TFT1 and the second thin film transistor TFT2 may be completed.

Since the first thin film transistor TFT1 and the second thin film transistor TFT2 are formed according to the above-described process procedure, the second channel portion CH2 of the second semiconductor layer ACT2 of the second thin film transistor TFT2 is The specific dopant doped in the second thin film transistor TFT2 is also doped into the second source connection part SC2 and the second drain connection part DC2 included in the second semiconductor layer ACT2 of the second thin film transistor TFT2, and the first thin film transistor TFT1 ), the first source connection part SC1 and the first drain connection part DC1 included in the first semiconductor layer ACT1 may be doped.

8 is another view of the first area A1 and the second area A2 in which the first thin film transistor TFT1 and the second thin film transistor TFT2 are formed in the thin film transistor array substrate according to embodiments of the present disclosure; It is a cross section.

Since the first gate insulating layer GI1 and the second gate insulating layer GI2 exist between the second gate electrode G2 and the second channel part CH2 in the second thin film transistor TFT2, the second thin film transistor ( The characteristics of TFT2) may change undesirably.

For example, whether or not current is conducted between the second drain electrode D2 and the second source electrode S2 is changed depending on the gate voltage applied to the second gate electrode G2, or the second drain electrode D2 and the second drain electrode D2 A gate voltage enabling current conduction between the two source electrodes S2 may be different.

To prevent this, the thickness Tb of the second gate insulating layer GI2 may be formed to be quite thin. To this end, for example, the second gate insulating layer GI2 may be formed through an atomic layer deposition (ALD) method in which a thin film is grown by injecting a raw material and a reactive gas crosswise.

According to the atomic layer deposition method, a thin film is grown in atomic units by reacting a raw material and a reactive gas, and the thin film thickness can be adjusted to a desired degree by repeating this.

As the second gate insulating layer GI2 is thinly formed, the thickness Tb of the second gate insulating layer GI2 may be smaller than the thickness Ta of the first gate insulating layer GI1 . For example, the thickness Tb of the second gate insulating layer GI2 may be about 30 Å (angstroms), and the thickness Ta of the first gate insulating layer GI1 is the thickness ( Tb) may be several times to several tens of times.

9 is a view for explaining a change in transistor characteristics according to a gate insulating structure (a heterogeneous gate insulating structure) and a change in transistor characteristics according to a heterogeneous channel characteristic (a specific dopant type) in a thin film transistor array substrate according to embodiments of the present disclosure; to be.

Referring to FIG. 9 , in the first thin film transistor TFT1 , the thickness of the gate insulating structure (GI structure) between the first channel part CH1 and the first gate electrode G1 in the first semiconductor layer ACT1 is the second 1 corresponds to the thickness Ta of the gate insulating layer GI1. In the second thin film transistor TFT2, the thickness of the gate insulating structure (GI structure) between the second channel part CH2 and the second gate electrode G2 in the second semiconductor layer ACT2 is the first gate insulating layer GI1 It corresponds to the sum of the thickness Ta and the thickness Tb of the second gate insulating layer GI2.

As described above, since the thickness of the gate insulating structure of the second thin film transistor TFT2 becomes thicker than that of the first thin film transistor TFT1 , the transistor characteristics of the second thin film transistor TFT2 may change.

For example, the amount of shift in the positive direction of the threshold voltage Vth of the second thin film transistor TFT2 may increase. In addition, the operating current level Current of the second thin film transistor TFT2 may decrease and the sub-threshold swing value SS may increase.

Accordingly, the second thin film transistor TFT2 may be suitable as a driving transistor for driving a light emitting element in each subpixel in the organic light emitting diode display. In contrast, the first thin film transistor TFT1 may be suitable for a switching transistor in each subpixel in the organic light emitting diode display.

Meanwhile, the second channel portion CH2 of the second semiconductor layer ACT2 of the second thin film transistor TFT2 is doped with a specific dopant. That is, the second semiconductor layer ACT2 of the second thin film transistor TFT2 includes a basic semiconductor material and a specific dopant.

For example, the specific dopant may include one or more of fluorine (F), nitrogen (N), yttrium (Y), and molybdenum (Mo).

Transistor characteristics of the second thin film transistor TFT2 may vary according to the type of a specific dopant doped in the second channel portion CH2 of the second semiconductor layer ACT2 of the second thin film transistor TFT2 .

For example, when a specific dopant doped in the second channel portion CH2 of the second semiconductor layer ACT2 of the second thin film transistor TFT2 includes yttrium (Y) or molybdenum (Mo), the second thin film The sub-threshold swing value SS of the transistor TFT2 may increase.

In other words, the sub-threshold swing value (SS) of the second thin film transistor (TFT2) is the sub-threshold swing value of the thin film transistor ( SS), the specific dopant doped in the second channel portion CH2 of the second semiconductor layer ACT2 of the second thin film transistor TFT2 may include yttrium (Y) or molybdenum (Mo).

In this case, the sub-threshold swing value SS of the second thin film transistor TFT2 may be greater than the sub-threshold swing value SS of the first thin film transistor TFT1 .

As another example, when the specific dopant doped in the second channel portion CH2 of the second semiconductor layer ACT2 of the second thin film transistor TFT2 includes fluorine (F) or nitrogen (N), the first 2 The sub-threshold swing value SS of the thin film transistor TFT2 may decrease.

In other words, the sub-threshold swing value SS of the second thin film transistor TFT2 is higher than the sub-threshold swing value of the thin film transistor having a semiconductor layer including a base semiconductor material undoped with specific dopants F and N. In the small case, certain dopants may include fluorine (F) or nitrogen (N).

In this case, the sub-threshold swing value SS of the second thin film transistor TFT2 may be greater or less than the sub-threshold swing value SS of the first thin film transistor TFT1, and may be similar to or equal to the sub-threshold swing value SS of the first thin film transistor TFT1 in some cases.

As another example, when the specific dopant doped in the second channel portion CH2 of the second semiconductor layer ACT2 of the second thin film transistor TFT2 includes fluorine (F) or nitrogen (N), The mobility or the operating current level of the second thin film transistor TFT2 may increase.

In other words, the mobility or operating current level of the second thin film transistor TFT2 is higher than the mobility or operating current level of the thin film transistor having a semiconductor layer including a base semiconductor material undoped with specific dopants (F, N). In larger cases, certain dopants may include fluorine (F) or nitrogen (N).

In this case, the mobility or operating current level of the second thin film transistor TFT2 may be smaller than or greater than the mobility or operating current level of the first thin film transistor TFT1 , and may be similar or the same in some cases.

As another example, when the specific dopant doped in the second channel portion CH2 of the second semiconductor layer ACT2 of the second thin film transistor TFT2 includes yttrium (Y) or molybdenum (Mo), the first 2 The mobility or the operating current level of the thin film transistor TFT2 may decrease.

In other words, the mobility or operating current level of the second thin film transistor TFT2 is higher than the mobility or operating current level of the thin film transistor having a semiconductor layer including a base semiconductor material undoped with specific dopants (Y, Mo). In the small case, the specific dopant may include yttrium (Y) or molybdenum (Mo).

In this case, the mobility or the operating current level of the second thin film transistor TFT2 may be smaller than the mobility or the operating current level of the first thin film transistor TFT1 .

As another example, when the specific dopant doped in the second channel portion CH2 of the second semiconductor layer ACT2 of the second thin film transistor TFT2 includes yttrium (Y) or molybdenum (Mo), Compared to a case in which a specific dopant doped in the second channel portion CH2 of the second semiconductor layer ACT2 of the second thin film transistor TFT2 includes fluorine (F) or nitrogen (N), the second thin film transistor The magnitude of the shift of the threshold voltage of (TFT2) in the positive direction may increase more.

Meanwhile, the thin film transistor array substrate according to embodiments of the present disclosure may be included in a display device including a plurality of subpixels. Each of the plurality of sub-pixels may include a light emitting device, a driving transistor supplying a driving current to the light emitting device, and a switching transistor controlling a voltage at a gate node of the driving transistor.

The second thin film transistor TFT2 may be a driving transistor that supplies a driving current to the light emitting device in the subpixel. The first thin film transistor TFT1 may be a switching transistor that transfers a voltage to the gate node of the driving transistor in the subpixel.

10 is a diagram illustrating a display device according to embodiments of the present disclosure, and FIG. 11 is a cross-sectional view illustrating a driving transistor (DRT) and a switching transistor (SWT) in each subpixel in the display device according to embodiments of the present disclosure to be.

Referring to FIG. 10 , a display device according to embodiments of the present disclosure may include a display panel 1010 , a data driving circuit 1020 , a gate driving circuit 1030 , and a controller 1040 .

The display panel 1010 includes a display area DA and a non-display area NDA that is an area outside the display area DA, and includes a plurality of data lines DL, a plurality of gate lines GL, and a plurality of Sub-pixels SP and the like may be disposed.

The data driving circuit 1020 may output data voltages VDATA to the plurality of data lines DL to drive the plurality of data lines DL.

The data driving circuit 1020 may be implemented as a tape carrier package (TCP) type, a chip on glass (COG) type, a chip on panel (COP) type, or a chip on film (COF) type. When the data driving circuit 1020 is implemented as a COG type or a COP type, the data driving circuit 1010 may be bonded to a pad portion formed in the non-display area NDA of the display panel 1010 . When the data driving circuit 1020 is implemented as a COF type, the data driving circuit 1010 is mounted on a circuit film, and a portion of the circuit film is formed on the pad portion formed in the non-display area NDA of the display panel 1010 . The sides can be bonded.

The gate driving circuit 1030 may output scan signals SCAN to the plurality of gate lines GL to drive the plurality of gate lines GL.

The gate driving circuit 1030 may implement a TCP type, a COG type, a COP type, a COF type, a GIP (Gate In Panel) type, or the like. When the gate driving circuit 1030 is implemented as a COG type or a COP type, the gate driving circuit 1030 may be bonded to a pad portion formed in the non-display area NDA of the display panel 1010 . When the gate driving circuit 1030 is implemented as a COF type, the gate driving circuit 1030 is mounted on a circuit film, and a portion of the circuit film is applied to the pad portion formed in the non-display area NDA of the display panel 1010 . The sides can be bonded. When the gate driving circuit 1030 is implemented as a GIP type, the gate driving circuit 1030 may be formed in a portion of the non-display area NDA of the display panel 1010 . When the gate driving circuit 1030 is implemented as a GIP type, the gate driving circuit 1030 may be formed together with other electrodes or wires in the display area DA during the manufacturing process of the display panel 1010 .

The controller 1040 may control the data driving circuit 1020 and the gate driving circuit 1030 . The controller 1040 may supply various data driving control signals DCS and image digital data Data for controlling the data driving timing to the data driving circuit 1020 . The data driving circuit 1020 converts the image digital data Data into a data voltage VDATA corresponding to an analog voltage, and converts the data voltage VDATA to the data line DL based on the data driving control signal DCS. can be printed out.

The controller 1040 may supply various signals required to generate various gate driving control signals GCS and scan signals SCAN for controlling gate driving timing to the gate driving circuit 1030 . The gate driving circuit 1030 may output the scan signal SCAN having the turn-on level gate voltage at a predetermined timing to the gate line GL based on the gate driving control signal DCS.

The display device according to embodiments of the present disclosure may be of various types, such as an organic light emitting diode (OLED) display, a quantum dot display, or a liquid crystal display (LCD). Referring to FIG. 10 , when the display device according to embodiments of the present disclosure is an organic light emitting diode (OLED) display device, each subpixel SP of the display panel 1010 includes a light emitting device ED and a driving transistor ( DRT), a switching transistor SWT, and a capacitor Cst.

The light emitting device ED may include a first electrode, a light emitting layer, and a second electrode. The emission layer may be disposed between the first electrode and the second electrode. The first electrode may be an anode electrode and the second electrode may be a cathode electrode. Conversely, the first electrode may be a cathode electrode and the second electrode may be an anode electrode. When the second electrode is a cathode electrode, a ground voltage VSS may be applied to the second electrode. For example, the base voltage VSS may be a ground voltage or a voltage similar to the ground voltage. For example, the light emitting device ED may be an organic light emitting diode (OLED), a light emitting diode (LED), or a quantum dot light emitting device.

The driving transistor DRT is a transistor for driving the light emitting device ED, and may control a current flowing into the light emitting device ED.

The driving transistor DRT may include a first node N1 , a second node N2 , and a third node N3 . The first node N1 of the driving transistor DRT may be a gate node and may be electrically connected to a source node or a drain node of the switching transistor SWT. The second node N2 of the driving transistor DRT may be electrically connected to the first electrode of the light emitting device ED, and may be a source node or a drain node. The third node N3 of the driving transistor DRT is a node to which the driving voltage VDD is applied, and may be electrically connected to the driving voltage line DVL supplying the driving voltage VDD, and may be a drain node or a source node. can be

The switching transistor SWT controls the connection between the first node N1 of the driving transistor DRT and the corresponding data line DL in response to the scan signal SCAN that is the gate signal supplied from the gate line GL. can

A drain node or a source node of the switching transistor SWT may be electrically connected to a corresponding data line DL. A source node or a drain node of the switching transistor SWT may be electrically connected to the first node N1 of the driving transistor DRT. A gate node of the switching transistor SWT may be electrically connected to the gate line GL to receive the scan signal SCAN.

The switching transistor SWT is turned on by the scan signal SCAN of the turn-on level voltage, and transmits the data signal Vdata supplied from the corresponding data line DL to the first node N1 of the driving transistor DRT. ) can be passed to

The switching transistor SWT is turned on by the scan signal SCAN of the turn-on level voltage, and is turned off by the scan signal SCAN of the turn-off level voltage. Here, when the switching transistor SWT is an n-type voltage, the turn-on level voltage may be a high level voltage, and the turn-off level voltage may be a low level voltage. When the switching transistor SWT is a p-type voltage, the turn-on level voltage may be a low-level voltage and the turn-off level voltage may be a high-level voltage.

The storage capacitor Cst may be electrically connected between the first node N1 and the second node N2 of the driving transistor DRT. The storage capacitor Cst may maintain the image data voltage Vdata corresponding to the image signal voltage or a voltage corresponding thereto for one frame time.

The storage capacitor Cst is not a parasitic capacitor (eg, Cgs or Cgd) which is an internal capacitor that exists between the first node N1 and the second node N2 of the driving transistor DRT. The storage capacitor Cst may be an external capacitor intentionally designed outside the driving transistor DRT.

Each of the driving transistor DRT and the switching transistor SWT may be an n-type transistor or a p-type transistor. Both the driving transistor DRT and the switching transistor SWT may be n-type transistors or p-type transistors. At least one of the driving transistor DRT and the switching transistor SWT may be an n-type transistor (or a p-type transistor), and the other may be a p-type transistor (or an n-type transistor).

The equivalent circuit of the sub-pixel SP illustrated in FIG. 10 is merely an example for description, and may further include one or more transistors or, in some cases, one or more capacitors. Alternatively, each of the plurality of sub-pixels SP may have the same structure, and some of the plurality of sub-pixels SP may have a different structure.

The display panel 1010 includes a thin film transistor array substrate, wherein the thin film transistor array substrate is a substrate SUB, a light emitting device ED disposed on the substrate SUB, and a driving device for supplying driving current to the light emitting device ED. The transistor DRT and the switching transistor SWT for controlling the voltage of the gate node of the driving transistor DRT may be included.

Referring to FIG. 11 , the switching transistor SWT may be the above-mentioned first thin film transistor TFT1 , and the driving transistor DRT may be the above-mentioned second thin film transistor TFT2 . Accordingly, the switching transistor SWT and the driving transistor DRT may have all structures and features corresponding to the first thin film transistor TFT1 and the second thin film transistor TFT2 . That is, all descriptions of the first thin film transistor TFT1 may be applied to the switching transistor SWT, and all descriptions of the second thin film transistor TFT2 may be applied to the driving transistor DRT. Hereinafter, the switching transistor SWT and the driving transistor DRT will be briefly described.

Referring to FIG. 11 , the switching transistor SWT may include a first semiconductor layer ACT1 , a first gate electrode G1 , a first source electrode S1 , and a first drain electrode D1 . The first semiconductor layer ACT1 includes a first channel part CH1 overlapping the first gate electrode G1 , a first source connection part SC1 positioned at one side of the first channel part CH1 , and a first channel A first drain connection part DC1 positioned on the other side of the part CH1 may be included.

Referring to FIG. 11 , the driving transistor DRT may include a second semiconductor layer ACT2 , a second gate electrode G2 , a second source electrode S2 , and a second drain electrode D2 . The second semiconductor layer ACT2 includes a second channel part CH2 overlapping the second gate electrode G2 , a second source connection part SC2 positioned at one side of the second channel part CH2 , and a second channel A second drain connection part DC2 positioned on the other side of the part CH2 may be included.

Referring to FIG. 11 , the distance L2 between the second semiconductor layer ACT2 and the second gate electrode G2 is the distance L1 between the first semiconductor layer ACT1 and the first gate electrode G1 . ) can be farther away.

Referring to FIG. 11 , the display panel 1010 includes a first gate insulating layer GI1 and a second semiconductor layer ACT2 and a second gate disposed between the first semiconductor layer ACT1 and the first gate electrode G1. A second gate insulating layer GI2 disposed between the electrodes G2 may be further included.

Referring to FIG. 11 , the first gate insulating layer GI1 extends from the first region A1 in which the switching transistor SWT is disposed to the second region A2 in which the driving transistor DRT is disposed to form a second semiconductor layer. It may be interposed between the ACT2 and the second gate insulating layer GI2. The second gate insulating layer GI2 may extend from the second area A2 to the first area A1 and be disposed on the first gate electrode G1 .

Referring to FIG. 11 , the second channel part CH2 of the second semiconductor layer ACT2 may be doped with an undoped specific dopant in the first channel part CH1 of the first semiconductor layer ACT1 .

A specific dopant doped into the second channel part CH2 included in the second semiconductor layer ACT2 of the driving transistor DRT is a second source connection part included in the second semiconductor layer ACT2 of the driving transistor DRT. (SC2) and the second drain connection part DC2 are doped, and the first source connection part SC1 and the first drain connection part DC1 included in the first semiconductor layer ACT1 of the switching transistor SWT are doped. there may be

The driving transistor DRT may have a larger sub-threshold swing value than the switching transistor SWT. The driving transistor DRT may have a lower mobility or a lower current level than the switching transistor SWT. A magnitude in which the threshold voltage of the driving transistor DRT is shifted in the positive direction may be greater than a magnitude in which the threshold voltage of the switching transistor SWT is shifted in the positive direction.

According to the above-described embodiments of the present disclosure, it is possible to provide a thin film transistor array substrate and a display device in which thin film transistors having different functions or uses have their own unique transistor characteristics.

According to embodiments of the present disclosure, it is possible to provide a thin film transistor array substrate and a display device including thin film transistors having different channel characteristics so that the thin film transistors can have different transistor characteristics.

According to embodiments of the present disclosure, it is possible to provide a thin film transistor array substrate and a display device including thin film transistors having different gate insulating structures so that the thin film transistors have different transistor characteristics.

According to the embodiments of the present disclosure, heterogeneous channel characteristics and heterogeneous gate insulation structures between thin film transistors that allow thin film transistors to have different transistor characteristics may be implemented through a simple manufacturing process method.

The above description is merely illustrative of the technical spirit of the present disclosure, and various modifications and variations will be possible without departing from the essential characteristics of the present disclosure by those of ordinary skill in the art to which the present disclosure pertains. In addition, since the embodiments disclosed in the present disclosure are for explanation rather than limiting the technical spirit of the present disclosure, the scope of the technical spirit of the present disclosure is not limited by these embodiments. The protection scope of the present disclosure should be construed by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present disclosure.

A1, A2: first area, second area
TFT1, TFT2: first thin film transistor, second thin film transistor
S1, G1, D1: first source electrode, first gate electrode, first drain electrode
S2, G2, D2: second source electrode, second gate electrode, second drain electrode
ACT1, ACT2: first semiconductor layer, second semiconductor layer
SC1, CH1, DC1: first source connection part, first channel part, first drain connection part
SC2, CH2, DC2: second source connection part, second channel part, second drain connection part
SUB: Substrate
GI1, GI2: first gate insulating film, second gate insulating film
ILD: interlayer insulating film
PAS: passivation layer
BUF: buffer layer

Claims (20)

Board;
a first thin film transistor disposed in a first region of the substrate and including a first semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode;
a second thin film transistor disposed in a second region of the substrate different from the first region and including a second semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode;
a first gate insulating layer disposed between the first semiconductor layer and the first gate electrode; and
a second gate insulating layer disposed between the second semiconductor layer and the second gate electrode;
The first semiconductor layer includes a first channel part overlapping the first gate electrode, a first source connection part positioned on one side of the first channel part, and a first drain connection part positioned on the other side of the first channel part. do,
The second semiconductor layer includes a second channel part overlapping the second gate electrode, a second source connection part positioned on one side of the second channel part, and a second drain connection part positioned on the other side of the second channel part. do,
the first gate insulating layer extends from the first region to the second region and is interposed between the second semiconductor layer and the second gate insulating layer;
the second gate insulating layer extends from the second region to the first region and is disposed on the first gate electrode;
A thin film transistor array substrate in which the second channel portion of the second semiconductor layer is doped with an undoped specific dopant in the first channel portion of the first semiconductor layer.
According to claim 1,
a distance between the second channel part doped with the specific dopant and the second gate electrode;
A thin film transistor array substrate having a greater distance between the first channel portion and the first gate electrode undoped with the specific dopant.
According to claim 1,
and an interlayer insulating layer disposed on the second gate insulating layer while covering the second gate electrode, wherein the first source electrode, the first drain electrode, the second source electrode, and the second drain electrode include the interlayer located on the insulating film,
The first source electrode is in electrical contact with the first source connection part through a first source contact hole penetrating the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer, and the first drain electrode is , in electrical contact with the first drain connection part through a first drain contact hole penetrating the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer,
The second source electrode is in electrical contact with the second source connection part through a second source contact hole penetrating the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer, and the second drain electrode is , A thin film transistor array substrate in electrical contact with the second drain connection part through a second drain contact hole penetrating the interlayer insulating layer, the second gate insulating layer, and the first gate insulating layer.
According to claim 1,
The specific dopant doped in the second channel portion of the second semiconductor layer,
The second source connection part and the second drain connection part included in the second semiconductor layer are doped,
The thin film transistor array substrate in which the first source connection part and the first drain connection part included in the first semiconductor layer are doped.
According to claim 1,
A thickness of the second gate insulating layer is thinner than a thickness of the first gate insulating layer.
According to claim 1,
wherein the second thin film transistor has a larger subthreshold swing value than that of the first thin film transistor.
According to claim 1,
The second thin film transistor is a thin film transistor array substrate having a lower mobility than the first thin film transistor.
According to claim 1,
A thin film transistor array substrate in which the threshold voltage of the second thin film transistor shifted in the positive direction is greater than the threshold voltage of the first thin film transistor shifted in the positive direction.
According to claim 1,
The specific dopant comprises at least one of fluorine, nitrogen, yttrium and molybdenum.
10. The method of claim 9,
the second semiconductor layer comprises a base semiconductor material and the specific dopant;
When the sub-threshold swing value of the second thin film transistor is greater than the sub-threshold swing value of the thin film transistor which is undoped with the specific dopant and has a semiconductor layer including the basic semiconductor material,
The specific dopant is a thin film transistor array substrate including yttrium or molybdenum.
10. The method of claim 9,
the second semiconductor layer comprises a base semiconductor material and the specific dopant;
When the sub-threshold swing value of the second thin film transistor is less than the sub-threshold swing value of the thin film transistor which is undoped with the specific dopant and has a semiconductor layer including the basic semiconductor material,
The specific dopant is a thin film transistor array substrate containing fluorine or nitrogen.
10. The method of claim 9,
the second semiconductor layer comprises a base semiconductor material and the specific dopant;
When the mobility of the second thin film transistor is greater than the mobility of the thin film transistor which is undoped with the specific dopant and has a semiconductor layer including the basic semiconductor material,
The specific dopant is a thin film transistor array substrate containing fluorine or nitrogen.
10. The method of claim 9,
the second semiconductor layer comprises a base semiconductor material and the specific dopant;
When the mobility of the second thin film transistor is less than the mobility of the thin film transistor which is undoped with the specific dopant and has a semiconductor layer including the basic semiconductor material,
The specific dopant is a thin film transistor array substrate including yttrium or molybdenum.
10. The method of claim 9,
When the specific dopant doped in the second channel includes yttrium or molybdenum, the threshold voltage of the second thin film transistor is positive compared to when the specific dopant doped in the second channel includes fluorine or nitrogen. A thin film transistor array substrate that increases in size shifted to
Board;
a light emitting device disposed on the substrate;
a driving transistor supplying a driving current to the light emitting device; and
A switching transistor for controlling the voltage of the gate node of the driving transistor,
The switching transistor may include a first semiconductor layer, a first gate electrode, a first source electrode, and a first drain electrode, wherein the first semiconductor layer includes a first channel portion overlapping the first gate electrode, and the first A first source connection part positioned on one side of the channel part and a first drain connection part positioned on the other side of the first channel part,
The driving transistor includes a second semiconductor layer, a second gate electrode, a second source electrode, and a second drain electrode, wherein the second semiconductor layer includes a second channel portion overlapping the second gate electrode and the second channel a second source connection part located on one side of the part and a second drain connection part located on the other side of the second channel part;
a distance from which the second semiconductor layer is separated from the second gate electrode is greater than a distance from which the first semiconductor layer is separated from the first gate electrode;
The second channel portion of the second semiconductor layer is doped with an undoped specific dopant into the first channel portion of the first semiconductor layer.
16. The method of claim 15,
a first gate insulating layer disposed between the first semiconductor layer and the first gate electrode; and
Further comprising a second gate insulating film disposed between the second semiconductor layer and the second gate electrode,
The first gate insulating layer extends from the first region in which the switching transistor is disposed to the second region in which the driving transistor is disposed and is interposed between the second semiconductor layer and the second gate insulating layer;
The second gate insulating layer extends from the second region to the first region and is disposed on the first gate electrode.
16. The method of claim 15,
The specific dopant doped into the second channel portion included in the second semiconductor layer of the driving transistor may include:
The second source connection part and the second drain connection part included in the second semiconductor layer of the driving transistor are doped,
The display device is doped with the first source connection part and the first drain connection part included in the first semiconductor layer of the switching transistor.
16. The method of claim 15,
The driving transistor has a larger subthreshold swing value than that of the switching transistor.
16. The method of claim 15,
The driving transistor has a lower mobility than the switching transistor.
16. The method of claim 15,
A magnitude in which the threshold voltage of the driving transistor is shifted in the positive direction is greater than a magnitude in which the threshold voltage of the switching transistor is shifted in the positive direction.

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