KR20210157858A - Semiconductor device with contact structure - Google Patents

Abstract

A semiconductor process system etches a thin film on a semiconductor wafer. The semiconductor process system comprises a machine learning-based analysis model. The analysis model dynamically selects a process condition for an etch process by receiving a static process condition and target thin film data. The analysis model identifies dynamic process condition data that obtains predicted residual film data consistent with target thin film data along with static process condition data. The process system then uses the static and dynamic process condition data for the next etch process.

Description

A semiconductor device having a contact structure

technical field

The present disclosure relates to the field of semiconductor manufacturing. The present disclosure relates more particularly to etching processes for semiconductor fabrication.

Description of related technology

There has been a continuous demand for increasing the computing performance of electronic devices, including smart phones, tablets, desktop computers, laptop computers, and many other types of electronic devices. Integrated circuits provide computing power to these electronic devices. One way to improve computing performance in integrated circuits is to increase the number of transistors and other integrated circuit features that can be included in a given area of a semiconductor substrate.

To continue reducing the size of features in integrated circuits, various thin film deposition techniques, etching techniques and other processing techniques are implemented. These techniques can form very small features. However, these techniques also face serious difficulties in ensuring that the features are properly formed.

1A-1R are cross-sectional views of an integrated circuit at various stages of processing in accordance with one embodiment.
2A is an enlarged cross-sectional view of a source/drain contact plug of an integrated circuit according to one embodiment;
2B is an enlarged cross-sectional view of a source/drain contact plug of an integrated circuit according to one embodiment.
3A is an enlarged cross-sectional view of a gate contact plug of an integrated circuit according to one embodiment.
3B is an enlarged cross-sectional view of a gate contact plug of an integrated circuit according to one embodiment.
4A is an enlarged cross-sectional view of a source/drain contact plug of an integrated circuit according to an embodiment.
4B is an enlarged cross-sectional view of a source/drain contact plug of an integrated circuit according to one embodiment.
5A is an enlarged cross-sectional view of a gate contact plug of an integrated circuit according to one embodiment.
5B is an enlarged cross-sectional view of a gate contact plug of an integrated circuit according to one embodiment.
6A is an illustration of a semiconductor process system in accordance with one embodiment.
6B is a graph illustrating fluid flow during a cycle of an atomic layer etch process.
7 is a block diagram of a control system of a semiconductor process system.
8A is a flow diagram of a process for training an analytical model of a control system according to an embodiment.
8B is a block diagram of an analysis model according to an exemplary embodiment.
9 is a flowchart of a process for performing a thin film deposition process with an analytical model according to an embodiment.

In the following description, many thicknesses and materials are described for various layers and structures within an integrated circuit die. Specific dimensions and materials for various embodiments are provided as examples. Those of ordinary skill in the art, in light of this disclosure, will recognize that other dimensions and materials may be used in many cases without departing from the scope of the disclosure.

The following disclosure provides a number of different embodiments or examples for implementation of various different features of the described subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. These are, of course, merely several examples and are not intended to be limiting. For example, the formation of a first feature on a second feature in the description that follows may include embodiments in which the first and second features are formed in direct contact and the first and second features may not be in direct contact. Embodiments may also include embodiments in which additional features may be formed between the first and second features. Additionally, this disclosure may repeat reference numbers and/or letters in the various instances. These repetitions are for the sake of simplicity and clarity and do not in themselves indicate a relationship between the various embodiments and/or configurations being discussed.

In addition, spatial relational terms such as "below" (eg, beneath, below, lower), "above" (eg, above, upper) are used herein to refer to other element(s) or feature(s) as exemplified in the drawings. It may be used for ease of description that describes the relationship of one element or feature to one another. Spatial relational terms are intended to include other orientations of the device in use or in operation in addition to the orientations represented in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatial relation descriptors used herein may be similarly interpreted accordingly.

In the following description, certain specific details are set forth in order to provide a thorough understanding of various embodiments of the present disclosure. However, it will be understood by those skilled in the art that the present disclosure may be practiced without these specific details. In other instances, well-known structures associated with electronic components and manufacturing techniques have not been described in detail to avoid unnecessarily obscuring the description of embodiments of the present disclosure.

Unless the context requires otherwise, throughout the following specification and claims, the words "comprises" and variations thereof, such as "comprises" and "comprising," have an open and inclusive meaning, i.e., "including but not limited to should be construed as "unlimited".

The use of ordinal numbers such as 1st, 2nd and 3rd does not necessarily imply rank meaning, but rather can only distinguish between several instances of an operation or structure.

Reference throughout this specification to “one embodiment” or “an embodiment” means that a particular feature, structure, or characteristic described in connection with the embodiment is included in at least one embodiment. Thus, the appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily all referring to the same embodiment. Moreover, a particular feature, structure, or characteristic may be combined in any suitable manner in one or more embodiments.

As used in this specification and the appended claims, the singular and the singular include plural referents unless the content clearly dictates otherwise. It should also be understood that the term "or" is generally used in its sense including "and/or", unless the context dictates otherwise.

Embodiments of the present disclosure provide thin films of reliable thickness and composition. Embodiments of the present disclosure use machine learning techniques to tune thin film etch process parameters between or even during etch processes. Embodiments of the present disclosure use machine learning techniques to train an analytical model to determine process parameters that should be implemented for the next thin film etch process or even the next step of the current thin film etch process. As a result, the thin film etch process produces a thin film with a residual thickness and composition that reliably meets target specifications. An integrated circuit including the thin film does not have performance problems that may occur if the thin film is not properly formed. Moreover, batches of semiconductor wafers improve yield and reduce wafer scrap.

1A is a cross-sectional view of an integrated circuit 100 according to one embodiment. The integrated circuit 100 includes a semiconductor substrate 102 . The semiconductor substrate 102 may include one or more of silicon, germanium, silicon germanium, gallium arsenide, silicon carbide, or other types of semiconductors. The semiconductor substrate 102 may include a single crystal semiconductor. The semiconductor substrate 102 may include multiple structures of different single crystal semiconductor materials. Other materials may be used for the semiconductor substrate 102 without departing from the scope of the present disclosure.

The semiconductor substrate 102 may include various doped regions. The doped regions may include N-wells, P-wells, source and drain regions, channel regions, anti-punch through regions, and other types of doped regions. The doped region may be formed by an ion implantation process, a diffusion process, or another type of doping process. The dopant may include an N-type dopant and a P-type dopant. Various doped regions may be used to form a transistor with the semiconductor substrate 102 .

In one embodiment, the semiconductor substrate 102 includes a plurality of semiconductor nanosheets or nanowires. The semiconductor nanosheet can be part of a gate-all-around transistor. Each nanosheet may be covered with one or more gate dielectric materials. One or more gate dielectric materials may be coated over the metal gate material. In one example, the nanosheet includes silicon or silicon germanium. The nanosheet may be formed of alternating layers of silicon and silicon germanium. Other types of materials and structures may be included in the semiconductor layer 102 without departing from the scope of the present invention.

The integrated circuit 100 includes a shallow trench isolation 104 . Shallow trench isolation 104 may be used to isolate groups of transistor structures formed with semiconductor substrate 102 . Shallow trench isolation 104 may include a dielectric material. The dielectric material for the shallow trench isolation 104 is silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-, formed by LPCVD (low pressure chemical vapor deposition), plasma enhanced CVD or flowable CVD. doped silicate glass (FSG) or low-k dielectric material. Other materials and structures may be used for the shallow trench isolation 104 without departing from the scope of the present disclosure.

The integrated circuit 100 includes a shallow trench isolation 104 and an interlayer dielectric layer 106 positioned over a substrate 102 . The interlayer dielectric layer 106 may include one or more of silicon oxide, silicon nitride, SiCOH, SiOC, or an organic polymer. Other types of dielectric materials may be used for the interlayer dielectric layer 106 without departing from the scope of the present disclosure.

The integrated circuit 100 includes an interlayer dielectric layer 108 positioned over an interlayer dielectric layer 106 . The interlayer dielectric layer 108 may include one or more of silicon oxide, silicon nitride, SICOH, SiOC, or an organic polymer. Other types of dielectric materials may be used for the interlayer dielectric layer 108 without departing from the scope of the present disclosure.

The integrated circuit 100 includes a metal gate 114 . The metal gate 114 may correspond to a gate electrode of a transistor formed with the semiconductor substrate 102 . In one example, the metal gate 114 is a metal gate of a gate-all-around transistor. In this case, the metal gate 114 may cover the semiconductor nanosheet as described above. The semiconductor nanosheets may be covered with one or more layers of dielectric material corresponding to the gate dielectric, which layers are in turn covered by the metal gate 114 . The nanosheet corresponds to the channel region of the gate-all-around transistor.

Metal gate 114 includes one or more layers of conductive material. Conductive materials may include polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloy or other type of conductive material. It may include one or more of the materials. Other materials may be used for the metal gate without departing from the scope of the present disclosure.

The metal gate 114 may be covered by sidewall spacers 116 . The sidewall spacers 116 may include a plurality of layers of dielectric material. The plurality of layers of dielectric material may include silicon nitride, SiON, SiOCN, SiCN, silicon oxide, or other dielectric material. Other dielectric materials may be used for the sidewall spacers 116 without departing from the scope of the present disclosure.

Integrated circuit 100 includes source and drain regions 110 which are epitaxial layers in the illustrated embodiment. Source and drain epitaxial layers 110 are formed epitaxially from substrate 102 . In the example of an N-channel transistor, the source and drain epitaxial layer 110 may include one or more of Si, SiP, and SiC in the example of SiCP. In the example of a P-channel transistor, the source and drain epitaxial regions 110 may include Si, Ge, or SiGe. The source and drain epitaxial regions 110 may be doped with various N-type and P-type dopants. Other materials and structures may be used for the source and drain epitaxial region 110 without departing from the scope of the present disclosure. Source and drain region epitaxial layer 110 and metal gate 114 are the terminals of transistor 103 .

The integrated circuit 100 includes trenches 120 , 121 formed in an interlayer dielectric layer 108 . Trench 120 extends to one of source and drain epitaxial regions 110 . Trench 121 extends to metal gate 114 . A dielectric material layer 122 covers the top surface of the interlayer dielectric layer 108 , the sidewalls of the trenches 120 , 121 and the top of the exposed source and drain epitaxial regions 110 and the metal gate 114 . In one example, the dielectric material layer includes silicon nitride, although other materials may be used without departing from the scope of the present disclosure.

1B is a cross-sectional view of an integrated circuit die 100 at an intermediate stage of processing in accordance with one embodiment. In FIG. 1B , a silicide layer 126 is formed over the source/drain epitaxial region 110 . In FIG. 1B , a titanium nitride layer 124 is deposited on the top surface of the interlayer dielectric layer 108 , the sidewalls 119 of the trenches 120 , 121 , the metal gate 114 , and the source/drain epitaxial region 110 . is formed The titanium nitride layer 124 may be formed by depositing a titanium layer on the nitride layer 122 of FIG. 1A . The titanium layer may be deposited by physical vapor deposition (PVD), CVD, or other suitable deposition process. After the titanium layer is deposited, the titanium nitride layer 124 is formed by nitridation of the titanium layer. Nitriding may be performed by flowing _{NH 3} to titanium at a temperature of 350 °C to 450 °C. This may allow nitrogen to be adsorbed to the titanium. As a result, a titanium nitride layer 124 is formed. Titanium nitride layer 124 is a barrier layer that inhibits diffusion of impurities from the metal plug in the trench to other layers and structures.

After the titanium nitride layer 124 is formed, silicide 126 is formed at the interface between the source/drain epitaxial region 110 and the titanium nitride layer 124 . The silicide 126 is TiSi _x (TiSi, TiSi _{2 ,} etc.), where “x” represents the number of silicon atoms for each titanium atom. The silicide 126 is thermally annealed after the titanium nitride layer 124 is deposited. It is formed by performing thermal annealing to produce _{TiSi x .}

In one embodiment, prior to deposition of the titanium layer, a pre-clean operation may be performed. A pre-clean operation may remove native oxides or other unwanted materials prior to deposition of titanium.

1C is a cross-sectional view of the integrated circuit 100 at an intermediate stage of processing according to one embodiment. A bottom anti-reflective coating 128 is deposited in the trenches 120 , 121 on the silicon nitride layer 124 . A bottom anti-reflective coating 128 is initially deposited in the trenches 120 , 121 on the titanium nitride layer 124 over the interlayer dielectric layer 108 . After deposition of the bottom anti-reflective coating 128 , a timed etch is performed to remove the bottom anti-reflective coating 128 from the top of the titanium nitride layer 124 over the interlayer dielectric layer 108 . An underlying anti-reflective coating 128 remains in the trenches 120 , 121 . The bottom anti-reflective coating 128 does not completely fill the trenches 120 , 121 . The bottom anti-reflective coating 128 may include an organic material or an inorganic material. In one example, the bottom anti-reflective coating 128 is formed of tetramethyl ammonium hydroxide, although other materials may be used without departing from the scope of the present disclosure.

1D is a cross-sectional view of the integrated circuit 100 at an intermediate stage of processing according to one embodiment. The titanium nitride layer 124 has been removed from the top of the interlayer dielectric layer 108 . The titanium nitride layer 124 may be removed by wet etching. Alternatively, other etching processes may be applied to remove the titanium nitride.

1E is a cross-sectional view of an integrated circuit 100 at an intermediate stage of processing according to one embodiment. 1D, the bottom anti-reflective coating 128 has been removed. The bottom anti-reflective coating 128 may be removed by performing an etching process. In one example, the etching process includes a plasma ash process in the presence of _{O 2 .} Other etching processes may be applied without departing from the scope of the present disclosure.

1F is a cross-sectional view of the integrated circuit 100 at an intermediate stage of processing according to one embodiment. In FIG. 1F , titanium nitride layer 124 has been etched away mostly from sidewalls 119 of trenches 120 and 121 . A portion of the titanium nitride layer 124 remains in contact with the sidewalls 119 of the bottom of the trenches 120 and 121 . A titanium nitride layer 124 remains on the silicide 126 and the metal gate 114 .

In one embodiment, an atomic layer etching (ALE) process is applied to etch the titanium nitride layer 124 to form the structure illustrated in FIG. 1F . The ALE process is similar to the atomic layer deposition process (ALD). In an ALE process, various gases, fluids or materials are introduced into the process chamber for a selected period of time. Each cycle of the ALE process involves flowing different materials in different stages. An atomic or molecular layer of titanium nitride layer 124 may be removed from each cycle.

In one example, the ALE cycle includes flowing _{WCl 5} into the process chamber for a selected time of, for example, 1 second to 10 seconds. The ALE cycle then includes a purge step, for example, flowing argon gas into the process chamber for 1-6 seconds. The ALE cycle then includes flowing _{O 2} into the process chamber for a selected time period of, for example, 1-10 seconds. The ALE cycle then includes a second purge step of flowing argon gas into the process chamber for a selected time period of, for example, 2-15 seconds. An atomic or molecular layer of titanium nitride layer 124 is removed from each cycle. By controlling the number of cycles of the ALE process, it is possible to strictly control the etching amount of the titanium nitride layer 124 . Other ALE processes, cycles, times, and materials may be used without departing from the scope of the present disclosure.

As described in more detail below, a machine learning process is applied to dynamically select parameters for the ALE process. The machine learning process trains the analytic model to dynamically select parameters for each ALE process. The analytical model may select the material, flow duration, flow pressure, temperature, and other parameters associated with the ALE process to remove the desired amount of titanium nitride layer 124 .

1G is a cross-sectional view of the integrated circuit 100 at an intermediate stage of processing according to one embodiment. In FIG. 1G , a titanium nitride layer 130 is deposited over the sidewalls 119 of the trenches 120 , 121 and the interlayer dielectric layer 108 . The titanium nitride layer 130 may be a barrier layer. The titanium nitride layer 130 may be formed by an ALD process. The ALD process deposits the titanium nitride layer 130 to the desired thickness in a highly controlled manner. In particular, the thickness of the titanium nitride layer 130 may be adjusted based on the number of ALD cycles used in the deposition process. Titanium nitride layer 130 may be deposited using other deposition processes without departing from the scope of the present disclosure. Titanium nitride layer 130 is in contact with titanium nitride layer 124 . The titanium nitride layer 130 is formed by nitridation of the titanium layer as described above with respect to FIG. 1B , whereas the titanium nitride layer 130 is formed by an atomic layer deposition process. It is different from the titanium nitride layer 124 . Both the titanium nitride layer 130 and the titanium nitride layer 124 abut the sidewalls 119 of the trenches 120 and 121 . Titanium nitride layer 130 has a vertical height in trenches 120 , 121 that is higher than a vertical extent of the remainder of titanium nitride layer 124 . In one embodiment, a pre-clean process is performed prior to forming the titanium nitride layer 130 .

In FIG. 1G , a cobalt seed layer 132 is formed on the titanium nitride layer 124 . The cobalt seed layer 132 may be formed by a PVD process. The cobalt seed layer 132 is very thin, for example less than 6 nm thick. Other deposition processes and thicknesses for the cobalt seed layer 132 may be applied without departing from the scope of the present disclosure.

1H is a cross-sectional view of the integrated circuit 100 at an intermediate stage of processing according to one embodiment. In FIG. 1H , a cobalt layer 134 dl is deposited on the seed layer 132 . In particular, the seed layer 132 is used to grow the cobalt layer 134 . A cobalt layer 134 fills the trenches 120 and 121 . In one example, the cobalt layer 134 is deposited by an electroless cobalt plating process. The electroless cobalt plating process grows the cobalt layer 134 from the seed layer 130 . The seed layer 130 is not referenced in FIG. 1H because it is covered by the copper layer 134 . Other processes may be applied to the deposition of the cobalt layer 134 without departing from the scope of the present disclosure.

1I is a cross-sectional view of the integrated circuit 100 at an intermediate processing stage according to one embodiment. In FIG. 1I , a chemical mechanical planarization process (CMP) was performed. The CMP process removes the cobalt layer 134 and the titanium nitride layer 130 from the top of the interlayer dielectric layer 108 . The CMP process also removes a portion of the interlayer dielectric layer 108 . A cobalt plug 136 was formed in the trenches 120 and 121 by this process. A cobalt plug 136 is positioned on the titanium nitride layer 124 and the titanium nitride layer 130 . Other processes may be used to form the cobalt plug 136 without departing from the scope of the present disclosure.

1J is a cross-sectional view of the integrated circuit 100 at an intermediate stage of processing according to one embodiment. In FIG. 1J , an MCESL layer 140 was deposited over the interlayer dielectric layer 108 and the cobalt plug 136 . In one example, the MCESL layer 140 has a thickness of 100 Angstroms to 140 Angstroms. The MCESL layer may be formed by physical vapor deposition, chemical vapor deposition, atomic layer deposition, or other suitable deposition process. Other processes and thicknesses may be applied to the MCESL layer 140 without departing from the scope of the present disclosure.

A titanium nitride layer 142 was deposited on the MCESL layer 140 . Titanium nitride layer 142 has a thickness of 40 Angstroms to 80 Angstroms. The titanium nitride layer 142 may be a high resistance titanium nitride layer formed by a PVD process. Other processes and thicknesses may be applied to the titanium nitride layer 142 without departing from the scope of the present disclosure.

An MCESL layer 144 was deposited on the titanium nitride layer 142 . In one example, the MCESL layer 144 has a thickness of 70 Angstroms to 110 Angstroms. The MCESL layer 144 may be formed by a PVD process, a CVD process, an ALD process, or other suitable deposition process. Other processes and thicknesses may be applied to the MCESL layer 144 without departing from the scope of the present disclosure.

1K is a cross-sectional view of the integrated circuit 100 at an intermediate stage of processing according to one embodiment. In FIG. 1K , a photolithography process is applied to pattern the edges of the titanium nitride layer 142 and the MCESL layer 144 . Accordingly, a portion of the MCESL layer 140 is exposed. The photolithography process may include depositing and patterning photoresist and performing wet etching, dry etching, or other types of etching.

11 is a cross-sectional view of an integrated circuit 100 at an intermediate stage of processing according to one embodiment. 11 , the MCESL layer 144 is again deposited. Specifically, an additional 80-120 Angstroms of MCESL was deposited on the layer 144 . Additionally, an interlayer dielectric layer 146 was deposited. Interlayer dielectric layer 146 may include silicon oxide. Interlayer dielectric layer 146 may be deposited by CVD, PVD, or other suitable deposition process. Other materials and processes may be applied to the interstitial dielectric layer 146 without departing from the scope of the present disclosure.

1M is a cross-sectional view of an integrated circuit 100 at an intermediate stage of processing according to one embodiment. In FIG. 1M , trenches 148 , 150 , 152 are opened in MCESL layer 144 , interlayer dielectric layer 146 and MCESL layer 140 to expose titanium nitride layer 142 and cobalt plug 136 . The trench may be formed by wet etching, dry etching, or other types of etching.

1N is a cross-sectional view of the integrated circuit 100 at an intermediate stage of processing according to one embodiment. In FIG. 1N , a portion of the cobalt plug 136 was removed through wet etching.

1O is a cross-sectional view of an integrated circuit 100 at an intermediate stage of processing according to one embodiment. In FIG. 1O , a cap 154 was formed over the exposed portion of the exposed cobalt plug 136 and the titanium nitride layer 142 . The cap 154 may include tungsten and may be formed by bottom-up deposition. Other materials and deposition processes may be applied to the cap 154 without departing from the scope of the present disclosure.

1P is a cross-sectional view of an integrated circuit 100 at an intermediate stage of processing according to one embodiment. In FIG. 1P , a conductive plug 156 has been formed in the trenches 148 , 150 , 152 to contact the cap 154 . The conductive plug 156 is electrically connected to the plug 136 and the titanium nitride layer 142 . The conductive plug 156 may include ruthenium and may be formed by a bottom-up external deposition process. Other materials and deposition processes may be applied for the plug 156 . A CMP process may be performed to planarize the top of the plug 156 , the layer 144 , and the interlayer dielectric layer 146 without departing from the scope of the present disclosure.

1Q is a cross-sectional view of the integrated circuit 100 at an intermediate stage of processing according to one embodiment. In FIG. 1Q , an aluminum oxide layer 160 and a low-k dielectric layer 162 were deposited. The low-k dielectric layer 162 may include porous silicon oxide, organosilicate glass, or other type of low-k dielectric. Materials other than those described above may be used without departing from the scope of the present disclosure.

Aluminum oxide layer 160 and low-k dielectric layer 162 were patterned and etched to form trenches 164 , 166 , 168 exposing conductive plug 156 . The trenches 164 , 166 , 168 may be formed using standard photolithography and etching techniques including patterning of photoresist and performing wet or dry etching.

1R is a cross-sectional view of an integrated circuit 100 according to one embodiment. In FIG. 1R , copper plugs 170 have been formed in trenches 164 , 166 , and 168 . Copper plug 170 may be formed by depositing copper seed layer 172 using physical vapor deposition or other suitable process. After the copper seed layer 172 is formed, the copper plug 170 may be formed by an electroless copper plating process. After the copper plug 170 is formed, a CMP process may be performed. Other processes and materials may be used without departing from the scope of the present disclosure.

2A is an enlarged cross-sectional view (along line 2A-2A of FIG. 1R ) of the integrated circuit 100 of FIGS. 1A-1R according to one embodiment. The view of FIG. 2A focuses on the region of the cobalt plug 136 in contact with the source/drain epitaxial region 110 . The diagram of FIG. 2A illustrates a portion 174 of a titanium layer deposited as part of a process of forming a titanium nitride layer 124 via nitridation. A portion 174 of the titanium layer is placed in contact with the silicide layer 126 . A titanium nitride layer 124 formed by nitriding as described above is located on the titanium layer 174 and contacts a lower portion of the sidewall 119 of the trench 120 formed in the interlayer dielectric layer 108 . As described above, the titanium nitride layer 130 formed by the ALD process is located on the titanium nitride layer 124 and is in contact with an upper portion of the sidewall 119 of the trench 120 .

The structure of Figure 2a has the advantage of providing low current leakage. Due to the extra buffer provided by the titanium nitride layer 124 in contact with the lower portion of the sidewall 119 of the trench 120, the structure can be formed by precisely controlling the ALE process described above. In particular, the ALE process may be performed in a manner that ensures that a portion of the titanium nitride layer 124 remains on the sidewalls 119 of the trench 120 .

2B is an enlarged cross-sectional view (along line 2A-2A of FIG. 1R) of the integrated circuit 100 of FIGS. 1A-1R according to another embodiment. In the embodiment of FIG. 2B , the ALE process was carefully controlled so that the titanium nitride layer 124 does not remain on the sidewalls 119 of the trench 120 . Thus provided the advantage of providing a low ohmic contact to the source/drain epitaxial region 110 .

3A is an enlarged cross-sectional view (along line 3A-3A of FIG. 1R ) of the integrated circuit 100 of FIGS. 1A-1R in accordance with one embodiment. The view of FIG. 3A focuses on the cobalt plug 136 in contact with the metal gate 114 . 3A illustrates a portion 176 of a titanium layer deposited as part of a process for forming a titanium nitride layer 120 via nitridation. A portion 176 of the titanium layer is placed in contact with the metal gate 114 . The titanium nitride layer 124 formed by nitriding as described above is located on the titanium layer 176 and contacts the lower portion of the sidewall 119 of the trench 121 formed in the interlayer dielectric layer 108 . As described above, the titanium nitride layer 130 formed by the ALD process is positioned on the titanium nitride layer 124 and is in contact with an upper portion of the sidewall 119 of the trench 121 .

The structure of Figure 3a has the advantage of providing low current leakage. Due to the extra buffer provided by the titanium nitride layer 124 in contact with the lower portion of the sidewall 119 of the trench 121, the structure can be formed by precisely controlling the ALE process described above. In particular, the ALE process may be performed in a manner that ensures that a portion of the titanium nitride layer 124 remains on the sidewall 119 of the trench 121 .

3B is an enlarged cross-sectional view (along line 3A-3A of FIG. 1R ) of the integrated circuit 100 of FIGS. 1A-1R in accordance with an alternative embodiment. In the embodiment of FIG. 3B , the ALE process was carefully controlled so that the titanium nitride layer 124 does not remain on the sidewalls 119 of the trenches 121 . This provides the advantage of providing a low resistance contact to the metal gate 114 .

4A is an enlarged cross-sectional view (along line 2A-2A of FIG. 1R ) of the integrated circuit 100 of FIGS. 1A-1R in accordance with one embodiment. The structure of FIG. 4A is substantially similar to the structure of FIG. 2A except that the titanium nitride layers 124 and 130 and the titanium layer 174 have a flat profile rather than a curved profile. 4B is an enlarged cross-sectional view (along line 2A-2A of FIG. 1R ) of the integrated circuit 100 of FIGS. 1A-1R in accordance with an alternative embodiment. The structure of FIG. 4B is substantially similar to the structure of FIG. 2B except that the titanium nitride layers 124 and 130 and the titanium layer 174 have a flat profile rather than a curved profile.

5A is an enlarged cross-sectional view (along line 3A-3A of FIG. 1R ) of the integrated circuit 100 of FIGS. 1A-1R according to one embodiment. The structure of FIG. 5A is substantially similar to the structure of FIG. 3A except that the titanium nitride layers 124 and 130 and the titanium layer 176 have a flat profile rather than a curved profile. 5B is an enlarged cross-sectional view (along line 3A-3A of FIG. 1R ) of the integrated circuit 100 of FIGS. 1A-1R in accordance with an alternative embodiment. The structure of FIG. 5B is substantially similar to the structure of FIG. 3B except that the titanium nitride layers 124 and 130 and the titanium layer 176 have a flat profile rather than a curved profile.

6A is an illustration of a semiconductor process system 600 according to one embodiment. The semiconductor process system 600 may be used to perform an ALE process in conjunction with the processes and structures illustrated and described with respect to FIGS. 1A-5B . The semiconductor process system 600 includes a process chamber 602 that includes an interior space 603 . A support 606 is positioned within the interior space 603 and is configured to support the substrate 604 during the thin film etching process. The semiconductor process system 600 is configured to etch a thin film on the substrate 604 . The semiconductor process system 600 includes a control system 624 that dynamically adjusts thin film etch parameters. Details of the control system 624 are provided after the description of the operation of the semiconductor process system 600 .

In one embodiment, the semiconductor process system 600 includes a first fluid source 608 and a second fluid source 610 . The first fluid supply source 608 supplies a first fluid to the interior space 603 . The second fluid supply source 610 supplies a second fluid to the internal space. Both the first and second fluids contribute to the etching of the thin film on the substrate 604 . 6A illustrates fluid sources 608 , 610 , in practice, fluid sources 608 , 610 may contain or supply materials other than fluids. For example, fluid sources 608 and 610 may include material sources that provide all materials for the etching process.

In one embodiment, the semiconductor process system 600 is an ALE system that performs an ALE process. The ALE system performs the etch process in several cycles. Each cycle purges the first etching fluid from the etch chamber by flowing a first etching fluid from a fluid source 608 and then a purge gas from one or both of the purge sources 612 , 624 , followed by a flow of the first etching fluid from the fluid source. purging the second etching fluid from the etch chamber by flowing a second etching fluid from 610 and then flowing a purge gas from one or both of the purge sources 612 , 624 . This corresponds to a single ALE cycle. Each cycle etches an atomic or molecular layer from the thin film being etched.

The parameters of the thin film produced by the semiconductor process system 600 may be affected by many process conditions. Process conditions include, but are not limited to, the residual amount of fluid or material remaining in fluid sources 608 , 610 , the flow rate of fluid or material from fluid sources 608 , 610 , provided by fluid sources 608 , 610 . the pressure of the fluid, the length of the tube or conduit that transports the fluid or material into the process chamber 602 , the duration of use of the ampoule defining or contained in the process chamber 602 , the temperature within the process chamber 602 , the process chamber 602 ), the pressure in the process chamber 602, the reflected light absorption in the process chamber 602, the surface characteristics of the semiconductor wafer 604, the composition of the material provided by the fluid sources 608, 610, the fluid sources 608. 610 ), the duration of the etching process, the duration of the individual steps of the etching process, and various other factors including factors not specifically listed above.

The combination of various process conditions during the etching process determines the remaining thickness of the thin film etched by the ALE process. A thin film that does not have a residual thickness corresponding to a target parameter may be generated due to process conditions. In this case, the integrated circuit formed from the semiconductor wafer 604 may not function properly. The quality of the batch of semiconductor wafers may be degraded. In some cases, it may be necessary to discard some semiconductor wafers.

The semiconductor process system 600 uses the control system 624 to dynamically adjust process conditions to ensure that the etch process produces thin films with parameters or properties that fall within target parameters or properties. Control system 624 is coupled to processing equipment associated with semiconductor process system 600 . The processing equipment may include components illustrated in FIG. 6A and components not illustrated in FIG. 6A . Control system 624 controls the flow rate of material from fluid sources 608 , 610 , the temperature of the material supplied by fluid sources 608 , 610 , the pressure of the fluid provided by fluid sources 608 , 610 , purge flow rate of material from sources 612 , 614 , duration of flow of material from fluid sources 608 , 610 and purge sources 612 , 614 , temperature within process chamber 602 , pressure within process chamber 602 . , the humidity within the process chamber 602 and other aspects of the thin film etching process. Control system 624 controls these process parameters so that the thin film etch process forms a thin film having target parameters such as target residual thickness, target composition, target crystal orientation, and the like. Further details regarding the control system are provided in connection with Figures 7-9.

In one embodiment, the control system 624 is communicatively coupled to the first and second fluid sources 608 , 610 via one or more communication channels 625 . The control system 624 can send signals to the first fluid source 608 and the second fluid source 610 via the communication channel 625 . Control system 624 may control the function of first and second fluid sources 608 , 610 in response to sensor signals from byproduct sensor 622 , in part.

In one embodiment, the semiconductor process system 600 may include one or more valves, pumps, or other flow control mechanisms for controlling the flow rate of the first fluid from the first fluid source 608 . This flow control mechanism may be part of the fluid source 608 or may be separate from the fluid source 608 . Control system 624 may be communicatively coupled to such a flow control mechanism or a system for controlling such a flow control mechanism. Control system 624 may control the flow rate of the first fluid by controlling these mechanisms. The control system 600 is a valve, pump, or other flow control that controls the flow of the second fluid from the second fluid source 610 in the same manner as described above with respect to the first fluid source 608 and the first fluid source 608 . Mechanisms may be included.

In one embodiment, semiconductor process system 600 includes a manifold mixer 616 and a fluid distributor 618 . The manifold mixer 616 receives the first fluid and the second fluid from the first fluid source 608 and the second fluid source 610 together or separately. Manifold mixer 616 provides a first fluid, a second fluid, or a mixture of first and second fluids to a fluid distributor 618 . The fluid distributor 618 receives one or more fluids from the manifold mixer 616 and distributes the one or more fluids into the interior space 603 of the process chamber 602 .

In one embodiment, the first fluid source 608 is coupled to the manifold mixer 616 by a first fluid channel 630 . The first fluid channel 630 carries a first fluid from the fluid source 608 to the manifold mixer 616 . The first fluid channel 630 may be a tube, pipe, or other suitable channel for passing a first fluid from the first fluid source 608 to the manifold mixer 616 . A second fluid source 610 is coupled to the manifold mixer 616 by a second fluid channel 632 . The second fluid channel 632 carries a second fluid from the second fluid source 610 to the manifold mixer 616 .

In one embodiment, the manifold mixer 616 is coupled to the fluid distributor 618 by a third fluid line 634 . A third fluid line 634 carries fluid from the manifold mixer 616 to the fluid distributor 618 . The third fluid line 634 may carry a first fluid, a second fluid, a mixture of first and second fluids, or another fluid, as described in more detail below.

The first and second fluid sources 608 , 610 may include fluid tanks. The fluid tank may store first and second fluids. The fluid tank may selectively drain the first and second fluids.

In one embodiment, the semiconductor process system 600 includes a first purge source 612 and a second purge source 614 . The first purge source is coupled to the first fluid line 630 by a first purge line 636 . A second purge source is coupled to the fluid line 632 by a second purge line 638 . In practice, the first and second purge sources may be a single purge source.

In one embodiment, the first and second purge sources 612 , 614 supply a purge gas into the interior space 603 of the process chamber 602 . The purge fluid is a fluid selected to purge or transport the first fluid, the second fluid, a byproduct of the first or second fluid, or another fluid from the interior space 603 of the process chamber 602 . The purge fluid is selected such that it does not interact with the substrate 604 , the thin film layer on the substrate 604 , the first and second fluids and byproducts of the first and second fluids. Accordingly, the purge fluid may be an inert gas including, but not limited to, _{Ar or N 2 .}

Although FIG. 6A illustrates a first fluid source 608 and a second fluid source 610 , in practice the semiconductor process system 600 may include other numbers of fluid sources. For example, semiconductor process system 600 may include only one fluid source or three or more fluid sources. Accordingly, semiconductor process system 600 may include more than two fluid sources without departing from the scope of the present disclosure.

6B is a graph illustrating a cycle of an ALE process according to an embodiment. The graph of FIG. 6B may correspond to the ALE process performed by the semiconductor process system 600 of FIG. 6A and may be used to perform the process illustrated and described in connection with FIGS. 1A-5B to create a structure. At time T1 the first etching fluid begins to flow. In the example of FIG. 6B , the first etching fluid is WCl ₅ . A first etching fluid flows from the fluid source 608 into the interior space 603 . In the interior space 603 , the first etching fluid reacts with the upper exposed layer of the titanium nitride layer 124 . At time T2 , the first etching fluid WCl ₅ stops flowing. In one example, the elapsed time between T1 and T2 is between 1 second and 10 seconds.

At time T3, the purge gas begins to flow. A purge gas flows from one or both of the purge sources 612 , 624 . In one example, the purge gas purges _{the first etching fluid WCl 5 without reacting with the argon, N 2} or titanium nitride layer 124 . It is one of the other inert gases that can do.At time T4, the purge gas stops flowing. For example, the elapsed time between T3 and T4 is between 6 seconds and 15 seconds.

At time T5 , a second etching fluid flows into the interior space 603 . A second etching fluid flows from the fluid source 610 into the interior space 603 . In one example, the second etching fluid is O ₂ . O ₂ reacts with the upper atomic or molecular layer of the titanium nitride layer 124 , and completes etching of the upper atomic or molecular layer of the titanium nitride layer 124 . At time T6, the second etching fluid stops flowing. In one example, the elapsed time between T5 and T6 is between 1 second and 10 seconds.

At time T7, the purge gas flows again to purge the interior space 603 of the second etching fluid. At time T8, the purge gas stops flowing. The time between T1 and T8 corresponds to a single ALE cycle.

In practice, the ALE process may include 5 to 50 cycles depending on the initial thickness of the titanium nitride layer and the desired final thickness of the titanium nitride layer. Each cycle removes an atomic or molecular layer of titanium nitride layer 124 . Other materials, processes, and elapsed times may be applied without departing from the scope of the present disclosure.

7 is a block diagram of a control system 624 according to one embodiment. The control system 624 of FIG. 7 is configured to control the operation of the ALE system 600 according to one embodiment. Control system 624 may be applied with the processes, structures, and systems described with respect to FIGS. 1A-6B . The control system 624 uses machine learning to tune parameters of the ALE system 600 . Control system 624 may adjust parameters of ALE system 600 between ALE runs or even between ALE cycles to ensure that the thin film layers formed by the ALE process fall within selected specifications.

In one embodiment, the control system 624 includes an analysis model 640 and a training module 641 . The training module trains the analytic model 640 in a machine learning process. The machine learning process trains the analytical model 640 to select parameters for the ALE process that forms a thin film with selected properties. Although the training module 641 is illustrated as separate from the analysis model 640 , in practice the training module 641 may be part of the analysis model 640 .

Control system 624 includes or stores training set data 642 . The training set data 642 includes historical thin film data 644 and historical process condition data 646 . The historical thin film data 644 includes data related to thin films generated from the ALE process. The historical process condition data 646 includes data related to process conditions during the ALE process in which the thin film is generated. As described in more detail below, the training module 641 utilizes the historical thin film data 644 and the historical process condition data 646 to train the analytical model 640 with a machine learning process.

In one embodiment, historical thin film data 644 includes data relating to the residual thickness of a previously etched thin film. For example, thousands or millions of semiconductor wafers may be processed over months or years during operation of a semiconductor manufacturing facility. Each of the semiconductor wafers may include a thin film etched by an ALE process. After each ALE process, the thickness of the thin film is measured as part of the quality control process. The historical thin film data 644 includes the thickness of each thin film etched by the ALE process. Accordingly, the historical thin film data 644 may include thickness data for a plurality of thin films etched by the ALE process.

In one embodiment, the historical thin film data 644 may also include data related to the thickness of the thin film at an intermediate stage of the thin film etching process. For example, an ALE process may include multiple etch cycles while individual layers of the thin film are being etched. The historical thin film data 644 may include thickness data for the thin film after an individual etch cycle or group of etch cycles. Accordingly, the historical thin film data 644 may include not only data related to the total thickness of the thin film after completion of the ALE process, but also data related to the thickness of the thin film at various stages of the ALE process.

In one embodiment, the historical thin film data 644 includes data related to the composition of the thin film etched by the ALE process. After the thin film is etched, measurements can be performed to determine the elemental or molecular composition of the thin film. Successful etching of the thin film results in a thin film with a specified residual thickness. An unsuccessful etching process can produce thin films that do not contain the desired thickness or composition. The historical thin film data 644 may include measurement data representing elements or compounds constituting various thin films.

In one embodiment, historical process conditions 646 include various process conditions or parameters during an ALE process for etching a thin film associated with historical thin film data 644 . Thus, for each thin film having data in the historical thin film data 644 , the historical process condition data 646 may include process conditions or parameters that were present during etching of the thin film. For example, historical process condition data 646 may include data related to pressure, temperature, and fluid flow rate within a process chamber during an ALE process.

The historical process condition data 646 may include data related to the residual amount of the precursor material remaining in the fluid source during the ALE process. The historical process condition data 646 includes the period of use of the process chamber 602 , the number of etching processes performed in the process chamber 602 , that is, the number of etching processes performed in the process chamber 602 after the most recent cleaning cycle of the process chamber 602 . data pertaining to the number of etching processes performed or other data pertaining to the process chamber 602 . The historical process condition data 646 may include data relating to a compound or fluid introduced into the process chamber 602 during an etching process. Data related to a compound may include the type of compound, the phase of the compound (solid, gas or liquid), a mixture of compounds, or other aspects related to the compound or fluid introduced into the process chamber 602 . The historical process condition data 646 includes data related to humidity in the process chamber 602 during the ALE process. The historical process condition data 646 may include data related to light absorption, light absorption, and light reflection related to the process chamber 602 . The historical process condition data 626 may include data relating to the length of a pipe, tube, or conduit that transports a compound or fluid into the process chamber 602 during an ALE process. The historical process condition data 646 may include data relating to conditions of a carrier gas that transports a compound or fluid into the process chamber 602 during an ALE process.

In one embodiment, historical process condition data 646 may include process conditions for each of a plurality of individual cycles of a single ALE process. Accordingly, the historical process condition data 646 may include process condition data for a very large number of ALE cycles.

In one embodiment, the training set data 642 connects the historical thin film data 644 with the historical process condition data 646 . That is, the thin film thickness, material composition, or crystal structure associated with the thin film in the historical thin film data 644 is coupled to process condition data related to the etching process. As will be described in more detail below, the labeled training set data can be utilized in a machine learning process to train the analytical model 640 to predict semiconductor process conditions to properly form thin films.

In one embodiment, the control system 624 includes a processing resource 648 , a memory resource 650 , and a communication resource 652 . Processing resources 648 may include one or more controllers or processors. The processing resource 648 is configured to execute software instructions, process data, determine thin film etch control, perform signal processing, read data from memory, write data to memory, and perform other processing tasks. is composed The processing resource 648 may include a physical processing resource 648 located at a site or facility of the semiconductor process system 600 . The processing resources may include remote virtual processing resources 648 remote from the site or facility where the semiconductor process system 600 is located. Processing resources 648 may include cloud-based processing resources, including processors and servers, accessed through one or more cloud computing platforms.

In one embodiment, memory resource 650 may include one or more computer readable memories. Memory resource 650 is configured to store software instructions related to the functioning of the control system and its components, including but not limited to analysis model 640 . The memory resource 650 may store data related to the functions of the control system 624 and its components. The data may include training set data 642 , current process condition data, and any other data related to control system 624 or any of its components. Memory resource 650 may include a physical memory resource located at a site or facility of semiconductor process system 600 . The memory resource may include a virtual memory resource located remotely from a site or facility of the semiconductor process system 600 . Memory resource 650 may include cloud-based memory resources accessed through one or more cloud computing platforms.

In one embodiment, the communication resource may include a resource that enables the control system 624 to communicate with equipment associated with the semiconductor process system 600 . For example, communication resource 652 includes wired and wireless communication resources that enable control system 624 to receive sensor data associated with semiconductor process system 600 and control equipment of semiconductor process system 600 . can do. Communication resource 652 may enable control system 624 to control the flow of fluid or other material from fluid sources 608 , 610 and purge sources 612 , 614 . Communication resource 652 may enable control system 624 to control heaters, voltage sources, valves, exhaust channels, wafer transfer equipment, and any other equipment associated with semiconductor process system 600 . The communication resource 652 may enable the control system 624 to communicate with a remote system. Communication resources 652 may include or enable communication over one or more networks, such as a wired network, a wireless network, the Internet, or an intranet. The communication resource 652 may enable the components of the control system 624 to communicate with each other.

In one embodiment, the analysis model 640 is implemented via a processing resource 648 , a memory resource 650 , and a communication resource 652 . Control system 624 may be a distributed control system with components and resources and locations remote from each other and remote from semiconductor process system 600 .

8A is a flow diagram of a process 800 for training an analytical model to identify process conditions that will induce proper etching of a thin film according to one embodiment. An example of an analysis model is the analysis model 640 of FIG. 7 . The various steps of process 800 may utilize the components, processes, and techniques described in connection with FIGS. 1A-7 . Accordingly, Fig. 8A is described with reference to Figs. 1A-7.

At 802 , process 800 collects training set data including historical thin film data and historical process condition data. This can be done using data mining systems or processes. A data mining system or process may collect training set data by accessing one or more databases associated with the semiconductor process system 600 and collecting and configuring various types of data contained in the one or more databases. A data mining system or process or other system or process may process and format the collected data to generate training set data. The training set data 642 may include historical thin film data 644 and historical process condition data 646 as described with reference to FIG. 7 .

At 804 , process 800 inputs historical process condition data into the analytical model. In one example, this may include inputting historical process condition data 646 into the analytical model 640 using the training module 641 as described with respect to FIG. 7 . The historical process condition data may be provided to the analytical model 640 as a continuous discrete set. Each individual set may correspond to a single thin film etch process or part of a single thin film etch process. The historical process condition data may be provided as a vector to the analysis model 640 . Each set may include one or more vectors formatted for receiving processing by the analysis model 640 . Historical process condition data may be provided to the analytical model 640 in other formats without departing from the scope of the present disclosure.

At 806 , process 800 generates predicted thin film data based on historical process condition data. In particular, the analytical model 640 generates predicted thin film data for each set of historical thin film condition data 646 . The predicted thin film data corresponds to the prediction of properties such as the residual thickness of the thin film obtained from a specific set of process conditions. The predicted thin film data may include the thickness, uniformity, composition, crystal structure, or other aspects of the residual thin film.

At 808 , the predicted thin film data is compared to historical thin film data 644 . In particular, the predicted thin film data for each historical process condition data set is compared to historical thin film data 644 associated with that historical process condition data set. The comparison may derive an error function indicating how closely the predicted thin film data matches the historical thin film data 644 . This comparison is performed for each predicted thin film data set. In one embodiment, the process may include generating an aggregation error function or indication indicating how the predicted thin film data totality compares to the historical thin film data 644 . This comparison may be performed by the training module 641 or by the analysis model 640 . The comparison may include other types of functions or data other than those described above without departing from the scope of the present disclosure.

At 810 , the process 800 determines whether the predicted thin film data matches the historical thin film data based on the comparison generated in 808 . For example, the process determines whether the predicted residual thickness matches the actual residual thickness after the historical etch process. In one example, if the aggregate error function is less than the tolerance, the process 800 determines that the thin film data does not match the historical thin film data. In one example, if the aggregation error function is greater than the tolerance, the process 800 determines that the thin film data matches the historical thin film data. As an example, the tolerance may include a tolerance of 0.1-0. That is, if the total percentage error is less than 0.1 or 60%, then process 800 considers the predicted thin film data to match the historical thin film data. If the total percentage error is greater than 0.1 or 60%, then the process 800 considers the predicted thin film data to be inconsistent with the historical thin film data. Other tolerances may be applied without departing from the scope of the present disclosure. The error score may be calculated in various ways without departing from the scope of the present disclosure. The training module 641 or the analysis model 640 may make a determination related to the process step 810 .

In one embodiment, if the thin film data predicted at step 810 do not match the historical thin film data 644 , the process proceeds to step 812 . At step 812 , process 800 adjusts an internal function associated with analysis model 640 . In one example, the training module 641 adjusts an internal function associated with the analysis model 640 . From step 812, the process returns to step 804. At 804 , historical process condition data is provided back to the analytical model 640 . Because the internal function of the analytical model 640 has been adjusted, the analytical model 640 will produce different predicted thin film data than in the previous cycle. The process proceeds to steps 806, 808 and 810 and an aggregation error is calculated. If the predicted thin film data does not match the historical thin film data, the process returns to step 812 and the internal function of the analytical model 640 is adjusted again. This process iterates until the analytical model 640 generates predictive thin film data consistent with the historical thin film data 644 .

In one embodiment, if the predicted thin film data matches the historical thin film data, process step 810 in process 800 proceeds to 814 . At step 814 , training is complete. The analytical model 640 is now ready to be utilized to identify process conditions and may be utilized in a thin film etch process performed by the semiconductor process system 600 . Process 800 may include other steps or configurations not illustrated and described herein without departing from the scope of the present disclosure.

8B is a block diagram illustrating an operational aspect and a training aspect of the analysis model 640 according to an embodiment. The analysis model 640 may correspond to the analysis model described with respect to FIGS. 6 and 7 . The analytical model 640 may be utilized with the processes, structures, and systems described with respect to FIGS. 1A-8A . As mentioned above, the training set data 642 includes data related to a plurality of thin film etching processes previously performed. Each thin film etching process previously performed was performed under specific process conditions to form a thin film having special properties. The process conditions for each previously performed thin film etch process are formatted into individual process condition vectors 852 . The process condition vector includes a plurality of data fields 854 . Each data field 854 corresponds to a specific process condition.

The example of FIG. 8B illustrates a single process condition vector 852 to be passed to the analytical model 640 during the training process. In the example of FIG. 8B , the process condition vector 852 includes nine data fields 854 . The first data field 854 corresponds to the temperature during the thin film etching process performed previously. The second data field 856 corresponds to the pressure during the thin film etching process performed previously. The third data field 854 corresponds to the humidity during the thin film etching process performed previously. The fourth data field 854 corresponds to the flow rate of the etching material during the thin film etching process performed previously. A fifth data field 854 corresponds to a phase (liquid, solid, or gas) of the etching material during a previously performed thin film etching process. The sixth data field 854 corresponds to the period of use of the ampoule used in the thin film etching process performed previously. The seventh data field 854 corresponds to the size of the etching area on the wafer during the thin film etching process previously performed. The eighth data field 854 corresponds to the density of the surface features of the wafer used during the thin film etching process performed previously. The ninth data field corresponds to the sidewall angle of the surface feature during the thin film etching process performed previously. Indeed, each process condition vector 852 may include more or fewer data fields than illustrated in FIG. 8B without departing from the scope of this disclosure. Each process condition vector 852 may include a different type of process condition without departing from the scope of the present disclosure. The specific process conditions illustrated in FIG. 8B are provided by way of example only. Each process condition is expressed as a numerical value in the corresponding data field 854 . For types of conditions that are not naturally numerically expressed, such as phases of matter, each possible phase can be assigned a number.

The analysis model 640 includes a plurality of neural layers 856a - e . Each neural layer includes a plurality of nodes 858 . Each node 858 may also be called a neuron. Each node 858 from the first neural layer 856a receives a data value for each data field from the processing condition vector 852 . Thus, in the example of FIG. 8B , each node 858 from the first neural layer 856a receives 9 data values because the orbital condition vector 852 has 9 data fields. Each neuron 858 includes a separate internal mathematical function denoted F(x) in FIG. 8B . Each node 858 of the first neural layer 856a generates a scalar value by applying an internal mathematical function F(x) to the data value from the data field 854 of the process condition vector 852 . Further details regarding the internal mathematical function F(x) are provided below.

Each node 858 of the second neural layer 856b receives a scalar value generated by each node 858 of the first neural layer 856a. Accordingly, in the example of FIG. 8B , each node of the second neural layer 856b receives four scalar values because there are four nodes 858 in the first neural layer 856a. Each node 858 of the second neural layer 856b generates a scalar value by applying a respective internal mathematical function F(x) to the scalar value from the first neural layer 856a.

Each node 858 of the third neural layer 856c receives a scalar value generated by each node 858 of the second neural layer 856b. Accordingly, in the example of FIG. 8B , each node of the third neural layer 856c receives five scalar values because five nodes 858 exist in the second neural layer 856b. Each node 858 of the third neural layer 856c generates a scalar value by applying a respective internal mathematical function F(x) to the scalar value from the node 858 of the second neural layer 856b.

Each node 858 of the neural layer 856d receives a scalar value generated by each node 858 of the previous neural layer (not shown). Each node 858 of neural layer 856d generates a scalar value by applying a respective internal mathematical function F(x) to the scalar value from node 858 of second neural layer 856b.

The final neural layer contains only one node 858 . The final neural layer receives the scalar value generated by each node 858 of the previous neural layer 856d. Node 858 of final neural layer 856e generates data values 868 by applying a mathematical function F(x) to the scalar value received from node 858 of neural layer 856d.

In the example of FIG. 8B , the data value 868 corresponds to the predicted residual thickness of the thin film generated by the process condition data corresponding to the value included in the process condition vector 852 . In other embodiments, the final neural layer 856e may generate multiple data, each corresponding to a particular thin film characteristic, such as thin film crystal orientation, thin film uniformity, or other properties of the thin film. The final neural layer 856e will include a respective node 858 for each output data value to be generated. For the predicted thin film thickness, the engineer may provide a constraint specifying that the predicted thin film thickness 868 must fall within a selected range, such as 0-50 nm, for example. The analytical model 640 will adjust the internal function F(x) to ensure that the data values 868 corresponding to the predicted thin film thicknesses fall within a certain range.

During the machine learning process, the analytical model compares the residual thickness predicted by data value 868 to the actual residual thickness of the thin film as indicated by data value 870 . As described above, the training set data 642 includes thin film characteristic data representing characteristics of a thin film formed in the historical thin film etching process for each historical process condition data set. Accordingly, the data field 870 contains the actual residual thickness of the thin film resulting from the etching process reflected in the process condition vector 852 . The analytical model 640 compares the predicted residual thickness from the data value 868 to the actual residual thickness from the data value 870 . The analytical model 640 generates an error value 872 representing an error or difference between the predicted residual thickness from the data value 868 and the actual residual thickness from the data value 870 . The error value 872 is used to train the analytical model 640 .

The training of the analytical model 640 may be more fully understood by discussing the internal mathematical function F(x). Although all nodes 858 are labeled with an internal mathematical function F(x), each node's mathematical function F(x) is unique. As an example, the form of each internal mathematical function is:

In the above equation, each value (x ₁ -x _n ) corresponds to a data value received from the node 858 of the previous neural layer, or in the case of the first neural layer 856a, each value (x ₁ -x _{n )} ) corresponds to each data value from data field 854 of process condition vector 852 . Thus, n for a given node is equal to the number of nodes in the previous neural layer. The w ₁ -w _n value is the scalar weight associated with the node in the previous layer. The analysis model 640 selects the values _{of the weights w 1} -w _{n .} The constant b is a scalar bias value and may be multiplied by a weight. The value generated by node 858 is based on weights w ₁ -w _n . Accordingly, each node 858 has n weights w ₁ -w _n . Although not illustrated above, each function F(x) may also include an activation function. The sum mentioned in the above equation is multiplied by an activation function. Examples of activation functions may include rectifying linear unit (ReLU) functions, sigmoid functions, hyperbolic tension functions, or other types of activation functions.

After the error value 872 is calculated, the analysis model 640 adjusts the weights w ₁ -w _n for the various nodes 858 of the various neural layers 856a - 356e. After the analytical model 640 _{adjusts the weights w 1} -w _n , the analytical model 640 again provides the process condition vector 852 to the input neural layer 856a. Because the weights are different for the various nodes 858 of the analysis model 640 , the predicted residual thickness 868 will be different than in the previous iteration. The analytical model 640 re-generates the error value 872 by comparing the actual residual thickness 870 to the predicted residual thickness 868 .

The analysis model 640 readjusts the _{weights w 1} -w _n associated with the various nodes 858 . The analysis model 640 again processes the idle condition vector 852 and produces a predicted residual thickness 868 and an associated error value 872 . The training process includes iteratively adjusting the _{weights w 1} -w _n until the error value 872 is minimized.

8B illustrates a single process condition vector 852 passed to the analytical model 640 . In practice, the training process passes a number of process condition vectors 852 through an analytical model 640 , generates a predicted residual thickness 868 for each process condition vector 852 , and each predicted residual thickness and generating an associated error value 872 for The training process may also include generating an aggregate error value representing the average error for all predicted residual thicknesses for the batch of process condition vectors 852 . The analysis model 640 adjusts the _{weights w 1} -w _n after processing each batch of the idle condition vector 852 . The training process continues until the average error across all idle condition vectors 852 is less than the selected threshold tolerance. If the average error is less than the selected threshold tolerance, training of the analytical model 640 is completed and the analytical model is trained to accurately predict the thickness of the thin film according to the process conditions. The analytical model 640 can then be used to predict the thin film thickness and select process conditions that will result in the desired thin film thickness. While using the trained model 640 , a process condition vector representing the current process conditions for the current thin film etching process to be performed and having the same format in the process condition vector 852 is provided to the trained analysis model 640 . Then, the trained analysis model 640 may predict the thickness of the thin film to be obtained from these process conditions.

A specific example of a neural network-based analysis model 640 has been described with respect to FIG. 8B . However, other types of neural network-based analysis models or types of analysis models other than neural networks may be applied without departing from the scope of the present disclosure. Moreover, a neural network may include different numbers of neural layers with different numbers of nodes without departing from the scope of the present disclosure.

9 is a flow diagram of a process 900 for dynamically selecting process conditions for a thin film etch process and performing a thin film etch process in accordance with one embodiment. The various steps of process 900 may utilize the components, processes, and techniques described with respect to FIGS. 1A-8B . Accordingly, Fig. 9 is described with reference to Figs. 6-3B.

At 902 , process 900 provides target thin film condition data to analysis model 640 . The target thin film condition data identifies selected characteristics of the thin film to be formed by the thin film etching process. The target thin film condition data may include a target residual thickness, a target composition, a target crystal structure, or other properties of the thin film. The target thin film condition data may include various thicknesses. The target condition or characteristic that may be selected is based on the thin film characteristic(s) utilized in the training process. In the example of FIG. 8B , the training process is focused on thin film thickness.

At 904 , the process 900 provides static process conditions to the analytical model 640 . Static process conditions include process conditions that will not be adjusted for the next thin film etch process. The static process conditions may include a target device pattern density indicative of a pattern density on a wafer to be subjected to a thin film etch process. Static process conditions include effective planar area crystal orientation, effective planar area roughness index, effective sidewall area of features on the semiconductor wafer surface, exposed effective sidewall tilt angle, exposed surface film functionalities, exposed sidewall functionalities, rotation or tilting of the semiconductor wafer. , process gas parameters (material, phase of material and temperature of material), residual amount of material fluid remaining in fluid sources 608, 610, residual fluid in purge sources 612, 614, humidity in process chamber, etching process may include the age of the ampoules used, the absorption or reflection of light within the process chamber, the length of the pipe or conduit that will provide fluid to the process chamber, or other conditions. Static process conditions may include conditions other than those described above without departing from the scope of the present disclosure. Also, in some cases, some of the static process conditions enumerated above may be dynamic process conditions that can be adjusted as described in more detail below. In the example of FIG. 8B, the dynamic process conditions include temperature, pressure, humidity and flow rate. Static process conditions include phase, ampoule age, etch area, etch density, and sidewall angle.

At 906 , the process 900 selects dynamic process conditions for the analytical model according to one embodiment. Dynamic process conditions may include any process conditions that are not specified as static process conditions. For example, the training set data may include many different types of process condition data in the historical process condition data 646 . Some of these types of process conditions will be defined as static process conditions and some of these types of process conditions will be defined as dynamic process conditions. Accordingly, when static process conditions are supplied in step 904 , the remaining types of process conditions may be defined as dynamic process conditions. The analytical model 640 may initially select initial values for dynamic process conditions. After selecting the initial values for the dynamic process conditions, the analytical model has the entire set of process conditions to be analyzed. In one embodiment, the initial values for the dynamic process conditions may be selected based on previously determined starting values or according to other schemes.

Dynamic process conditions may include flow rates of fluids or materials from fluid sources 608 , 610 during the etching process. Dynamic process conditions may include flow rates of fluids or materials from purge sources 612 , 614 . Dynamic process conditions may include pressure within the process chamber, temperature within the process chamber, humidity within the process chamber, durations of various steps of the etching process, or voltages or electric fields generated within the process chamber. Dynamic process conditions may include other types of conditions without departing from the scope of the present disclosure.

At 908 , the analytical model 640 generates predicted thin film data based on the static and dynamic process conditions. The predicted thin film data includes the same type of thin film characteristics set in the target thin film condition data. In particular, the predicted thin film data includes the type of thin film data predicted from the training process described with respect to FIGS. 8A and 8B . For example, the predicted thin film data may include thin film thickness, thin film composition, or other parameters of the thin film.

At 910 , the process compares the predicted thin film data to the target thin film data. In particular, the analysis model 640 compares the predicted thin film data with the target thin film data. The comparison indicates how closely the predicted thin film data matches the target thin film data. The comparison may indicate whether the predicted thin film data is within a tolerance or range set by the target thin film data. For example, if the target thin film thickness is 6-9 nm, the comparison will indicate whether the predicted thin film data is within this range.

At 912 , if the predicted thin film data does not match the target thin film data, the process proceeds to 914 . At 914 , the analytical model 640 adjusts the dynamic process condition data. At 914 , the process returns to 908 . At 908 , the analytical model 640 again generates predicted thin film data based on the static process conditions and the adjusted dynamic process conditions. Then, the analysis model compares the predicted thin film data with the target thin film data at 910 . At 912 , if the predicted thin film data does not match the target thin film data, the process proceeds to 914 and the analytical model 640 again adjusts the dynamic process conditions. This process continues until predicted thin film data matching the target thin film data is generated. If the predicted thin film data matches the target thin film data 912 , the process proceeds to 916 .

At 916 , the process 900 adjusts thin film processing conditions of the semiconductor process system 600 based on the dynamic process conditions obtained with the thin film data predicted within the target thin film data. For example, control system 624 may adjust fluid flow rate, etch step duration, pressure, temperature, humidity, or other factors according to dynamic process condition data.

At 918 , the semiconductor process system 600 performs a thin film etch process according to the adjusted dynamic process conditions identified by the analytical model. In one embodiment, the thin film etch process is an ALE process. However, other thin film etching processes may be applied without departing from the scope of the present disclosure. In one embodiment, semiconductor process system 600 adjusts process parameters based on analytical models between individual etch steps within a thin film etch process. For example, in ALE processes, thin films are etched one layer at a time. The analysis model 640 may identify parameters to be utilized for etching the next layer. Thus, the semiconductor processing system can adjust the etch conditions between the various etch steps.

In one embodiment, an integrated circuit includes a transistor including a terminal. The integrated circuit comprises a dielectric layer, the dielectric layer disposed over the terminal and having a first trench exposing the first terminal and including a sidewall, a first barrier layer disposed over the terminal, and a first barrier layer and and a second barrier layer disposed on the sidewall and having a vertical height of the trench greater than a vertical height of the first barrier layer of the trench. The integrated circuit includes a conductive plug positioned within the trench and in contact with the second barrier layer.

In one embodiment, a method includes forming a dielectric layer on a terminal of the transistor, exposing the terminal by forming a trench in the dielectric layer, and forming a first titanium nitride layer in the trench on the terminal of the transistor do. The method includes forming a second titanium nitride layer in the trench over the first barrier layer and on sidewalls of the trench and forming a cobalt plug in the trench.

In one embodiment, a method includes training an analytical model with a machine learning process to select parameters for an atomic layer etching process and etching a thin film over a transistor. The method includes selecting etch parameters for etching the thin film with an atomic layer process comprising the selected etch parameters.

Embodiments of the present disclosure provide thin films of reliable thickness and composition. Embodiments of the present disclosure dynamically adjust process parameters to ensure that the thin film has the desired properties.

The various embodiments described above may be combined to provide further embodiments. All US patent application publications and US patent applications referred to herein and/or listed in the application data sheet are hereby incorporated by reference in their entirety. Aspects of the embodiments may be modified as necessary to employ the concepts of various patents, applications, and publications to provide still further embodiments.

These and other changes can be made to the above embodiments in light of the above detailed description. In general, the terminology used in the following claims is not to be construed as limiting the claims to the specific embodiments disclosed in the specification and claims, but rather to limit all possible embodiments together with the full scope of equivalents of the entitlement of such claims. should be construed as including Accordingly, the claims are not limited by the present disclosure.

[Example 1]

An integrated circuit comprising:

a transistor including a terminal;

a dielectric layer disposed over the terminal, the dielectric layer exposing the terminal and having a first trench including a sidewall;

a first barrier layer disposed on the terminal;

a second barrier layer disposed on the first barrier layer and on the sidewall and having a vertical height in the trench greater than a vertical extent of the first barrier layer in the trench; and

a conductive plug positioned within the trench and in contact with the second barrier layer

comprising: an integrated circuit.

[Example 2]

In Example 1,

and the first barrier layer is located on the sidewall below the second barrier layer.

[Example 3]

In Example 1,

and the second barrier layer isolates the first barrier layer from the sidewall.

[Example 4]

In Example 1,

wherein the first and second barrier layers are titanium nitride.

[Example 5]

In Example 4,

and the conductive plug is cobalt.

[Example 6]

In Example 4,

and the first barrier layer is formed by nitridation of titanium.

[Example 7]

In Example 6,

wherein the first barrier layer is formed by an atomic layer deposition process.

[Example 8]

In Example 1,

and the terminal is a metal gate of the transistor.

[Example 9]

In Example 1,

and the terminal is a source terminal of the transistor.

[Example 10]

In Example 1,

wherein the transistor comprises a plurality of semiconductor nanosheets.

[Example 11]

As a method,

forming a dielectric layer on the terminals of the transistor;

exposing the terminal by forming a trench in the dielectric layer;

forming a first titanium nitride layer in a trench on a terminal of the transistor;

forming a second titanium nitride layer in the trench over the first barrier layer and on sidewalls of the trench; and

forming a cobalt plug in the trench;

A method comprising

[Example 12]

In Example 11,

selecting parameters for an atomic layer etching process of the first barrier layer; and

forming the first titanium nitride layer in the trench by etching the first titanium nitride layer to a selected height within the trench with the atomic layer etch process comprising the selected parameters;

A method further comprising:

[Example 13]

In Example 11,

The step of forming the first titanium nitride layer,

depositing a layer of titanium; and

nitriding the titanium

A method comprising

[Example 14]

In Example 13,

and nitridizing the first titanium nitride layer comprises flowing _{NH 3 in the presence of the titanium.}

[Example 15]

In Example 13,

wherein forming the second titanium nitride layer comprises performing an atomic layer deposition process.

[Example 16]

In Example 11,

The method of claim 1, wherein forming the cobalt plug comprises performing an electroless cobalt plating process.

[Example 17]

As a method,

training an analytical model with a machine learning process to select parameters for an atomic layer etch process;

forming a thin film on the transistor;

selecting etching parameters for etching the thin film; and

etching the thin film with an atomic layer etching process comprising the selected etching parameters;

A method comprising

[Example 18]

In Example 17,

wherein the selected parameter comprises a number of atomic layer etch cycles.

[Example 19]

In Example 18,

wherein the selected parameter comprises a flow rate of the etching fluid.

[Example 20]

In Example 17,

and the analytical model selects the parameter based in part on the selected residual thickness of the thin film.

Claims (10)

An integrated circuit comprising:
a transistor including a terminal;
a dielectric layer disposed over the terminal, the dielectric layer exposing the terminal and having a first trench including a sidewall;
a first barrier layer disposed on the terminal;
a second barrier layer disposed on the first barrier layer and on the sidewall and having a vertical height in the trench greater than a vertical extent of the first barrier layer in the trench; and
a conductive plug positioned within the trench and in contact with the second barrier layer
comprising: an integrated circuit. According to claim 1,
and the first barrier layer is located on the sidewall below the second barrier layer. According to claim 1,
and the second barrier layer isolates the first barrier layer from the sidewall. According to claim 1,
wherein the first and second barrier layers are titanium nitride. 5. The method of claim 4,
and the conductive plug is cobalt. 5. The method of claim 4,
and the first barrier layer is formed by nitridation of titanium. According to claim 1,
and the terminal is a metal gate or source terminal of the transistor. According to claim 1,
wherein the transistor comprises a plurality of semiconductor nanosheets. As a method,
forming a dielectric layer on the terminals of the transistor;
exposing the terminal by forming a trench in the dielectric layer;
forming a first layer of titanium nitride in the trench on a terminal of the transistor;
forming a second titanium nitride layer in the trench over the first barrier layer and on sidewalls of the trench; and
forming a cobalt plug in the trench;
A method comprising As a method,
training an analytical model with a machine learning process to select parameters for an atomic layer etch process;
forming a thin film on the transistor;
selecting etching parameters for etching the thin film; and
etching the thin film with an atomic layer etching process comprising the selected etching parameters;
A method comprising

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