KR20210157748A - Method for repairing semiconductor memory module and elecronic device therefor - Google Patents

Abstract

Disclosed is an electronic device including a display, a semiconductor memory module, a memory controller, a processor, and a memory operatively coupled to the processor. The electronic device generates a test signal to detect a defective memory cell of the semiconductor memory module based on a specified period; performs a test operation based on the test signal to detect at least one defective memory cell in a memory cell array included in the semiconductor memory module; and stores data associated with the at least one bad memory cell in the memory when the at least one defective memory cell is detected, wherein the memory controller stores one or more instructions for generating and transmitting a repair signal including data associated with the at least one defective memory cell stored in the memory to the semiconductor memory module. In addition, various embodiments identified through the specification are possible.

Description

Semiconductor memory module repair method and electronic device therefor

Various embodiments disclosed in this document relate to a semiconductor memory module repair method and an electronic device therefor.

As the usage period of the semiconductor memory module elapses, at least one memory cell included in the memory cell array may deteriorate, resulting in deterioration in performance. In preparation for a case in which the memory cell is defective due to deterioration, the semiconductor memory module may include a redundancy circuit and/or a redundancy memory cell. In addition, the semiconductor memory module may include a fuse circuit for changing an internal setting value or programming a repair address.

The semiconductor memory module performs a test on memory cells at the wafer level, and when there is a bad memory cell, a bad address is programmed in the redundancy circuit included therein. An alternative repair function may be provided.

Meanwhile, the semiconductor memory module may store an address and/or specific setting information by performing a fuse programming function through a fuse included in the fuse circuit. In particular, a fuse that can be programmed in the package state is collectively referred to as an electrical fuse, and can be programmed by applying electrical stress (eg, overcurrent and/or high voltage) to change the electrical connection state of the fuse. have.

In the conventional semiconductor memory module, it is possible to test whether the memory cell is defective at the package level, and to perform a repair operation when the defective memory cell is detected. However, it is difficult to perform a repair operation on a defect caused by deterioration after the semiconductor memory module is packaged in an electronic device (eg, a mobile terminal device).

A user cannot recognize deterioration in performance due to deterioration occurring in the process of using the electronic device in which the semiconductor memory module is mounted, and after the semiconductor memory module is packaged, the electronic device directly detects whether the semiconductor memory module is deteriorated or repairs it. There is discomfort in being unable to perform an action.

An electronic device according to an embodiment disclosed herein includes a display, a semiconductor memory module, a memory controller, a processor, and a memory operatively connected to the processor, wherein the memory, when executed The processor generates a test signal to detect a defective memory cell of the semiconductor memory module based on a specified period, and performs a test operation based on the test signal to perform a test operation on at least one memory cell array included in the semiconductor memory module. , and when the at least one bad memory cell is detected, the data associated with the at least one bad memory cell is stored in the memory, and the memory controller is configured to store the at least one bad memory cell stored in the memory. One or more instructions for generating and transmitting a repair signal including data associated with a memory cell to the semiconductor memory module may be stored.

According to an embodiment of the present disclosure, a method for an electronic device to provide a function of repairing a semiconductor module includes generating a test signal for detecting a defective memory cell of the semiconductor module based on a specified period; detecting at least one bad memory cell in the memory cell array included in the semiconductor memory module by performing a test operation based on a test signal; when the at least one bad memory cell is detected, the at least one bad memory Storing cell-related data in the memory, and generating a repair signal including data associated with the at least one defective memory cell stored in the memory using a memory controller and transmitting it to the semiconductor module can

According to various embodiments of the present disclosure, it is possible to periodically detect whether the semiconductor memory module has deteriorated and detect a potentially defective memory cell through a test according to a parameter change. When a defective memory cell is detected, the electronic device may control the repair operation by itself to prevent deterioration of the function of the electronic device.

According to various embodiments of the present disclosure, when a defect of a level that is difficult for the electronic device to handle by itself occurs in the semiconductor memory module, data related to the defect of the semiconductor memory module is displayed on the display to provide information to the user. can provide

In addition, various effects directly or indirectly identified through this document may be provided.

1 is a block diagram of an electronic device in a network environment, according to various embodiments of the present disclosure;
2 is a block diagram illustrating a configuration of an electronic device according to various embodiments of the present disclosure;
3 is a block diagram of a semiconductor memory module according to various embodiments of the present disclosure;
4 is a block diagram of a semiconductor memory module according to various embodiments of the present disclosure;
5 illustrates a voltage level graph related to an operation of a memory module according to various embodiments of the present disclosure;
6 is a block diagram illustrating components involved in an operation of avoiding or blocking access to a memory cell address of an electronic device, according to various embodiments of the present disclosure;
7 is a flowchart illustrating an operation of an electronic device according to various embodiments of the present disclosure;
8 is a flowchart illustrating an operation of an electronic device according to various embodiments of the present disclosure;
In connection with the description of the drawings, the same or similar reference numerals may be used for the same or similar components.

Hereinafter, various embodiments of the present document will be described with reference to the accompanying drawings. However, this is not intended to limit the technology described in this document to specific embodiments, and it should be understood that various modifications, equivalents, and/or alternatives of the embodiments of this document are included. .

1 is a block diagram of an electronic device 101 in a network environment 100 according to various embodiments. Referring to FIG. 1 , in a network environment 100 , an electronic device 101 communicates with an electronic device 102 through a first network 198 (eg, a short-range wireless communication network) or a second network 199 . It may communicate with the electronic device 104 or the server 108 through (eg, a long-distance wireless communication network). According to an embodiment, the electronic device 101 may communicate with the electronic device 104 through the server 108 . According to an embodiment, the electronic device 101 includes a processor 120 , a memory 130 , an input module 150 , a sound output module 155 , a display module 160 , an audio module 170 , and a sensor module ( 176), interface 177, connection terminal 178, haptic module 179, camera module 180, power management module 188, battery 189, communication module 190, subscriber identification module 196 , or an antenna module 197 may be included. In some embodiments, at least one of these components (eg, the connection terminal 178 ) may be omitted or one or more other components may be added to the electronic device 101 . In some embodiments, some of these components (eg, sensor module 176 , camera module 180 , or antenna module 197 ) are integrated into one component (eg, display module 160 ). can be

The processor 120, for example, executes software (eg, a program 140) to execute at least one other component (eg, a hardware or software component) of the electronic device 101 connected to the processor 120 . It can control and perform various data processing or operations. According to one embodiment, as at least part of data processing or operation, the processor 120 converts commands or data received from other components (eg, the sensor module 176 or the communication module 190 ) to the volatile memory 132 . may be stored in the volatile memory 132 , and may process commands or data stored in the volatile memory 132 , and store the result data in the non-volatile memory 134 . According to an embodiment, the processor 120 is the main processor 121 (eg, a central processing unit or an application processor) or a secondary processor 123 (eg, a graphic processing unit, a neural network processing unit) a neural processing unit (NPU), an image signal processor, a sensor hub processor, or a communication processor). For example, when the electronic device 101 includes the main processor 121 and the sub-processor 123 , the sub-processor 123 may use less power than the main processor 121 or may be set to be specialized for a specified function. can The auxiliary processor 123 may be implemented separately from or as a part of the main processor 121 .

The auxiliary processor 123 is, for example, on behalf of the main processor 121 while the main processor 121 is in an inactive (eg, sleep) state, or the main processor 121 is active (eg, executing an application). ), together with the main processor 121, at least one of the components of the electronic device 101 (eg, the display module 160, the sensor module 176, or the communication module 190) It is possible to control at least some of the related functions or states. According to an embodiment, the co-processor 123 (eg, an image signal processor or a communication processor) may be implemented as part of another functionally related component (eg, the camera module 180 or the communication module 190). have. According to an embodiment, the auxiliary processor 123 (eg, a neural network processing device) may include a hardware structure specialized for processing an artificial intelligence model. Artificial intelligence models can be created through machine learning. Such learning may be performed, for example, in the electronic device 101 itself on which artificial intelligence is performed, or may be performed through a separate server (eg, the server 108). The learning algorithm may include, for example, supervised learning, unsupervised learning, semi-supervised learning, or reinforcement learning, but in the above example not limited The artificial intelligence model may include a plurality of artificial neural network layers. Artificial neural networks include deep neural networks (DNNs), convolutional neural networks (CNNs), recurrent neural networks (RNNs), restricted boltzmann machines (RBMs), deep belief networks (DBNs), bidirectional recurrent deep neural networks (BRDNNs), It may be one of deep Q-networks or a combination of two or more of the above, but is not limited to the above example. The artificial intelligence model may include, in addition to, or alternatively, a software structure in addition to the hardware structure.

The memory 130 may store various data used by at least one component of the electronic device 101 (eg, the processor 120 or the sensor module 176 ). The data may include, for example, input data or output data for software (eg, the program 140 ) and instructions related thereto. The memory 130 may include a volatile memory 132 or a non-volatile memory 134 .

The program 140 may be stored as software in the memory 130 , and may include, for example, an operating system 142 , middleware 144 , or an application 146 .

The input module 150 may receive a command or data to be used in a component (eg, the processor 120 ) of the electronic device 101 from the outside (eg, a user) of the electronic device 101 . The input module 150 may include, for example, a microphone, a mouse, a keyboard, a key (eg, a button), or a digital pen (eg, a stylus pen).

The sound output module 155 may output a sound signal to the outside of the electronic device 101 . The sound output module 155 may include, for example, a speaker or a receiver. The speaker can be used for general purposes such as multimedia playback or recording playback. The receiver may be used to receive an incoming call. According to one embodiment, the receiver may be implemented separately from or as part of the speaker.

The display module 160 may visually provide information to the outside (eg, a user) of the electronic device 101 . The display module 160 may include, for example, a control circuit for controlling a display, a hologram device, or a projector and a corresponding device. According to an embodiment, the display module 160 may include a touch sensor configured to sense a touch or a pressure sensor configured to measure the intensity of a force generated by the touch.

The audio module 170 may convert a sound into an electric signal or, conversely, convert an electric signal into a sound. According to an embodiment, the audio module 170 acquires a sound through the input module 150 , or an external electronic device (eg, a sound output module 155 ) connected directly or wirelessly with the electronic device 101 . A sound may be output through the electronic device 102 (eg, a speaker or headphones).

The sensor module 176 detects an operating state (eg, power or temperature) of the electronic device 101 or an external environmental state (eg, user state), and generates an electrical signal or data value corresponding to the sensed state. can do. According to an embodiment, the sensor module 176 may include, for example, a gesture sensor, a gyro sensor, a barometric pressure sensor, a magnetic sensor, an acceleration sensor, a grip sensor, a proximity sensor, a color sensor, an IR (infrared) sensor, a biometric sensor, It may include a temperature sensor, a humidity sensor, or an illuminance sensor.

The interface 177 may support one or more designated protocols that may be used by the electronic device 101 to directly or wirelessly connect with an external electronic device (eg, the electronic device 102 ). According to an embodiment, the interface 177 may include, for example, a high definition multimedia interface (HDMI), a universal serial bus (USB) interface, an SD card interface, or an audio interface.

The connection terminal 178 may include a connector through which the electronic device 101 can be physically connected to an external electronic device (eg, the electronic device 102 ). According to an embodiment, the connection terminal 178 may include, for example, an HDMI connector, a USB connector, an SD card connector, or an audio connector (eg, a headphone connector).

The haptic module 179 may convert an electrical signal into a mechanical stimulus (eg, vibration or movement) or an electrical stimulus that the user can perceive through tactile or kinesthetic sense. According to an embodiment, the haptic module 179 may include, for example, a motor, a piezoelectric element, or an electrical stimulation device.

The camera module 180 may capture still images and moving images. According to an embodiment, the camera module 180 may include one or more lenses, image sensors, image signal processors, or flashes.

The power management module 188 may manage power supplied to the electronic device 101 . According to an embodiment, the power management module 188 may be implemented as, for example, at least a part of a power management integrated circuit (PMIC).

The battery 189 may supply power to at least one component of the electronic device 101 . According to one embodiment, battery 189 may include, for example, a non-rechargeable primary cell, a rechargeable secondary cell, or a fuel cell.

The communication module 190 is a direct (eg, wired) communication channel or a wireless communication channel between the electronic device 101 and an external electronic device (eg, the electronic device 102, the electronic device 104, or the server 108). It can support establishment and communication performance through the established communication channel. The communication module 190 may include one or more communication processors that operate independently of the processor 120 (eg, an application processor) and support direct (eg, wired) communication or wireless communication. According to one embodiment, the communication module 190 is a wireless communication module 192 (eg, a cellular communication module, a short-range wireless communication module, or a global navigation satellite system (GNSS) communication module) or a wired communication module 194 (eg, : It may include a LAN (local area network) communication module, or a power line communication module). A corresponding communication module among these communication modules is a first network 198 (eg, a short-range communication network such as Bluetooth, wireless fidelity (WiFi) direct, or infrared data association (IrDA)) or a second network 199 (eg, legacy It may communicate with the external electronic device 104 through a cellular network, a 5G network, a next-generation communication network, the Internet, or a computer network (eg, a telecommunication network such as a LAN or a WAN). These various types of communication modules may be integrated into one component (eg, a single chip) or may be implemented as a plurality of components (eg, multiple chips) separate from each other. The wireless communication module 192 uses the subscriber information (eg, International Mobile Subscriber Identifier (IMSI)) stored in the subscriber identification module 196 within a communication network such as the first network 198 or the second network 199 . The electronic device 101 may be identified or authenticated.

The wireless communication module 192 may support a 5G network after a 4G network and a next-generation communication technology, for example, a new radio access technology (NR). NR access technology includes high-speed transmission of high-capacity data (eMBB (enhanced mobile broadband)), minimization of terminal power and access to multiple terminals (mMTC (massive machine type communications)), or high reliability and low latency (URLLC (ultra-reliable and low-latency) -latency communications)). The wireless communication module 192 may support a high frequency band (eg, mmWave band) to achieve a high data rate, for example. The wireless communication module 192 includes various technologies for securing performance in a high-frequency band, for example, beamforming, massive multiple-input and multiple-output (MIMO), all-dimensional multiplexing. It may support technologies such as full dimensional MIMO (FD-MIMO), an array antenna, analog beam-forming, or a large scale antenna. The wireless communication module 192 may support various requirements specified in the electronic device 101 , an external electronic device (eg, the electronic device 104 ), or a network system (eg, the second network 199 ). According to an embodiment, the wireless communication module 192 may include a peak data rate (eg, 20 Gbps or more) for realizing eMBB, loss coverage (eg, 164 dB or less) for realizing mMTC, or U-plane latency for realizing URLLC ( Example: downlink (DL) and uplink (UL) each 0.5 ms or less, or round trip 1 ms or less).

The antenna module 197 may transmit or receive a signal or power to the outside (eg, an external electronic device). According to an embodiment, the antenna module 197 may include an antenna including a conductor formed on a substrate (eg, a PCB) or a radiator formed of a conductive pattern. According to an embodiment, the antenna module 197 may include a plurality of antennas (eg, an array antenna). In this case, at least one antenna suitable for a communication method used in a communication network such as the first network 198 or the second network 199 is connected from the plurality of antennas by, for example, the communication module 190 . can be selected. A signal or power may be transmitted or received between the communication module 190 and an external electronic device through the selected at least one antenna. According to some embodiments, other components (eg, a radio frequency integrated circuit (RFIC)) other than the radiator may be additionally formed as a part of the antenna module 197 .

According to various embodiments, the antenna module 197 may form a mmWave antenna module. According to one embodiment, the mmWave antenna module comprises a printed circuit board, an RFIC disposed on or adjacent to a first side (eg, bottom side) of the printed circuit board and capable of supporting a designated high frequency band (eg, mmWave band); and a plurality of antennas (eg, an array antenna) disposed on or adjacent to a second side (eg, top or side) of the printed circuit board and capable of transmitting or receiving signals of the designated high frequency band. can do.

At least some of the components are connected to each other through a communication method between peripheral devices (eg, a bus, general purpose input and output (GPIO), serial peripheral interface (SPI), or mobile industry processor interface (MIPI)) and a signal ( eg commands or data) can be exchanged with each other.

According to an embodiment, the command or data may be transmitted or received between the electronic device 101 and the external electronic device 104 through the server 108 connected to the second network 199 . Each of the external electronic devices 102 or 104 may be the same as or different from the electronic device 101 . According to an embodiment, all or a part of operations executed in the electronic device 101 may be executed in one or more external electronic devices 102 , 104 , or 108 . For example, when the electronic device 101 is to perform a function or service automatically or in response to a request from a user or other device, the electronic device 101 may perform the function or service itself instead of executing the function or service itself. Alternatively or additionally, one or more external electronic devices may be requested to perform at least a part of the function or the service. One or more external electronic devices that have received the request may execute at least a part of the requested function or service, or an additional function or service related to the request, and transmit a result of the execution to the electronic device 101 . The electronic device 101 may process the result as it is or additionally and provide it as at least a part of a response to the request. For this, for example, cloud computing, distributed computing, mobile edge computing (MEC), or client-server computing technology may be used. The electronic device 101 may provide an ultra-low latency service using, for example, distributed computing or mobile edge computing. In another embodiment, the external electronic device 104 may include an Internet of things (IoT) device. Server 108 may be an intelligent server using machine learning and/or neural networks. According to an embodiment, the external electronic device 104 or the server 108 may be included in the second network 199 . The electronic device 101 may be applied to an intelligent service (eg, smart home, smart city, smart car, or health care) based on 5G communication technology and IoT-related technology.

The electronic device according to various embodiments disclosed in this document may have various types of devices. The electronic device may include, for example, a portable communication device (eg, a smart phone), a computer device, a portable multimedia device, a portable medical device, a camera, a wearable device, or a home appliance device. The electronic device according to the embodiment of the present document is not limited to the above-described devices.

The various embodiments of this document and terms used therein are not intended to limit the technical features described in this document to specific embodiments, but it should be understood to include various modifications, equivalents, or substitutions of the embodiments. In connection with the description of the drawings, like reference numerals may be used for similar or related components. The singular form of the noun corresponding to the item may include one or more of the item, unless the relevant context clearly dictates otherwise. As used herein, "A or B", "at least one of A and B", "at least one of A or B", "A, B or C", "at least one of A, B and C", and "A , B, or C" each may include any one of the items listed together in the corresponding one of the phrases, or all possible combinations thereof. Terms such as "first", "second", or "first" or "second" may be used simply to distinguish the element from other elements in question, and may refer to elements in other aspects (e.g., importance or order) is not limited. It is said that one (eg, first) component is "coupled" or "connected" to another (eg, second) component, with or without the terms "functionally" or "communicatively". When referenced, it means that one component can be connected to the other component directly (eg by wire), wirelessly, or through a third component.

The term “module” used in various embodiments of this document may include a unit implemented in hardware, software, or firmware, and is interchangeable with terms such as, for example, logic, logic block, component, or circuit. can be used as A module may be an integrally formed part or a minimum unit or a part of the part that performs one or more functions. For example, according to an embodiment, the module may be implemented in the form of an application-specific integrated circuit (ASIC).

According to various embodiments of the present document, one or more instructions stored in a storage medium (eg, internal memory 136 or external memory 138) readable by a machine (eg, electronic device 101) may be implemented as software (eg, the program 140) including For example, a processor (eg, processor 120 ) of a device (eg, electronic device 101 ) may call at least one command among one or more commands stored from a storage medium and execute it. This makes it possible for the device to be operated to perform at least one function according to the called at least one command. The one or more instructions may include code generated by a compiler or code executable by an interpreter. The device-readable storage medium may be provided in the form of a non-transitory storage medium. Here, 'non-transitory' only means that the storage medium is a tangible device and does not include a signal (eg, electromagnetic wave), and this term is used in cases where data is semi-permanently stored in the storage medium and It does not distinguish between temporary storage cases.

According to one embodiment, the method according to various embodiments disclosed in this document may be provided as included in a computer program product. Computer program products may be traded between sellers and buyers as commodities. The computer program product is distributed in the form of a machine-readable storage medium (eg compact disc read only memory (CD-ROM)), or via an application store (eg Play Store™) or on two user devices ( It can be distributed (eg downloaded or uploaded) directly between smartphones (eg: smartphones) and online. In the case of online distribution, at least a part of the computer program product may be temporarily stored or temporarily created in a machine-readable storage medium such as a memory of a server of a manufacturer, a server of an application store, or a relay server.

According to various embodiments, each component (eg, module or program) of the above-described components may include a singular or a plurality of entities, and some of the plurality of entities may be separately disposed in other components. have. According to various embodiments, one or more components or operations among the above-described corresponding components may be omitted, or one or more other components or operations may be added. Alternatively or additionally, a plurality of components (eg, a module or a program) may be integrated into one component. In this case, the integrated component may perform one or more functions of each component of the plurality of components identically or similarly to those performed by the corresponding component among the plurality of components prior to the integration. . According to various embodiments, operations performed by a module, program, or other component are executed sequentially, in parallel, repeatedly, or heuristically, or one or more of the operations are executed in a different order, or omitted. or one or more other operations may be added.

2 is a block diagram 200 illustrating a configuration of an electronic device according to various embodiments of the present disclosure.

Referring to FIG. 2 , an electronic device (eg, the electronic device 101 of FIG. 1 ) includes a processor 120 , a display module 160 , a storage module 210 , a memory module 220 , a memory controller 230 , and/or an internal memory 240 . The configuration of the electronic device illustrated in FIG. 2 is exemplary and embodiments of the present document are not limited thereto. For example, the electronic device may not include at least one of the components illustrated in FIG. 2 . As another example, the electronic device may further include a configuration not shown in FIG. 2 . Unless otherwise described, descriptions of components having the same reference numerals as those of FIG. 1 may be referred to by the description of FIG. 1 .

The processor 120 may be implemented as a single-chip system (System on Chip, SoC). The processor 120 of FIG. 2 may be referred to as a component distinct from the processor 620 of FIG. 6 to be described later. For example, the processor 620 of FIG. 6 may be defined as a separate processor (eg, a CPU processor) included in an application processor (eg, the processor 120 of FIG. 2 ) chip. The processor 120 may be operatively connected to the display module 160 , the storage module 210 , and the memory module 220 to operate. The processor 120 may include a memory controller 230 and an internal memory 240 . For example, the processor 120 may control an operation of the storage module 210 to process data (eg, a data read operation and/or a data write operation). The processor 120 may transmit a test signal (eg, a test command) for detecting whether the memory module 220 is deteriorated to the memory module 220 using the memory controller 230 . For example, the test signal may mean a signal generated by the processor 620 loading and executing a boot loader program in the internal memory 240 included in the application processor (eg, the processor 120 of FIG. 2 ). have. Details regarding the processor 620 may be referred to in more detail in the description of FIG. 6 to be described later. The processor 120 may be configured to transmit the test signal based on a specified cycle (eg, 1 day, 1 week, or 1 year). For example, the test cycle of the memory module 220 may be designated by a user or may be a cycle set by the electronic device (eg, the electronic device 101 of FIG. 1 ). In addition to the specified period, the processor 120 transmits a test signal to the memory controller 3230 in response to an operation of the electronic device executing a training (eg, double-data rate (DDR) training) function of the memory module 220 . can The test signal includes a test algorithm, test pattern, test condition, and/or test performed based on various parameters (eg, alternating current (AC) parameters, direct current (DC) parameters, frequency characteristics, and/or refresh parameters). An address for at least one memory cell region to be used may be included. For example, the test signal may include information including an algorithm for allowing a test to be performed only at a specified memory operating frequency or for adjusting a voltage associated with an operation of the memory module 220 when a test function is executed. For another example, the test signal may include changing AC timing parameters (tRAS, tRP, tRCD, tWR, tREF, and tPAUSE) and/or refresh-related parameters (eg refresh rate, polling time). Information including an algorithm to proceed with the test may be included. The processor 120 may deteriorate the operating performance of the memory module 220 by increasing the refresh rate to detect a defective memory cell and/or a memory cell with a high probability of occurrence in advance. Various components related to the above-described test function of the memory module 220 may be stored in the storage module 210 . The processor 120 may load and execute at least some data of the boot loader area of the storage module 210 into the internal memory 240 in order to execute the test function of the memory module 220 . For example, the processor 120 may execute a test function for the memory module 220 by executing a program corresponding to the test function of the memory module 220 using the internal memory 240 . For example, a program corresponding to the test function may be included in a boot loader program. The at least some data is an AC (Alternating Current) parameter, a DC (Direct Current) parameter, a test algorithm based on a frequency characteristic, and/or a refresh parameter, a test pattern, a test condition, and/or at least one of at least one test to be performed. An address for the memory cell region may be included. The processor 120 may store test result data of the memory module 220 in the storage module 210 . The test result data may include a bad memory cell address. After the test of the memory module 220 is finished, the processor 120 may be set to execute different operations according to the degree of failure. The repair operation for the defective memory cell may be at least one of hardware repair and software repair. For example, the processor 120 may control to perform a hardware repair operation for replacing defective memory cells of the memory cell array with redundancy cells. As another example, when data read from the memory module 220 is included in the bad memory cell, the processor 120 blocks or avoids access to the bad memory cell using the memory controller 230 . It can be controlled to execute a software repair operation that makes it possible. When the defect degree of the memory module 220 exceeds the specified range, the processor 120 may output information related to the defective memory cell of the memory module 220 to the display module 160 . The processor 120 may generate a repair signal for causing the memory module 220 to perform a repair operation on the defective memory cell and transmit it to the memory controller 230 .

The display module 160 may output information related to a defective memory cell and provide it to the user under the control of the processor 120 . For example, when it is determined that the degree of failure of the memory module 220 exceeds a specified range, the electronic device may output information related to the defective memory cell to the display module 160 . The information associated with the defective memory cell may include a performance state of the memory module 220 , operation information, A/S information, and/or a degree of deterioration.

The storage module 210 may include a boot loader area and a normal area. The boot loader may mean a program necessary to operate the processor 120 . That is, it may mean a program necessary for properly loading an operating system used by the processor 120 . According to various embodiments of the present document, the boot loader program may include a function of executing a test function of the memory module 220 . According to an embodiment, the processor 120 may use the internal memory 240 to execute a boot loader program to execute a test function of the memory module 220 . The storage module 210 may store parameters related to a test function of the memory module 220 , a test pattern, and an operating frequency of the memory module 220 . The storage module 210 may store at least a portion of test result data for the memory module 220 . For example, when it is determined that a defective memory cell has occurred due to functional deterioration of the memory module 220 , the storage module 210 may store an address and/or a flag signal corresponding to the defective memory cell. . The storage module 210 is a hard disk drive (HDD), flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), ferroelectric RAM (FRAM), or solid-state drive (SSD). State Drive) may include at least one non-volatile memory. The storage module 210 may communicate with the processor 120 through various interfaces. For example, advanced technology attachment (ATA), serial ATA (SATA), external SATA (e-SATA), small computer small interface (SCSI), serial attached SCSI (SAS), peripheral component interconnection (PCI), PCI-E (PCI express), IEEE 1394, USB (universal serial bus), SD (secure digital) card, MMC (multimedia card), eMMC (embedded multimedia card), or CF (compact flash) card interface through at least one interface It may communicate with the processor 120 . In FIG. 3 , the storage module 210 is illustrated as communicating with the processor 120 , but is not limited thereto. For example, the storage module 210 may communicate with a CPU, a microprocessor, and/or an application processor (AP).

The memory module 220 may be operatively connected to the processor 120 and/or the memory controller 230 to transmit/receive data. The memory module 220 may receive a control signal from the processor 120 and/or the memory controller 230 and operate (eg, a test operation and/or a repair operation) based on the received control signal. For example, the control signal is a signal generated by the electronic device (eg, the processor 620 of FIG. 6 ) using a memory (eg, the internal memory 240 ) to load at least some data in the boot loader area. can mean In other words, the control signal may mean a signal generated by the processor 620 loading and executing a boot loader program in the internal memory 240 included in the application processor (eg, the processor 120 of FIG. 2 ). . For example, the memory module 220 includes SRAM (Static RAM), SDRAM (Synchronous DRAM), ROM (Read Only Memory), PROM (Programmable ROM), EPROM (Electrically Programmable ROM), EEPROM (Electrically Erasable and Programmable ROM). , flash memory, phase-change RAM (PRAM), magnetic RAM (MRAM), resistive RAM (RRAM), or ferroelectric RAM (FRAM). The memory controller 230 may operate in connection with the at least one memory. The memory module 220 may be a DRAM module including at least one DRAM chip or at least one DRAM package. The memory module 220 may include a memory cell array, a mode detection unit, an address register, a plurality of anti-fuses, a repair address latch unit, and/or a repair control circuit. Components included in the memory module 220 may be described in more detail with reference to FIG. 3 .

The memory controller 230 may transmit/receive data to and from the memory module 220 through a data node and/or a data line. The memory controller 230 has a test signal, a memory cell address, a write command, and/or a read for executing a test of the memory module 220 at a specified period (eg, 1 day, 1 week, or 1 year). A (read) command may be received from the processor 120 . The cycle of the memory module 220 test may be designated by a user or may be a cycle set by the electronic device (eg, the electronic device 101 of FIG. 1 ). In addition to the specified period, the memory controller 230 may receive a test signal in response to an operation in which the electronic device executes a training (eg, double-data rate (DDR) training) function for the memory module 220 . The test signal may include a test start signal, a test end signal, test data, and/or a test pattern of the memory module 220 . According to an embodiment, the memory controller 230 may transmit commands received from an external (eg, the processor 120 ) to the memory module 220 .

3 is a block diagram of a semiconductor memory module 300 according to various embodiments of the present disclosure.

Referring to FIG. 3 , the semiconductor memory module 300 (eg, the memory module 220 of FIG. 2 ) includes a control logic 310 , an address register 320 , a row address multiplexer 335 , and a bank control logic 340 . , column address latch 350, row decoders 360a, 360b, 360c, and 360d, column decoders 370a, 370b, 370c, and 370d, memory cell arrays 380a, 380b, 380c, and 380d, sense amplifiers parts 385a , 385b , 385c , and 385d , input/output gating circuitry 390 , data input/output buffer 395 , refresh control circuitry 330 , repair control circuitry 310 and/or error detection circuitry 375 . do.

The memory cell array may include first to fourth bank arrays 380a, 380b, 380c, and 380d. In addition, the row decoder includes first to fourth bank row decoders 360a, 360b, 360c, and 360d respectively connected to the first to fourth bank arrays 380a, 380b, 380c, and 380d, and the column The decoder includes first to fourth bank column decoders 370a, 370b, 370c, and 370d respectively connected to the first to fourth bank arrays 380a, 380b, 380c, and 380d, and the sense amplifier unit includes a first It may include first to fourth bank sense amplifiers 385a, 385b, 385c, and 385d respectively connected to the to fourth bank arrays 380a, 380b, 380c, and 380d. First to fourth bank arrays 380a, 380b, 380c, and 380d, first to fourth bank sense amplifiers 385a, 385b, 385c, and 385d, first to fourth bank row decoders 460a and 460b , 460c and 460d) and the first to fourth bank column decoders 370a, 370b, 370c, and 370d may configure the first to fourth banks, respectively.

3 illustrates an example of the semiconductor memory module 300 including four banks, but is not limited thereto. For example, the semiconductor memory module 300 may include any number of banks.

According to various embodiments, the semiconductor memory module 300 includes a DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory), LPDDR (Low Power Double Data Rate) SDRAM, GDDR (Graphics Double Data Rate) SDRAM, RDRAM (Rambus Dynamic Random Access Memory). It may be a dynamic random access memory (DRAM), such as a random access memory, or any semiconductor memory module requiring a repair operation and a refresh operation.

The address register 320 may receive an address ADDR including a bank address BANK_ADDR, a row address ROW_ADDR, and a column address COL_ADDR from a memory controller (eg, the memory controller 230 of FIG. 2 ). . The address register 320 provides the received bank address BANK_ADDR to the bank control logic 340 , the received row address ROW_ADDR to the row address multiplexer 335 , and the received column address COL_ADDR It may be provided to the column address latch 350 .

The bank control logic 340 may generate bank control signals in response to the bank address BANK_ADDR. In response to the bank control signals, a bank row decoder corresponding to a bank address BANK_ADDR among the first to fourth bank row decoders 360a, 360b, 360c, and 360d is activated, and the first to fourth bank columns are activated. A bank column decoder corresponding to the bank address BANK_ADDR among the decoders 370a, 370b, 370c, and 370d may be activated.

The row address multiplexer 335 may receive a row address ROW_ADDR from the address register 320 and a refresh address REF_ADDR from the refresh control circuit 330 . The row address multiplexer 335 may selectively output a row address ROW_ADDR or a refresh address REF_ADDR. The row address output from the row address multiplexer 335 may be applied to the first to fourth bank row decoders 360a, 360b, 360c, and 360d, respectively.

Among the first to fourth bank row decoders 360a, 360b, 360c, and 360d, the bank row decoder activated by the bank control logic 340 decodes the row address output from the row address multiplexer 335 to provide the row address The corresponding word line can be activated. For example, the activated bank row decoder may apply a word line driving voltage to a word line corresponding to a row address.

The column address latch 350 may receive the column address COL_ADDR from the address register 320 and temporarily store the received column address COL_ADDR. The column address latch 350 may apply the temporarily stored column address COL_ADDR to the first to fourth bank column decoders 370a, 370b, 370c, and 370d, respectively.

The bank column decoder activated by the bank control logic 340 among the first to fourth bank column decoders 370a , 370b , 370c , and 370d includes a bank address BANK_ADDR and a column address (BANK_ADDR) through the input/output gating circuit 390 . COL_ADDR) can activate the corresponding sense amplifier.

The input/output gating circuit 390 is a read data latch for storing input data mask logic and data output from the first to fourth bank arrays 380a, 380b, 380c, and 380d together with circuits for gating the input/output data. and write drivers for writing data to the first to fourth bank arrays 380a, 380b, 380c, and 380d.

Data DQ to be read from one of the first to fourth bank arrays 380a, 380b, 380c, and 380d is sensed by a sense amplifier corresponding to the one bank array, and the read data latches can be stored in The data DQ stored in the read data latches may be provided to the memory controller through the data input/output buffer 395 . Data DQ to be written to one of the first to fourth bank arrays 380a, 380b, 380c, and 380d may be provided from the memory controller to the data input/output buffer 395 . The data DQ provided to the data input/output buffer 395 may be written to the single bank array through the write drivers.

The control logic 310 may control the operation of the semiconductor memory module 300 . For example, the control logic 310 may generate control signals so that the semiconductor memory module 300 performs a write operation and/or a read operation. The control logic 310 may include a command decoder 311 for decoding a command CMD received from the memory controller and a mode register 312 for setting an operation mode of the semiconductor memory module 300 . For example, the command decoder 311 decodes the write enable signal (/WE), the row address strobe signal (/RAS), the column address strobe signal (/CAS), the chip select signal (/CS), etc. CMD) corresponding to the control signals may be generated. Also, the control logic 310 may further receive a clock signal CLK and a clock enable signal /CKE for driving the semiconductor memory module 300 in a synchronous manner.

The refresh control circuit 330 may generate a refresh address REF_ADDR under the control of the control logic 310 and provide it to the row address multiplexer 335 . A refresh operation may be performed on the plurality of memory cells based on the refresh address REF_ADDR. The error detection circuit 375 may detect a bad memory cell among the plurality of memory cells. The repair control circuit 310 may perform a repair operation on the defective memory cell. The repair control circuit 310 may include a repair address latch unit, an anti-fuse unit, and/or a repair processing unit. The repair address latch unit may store at least one of addresses stored in the address register 320 in response to a repair operation signal transmitted from the memory controller. The anti-fuse unit may include a plurality of anti-fuses. The anti-fuse unit may receive a rupture signal generated based on the repair operation signal, and may electrically program at least some of the addresses stored in the repair address latch unit. For example, the rupture signal may be defined as a signal output from the mode register 312 or a signal output from an internal command block. As another example, the rupture signal may be defined as a signal directly input from the outside. The rupture signal may mean a signal instructing a programming operation of the anti-fuse unit.

The description of the repair control circuit 310 shown in FIG. 3 may be described in more detail with reference to FIG. 4 to be described later.

4 is a block diagram of a semiconductor memory module 400 according to various embodiments of the present disclosure.

Referring to FIG. 4 , the semiconductor memory module 400 (eg, the semiconductor memory module 300 of FIG. 3 ) includes a mode register 403 (eg, the mode register 312 of FIG. 3 ), an address register 305 ( For example, the address register 320 of FIG. 3 ), and/or the repair control circuit 410 (eg, the repair control circuit 310 of FIG. 3 ) may be included.

The mode register 403 may be a component for setting an operation mode of the semiconductor memory module 400 . In order for the semiconductor memory module 400 to operate in at least one of a refresh mode, a repair mode, and a test mode, a corresponding operation mode may be set in the mode register 403 . The mode register 403 may include a test mode register set interface (TMRS Interface). For example, the mode register 403 receives a test operation signal for detecting a bad memory cell of the semiconductor memory module 400 from a memory controller (eg, the memory controller 230 of FIG. 2 ), and the semiconductor memory module 400 . ) can be set to test mode. As another example, when the detection of the defective memory cell of the semiconductor memory module 400 is completed, the mode register 403 receives a repair operation signal for the defective memory cell from the memory controller and operates the semiconductor memory module 400 . You can set the mode to repair mode.

The address register 405 may receive a specified address from an external (eg, a memory controller), and the semiconductor memory module 400 may perform a repair operation based on the specified address. For example, the designated address may be an address corresponding to a defective memory cell derived as a result of executing a test operation of the semiconductor memory module 400 . The address register 405 may store an address corresponding to the defective memory cell. The address register 405 may transmit the designated address to the repair control circuit 410 .

The repair control circuit 410 may control the semiconductor memory module 400 to operate in a repair mode based on an externally received repair operation signal. In the repair mode, the semiconductor memory module 400 may be set to repair defective memory cells derived as a result of the test operation execution under the control of the repair control circuit 410 . For example, the repair operation may include an operation of allowing the semiconductor memory module 400 to access a redundant memory cell instead of the defective memory cell when an access request for the defective memory cell occurs. As another example, if it is determined that the first memory cell is defective, and an access request is made to the first memory cell, the semiconductor memory module 400 may change the address corresponding to the first memory cell to the address corresponding to the second memory cell. It is possible to block access to the bad memory cell by avoiding it. The repair control circuit 410 may include a repair address latch unit 412 , an anti-fuse unit 414 , and/or a repair processing unit 416 .

The repair address latch unit 412 may temporarily store at least one address. For example, the repair address latch unit 412 may temporarily store at least some of the specified addresses stored in the address register 405 in response to a repair operation signal of the semiconductor memory module 400 . The designated address may include an address corresponding to at least a portion of memory cells included in a memory cell array (eg, the memory cell array of FIG. 3 ) of the semiconductor memory module 400 . The repair address latch unit 412 may further include components not shown in FIG. 4 . For example, the repair address latch unit 412 may include a switching unit and/or a latch unit. The switching unit may selectively output an address input to the repair control circuit 410 based on the repair operation signal. The latch unit may temporarily store a signal output from the switching unit.

The anti-fuse unit 414 may store various information related to the operation of the semiconductor memory module 400 . Unlike general fuse circuits such as laser fuse circuits and electrical fuse circuits, the anti-fuse unit 414 may start in a high resistance state and change to a low resistance state by a programming operation to store information. The anti-fuse unit 414 may have a structure (eg, a capacitor structure) having two conductive layers and a dielectric layer therebetween, and by applying a high voltage between the two conductive layers to breakdown the dielectric layer. A programming operation can be performed. The anti-fuse unit 414 controls internal settings of the semiconductor memory electronic device 400 (eg, the number of row and column addresses, a data width, the number of ranks, or a memory density per rank) or programs the addresses. can do. For example, the anti-fuse unit 414 may receive a rupture signal based on the repair operation signal, and may electrically program at least some of the addresses selectively output from the repair address latch unit 412 .

The repair processing unit 416 may perform a repair operation on the defective memory cell based on the repair operation signal. For example, when the memory module receives a cell address used whenever a specific function is executed in real time, the repair processing unit 416 receives at least some of the addresses electrically programmed by the anti-fuse unit 414 and the received cell address in real time. Cell addresses can be compared with each other. When the real-time received cell address and the address electrically programmed by the anti-fuse unit 414 match, the repair processing unit 416 may activate a repair operation signal to perform a repair operation using the redundancy memory cell. In the repair operation using the redundancy memory cell, for example, the repair processing unit 416 replaces the defective memory cell based on the repair operation signal to the first redundancy memory cell corresponding to the defective memory cell among the plurality of redundancy memory cells. It may include an action to access. For example, when it is determined that a memory cell determined to be defective satisfies a specified condition (eg, within a range of a defined quantity), access to an address corresponding to the defective memory cell is avoided and/or blocked can be set to A repair operation for avoiding and/or blocking access corresponding to a specific address may be described in more detail with reference to FIG. 6 . As another example, when it is determined that the memory cell determined to be defective exceeds the specified condition range (eg, a repair operation using the redundancy memory cell, or an operation to avoid and/or block access to an address is impossible) , the repair processing unit 416 transmits a signal including defective data of the memory cell (eg, address information corresponding to the defective memory cell, a defect occurrence flag, and/or the number of memory cells determined to be defective) to the processor ( For example, it may be transmitted to the processor 120 of FIG. 3 ). The processor receives a signal including bad data of the memory cell, and controls to display information on the bad content of the memory cell on the display module (eg, the display module 160 of FIG. 1 ) based on the received signal. can For example, the information displayed on the display module may include information related to a defect degree of a memory cell, a performance state of the semiconductor memory module 400 , whether repair is possible, and/or a repair method.

5 illustrates a voltage level graph 500 related to an operation of a memory module according to various embodiments of the present disclosure.

Referring to FIG. 5 , the electronic device (eg, the electronic device 101 of FIG. 1 ) adjusts a voltage level associated with an operation of a memory module (eg, the memory module 320 of FIG. 3 ) to detect a bad memory cell. can

According to an embodiment, the memory module may be divided into a peripheral area and a core. For example, the peripheral region is a region other than the core, and may be referred to as a region including a circuit region for controlling a memory cell address, a command signal, and data input/output.

According to an embodiment, the memory controller (eg, the memory controller 230 of FIG. 2 ) may transmit a test operation signal for performing a test operation to the memory module to detect whether a memory cell included in the memory module is deteriorated. have. The memory controller may adjust a voltage level related to a memory operation while the memory module performs a test operation. The memory controller may control the voltage level when performing the normal operation 520 and/or the test operation 530 after power-up 510 of the memory module.

According to an embodiment, when the memory module performs the normal operation 520, the memory controller sets the voltages used for the core region, the peripheral region, and the input/output interface included in the memory module to VDD11, It can be controlled to be set to the level of VDD21 and VDDQ1.

According to an embodiment, when the memory module performs the test operation 530 , the memory controller determines that voltages used for the core region, the peripheral region, and the in-out interface included in the memory module are VDD12, VDD22, and VDDQ2, respectively. You can control it to be set to a level. For example, the levels of VDD12, VDD22, and VDDQ2 set when the test operation 530 of the memory module is performed may be referred to as values lower than the levels of VDD11, VDD21, and VDDQ1 set when the normal operation 520 is performed, respectively. have. When the test operation 530 is finished, the memory controller may reset the voltage level set to a low value to the values (eg, VDD11, VDD21, and VDDQ1) set when the normal operation 520 is performed.

6 is a block diagram 600 illustrating components involved in an operation of avoiding or blocking access to a memory cell address of an electronic device, according to various embodiments of the present disclosure.

At least some of the components of FIG. 6 (eg, the processor 620 and/or the MMU 645 ) are provided in an electronic device (eg, the electronic device 101 of FIG. 1 ) in a single-chip system (System on chip, SoC). It may be included in the implemented application processor (eg, the processor 120 of FIG. 2 ). For example, the processor 620 may be defined as a separate processor included in an application processor (eg, the processor 120 of FIG. 2 ) included in the electronic device. As another example, the MMU 645 may be defined as a hardware module included in the application processor.

Referring to FIG. 6 , the processor 620 may include a memory allocator 630 , and the memory allocator 630 may include a page storage 632 and a page table 634 . The page table 634 may be electrically connected to a memory management unit (MMU) 645 to transmit/receive data. The page storage 632 may store a mapping table required to map a virtual address and a physical address. For example, the page storage 632 may store a page including a memory cell detected as defective as a result of a test of the memory module, and transfer the remaining pages to the page table 634 . The memory allocator 630 , the page storage 632 , and the page table 634 of FIG. 6 may be defined as program modules. Specifically, the processor 620 loads program data using the memory module 220 after booting, and controls the memory allocator 630 , the page storage 632 , and the page table 634 to operate through this. can do.

According to an embodiment, when it is determined that bad memory cells are adjacent to each other and multiple are detected as a result of performing a bad memory cell test on the memory module (eg, the memory module 220 of FIG. 2 ), the electronic device (eg, : The electronic device 101 of FIG. 1 ) may execute an address mapping 640 operation to map a page of a virtual address and a page of a physical address using the MMU 645 . For example, for the address mapping 640 operation, the processor 620 defines the page data of the virtual address and the page data of the physical address as one ordered pair and stores it in the page table 634 in the memory allocator 630 . It can be controlled to transmit one piece of information to the MMU 645 . After executing the test operation of the memory module, the processor 620 may store a page list including the detected bad memory cells in the page storage 632 . For example, when the MMU 645 performs a page mapping operation using the page table 634 , the processor 620 pages the mapping data except for a page including a bad memory cell stored in the page storage 632 . It can be controlled to transmit to the table 634 . The page table 634 may cause the MMU 645 to execute the address mapping 640 operation for the virtual address and the physical address by using the remaining pages except for the page including the bad memory cell.

The operations of the electronic device described in FIG. 6 (eg, operations in which the electronic device avoids or blocks access to a memory cell address) are performed by a program (eg, operation) operated in a memory module (eg, the memory module 220 of FIG. 2 ). system) and can be implemented. For example, the operations of the electronic device may be performed by being included in the operation of the processor 620 executing a program in the memory module 220 .

7 is a flowchart illustrating an operation of an electronic device 700 according to various embodiments of the present disclosure.

Referring to FIG. 7 , in operation 705 , the electronic device (eg, the electronic device 101 of FIG. 1 ) performs a test operation for detecting whether a memory module (eg, the memory module 220 of FIG. 2 ) is defective. can For example, the error detection circuit (eg, the error detection circuit 375 of FIG. 3 ) included in the memory module may include a defective memory cell among a plurality of memory cells included in the memory cell array (eg, the memory cell array of FIG. 3 ). can be detected. The test operation of the memory module may be repeatedly performed based on a specified period. For example, the processor (eg, the processor 120 of FIG. 1 ) may be configured to transmit a test signal of the memory module based on a specified period (eg, 1 day, 1 week, or 1 year). The test cycle of the memory module may be designated by a user or may be a cycle set by the electronic device itself. In addition to the specified period, the processor transmits a test signal to the memory controller (eg, the memory controller 230 of FIG. 2 ) in response to an operation in which the electronic device executes a training (eg, double-data rate (DDR) training) function of the memory module. ) can be transmitted. The test signal includes a test algorithm, test pattern, test condition, and/or test performed based on various parameters (eg, alternating current (AC) parameters, direct current (DC) parameters, frequency characteristics, and/or refresh parameters). An address for at least one memory cell region to be used may be included. For example, the test signal may include information including an algorithm for allowing a test to be performed only at a specified memory operating frequency or for adjusting a voltage associated with an operation of a memory module when a test function is executed. For another example, the test signal may include changing AC timing parameters (tRAS, tRP, tRCD, tWR, tREF, and tPAUSE) and/or refresh-related parameters (eg refresh rate, polling time). Information including an algorithm to proceed with the test may be included. The processor may deteriorate the operating performance of the memory module by increasing the refresh rate to detect a defective memory cell and/or a memory cell having a high probability of occurrence in advance.

In operation 710 , when it is determined that a defective memory cell is detected as a result of performing the test operation of the memory module (eg, operation 710 - Yes), the processor may perform operation 715 .

In operation 710 , when it is determined that a defective memory cell is not detected as a result of performing a test operation of the memory module (eg, operation 710 - Yes), the processor may repeatedly perform operation 705 based on a specified period. In this case, the designated period may be designated by the user or may be a period set by the electronic device itself.

In operation 715 , the processor may store data related to the result of performing the test operation of the memory module in the storage module (eg, the storage module 210 of FIG. 2 ). For example, the processor may store address information corresponding to a memory cell detected as a defective memory cell as a result of a test, a defect occurrence flag, and/or a quantity of memory cells determined to be defective in the storage module. The processor 120 may store test result data of the memory module 220 in the storage module 210 .

In operation 720, the processor may determine the degree of a defect in the memory cell, and may perform a specified repair operation in response to the determination result. For example, the repair operation may be at least one of hardware repair and software repair. The hardware repair operation may refer to an operation of replacing defective memory cells of the memory cell array with redundancy cells. The software repair operation may refer to an operation of blocking or avoiding access to the bad memory cell using a memory controller when data read from the memory module is included in the bad memory cell.

The operations (eg, memory cell repair operations) of the electronic device described with reference to FIG. 7 may be implemented by being included in a program (eg, boot loader) operating in an internal memory (eg, internal memory 240 of FIG. 2 ). For example, the operations of the electronic device may be executed by being included in the operation of the processor executing a program in the internal memory 240 .

8 is a flowchart illustrating an operation of an electronic device 800 according to various embodiments of the present disclosure.

In operation 805, a separate processor (eg, the processor 620 of FIG. 6) included in the application processor (eg, the processor 120 of FIG. 2) is a memory module (eg, the memory module 220 of FIG. 2) can analyze the test result of , and determine the degree of defect of the memory module based on the analysis contents. For example, the test may be performed based on a test signal generated by the processor loading and executing a boot loader program in an internal memory (eg, the internal memory 240 of FIG. 2 ).

In operation 810 , when it is determined that the defect degree of the memory module exceeds a specified range (eg, operations 810 - Yes), the processor may perform operation 815 . For reference, the processor may omit operation 815 of outputting information related to the bad memory cell and providing it to the user.

In operation 810 , when it is determined that the defect degree of the memory module does not exceed a specified range (eg, operations 810 - No), the processor may perform operation 813 .

In operation 813, the processor may control the memory module to perform a repair operation. For example, the processor may transmit a repair operation signal including information related to the repair operation of the memory module to the memory controller (eg, the memory controller 230 of FIG. 2 ). The memory controller may transmit a control signal (eg, a repair operation signal) for causing the memory module to operate in the repair mode based on the received repair operation signal to the repair control circuit (eg, the repair control circuit 310 of FIG. 3 ). have. The repair control circuit may include a repair address latch unit (eg, the repair address latch unit 412 of FIG. 4 ), an anti-fuse unit (eg, the anti-fuse unit 414 of FIG. 4 ), and/or a repair processing unit (eg, FIG. 4 ). of the repair processing unit 416). In the repair mode, the memory module (eg, the semiconductor memory module 400 of FIG. 4 ) may be set to repair defective memory cells derived as a result of the test operation execution under the control of the repair control circuit 410 . For example, the repair operation may include an operation of allowing the semiconductor memory module 400 to access a redundant memory cell instead of the defective memory cell when an access request for the defective memory cell occurs. As another example, the repair operation may include avoiding an address corresponding to the first memory cell to an address corresponding to the second memory cell when an access request is made to the first memory cell when it is determined that the first memory cell is defective. Thus, an operation of blocking access to the bad memory cell may be included.

In operation 815 , the processor may output information related to a bad memory cell to a display module (eg, the display module 160 of FIG. 1 ) and provide it to the user. For example, when it is determined that the defect degree of the memory module exceeds a specified range, the processor may control to output information related to the defective memory cell to the display module. The information associated with the defective memory cell may include a performance state of the memory module, operation information, A/S information, and/or a degree of deterioration. For reference, the processor may omit operation 815 of outputting information related to the bad memory cell and providing it to the user.

In operation 815, when the defect degree of the memory module exceeds a specified range, information related to the defective memory cell is output and provided to the user. However, embodiments of the present document are not limited thereto. For example, when it is determined that the defect degree of the memory module exceeds a specified range, the processor stores data including information associated with the defective memory cell in the storage module (eg, the storage module 210 of FIG. 2 ). can do. As another example, the processor uses a communication module (eg, the communication module 190 of FIG. 1 ) to transmit data including information related to a bad memory cell to an external electronic device (eg, the electronic device 102 of FIG. 1 ); may be transmitted to the electronic device 104 of FIG. 1 or the server 108 of FIG. 1 .

According to various embodiments of the present document, an electronic device may include a display, a semiconductor memory module, a memory controller, a processor, and a memory operatively connected to the processor.

According to an embodiment, the memory generates a test signal that, when executed, causes the processor to detect a defective memory cell of the semiconductor memory module based on a specified period, and performs a test operation based on the test signal to detect at least one defective memory cell in the memory cell array included in the semiconductor memory module, and when the at least one defective memory cell is detected, store data associated with the at least one defective memory cell in the memory; , one or more instructions for causing the memory controller to generate and transmit a repair signal including data associated with the at least one defective memory cell stored in the memory to the semiconductor memory module.

According to an embodiment, the test signal for detecting a defective memory cell of the semiconductor memory module based on the specified period sets the operating voltage of the semiconductor memory module to be lower than the operating voltage during the normal operation when performing the test operation. It may include information that allows it to be set.

According to an embodiment, the test signal for detecting the bad memory cell of the semiconductor memory module based on the specified period may include information for detecting the bad memory cell after changing and setting an AC timing parameter. have.

According to an embodiment, the test signal for detecting the defective memory cell of the semiconductor memory module based on the specified period may include information for detecting the defective memory cell after changing and setting a refresh parameter. .

According to an embodiment, the test signal for detecting the bad memory cell of the semiconductor memory module based on the specified period may include information for detecting the bad memory cell after changing and setting a polling time. .

According to an embodiment, when the one or more instructions are executed, the processor inputs an address corresponding to the at least one defective memory cell into an address register included in the semiconductor memory module, and the semiconductor memory module A repair operation may be performed based on the received address.

According to an embodiment, the one or more instructions, when executed, cause the processor to detect the at least one bad memory cell in response to an operation in which the semiconductor memory module performs a training function. The test signal may be generated.

According to an embodiment, when the one or more instructions are executed, the processor, when the semiconductor memory module receives the repair signal, replaces the at least one defective memory cell among a plurality of redundancy memory cells. A redundancy memory cell corresponding to the at least one defective memory cell may be accessed.

According to an embodiment, when the processor receives the repair signal from the semiconductor memory module when the one or more instructions are executed, data read from the semiconductor memory module is stored in the at least one defective memory cell. When included, access to the at least one bad memory cell may be blocked or avoided by using a memory management unit (MMU).

According to an embodiment, when the processor determines that the degree of failure of the semiconductor memory module exceeds a specified range at the time of execution of the one or more instructions, information associated with a defective memory cell is displayed in the display module may be displayed, and the information associated with the defective memory cell may include at least one of a performance state of the semiconductor memory module, operation information, A/S information, and a degree of failure.

According to various embodiments of the present disclosure, a method for providing a function for an electronic device to repair a semiconductor memory module includes: generating a test signal to detect a defective memory cell of the semiconductor module based on a specified period; detecting at least one defective memory cell in the memory cell array included in the semiconductor memory module by performing a test operation based on the test signal; when the at least one defective memory cell is detected, the at least one defective storing data related to a memory cell in the memory, and generating a repair signal including data related to the at least one defective memory cell stored in the memory using a memory controller and transmitting it to the semiconductor module can do.

According to an embodiment, the generating of the test signal for detecting the defective memory cell of the semiconductor module based on the specified period corresponds to the operation of the semiconductor memory module performing a training function. and generating the test signal to detect one bad memory cell.

According to an embodiment, in the method for providing the function of the electronic device to repair a semiconductor memory module, when the semiconductor memory module receives the repair signal, a plurality of redundancy memories are replaced by the at least one defective memory cell. The method may further include accessing a redundancy memory cell corresponding to the at least one defective memory cell among cells.

According to an embodiment, in the method of the electronic device performing a function of repairing a semiconductor memory module, the semiconductor memory module receives the repair signal, and data read from the semiconductor memory module is transmitted to the at least one defective memory. When included in the cell, the operation of blocking or avoiding access to the at least one bad memory cell by using a memory management unit (MMU) may be further included.

According to an embodiment, in the method of the electronic device performing a function of repairing a semiconductor memory module, when it is determined that the defect degree of the semiconductor memory module exceeds a specified range, the display module is associated with a defective memory cell. The method may further include displaying information, wherein the information related to the defective memory cell may include at least one of a performance state of the semiconductor memory module, operation information, A/S information, and a degree of failure. .

Meanwhile, the method for providing a camera preview according to various embodiments of the present document described above may be stored in a non-transitory readable medium. Such a non-transitory readable medium may be mounted on various devices and used.

Here, the non-transitory readable recording medium refers to a medium that stores data semi-permanently and can be read by a device, rather than a medium that stores data for a short moment, such as a register, a cache, or a memory. Specifically, the above-described programs may be provided by being stored in a non-transitory readable recording medium such as a CD, DVD, hard disk, Blu-ray disk, USB, memory card, ROM, and the like.

Claims (20)

In an electronic device,
display;
semiconductor memory module;
memory controller;
processor; and
a memory operatively coupled to the processor, wherein the memory, when executed, causes the processor to:
generating a test signal to detect defective memory cells of the semiconductor memory module based on a specified period;
detecting at least one defective memory cell in a memory cell array included in the semiconductor memory module by performing a test operation based on the test signal;
When the at least one defective memory cell is detected, data associated with the at least one defective memory cell is stored in the memory;
The memory controller stores one or more instructions for generating a repair signal including data associated with the at least one defective memory cell stored in the memory and transmitting the generated repair signal to the semiconductor memory module.
The method according to claim 1,
The test signal for detecting the defective memory cell of the semiconductor memory module based on the specified period includes information for setting the operating voltage of the semiconductor memory module to be lower than the operating voltage for the normal operation when performing the test operation which is an electronic device.
The method according to claim 1,
The test signal for detecting the bad memory cell of the semiconductor memory module based on the specified period includes information for detecting the bad memory cell after changing and setting an AC timing parameter.
The method according to claim 1,
The test signal for detecting the defective memory cell of the semiconductor memory module based on the specified period includes information for detecting the defective memory cell after changing and setting a refresh parameter.
The method according to claim 1,
The test signal for detecting the defective memory cell of the semiconductor memory module based on the specified period includes information for detecting the defective memory cell after changing and setting a polling time.
The method according to claim 1,
The one or more instructions, when executed, cause the processor to:
inputting an address corresponding to the at least one defective memory cell into an address register included in the semiconductor memory module;
causing the semiconductor memory module to perform a repair operation based on the received address.
The method according to claim 1,
The one or more instructions, when executed, cause the processor to:
and generate the test signal for detecting the at least one defective memory cell in response to an operation of the semiconductor memory module performing a training function.
The method according to claim 1,
The one or more instructions, when executed, cause the processor to:
and when the semiconductor memory module receives the repair signal, accesses a redundancy memory cell corresponding to the at least one defective memory cell among a plurality of redundancy memory cells instead of the at least one defective memory cell.
The method according to claim 1,
The one or more instructions, when executed, cause the processor to:
When the semiconductor memory module receives the repair signal, when the data read from the semiconductor memory module is included in the at least one defective memory cell, it is stored in the at least one defective memory cell using a memory management unit (MMU). An electronic device to block or avoid access to.
The method according to claim 1,
The one or more instructions, when executed, cause the processor to:
When it is determined that the defect degree of the semiconductor memory module exceeds a specified range, display information related to the defective memory cell on the display;
The information associated with the defective memory cell may include at least one of a performance state of the semiconductor memory module, operation information, A/S information, and a degree of failure.
A method for providing a function for an electronic device to repair a semiconductor memory module, comprising:
generating a test signal to detect a defective memory cell of the semiconductor module based on a specified period;
detecting at least one defective memory cell in a memory cell array included in the semiconductor memory module by performing a test operation based on the test signal;
storing data related to the at least one defective memory cell in the memory when the at least one defective memory cell is detected; and
generating a repair signal including data associated with the at least one defective memory cell stored in the memory using a memory controller and transmitting the repair signal to the semiconductor module; A method comprising
12. The method of claim 11,
The test signal for detecting the defective memory cell of the semiconductor memory module based on the specified period includes information for setting the operating voltage of the semiconductor memory module to be lower than the operating voltage for the normal operation when performing the test operation How to.
12. The method of claim 11,
The test signal for detecting the bad memory cell of the semiconductor memory module based on the specified period includes information for detecting the bad memory cell after changing and setting an AC timing parameter.
12. The method of claim 11,
The test signal for detecting the defective memory cell of the semiconductor memory module based on the specified period includes information for detecting the defective memory cell after changing and setting a refresh parameter.
12. The method of claim 11,
The test signal for detecting the bad memory cell of the semiconductor memory module based on the specified period includes information for detecting the bad memory cell after changing and setting a polling time.
12. The method of claim 11,
inputting an address corresponding to the at least one defective memory cell into an address register included in the semiconductor memory module; and
executing, by the semiconductor memory module, a repair operation based on the received address; A method further comprising
12. The method of claim 11,
The operation of generating a test signal for detecting a defective memory cell of the semiconductor module based on the specified period includes:
generating the test signal for detecting the at least one defective memory cell in response to the operation of the semiconductor memory module performing a training function; A method comprising
12. The method of claim 11,
when the semiconductor memory module receives the repair signal, accessing a redundancy memory cell corresponding to the at least one defective memory cell from among a plurality of redundancy memory cells in place of the at least one defective memory cell; A method further comprising:
12. The method of claim 11,
When the semiconductor memory module receives the repair signal and the data read from the semiconductor memory module is included in the at least one defective memory cell, it is stored in the at least one defective memory cell using a memory management unit (MMU). an operation to block or avoid access to; A method further comprising:
12. The method of claim 11,
displaying information related to the defective memory cell on the display when it is determined that the defect degree of the semiconductor memory module exceeds a specified range; further comprising,
The information associated with the defective memory cell may include at least one of a performance state of the semiconductor memory module, operation information, after-sales service information, and a degree of failure.

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