KR20210148852A - Host controller interface using multiple circular queue, and operating method thereof - Google Patents

Abstract

A host controller interface configured to provide interfacing between a host device and a storage device is disclosed. The host controller interface according to an exemplary embodiment of the technical idea of the present disclosure includes: a doorbell register configured to store a head pointer and a tail pointer of at least one queue; an entry buffer configured to store a first command or a first response included in the at least one queue; an arbiter configured to arbitrate the order of the at least one queue; a first router configured to route the first command to be stored in the entry buffer in an order; and a second router configured to route the first response to be stored in the doorbell register.

Description

HOST CONTROLLER INTERFACE USING MULTIPLE CIRCULAR QUEUE, AND OPERATING METHOD THEREOF

The technical idea of the present disclosure relates to a host controller interface that transmits a command to a storage device, and more particularly, to a host controller interface having a bitmap-based doorbell structure and using multiple circular queues. .

Interface used in storage systems based on storage devices (e.g. solid state drives; SSDs); Serial ATA (SATA), Peripheral Component Interconnect Express (PCIe), Serial Attached SCSI (SAS), embedded MMC (eMMC) , and UFS (Universal Flash Strage) are used. Storage devices are gradually improving, and the amount of data being processed at the same time is also increasing. However, an interface such as SATA is not an interface specialized for storage devices such as SSD, and therefore has a fundamental limitation.

Recently, as part of an effort to create a standardized interface that can be applied to data storage devices, NVMe (Non-Volatile Memory Express) and UFS were born. NVMe can provide a function of direct memory access to storage devices (or non-volatile memories) connected through a PCIe bus, and UFS can provide the M-PHY and It is a structure adopting UniPro.

When a single bitmap doorbell is shared by a plurality of cores, resource occupation overhead may occur, thereby degrading the overall system performance. For example, according to the UFS standard, when any one of a plurality of cores accesses the bitmap doorbell, other cores cannot access the bitmap doorbell.

SUMMARY OF THE INVENTION An object of the technical spirit of the present disclosure is to provide a host controller interface having a bitmap-based doorbell structure and using multiple circular queues, and an operating method thereof.

In order to achieve the above object, the host controller interface configured to provide interfacing between the host device and the storage device according to an exemplary embodiment of the present disclosure is a doorbell configured to store a head pointer and a tail pointer of at least one queue a register, an entry buffer configured to store a first command or a first response included in the at least one queue, an arbiter configured to arbitrate an order of the at least one queue, according to an order, the first command is stored in the entry buffer a first router configured to route to be stored and a second router configured to route such that the first response is stored to the doorbell register.

A storage system according to an exemplary embodiment of the present disclosure includes a host device and a storage device, wherein the host device transmitting a command to the storage device includes a host memory that stores at least one queue, and the at least one a host controller comprising at least one core configured to process a queue, and a host controller interface configured to provide interfacing with the host memory, wherein the storage device is a result of performing a memory operation based on the command. A response may be provided to the host device, and the host controller interface may include a doorbell register configured to store a head pointer and a tail pointer for the at least one queue.

An operating method of a host controller interface configured to provide interfacing between a host device and a storage device using at least one queue including at least one command according to an exemplary embodiment of the present disclosure includes a first command included in a first queue Arbitrating the order of a plurality of commands comprising: storing the first command in an entry buffer; updating a first head pointer of the first queue; , updating a second head pointer of a second queue including the second command, and sequentially providing the first command and the second command to the storage device.

Since the host controller interface according to the technical idea of the present disclosure can use a multi-circular queue, it is possible to solve an overhead caused by a problem of occupying a shared resource between a plurality of cores and maximize performance.

In addition, in using the multi-circular queue, the host controller interface according to the technical idea of the present disclosure maintains the bitmap-based doorbell structure applied to UFS as it is, but additionally uses an arbiter and a router to improve the interface between HCI and storage. Structural change can be minimized, and compatibility with existing devices can be maintained.

In addition, according to the host controller interface according to the technical spirit of the present disclosure, an overhead caused by multiple cores occupying a resource may be reduced and data processing performance may be improved.

1 is a block diagram illustrating a storage system according to an exemplary embodiment of the present disclosure.
FIG. 2 is a block diagram illustrating an implementation example of the host device shown in FIG. 1 .
FIG. 3 is a block diagram illustrating an example implementation of the storage controller illustrated in FIG. 1 .
4 is a block diagram illustrating an implementation example of a storage system to which a UFS interface is applied.
5 is a diagram illustrating an operation of a storage system according to an exemplary embodiment of the present disclosure.
6 is a flowchart illustrating a method of operating a host device according to an exemplary embodiment of the present disclosure.
7 is a block diagram illustrating a storage system to which a command is written according to an exemplary embodiment of the present disclosure.
8 is a block diagram illustrating a storage system to which a response is written according to an exemplary embodiment of the present disclosure.
9 is a diagram illustrating a process in which a command is written into a circular queue according to an exemplary embodiment of the present disclosure.
10 is a flowchart illustrating a method of operating a storage system according to an exemplary embodiment of the present disclosure.
11 and 12 are block diagrams illustrating examples of various types of information stored in a host memory and a register in the host controller.
13 is a diagram illustrating an implementation example of a data read operation and a packet according to a UFS interface.
14A and 14B are diagrams illustrating the structure of a packet according to an exemplary embodiment of the present disclosure.
15 is a diagram illustrating a system to which a storage device according to an exemplary embodiment of the present disclosure is applied.
16 is a diagram for explaining a UFS system according to an exemplary embodiment of the present disclosure.
17A to 17C are diagrams for explaining a form factor of a UFS card according to an exemplary embodiment of the present disclosure.
18A is a block diagram illustrating a host-storage system according to an exemplary embodiment of the present disclosure, and FIGS. 18B to 18E are detailed block diagrams of the configurations of FIG. 18A .
19 is a block diagram illustrating a memory system according to an exemplary embodiment of the present disclosure.
20 is a block diagram illustrating a memory system according to an exemplary embodiment of the present disclosure.
21 is a block diagram illustrating a memory device according to an exemplary embodiment of the present disclosure.
22 is a diagram for explaining a 3D V-NAND structure applicable to a UFS device according to an exemplary embodiment of the present disclosure.
23 is a cross-sectional view illustrating a memory device according to an exemplary embodiment of the present disclosure.
24 is a diagram illustrating a data center to which a host storage system according to an exemplary embodiment of the present disclosure is applied.

Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a storage system 10 according to an exemplary embodiment of the present disclosure.

The storage system 10 may include a host device 100 and a storage device 200 .

Many standards are being developed or are currently being developed for smooth data transmission between the host device 100 and the storage device 200 . As one of the standard specifications, Universal Flash Storage (UFS) has been developed by the Joint Electron Device Engineering Council (JEDEC) for flash memory-based storage in mobile devices such as smart phones and tablet computers. UFS employs a command protocol and Small Computer System Interface (SCSI) architectural model that supports multiple commands with the characteristics of a command queue, thereby enabling a multi-threaded programming paradigm.

Another standard developed by JEDEC is the eMMC (embedded MultiMediaCard) standard. eMMC can provide simplified application interface design, small package size and low power consumption. eMMC flash memory based storage devices are currently one of the main forms of storage in mobile devices.

The storage system 10 according to the technical spirit of the present disclosure may use standard standards for flash memory-based storage devices such as UFS and eMMC. However, the present embodiment is not limited thereto.

The storage system 10 may include, for example, a desktop computer, and a personal computer (PC), including a desktop computer, and a laptop computer, a data server, a network-attached storage (NAS), It may be implemented as an Internet of Things (IoT) device, a workstation, a server, an electric vehicle, or a portable electronic device. Portable electronic devices include laptop computers, mobile phones, smart phones, tablet PCs, personal digital assistants (PDAs), enterprise digital assistants (EDAs), digital still cameras, digital video cameras, audio devices, PMPs (portable multimedia players), PNDs. (personal navigation device), an MP3 player, a handheld game console, an e-book, and/or a wearable device may be included.

The storage system 10 may store or retrieve data from the storage device 200 according to a command CMD of the host device 100 . In an exemplary embodiment, the host device 100 may provide data to be written to the storage device 200 , and may read data by receiving a response RESP from the storage device 200 . can According to an exemplary embodiment, the host device 100 may issue a command CMD and transmit it to the storage device 200 , and the storage device 200 reads, erases, or writes data according to the command CMD. , and as a result, a response RESP may be generated and provided to the host device 100 .

The command CMD may be included in the command packet PACKET_C and managed, and the response RESP may be included and managed in the response packet PACKET_R. The structure of the packet will be described in detail with reference to FIGS. 14A and 14B.

The host device 100 may include a host controller 110 and a host memory 130 .

The host device 100 may provide various services to a user of the host device 100 according to operations of one or more electronic circuits, chips, and devices. According to an exemplary embodiment, the host device 100 may perform various operations to process a command received from the user of the host device 100 and provide the operation result to the user of the host device 100 . can The host device 100 according to an exemplary embodiment may include an operating system, an application, and the like. The host device 100 according to an exemplary embodiment of the present disclosure may include a UFS host control driver for supporting a Universal Flash Storage (UFS) protocol. However, the present disclosure is not limited thereto, and the host device 100 may include a driver for supporting an embedded Multi-Media Card (eMMC) protocol or a Non Volatile Memory express (NVMe) protocol.

The host controller 110 may control the overall operation of the host device 100 , more specifically, the operations of other components constituting the host device 100 . In an exemplary embodiment, the host controller 110 may be implemented as a general-purpose processor, a dedicated processor, or an application processor. In addition to this, the host controller 110 includes an operation processor (eg, a central processing unit (CPU), a GPU) including a dedicated logic circuit (eg, field programmable gate array (FPGA), application specific integrated circuits (ASICs), etc.) (Graphic Processing Unit), AP (Application Processor), etc.), but is not limited thereto.

The host controller 110 may execute various software loaded into the host memory 130 . For example, the host controller 110 may execute an operating system (OS) and applications (applications).

The host controller 110 may generate a command CMD according to a user's request and determine whether to transmit the command CMD to the storage device 200 . Also, the host controller 110 may receive a response RESP. In an exemplary embodiment, the host controller 110 may write the command CMD and/or the response RESP to or remove it from a queue that is a processing queue.

The host controller 110 may include one or more cores, and may further include another intelligent property (IP) for controlling the memory and/or the storage device 200 . According to an exemplary embodiment, the core may execute a queue that is a processing queue of a command CMD and a response RESP processed by the host device 100 . According to an exemplary embodiment, the host controller 110 may further include an accelerator, which is a dedicated circuit for high-speed data operation such as artificial intelligence (AI) data operation, and the accelerator includes a graphics processing unit (GPU), a neural processing unit (NPU), etc. unit) and/or a data processing unit (DPU), and may be implemented as a separate chip physically independent from other components of the host controller 110 .

The host controller 110 may include a host controller interface (HCI), which stores data (eg, write data) of the host memory 130 in the non-volatile memory 230 . Alternatively, an operation of storing data (eg, read data) of the nonvolatile memory 230 in the host memory 130 may be managed. Also, the storage controller 210 may include a device controller interface (not shown) for an interface with the host controller 110 .

The submission queue SQ may refer to a queue in which various types of events including a request and a command CMD of the host device 100 are waiting to be processed. The command CMD stored in the submission queue SQ may be fetched by the host controller 110 and transmitted to the storage device 200 . The completion queue CQ may refer to a column for processing various types of events including a request of the storage device 200 and a response RESP. The response RESP stored in the completion queue CQ is fetched by the host controller 110, and thus meta data to be processed by the host after a memory operation (eg, writing, reading, or erasing data) is completed. can be ordered to update. The submission queue SQ and the completion queue CQ may be generated in the host memory 130 of the host device 100 . In the present disclosure, for convenience of description, it has been exemplified that the submission queue and the completion queue are implemented as a circular queue, but the present disclosure is not limited thereto.

According to an exemplary embodiment of the present disclosure, the host controller 110 may include a doorbell register. The doorbell register is a register allocated to manage a Submission Queue (SQ) and a Completion Queue (CQ). For example, the host controller 110 accesses the submission queue SQ and the completion queue CQ through the doorbell register, and thus the submission queue SQ and the completion queue with the host memory 130 . An interface operation for (CQ) may be performed. According to an exemplary embodiment, the doorbell register may be included in the host controller interface.

The doorbell register according to an exemplary embodiment of the present disclosure may manage or control a queue pair generated by the host device 100 . The doorbell register may correspond to one cue pair. According to an exemplary embodiment, the head pointer HP and the tail pointer TP of the doorbell register queue may be stored. For example, the doorbell register may store a tail pointer TP indicating the tail of the submission queue and a head pointer HP indicating the head of the completion queue.

In the present disclosure, a doorbell register related to the submission queue SQ is referred to as an SQ doorbell register, and a doorbell register related to the completion queue CQ is referred to as a CQ doorbell register, respectively. Also, a data structure in which a doorbell corresponding to one cue pair is expressed as a bitmap that is a set of 1-bit data spaces is referred to as a bitmap doorbell. According to an exemplary embodiment of the present disclosure, an SQ doorbell register, a CQ doorbell register, and a bitmap doorbell may be managed by a host controller interface. The host controller interface is described in more detail in FIG. 5 .

The host memory 130 may be used as a main memory or a cache memory. Also, the host memory 130 may be used as a driving memory for driving software, an application, or firmware. Programs or data to be processed by the host controller 110 may be loaded into the host memory 130 . For example, the host memory 130 may be loaded with a file system, applications and device drivers. The file system may provide a logical address according to a command (eg, a write command or a read command) to the storage device 200 . The file system may be used according to a specific operating system running on the host device 200 . The file system may be implemented through software, an application, or firmware. For example, the host device 200 may execute Windows, Linux, Unix, or the like.

The host memory 130 may load a submission queue SQ and a completion queue CQ used for an interfacing operation between the host device 100 and the storage device 200 . The submission queue SQ may store a command CMD to be provided to the storage device 200 , and the completion queue CQ may receive a response RESP that is completion information for an operation completed in the storage device 200 . can be saved

According to an exemplary embodiment of the present disclosure, the submission queue SQ and the completion queue CQ loaded by the host memory 130 may be referenced by the host controller 110 . For example, the host controller 110 may write a command CMD or a response RESP to the submission queue SQ by referring to the tail pointer TP, and the command (CMD) by referring to the head pointer HP. CMD) or response (RESP) may be read from the completion queue (CQ). For example, after the command CMD or the response RESP is written in the submission queue SQ or the completion queue CQ, the host controller 110 TAIL to indicate the next empty space. value can be increased. An operation in which the command CMD or the response RESP is written to or read from the queue will be described in more detail with reference to FIG. 9 .

According to an exemplary embodiment, the host controller 110 and the host memory 130 may be implemented as separate semiconductor chips. Alternatively, in some embodiments, the host controller 110 and the host memory 130 may be integrated on the same semiconductor chip. As an example, the host controller 110 may be any one of a plurality of modules included in an application processor, and the application processor may be implemented as a system on chip (SoC). In addition, the host memory 130 may be an embedded memory provided in the application processor or a memory device or memory module disposed outside the application processor.

The host device 100 may further include various devices related to driving of the storage device 200 . As an example, a software module (not shown) such as a host application and a device driver may be further provided, and the software module may be loaded into the host memory 130 and executed by a processor (not shown).

The storage device 200 may include a storage controller 210 and a non-volatile memory device (NVM) 230 . The non-volatile memory 230 may include a non-volatile memory core (NVM Core).

The storage device 200 may include storage media for storing data according to a request from the host device 100 . As an example, the storage device 200 may include one or more solid state drives (SSDs). When the storage device 200 includes a solid state drive, the storage device 200 may include a plurality of flash memory chips (eg, NAND memory chips) that non-volatilely store data.

According to an exemplary embodiment, the storage device 200 may correspond to a flash memory device including one or more flash memory chips. The flash memory device may be a non-volatile data storage medium to which data may be electrically written to and erased from. In an exemplary embodiment, the storage device 200 may be an embedded memory embedded in the storage system 10 . For example, the storage device 200 may be an Emmc or embedded UFS memory device. In an exemplary embodiment, the storage device 200 may be an external memory that is removable to the storage system 10 . For example, the storage device 200 may be a UFS memory card, Compact Flash (CF), Secure Digital (SD), Micro-SD (Micro Secure Digital), Mini-SD (Mini Secure Digital), xD (extreme Digital) or It may include various flash memory-based storage devices, including memory sticks, solid state drives (SSDs), and universal serial bus (USB) flash drives.

When the storage device 200 includes a flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. The 3D memory array is a monolithic array of memory cells having an active region disposed over a silicon substrate, or at least one physical level of circuitry formed on or within the substrate as circuitry associated with the operation of the memory cells. is formed with The term "monolithic" means that the layers of each level constituting the array are stacked directly on top of the layers of each lower level of the array.

In an exemplary embodiment, the 3D memory array includes vertical NAND strings arranged in a vertical direction such that at least one memory cell is positioned on top of another memory cell. The at least one memory cell may include a charge trap layer.

U.S. Patent Publication Nos. 7,679,133, 8,553,466, 8,654,587, 8,559,235, and U.S. Patent Application Publication No. 2011/0233648 disclose that a 3D memory array is constructed in multiple levels and contains word lines and/or Those detailing suitable configurations for a 3D memory array in which bit lines are shared between levels, are incorporated herein by reference.

As another example, the storage device 200 may include other various types of non-volatile memories. For example, the storage device 200 includes a magnetic RAM (MRAM), a spin-transfer torque MRAM (MRAM), a conductive bridging RAM (CBRAM), a ferroelectric RAM (FeRAM), a phase RAM (PRAM), a resistive memory ( Resistive RAM) and various other types of memory may be applied.

The storage controller 210 may control overall operations of the storage device 200 . For example, the storage controller 210 may schedule operations of the nonvolatile memory 230 or encode and decode signals/data processed in the storage device 200 . In an exemplary embodiment, the storage controller 210 may control the nonvolatile memory 230 to write, read, or erase data in the nonvolatile memory 230 .

The non-volatile memory 230 may include storage media for storing data according to a request from the host device 100 . As described above, the non-volatile memory 230 may include at least one flash memory chip that non-volatilely stores data, and may include a NAND or VNAND memory array in an exemplary embodiment.

The host device 100 and the storage device 200 may communicate with each other through various types of interfaces. As an example, the host device 100 and the storage device 200 may include universal flash storage (UFS), serial ATA (SATA), small computer small interface (SCSI), serial attached SCSI (SAS), and embedded Multi Media Card (eMMC). ) can be connected via standard interfaces such as The host device 100 and the storage device 200 may each generate a packet according to a protocol of an adopted interface and transmit it. In the example of FIG. 1 , a command packet (PACKET_C) generated by the host device 100 and transmitted to the storage device 200, and a response packet (PACKET_R) generated by the storage device 200 and transmitted to the host device 100 This is exemplified.

According to the spirit of the present disclosure, the host device 100 directly controls the SQ doorbell register, the CQ doorbell register, the bitmap doorbell, and the arbitration and routing of SQ and CQ, so that the computing of the host device 100 is performed. It can solve the resource occupation problem and maximize performance.

FIG. 2 is a block diagram illustrating an example implementation of the host device 100 illustrated in FIG. 1 . In the example of FIG. 2 , an application processor (AP) including a host controller 110 is illustrated. Hereinafter, the host device 100 will be described using an application processor (AP), but the technical idea of the present disclosure is not limited to being implemented as an application processor (AP), and various host devices capable of providing host-slave functions. It should be understood that (100) can be applied.

Referring to FIG. 2 together with FIG. 1 , the host device 100 includes an application processor (AP) and a host memory 130, and the application processor (AP) configures one or more modules as an intelligent device (Intellectual Property, IP). may include In an exemplary embodiment, the application processor (AP) includes a host controller 110 , at least one core 120 , a host memory controller 140 , a modem 150 , an embedded memory 160 , a camera interface 170 , and a display interface 170 . The host controller 110 , at least one core 120 , the host memory controller 140 , the modem 150 , the embedded memory 160 , the camera interface 170 , and the display interface 170 are connected to each other through an internal bus. Signals can be sent and received. The host controller 110 may include a register 111 and a host controller interface (HCI) 190 .

In FIG. 2 , the host memory 130 is illustrated as an external memory of the application processor AP, but the embodiment of the present disclosure is not limited thereto. For example, the embedded memory 160 inside the application processor (AP) may be used as the host memory 130 in the above-described embodiment. Meanwhile, the components illustrated in FIG. 2 are only one embodiment, and the application processor (AP) may further include other components in addition to the components illustrated in FIG. 2 , or some of the components illustrated in FIG. 2 . may not be provided in the application processor (AP).

At least one core 120 may control the overall operation of the application processor (AP). As an example, software (eg, an application processor and a device driver) for managing data write/read operations for the storage system 10 is loaded into the host memory 130 or the embedded memory 160 , and the core 120 ) can manage data write/read operations by executing software. The host memory 130 may be implemented as a volatile memory or a non-volatile memory, and according to an embodiment, the host memory 130 is a volatile memory such as dynamic random access memory (DRAM) and/or static random access memory (SRAM). may include

At least one core 120 may be a homogeneous multi-core processor or a heterogeneous multi-core processor.

According to an exemplary embodiment of the present disclosure, if the at least one core 120 includes a plurality of cores, different cores may perform a task that is a processing unit of a job by running different software. For example, a first core may perform a first task, and a second core that is the same as or different from the first core may perform a second task. The plurality of cores may have a dedicated queue for each core. For example, the first core uses the first submission queue and the first completion queue, and the second core uses the second submission queue and the second completion queue, respectively, so that different tasks can be executed in parallel. can be done with

According to an exemplary embodiment, the application processor AP may perform a camera control operation, a display control operation, and a modem operation. As the modem 150 is included in the application processor (AP), the application processor (AP) may be referred to as a ModAP.

The host controller 110 may transmit/receive a packet PACKET including a command CMD or a response RESP to and from the storage device 200 according to the above-described embodiment. The host controller 110 may include a register 111 that stores one or more transmission requests.

According to an exemplary embodiment, transmission requests related to writing and/or reading from the storage device may be stored in the register 111 based on the control of the core 120 . In addition, various types of information for generating a packet (PACKET) corresponding to the transmission requests based on the control of the core 120 may be stored in the host memory 130, for example, depending on the type of the packet (PACKET). Table information including related information and the address ADDRESS may be stored in the host memory 130 . In addition, in the case of a data write request, write data may be stored in a plurality of data buffers of the host memory 130 based on the control of the core 120 . The host controller 110 may check the transmission requests stored in the internal register 111 and interface with the storage device based thereon.

As in the aforementioned embodiment, the host controller 110 receives a response packet PACKET_R including a response RESP from the storage device ( FIGS. 1 and 200 ), and receives a response RESP from the received packet PACKET. , and it is possible to check whether the memory operation is processed according to the parsed response RESP.

The host controller interface 190 converts or exchanges data formats such as commands (eg, read commands, write commands, etc.) corresponding to various access requests issued by the host device 100 , logical addresses, and data. By converting the format of , the host device 100 may be connected to the storage device 200 . Protocols applied to the host controller interface 190, in addition to the above-described UFS and eMMC, USB (Universal Serial Bus), SCSI (Small Computer System Interface), PCIe (Peripheral Component Interconnect express), ATA (Advanced Technology Attachment), PATA ( Parallel ATA), SATA (Serial ATA), or SAS (Serial Attached SCSI). However, the present invention is not limited thereto, and various standard specifications supporting interfacing between different devices may be applied.

According to an exemplary embodiment of the present disclosure, the host controller interface 190 includes the host controller interface 190, the SQ doorbell register, SQ arbiter, bitmap doorbell router, bitmap doorbell entry, CQ router, CQ door It may include a bell register. A detailed configuration included in the host controller interface 190 will be described in more detail with reference to FIG. 5 .

3 is a block diagram illustrating an example implementation of the storage controller 210 illustrated in FIG. 1 .

1 and 3 , the storage controller 210 may include a host interface 211 , a central processing unit (CPU) 212 as a processor, and a memory interface 216 . In addition, the storage controller 210 may further include a Flash Translation Layer (FTL) 213 , a packet manager 214 , and a buffer manager 215 . The storage controller 210 may further include a working memory (not shown) into which the flash conversion layer 213 is loaded. When the central processing unit 212 executes the flash translation layer 213 , data writing and reading operations to and from the memory core may be controlled.

The host interface 211 may transmit and receive packets PACKET to and from the host device 100 , and according to the above-described embodiment, the packet PACKET transmitted/received by the host interface 211 may be stored in a buffer area within the host device 100 . A buffer address indicating the location of the data buffer may be included. Also, the memory interface 216 may perform an operation of writing or reading data by interfacing with the memory core.

The packet manager 214 may generate a packet (PACKET) according to a protocol of an interface negotiated with the host device 100 or parse various types of information from the received packet (PACKET). Also, the buffer manager 215 may manage an operation of storing various types of information parsed from the packet PACKET in a buffer, and as an example, storing a command CMD or a response RESP parsed from the packet PACKET You can manage your actions.

The buffer manager 215 may manage an operation of storing the write data parsed from the packet PACKET in the buffer, and may manage the operation of storing the data read from the memory core in the buffer. According to an embodiment, the buffer manager 215 may be a buffer memory 215 provided in the storage controller 210 . According to an embodiment, the buffer manager 215 may manage a buffer provided in addition to the storage controller 210 .

For example, during a data write operation, a write command CMD and a first buffer address corresponding thereto may be parsed from a packet PACKET received from the host device 100 , and the first buffer address is the storage device 200 . ) can be stored in the buffer. As a response to the write command, the storage device 200 may generate a packet PACKET including a response RESP requesting transmission of write data in a unit of a predetermined size. In this case, the first buffer address corresponding to the write command may be included in the packet PACKET, and the host device 100 refers to the response RESP and the first buffer address included in the packet PACKET. , the write data stored in the data buffer at the position indicated by the first buffer address may be transmitted to the storage device 200 .

Similarly, taking the data read operation as an example, the read command CMD and a second buffer address corresponding thereto are parsed from the packet PACKET received from the host device 100 , and the second buffer address is the storage device 200 . ) can be stored in the buffer. The storage device 200 generates a packet PACKET including read data in response to the read command CMD, and a second buffer address corresponding to the read command is stored in the packet PACKET together with the response RESP. may be included. Also, the host device 100 may refer to the response RESP and the second buffer address included in the packet PACKET, and store the read data in the data buffer at the location indicated by the second buffer address.

The host interface 211 , the central processing unit 212 , the flash translation layer 213 , the packet manager 214 , the buffer manager 215 , and the memory interface 216 in FIG. 3 will be described again in FIG. 18A . do.

4 is a block diagram illustrating an implementation example of the storage system 20 to which the UFS interface is applied. The storage system 10 of FIG. 1 may be applied to the storage system 20 of FIG. 4 .

Referring to FIG. 4 together with FIG. 1 , the UFS host of the storage system 20 and the UFS storage device may communicate according to the UFS interface, and the UFS host includes a host memory 21, a software module ( 23), and a UFS host controller 25 corresponding to a hardware module. Since the host memory 21 may provide a function similar to that of the host memory 130 described with reference to FIGS. 1 and 2 , a redundant description will be omitted. In FIG. 4 , a host device ( FIGS. 1 and 100 ) interfaced by adopting the UFS standard is abbreviated as a UFS host, and a storage device ( FIGS. 1 and 200 ) interfaced by adopting the UFS standard is abbreviated as a UFS device.

The software module 23 may include software (eg, an application) and a UFS host controller driver. The software can be various applications running on the UFS host, and the UFS host controller driver is for managing the operation of peripheral devices connected to the UFS host, and data management operations such as writing and reading data to and from the storage device are This can be done by running the host controller driver. The application software and the UFS host controller driver may be loaded into the host memory 21 or other working memory in the UFS host and executed by the processor.

The UFS host controller 25 may be an implementation example of the host controller 110 of FIG. 2 . The UFS host controller 25 may include a UFS host controller interface (UFS HCI), a UTP protocol engine, and a UFS interconnect layer (UFS Interconnect Layer (UIC)).

The UFS Host Controller Interface (UFS HCI) may receive a request generated through the UFS Host Controller Driver and forward it to the UTP Protocol Engine, or may provide the data access result transmitted from the UTP Protocol Engine to the UFS Host Controller Driver.

The UTP protocol engine may provide services for an upper layer (or an application layer), and may parse information therein by generating a packet or releasing a packet as an example.

The UFS interconnect layer may communicate with the UFS storage device 27 , and as an example, the UFS interconnect layer may include a link layer and a physical layer (PHY Layer). The link layer may be a Mobile Industry Processor Interface (MIPI) UniPro, and the physical layer may be a MIPI M-PHY. Also, according to the UFS interface, the UFS host may provide a reference clock (Ref Clock) and a reset signal (Reset) signal to the UFS storage device 27 .

Meanwhile, the UFS storage device 27 may include a storage controller and a memory core. According to an embodiment, in FIG. 4 , the storage controller may include a UFS interconnect layer, a UTP protocol engine, and a UFS storage device interface. Also, the memory core may be a core (NVM Core) including non-volatile memory.

In the structure in which the UFS host controller 25 and the UFS storage device 27 communicate, data transmission/reception according to a request from the UFS host controller driver may be performed through the UFS host controller interface. As an example, during a data write operation, write data is stored in a data buffer of the host memory 21 by the software module 23 , and the UFS host controller interface Buffer), and the accessed write data may be transferred to the UFS storage device 27 . A command CMD for a data transmission/reception operation may be stored in a queue. In an exemplary embodiment, when a circular queue is used, the head pointer HP and the tail pointer TP in which commands are stored may be stored in the host memory 21 . For example, the head pointer HP and the tail pointer TP may be stored in a doorbell register of the host memory 21 .

According to an exemplary embodiment of the present disclosure, the command packet (PACKET_C) transmitted from the UFS host to the UFS storage device 27 and/or the response packet (PACKET_R) transmitted from the storage device 200 to the host device 100 includes: A buffer address indicating a location of a data buffer in the host memory 21 may be included. The buffer address may correspond to a physical address indicating the location of the data buffer. As an example, table information (eg, Physical Region Description Table (PRDT)) including buffer addresses may be stored in one region of the host memory 21 , and the UTP protocol engine of the UFS host uses the PRDT to store the buffer address. may be checked, and a command packet PACKET_C including the confirmed buffer address may be generated. Also, the UTP protocol engine of the storage device 200 may generate a response packet PACKET_R including a buffer address stored and managed in the storage device 200 .

In addition, the UFS host controller 25 and the UFS storage device 27 are connected in the form of port-mapped I/O, and write and read operations can be processed in a multi-task manner. have. Accordingly, the UFS storage device 27 may store and manage a plurality of commands parsed from a plurality of packets and buffer addresses corresponding thereto.

As the UFS interface is applied, various types of packets may be defined, and embodiments of the present disclosure may be applied to at least some of the various types of packets.

In an exemplary embodiment, a packet according to the UFS interface may be defined as a UFS Protocol information unit (UPIU), and as its types, a command UPIU (Command UPIU) for write and read requests, a Response UPIU (UPIU), and read data Packets such as Data_In UPIU including write data, Data_Out UPIU including write data, task management request UPIU (TM Request UPIU), and data transfer request UPIU (Ready To Transfer (RTT) UPIU) may be defined.

Also, according to an exemplary embodiment of the present disclosure, the above-described buffer address may be included in at least some types of packets defined in the UFS interface. For example, the above-described buffer address may be included in a packet requesting access to the data buffer of the host memory 21 . According to the technical idea of the present disclosure, among packets communicated between the host device 100 and the storage device 200 , the command packet PACKET_C includes a command CMD, a submission queue ID SQ_ID, and a completion queue ID. (CQ_ID), and the response packet (PACKET_R) may include a response (RESP), a submission queue ID (SQ_ID), and a completion queue ID (CQ_ID). The structure of each packet will be described with reference to FIGS. 14A and 14B.

Hereinafter, specific operation examples of the interface between the host and the storage device according to embodiments of the present disclosure will be described. In the following embodiments, a host and a storage device employing a UFS interface will be exemplified. As described above, the embodiments of the present disclosure may be applied to various types of interfaces other than the UFS interface.

5 is a diagram illustrating an operation of the storage system 10 according to an exemplary embodiment of the present disclosure. 1 and 2 are referred to together.

The host device 100 may include a plurality of processors or may include a plurality of cores 120 in one processor. For convenience of description, it is assumed that one or more processors include a plurality of cores 120 . Also, for interfacing between the host device 100 and the storage device 200 , it is assumed that the UFS standard is applied.

At least one core 120 may perform an interfacing operation with the storage device 200 based on at least one submission queue SQ and at least one completion queue CQ, respectively. The interface operation may be performed in units of queue pairs including the submission queue SQ for inputting the requested command CMD and the completion queue CQ for writing the processing result of the corresponding command.

According to an exemplary embodiment of the present disclosure, at least one core 120 may process a memory operation using the submission queue SQ and the completion queue CQ. In addition, the submission queue (SQ) may store the processing address of the command (CMD) or the response (RESP) in the submission queue head pointer (SHP) and the submission queue tail pointer (STP), the completion queue (CQ) ) may store the processing address of the command (CMD) or response (RESP) in the completion queue head pointer (CHP) and the completion queue tail pointer (CTP).

Host controller interface 190 includes SQ doorbell register 191, SQ arbiter 192, bitmap doorbell router 193, bitmap doorbell register 194, entry buffer 195, CQ router 196 ), the CQ doorbell register 197 may be included.

The SQ doorbell register 191 may be a pointer storage space for storing the order or position of the submission queue SQ. The SQ doorbell register 191 may store a pointer indicating a tail or a head. According to an exemplary embodiment, the SQ doorbell register 191 may include a register indicating a base address of a submission queue (SQ) entry space, and a register indicating a size of a submission queue (SQ) entry. According to an exemplary embodiment, the SQ doorbell register 191 may store a submission queue head pointer (SHP) and a submission queue tail pointer (STP).

The address SQ ENTRY ADDR at which the entry of the submission queue SQ is stored on the host controller interface 190 may be calculated as in Equation 1.

[Equation 1]

That is, the submission queue entry address (SQ ENTRY ADDR) is a position obtained by adding the size of the submission queue head pointer (SHP) multiplied by the submission queue entry size to the submission queue entry base address (SQ ENTRY BASE ADDR). can

The pointers stored in the SQ doorbell register 191 may be updated for each doorbell notification generated according to input of a command CMD or input/output of data. According to an exemplary embodiment of the present disclosure, the core 120 may write the command CMD to the submission queue SQ. After the command CMD is written to the submission queue SQ, the submission queue tail pointer STP may be changed. The commands CMD may be transmitted to the storage device 200 sequentially or at once by being fetched by the core 120 . For example, the core 120 may fetch the submission queue SQ and transmit a command CMD stored in the submission queue to the storage device 200 . After the command CMD written in the submission queue SQ is transmitted to the host controller interface 190 , the submission queue head pointer SHP may be changed.

Based on the submission queue head pointer (SHP) and the submission queue tail pointer (STP) stored in the SQ doorbell register 191 , the command CMD written to the submission queue is to be transmitted to the SQ arbiter 192 . can Since the submission queue SQ can be used on the host memory ( FIGS. 1 and 130 ), a command from the SQ doorbell register 191 in which the head pointer SHP or the tail pointer STP of the submission queue SQ is stored or to provide a signal. According to an exemplary embodiment of the present disclosure, since there may be a plurality of cores 120 , a plurality of submission queues SQ may exist, and the SQ arbiter 192 receives the plurality of submission queues SQ. can do.

The SQ arbiter 192 may arbitrate a processing order according to a change in the submission queue SQ by selecting one of the plurality of submission queues SQ according to a criterion. For example, the SQ arbiter 192 may determine the order of the commands CMD to be processed among the plurality of submission queues SQ, and each of the plurality of submission queues SQ is first-in, first-out (first-in-first-out) according to the predetermined order. Commands stored in the circular queue can be executed in the First In, First Out) method. In addition, as a method in which the SQ arbiter 192 selects any one of the submission queues, according to the scheduling application time, non-preeptive scheduling or preemptive scheduling, whether the priority of scheduling is changed Various algorithms used for static scheduling and dynamic scheduling may be used. For example, the SQ arbiter 192 selects the submission queues sequentially (or cyclically) so that the processing time between the submission queues is uniform in a round robin method, which is relatively important among the submission queues. A weighted round robin method that non-uniformly allocates processing time between submission queues by placing weights on the submission queues and processing the queues in order of increasing weights. A fixed priority method for assigning priority, etc. may be applied, but it is not limited to the above-described method.

The SQ arbiter 192 may arbitrate the order of the plurality of submission queues SQ by comparing differences between the plurality of submission queues SQ. According to an exemplary embodiment of the present disclosure, the SQ arbiter 192 may compare the tail and the head of the submission queue (SQ). The SQ arbiter 192 may refer to the SQ head pointer (SHP) and the SQ tail pointer (STP) stored in the SQ doorbell register 191 to obtain the submission queue (SQ) information.

The SQ arbiter 192 according to an exemplary embodiment of the present disclosure accesses the SQ doorbell register 191 present in the host controller interface 190, thereby processing the submission queue ( The head and tail of SQ) can be referred to, and it can be arbitrated so that the submission queue (SQ) with insufficient empty space is processed.

According to an exemplary embodiment of the present disclosure, the SQ arbiter 192 may arbitrate the order of the submission queues SQ to be processed from the submission queue SQ to which a flag requiring priority processing is attached.

According to an exemplary embodiment of the present disclosure, the SQ arbiter 192 may determine a selected submission queue (SQ) from among a plurality of submission queues or a submission queue (SQ) that is a priority as a result of comparison. The SQ arbiter 192 may transmit the command CMD written in the confirmed submission queue SQ to the bitmap doorbell router 193 .

The bitmap doorbell router 193 may designate (ie, route) a space in which the command CMD is to be stored in the entry buffer 195 . According to an exemplary embodiment of the present disclosure, the bitmap doorbell router 193 searches the bitmap doorbell register 194 including information on the occupied space and the idle space of the entry buffer 195, and the idle space A path may be specified or address information may be provided so that the command CMD can be written to the . According to an exemplary embodiment, the bitmap doorbell router 193 may designate a space in which the command selected from the SQ arbiter 192 is stored in the entry buffer 195 .

The bitmap doorbell register 194 may be a bit storage space that may indicate the state of the storage space of the entry buffer 195 . A bitmap doorbell is a data structure expressed as a bitmap, which is a set of 1-bit data spaces. Since the bitmap doorbell register 194 expresses whether or not the data space is occupied by bit “0” and bit “1”, the bitmap doorbell router 193 searches for bit “0” by searching for bit “0” to A selected command (CMD) (or action) can be written in the space.

In an exemplary embodiment, when a command (CMD) or response (RESP) is written to the idle space of the bitmap doorbell register 194 , the bitmap for the corresponding space may be changed to bit “1”. In an exemplary embodiment, when a command (CMD) or response (RESP) written in the space occupied by the bitmap doorbell register 194 is processed, the bitmap for the corresponding space may be changed to bit “0”.

The entry buffer 195 may include entries for a submission queue (SQ) and a completion queue (CQ) to be exchanged with the storage device ( FIGS. 1 and 200 ). In addition to the data storage space indicating whether data is occupied, the entry buffer 195 includes other information necessary for data transmission (UTP Transfer Request Descriptor (UTRD), PRDT, submission queue ID (SQ_ID), completion queue ID (CQ_ID)). ) may further include a buffer to store the .

According to an exemplary embodiment, the entry buffer 195 includes a submission queue ID (SQ_ID) indicating in which submission queue the transmitted command (CMD) is written, and the completion of the transmitted command (CMD). A completion queue ID (CQ_ID) indicating whether it is related to the completion queue may be provided to the storage controller ( FIGS. 1 and 210 ). Similarly, the entry buffer 195 includes a submission queue ID (SQ_ID) indicating which submission queue the received response (RESP) is related to, and which completion queue the transmitted response (RESP) is related to. The indicated completion queue ID CQ_ID may be provided from the storage controller 210 .

The host device 100 refers to the entry buffer 195 , and provides a command CMD in which data is stored (ie, “1” is stored in the bitmap doorbell register 194 ) to the storage device 200 . can The storage device 200 may perform a predetermined operation on the command CMD and, as a result, may provide a response RESP to the host device 100 . The response RESP may be stored back in the entry buffer 195 . Data may be communicated between the host device 100 and the storage device 200 in units of packets, and the command CMD is in the command packet PACKET_C and the response RESP is in the response packet PACKET_R, respectively. may be included.

According to an exemplary embodiment of the present disclosure, the entry buffer 195 may buffer a plurality of submission queue (SQ) entries and/or completion queue (CQ) entries. For example, the entry buffer 195 may buffer UTRD, PRDT, command (CMD), response (RESP), submission queue ID (SQ_ID), completion queue ID (CQ_ID), and the like.

The CQ router 196 may designate (ie, route) the completion queue CQ to which the response RESP stored in the entry buffer 195 is to be processed. After the response RESP is provided from the storage device 200 , it may be buffered in the entry buffer 195 before processing.

According to an exemplary embodiment of the present disclosure, the CQ router 196 may search for a core in which a response (RESP) can be processed, and a response (RESP) to a completion queue (CQ) processed by the discovered core ) can be routed to be written. According to an exemplary embodiment, as a result of the CQ router 196 designating the response RESP to the completion queue CQ, the head pointer or tail pointer of the completion queue CQ in the CQ doorbell register 197 (eg CHP, CTP) may be updated.

In an exemplary embodiment, the CQ router 196 refers to the completion queue ID (CQ_ID) provided by the storage device 200 , so that the response RESP is loaded into any core among the plurality of cores. It can be determined whether or not to be written to the queue. For example, the CQ router 196 may write the response RESP to the first completion queue by receiving the first completion queue ID CQ_ID loaded into the first core. Similar to the above-described submission queue selection method, various selection algorithms may be applied to a method in which the CQ router 196 searches the completion queue.

In addition, according to an exemplary embodiment of the present disclosure, the CQ router 196 performs data input/output between the completion queue CQ and the entry buffer 195 so that the completion queue CQ does not overflow. can be controlled For example, the CQ router 196 connects between the completion queue CQ and the entry buffer 195 so that the completion queue CQ is full and the response RESP is not overflowed. You can control the data flow.

The CQ doorbell register 197 may be a pointer storage space for storing the order or position of the completion queue CQ. The CQ doorbell register 197 may store a pointer indicating a tail or a head. According to an exemplary embodiment, the CQ doorbell register 197 may include a register indicating a base address of a completion queue (CQ) entry space, and a register indicating a size of a completion queue (CQ) entry. . According to an exemplary embodiment, the CQ doorbell register 197 may store a completion queue head pointer (CHP) and a completion queue tail pointer (CTP).

The address (CQ ENTRY ADDR) at which the entry of the completion queue (CQ) is stored on the host controller interface 190 may be calculated as in Equation (2).

[Equation 2]

That is, the completion queue entry address (CQ ENTRY ADDR) is equal to the size of the completion queue head pointer (CHP) multiplied by the completion queue entry size to the completion queue entry base address (CQ ENTRY BASE ADDR). It may be a combined location.

The pointers stored in the CQ doorbell register 197 may be updated for each doorbell notification generated according to input of a command CMD or input/output of data. According to an exemplary embodiment of the present disclosure, the core 120 may write the response RESP received from the host controller interface 190 in the completion queue CQ. After the response RESP is written in the completion queue CQ, the completion queue tail pointer CTP may be changed. The responses RESP may be processed sequentially or at once by being fetched by the core 120 . For example, the core 120 may fetch the completion queue CQ and perform a processing operation corresponding to the response RESP stored in the completion queue. After the response RESP written in the completion queue CQ is processed, the completion queue head pointer CHP may be changed.

The SQ arbiter 192, the bitmap doorbell router 193, and the CQ router 196 may be implemented as processing circuitry, such as hardware including logic circuitry, or software to perform arbitration operations and/or routing operations. It can be implemented as a combination of hardware and software, such as an executing processor. In particular, the processing circuit includes a central processing unit (CPU), an arithmetic logic unit (ALU) that performs arithmetic and logic operations, bit shift, and the like, a digital signal processor (DSP), a microprocessor, and an ASIC (Application). Specific Integrated Circuit), but is not limited thereto.

When a single bitmap doorbell is shared by a plurality of cores, resource occupation overhead may occur, thereby degrading the overall system performance. For example, according to the UFS standard, when any one of a plurality of cores accesses the bitmap doorbell, other cores cannot access the bitmap doorbell.

The storage system ( FIGS. 1 and 10 ) according to the technical idea of the present disclosure includes an SQ arbiter 192 and a CQ router 196 to prevent resource occupation of multiple queues, so that the UFS standard is adopted even in a multi-queue environment. Interfacing between the host device and the storage device may be smoothly performed.

According to the spirit of the present disclosure, in the host controller interface 190 , a dedicated submission queue (SQ) and a dedicated completion queue (CQ) suitable for each of a plurality of cores, and a queue doorbell (ie, SQ) for each doorbell, and CQ doorbell) can be used directly. That is, according to the technical idea of the present disclosure, the bitmap doorbell structure applied to UFS is maintained as it is, but the SQ arbiter 192, the bitmap doorbell router 193, and the CQ router 196 are additionally used to store storage. Changes in the structure of the system 10 can be minimized, and compatibility with other devices adopting the UFS standard can be maintained.

As a result, in the storage system 10 according to the technical spirit of the present disclosure, when the host controller interface 190 directly transmits the command CMD to the storage device 200 , the multi-circular queue (eg, the submission queue SQ) ) and completion queue (CQ)), it is possible to solve the overhead of occupying shared resources between a plurality of cores and maximize performance.

6 is a flowchart illustrating an operation method of the host device ( FIGS. 1 and 100 ) according to an exemplary embodiment of the present disclosure. In conjunction with FIG. 6 , reference is made to FIGS. 1 and 5 .

In operation S110 , the host device 100 may arbitrate the plurality of commands CMDs written in the plurality of submission queues SQ. According to an exemplary embodiment, there may be a plurality of cores, and one core uses at least one submission queue (SQ) and at least one completion queue (CQ) to perform a command (CMD) and/or response ( RESP) can be processed. For example, the SQ arbiter 192 refers to the head pointer (SHP) and the tail pointer (STP) of the submission queue entry stored in the SQ doorbell register 191 to arbitrate the priority between the commands (CMD). can

In operation S120 , the host device 100 may write a submission queue (SQ) entry to the entry buffer 195 . In an exemplary embodiment, the host device 100 may store only the commands CMD included in the submission queue SQ in the entry buffer 195 , not all entries in the submission queue SQ.

In operation S130 , the host device 100 may set a bitmap doorbell. In an exemplary embodiment, the command CMD is stored in the entry buffer 195 , and a specific value of the bitmap doorbell may be set.

For example, the SQ arbiter 192 may transmit a selected one command (CMD) to the bitmap doorbell router 193 , and the bitmap doorbell router 193 may transmit the bitmap doorbell register 194 . The command CMD may be stored in the entry buffer 195 by designating an idle space in which the command CMD of 'CMD' is to be written. As the command CMD is written to the entry buffer 195 , the data area corresponding to the entry buffer of the bitmap doorbell register 194 may be changed from bit “0” to bit “1”.

In step S140 , the host device 100 may update the submission queue doorbell. According to an exemplary embodiment, the host device 100 may update the head pointer SHP in the SQ doorbell register 191 as the command CMD is written into the entry buffer 195 .

According to an exemplary embodiment of the present disclosure, as long as the command CMD to be processed is written in the entry buffer 195 , the command CMD is scheduled to be transmitted to the storage device ( FIGS. 1 and 200 ), and the host device 100 . ) will not be processed. Accordingly, the host device 100 may improve the space of the submission queue SQ by updating the submission queue head pointer SHP.

In operation S150 , the host device 100 may transmit a command CMD and receive a response RESP. According to an exemplary embodiment, the host device 100 may transmit a command CMD to the storage device 200 . The storage device 200 may perform a specific memory operation based on the command CMD, and may provide a response RESP, which is metadata about the execution result, back to the host device 100 . In operation S160 , the host device 100 may store the received response RESP in the entry buffer 195 . According to an exemplary embodiment of the present disclosure, the entry buffer 195 may buffer a command CMD and a response RESP.

In operation S170 , the host device 100 may designate (route) the response RESP to be stored in any one of a plurality of completion queues CQ. For example, the CQ router 196 refers to a plurality of written responses (RESP) by referring to the bitmap doorbell register 194, and receives a response (RESP) of any one of the plurality of responses (RESP). It may be selected according to a predetermined criterion (eg, priority), and the response RESP may be stored in the CQ doorbell register 197 .

In operation S180 , the host device 100 may update the completion queue doorbell. According to an exemplary embodiment, as a result of the CQ router 196 designating the response RESP to the completion queue CQ, the tail pointer of the completion queue CQ (eg, the CQ doorbell register 197 ) For example, CTP) can be updated.

According to an exemplary embodiment of the present disclosure, the host controller interface 191 may mediate the order of the plurality of submission queues (SQs). The host controller interface 191 may determine the priority and store the command included in the selected submission queue entry in the entry buffer 195 . For example, the first command stored in the first submission queue may be stored in the entry buffer 195 . After the first command is stored in the entry buffer 195 , the host controller interface 191 may update the head pointer of the first submission queue.

The host controller interface 191 may select a next order from among the plurality of submission queues SQs. The host controller interface 191 may store the second command stored in the second submission queue in the entry buffer 195 . After the second command is stored in the entry buffer 195 , the host controller interface 191 may update the head pointer of the second submission queue. This is repeated sequentially. Meanwhile, the first command and the second command stored in the entry buffer 195 may be transmitted to the storage device 200 in an input order.

7 is a block diagram illustrating the storage system 10 to which a command CMD is written according to an exemplary embodiment of the present disclosure. 5 and 6 are referenced together with FIG. 7 .

The storage system 10 may include a host device 100 and a storage device 200 . Since the silver host device 100 and the storage device 200 of FIG. 1 may be applied to the silver host device 100 and the storage device 200 of FIG. 7 , respectively, overlapping descriptions will be omitted in a non-conflicting range.

The host device 100 may include a first core 121 and a second core 123 .

The first core 121 may write the command CMD to the first submission queue SQ1 and refer to the first submission queue head pointer SHP1 and the first submission queue tail pointer STP1. can The first submission queue head pointer SHP1 and the first submission queue tail pointer STP1 may be included in the first submission queue doorbell. In addition, the first core 121 refers to the first completion queue head pointer CHP1 and the first completion queue tail pointer CTP1 to refer to the response RESP written in the first completion queue CQ1. ) can be dealt with.

The second core 123 may write the command CMD to the second submission queue SQ2 and refer to the second submission queue head pointer SHP2 and the second submission queue tail pointer STP2. can Also, the second core 123 may include a second completion queue head pointer CHP2 and a second completion queue tail pointer CTP2 of the second completion queue CQ2, respectively.

According to an exemplary embodiment of the present disclosure, as a result of fetching the first submission queue SQ1 executed by the first core 112 , the host device 100 stores the first command CMD1 into the entry buffer (195) may be provided. For example, the bitmap doorbell router 193 may search for an empty space by referring to the bit stored in the bitmap doorbell register 135 . The entry buffer 195 may write the first command CMD1 to the data space for buffering, and a bitmap value corresponding to the space in which the first command CMD1 of the bitmap doorbell register 194 is written. may be changed from bit “0” to bit “1”.

According to an exemplary embodiment, along with the transmission of the first command CMD1 , the command CMD that has been written in which submission queue among the first submission queue SQ1 and the second submission queue SQ2 is transmitted A submission queue ID (SQ_ID) indicating , may be stored in the entry buffer 195 . In addition, completion indicating a completion queue CQ with sufficient computing resources or an empty data space of the first completion queue CQ1 and the second completion queue CQ2 A queue ID (CQ_ID) may be transmitted to the entry buffer 195 . The first command CMD1, the submission queue ID SQ_ID, and the completion queue ID CQ_ID may be transmitted in the form of a packet PACKET.

In an exemplary embodiment of the present disclosure, after the first command CMD1 is transmitted, the submission queue head pointer SHP1 of the first submission queue SQ1 may be updated (HP update). For example, when the value of the head of the submission queue head pointer SHP1 increases by 1 (++HEAD), the writing space indicated by the head of the first submission queue SQ1 may be changed. As the first submission queue head pointer SHP1 increases by 1, the first command CMD1 written in the first submission queue SQ1 may be erased. That is, the first command CMD1 may be removed from the queue (CMD1 dequeue).

According to an exemplary embodiment of the present disclosure, as long as the command CMD to be processed is written in the entry buffer 195 , the command CMD is not scheduled to be processed by the host device 100 . For example, as the storage space of the first command CMD1 moves from the first submission queue SQ1 to the entry buffer 195 , the first submission queue SQ1 is no longer the first command CMD1 . no need to save Due to the characteristics of the circular queue in which the write space is limited, unnecessary commands must be removed before new commands can be written. Accordingly, after the first command CMD1 is stored in the entry buffer 195 , the first command CMD1 written in the first submission queue SQ1 is updated by updating the submission queue head pointer SHP1 in the write space. It can be removed from the queue (ie, by incrementing the head value by 1). Accordingly, the host device 100 may increase input/output efficiency by removing the first command CMD1 from the first submission queue SQ1 .

The host device 100 may provide the first command CMD1 to the storage device 200 through the entry buffer 195 . After the first command CMD1 is transmitted, the bitmap doorbell register 194 changes the value of the bitmap corresponding to the space in which the first command CMD1 was written from bit “1” to bit “0”. can do it

8 is a block diagram illustrating a storage system 10 to which a response RESP is written according to an exemplary embodiment of the present disclosure. Since FIG. 8 shows an operation after the first command CMD1 according to FIG. 7 is written, a description overlapping with FIG. 7 will be omitted. 5 to 7 are referenced together with FIG. 8 .

According to an exemplary embodiment of the present disclosure, the storage device 200 generates a second response RESP2 as a result of performing the first command CMD, and sends the second response RESP2 back to the host device 100 . can be transmitted

According to an exemplary embodiment of the present disclosure, the entry buffer 195 may store a response RESP. For example, the entry buffer 195 may write the second response RESP2 to the data space for buffering, and the second response RESP2 of the bitmap doorbell register 194 may correspond to the written space. The value of the bitmap may be changed from bit “0” to bit “1”.

Along with the transmission of the second response RESP2, a command related to any of the first submission queue SQ1 and the second submission queue SQ2 (eg, the first command CMD1) is processed A submission queue ID (SQ_ID) indicating whether or not a completion queue has been transmitted A session queue ID (CQ_ID) may be transmitted to the host device 100 . The second response RESP2, the submission queue ID SQ_ID, and the completion queue ID CQ_ID may be transmitted in the form of a packet PACKET.

In an exemplary embodiment, the response RESP is based on the completion queue ID CQ_ID provided by the storage device 200 , the complete referenced among the first core 121 and the second core 123 . It may be written in the completion queue (CQ) corresponding to the completion queue ID (CQ_ID). For example, the response RESP is the second completion queue CQ2 according to the completion queue ID CQ_ID indicating the second completion queue CQ2 loaded in the second core 113 . can be entered in

According to an exemplary embodiment of the present disclosure, the CQ router 196 may designate (ie, route) the response RESP to the completion queue CQ. According to an exemplary embodiment, the second response RESP2 may be temporarily stored in the entry buffer 195 until it is determined whether the host device 100 can access the second completion queue CQ2.

In an exemplary embodiment, after the second response RESP2 is written, the second completion queue tail pointer CTP2 of the second completion queue CQ2 may be updated (CP update). For example, when the value of the tail of the second completion queue tail pointer CTP2 increases by 1 (++TAIL), the write space indicated by the tail of the second completion queue CQ2 may be changed. . That is, as the tail pointer increases by 1, the second response RESP2 may be additionally written into the second completion queue CQ2 (RESP2 enqueue).

The bitmap doorbell register 194 holds the state of the space in which the second response RESP2 was written after the second response RESP2 has been written to the second completion queue CQ2 in bit “1”. It can be changed to "0".

9 is a diagram illustrating a process in which a command is written into a circular queue according to an exemplary embodiment of the present disclosure. The circular queue shown in FIG. 9 may be applied to the submission queue SQ and/or the completion queue CQ disclosed in FIGS. 1 to 8 . 1 and 2 are referred to together.

A circular queue is an array with a connected beginning and an end, and is a data structure in which data can be inserted and deleted. The initial value of the head and tail of the circular queue is 0, and if the value of the head and the value of the tail are the same, the circular queue is interpreted as empty. In an initial state in which the values of the head HEAD and the tail TAIL are 0, new data (eg, a command) may be written. New data (eg, a command) may be written in a space indicated by the TAIL.

Referring to FIG. 9 , it is assumed that there are 8 writable spaces in the circular queue, and that the first command CMD1 , the second command CMD2 , and the third command CMD3 have been written.

A command may be written in the space indicated by the TAIL, and each time one command is written, the value of the pointer may increase by one. For example, the initial value of the head HEAD may be 0, and the value of the tail TAIL may be 3 after the first to third commands CMD1 to CMD3 are written. That is, the tail indicates a space in which a command is to be written, and after data is written, the value may increase to indicate a space immediately following the space in which data is written. According to an exemplary embodiment, as the first command CMD1 , the second command CMD2 , and the third command CMD3 are sequentially written, the tail TAIL may increase by 1 and the third command CMD3 As CMD3 is written, the tail TAIL may indicate a space immediately following the third command CMD3 .

In an exemplary embodiment, the fourth command CMD4 may be written to the circular queue (Enqueue CMD4). The head HEAD may maintain an initial value of 0, and the tail TAIL may increase the value by 1 according to writing of a new command (++TAIL). Accordingly, the tail TAIL may indicate a space immediately following the fourth command CMD4 .

As the commands are sequentially written to the circular queue as described above, the head is the same but the value of the tail increases by 1 (++TAIL). If the value of tail + 1 is equal to the value of head, it is interpreted that the circular queue is full. In an exemplary embodiment, since the queue depth, which is the data accommodating capacity of the circular queue, is limited, the value of the TAIL may be allocated in a wrap-around method that reuses an existing address. For example, when the queue depth of the circular queue is N, the tail TAIL may have 0 as a value corresponding to the address again as the value of the increased tail TAIL is N. As such, the circular queue has a characteristic that the next address of the last address becomes the first address, so it is advantageous in a limited data space allocation environment and is easy to implement.

According to an exemplary embodiment of the present disclosure, the submission queue SQ and/or the completion queue CQ of FIGS. 1 to 8 may be implemented as a circular queue. If the circular queue structure is used, a command (or response) is sent to the submission queue and/or the completion queue by simply incrementing the tail pointer, which is the address of the write space indicated by the TAIL, by 1 (++TAIL). It can be written easily. Similarly, by incrementing the head pointer by one (++HEAD), it is possible to easily clear the command (or response) written to the submission queue and/or the completion queue.

10 is a flowchart illustrating an operating method of the storage system 10 according to an exemplary embodiment of the present disclosure. FIG. 10 is referred to in conjunction with FIGS. 1 and 5 .

In step S205 , the core 120 may issue a command CMD. The command CMD may be written to the submission queue SQ entry.

In step S210 , the core 120 may write the command CMD issued to the submission queue SQ and update the SQ doorbell. For example, the core 120 may update the tail pointer (STP) of the SQ doorbell to perform processing according to data writing.

In operation S215 , the core 120 may transmit a submission queue (SQ) entry to the host controller interface 190 . The submission queue SQ itself is substantially stored in the host memory ( FIGS. 1 and 130 ) and may be managed by the core 120 . Accordingly, the core 120 may transmit entry information of the submission queue SQ to the host controller interface 190 .

In operation S220 , the host controller interface 190 may store a submission queue (SQ) entry in the entry buffer 195 . According to an exemplary embodiment, the host controller interface 190 may arbitrate a plurality of commands CMDs written to a plurality of submission queues SQ, and the SQ arbiter 192 is an SQ doorbell register. With reference to the head pointer (SHP) and the tail pointer (STP) of the submission queue entry stored in ( 191 ), it is possible to arbitrate the priority between the commands (CMD). As a result of the arbitration, the host controller interface 190 may store the command CMD included in the submission queue SQ in the entry buffer 195 .

In step S225 , the host controller interface 190 may set a bitmap doorbell. For example, the entry buffer 195 may write a command CMD to a data space for buffering, and a bitmap value corresponding to the space in which the command CMD of the bitmap doorbell register 194 is written. may be changed from bit “0” to bit “1”.

In step S230 , the host controller interface 190 may update the submission queue doorbell. According to an exemplary embodiment, the host controller interface 190 may update the submission queue head pointer SHP in the SQ doorbell register 191 as the command CMD is written into the entry buffer 195 .

According to an exemplary embodiment of the present disclosure, when a command (CMD) to be processed is written to the entry buffer 195 , the host controller interface 190 updates the submission queue head pointer SHP to thereby set the submission queue SQ. space can be made efficient.

In operation S235 , the host controller interface 190 may transmit a command CMD and receive a response RESP. According to an exemplary embodiment, the host controller interface 190 may transmit a command CMD to the storage device 200 . The storage device 200 may perform a specific memory operation based on the command CMD, and may provide a response RESP, which is metadata about the execution result, back to the host controller interface 190 .

In operation S240 , the host controller interface 190 may store the received response RESP in the entry buffer 195 . According to an exemplary embodiment of the present disclosure, the entry buffer 195 may buffer the response RESP until the path of the response RESP is established.

In operation S245 , the host controller interface 190 may transmit a response RESP to a completion queue CQ entry. According to an exemplary embodiment of the present disclosure, the CQ router 196 may designate (route) the response RESP to be stored in any one completion queue CQ among a plurality of completion queues. For example, by referring to the bitmap doorbell register 194 , the CQ router 196 selects any one of a plurality of responses RESP according to a predetermined criterion (eg, priority). selected, and the pointer of the response RESP may be stored in the CQ doorbell register 197 . Thereafter, the response RESP may be written to the completion queue CQ. The completion queue CQ itself is substantially stored in the host memory 130 , and the host controller interface 190 may transmit entry information of the completion queue CQ to the core 120 .

In step S250, the host controller interface 190 may send the completion queue doorbell ROD. According to an exemplary embodiment, the host controller interface 190 may update the completion queue tail pointer CTP in the CQ doorbell register 197 as the response RESP is written to the completion queue CQ. can

In step S255, the host controller interface 190 may erase the bitmap doorbell. According to an exemplary embodiment, the host controller interface 190 stores the CQ doorbell register 197 to designate a response RESP according to the command CMD to a specific completion queue CQ, and then stores the corresponding command By removing the bitmaps related to the submission queue SQ related to (CMD) and the completion queue CQ related to the corresponding response RESP, an idle space of the bitmap doorbell can be secured.

For example, referring to the processes of FIGS. 7 and 8 , the first command CMD1 written in the first submission queue SQ1, the submission queue ID SQ_ID, and the completion queue ID CQ_ID ) is stored in the entry buffer 195 and may change the state of the memory area of the bitmap doorbell register 194 (bit “0” → bit “1”). The first command CMD1 may be provided to the storage device 200 , and the second response RESP2 according to the first command CMD1 may include a submission queue ID SQ_ID and a completion queue ID CQ_ID. together with may be stored in the entry buffer 195 again. The second response RESP2 may be designated as the second completion queue CQ2 and stored in the CQ doorbell register 197 . Data generated or stored in the process of the first command CMD1 and the second response RESP2 (the first command CMD1 and the second response RESP2), and the submission queue ID SQ_ID stored in the entry buffer 195 ), and the completion queue ID (CQ_ID)) may be deleted as the second response RESP2 is processed. As a result, the bitmap doorbell register 194 and the entry buffer 195 can be initialized.

In step S260, the completion queue (CQ) entry may be consumed. According to an exemplary embodiment, the completion queue CQ may access a location where the response RESP is stored by referring to the pointer of the CQ doorbell register 197 . For example, the second core ( FIGS. 8 and 123 ) may write the second response RESP2 to the second completion queue CQ2 by referring to the second completion queue tail pointer CTP2 , The second response RESP2 may be processed by the second core 123 .

In step S265, the completion queue (CQ) doorbell may be updated. According to an exemplary embodiment, after the second response RESP2 is processed by the second core 123 , a free space is generated again in the second completion queue CQ2 . The CQ doorbell register 197 may increase the input/output efficiency of the second completion queue CQ2 by updating the head pointer CHP2 of the completion queue CQ.

11 and 12 are block diagrams illustrating examples of various types of information stored in the register 111 in the host memory ( FIGS. 1 and 130 ) and the host controller ( FIGS. 1 and 110 ). 1 and 2 are referenced together with FIGS. 11 and 12 .

Referring to FIG. 11 , the host device 100 includes a host memory 130 and a register 111 , the register 111 is provided in the host controller 110 , and the host memory 130 is a host device. It may be disposed outside the controller 110 . For data management of the storage system 10 , various commands and parameters defined in JEDEC UFS standards may be stored in the host memory 130 and the register 111 .

A UTP Transfer Request Descriptor may be stored in a descriptor area of the host memory 130 , and UPIU information and corresponding PRDT information may be stored in another area of the host memory 130 . Also, the UTP transfer request descriptors may be stored in the host memory 130 or identified in the host memory 130 through a UTP transfer request stored in the register 111 .

In addition, write data and read data are stored in a plurality of data buffers included in the buffer area of the host memory 130 , and the PRDT information may include a buffer address as a physical address of the data buffer. Also, PRDT information may not be stored for some command UPIUs, and as an example, PRDT information may not be stored for command UPIUs irrelevant to data buffer access.

In addition, in FIG. 11 , other various information defined in the JEDEC UFS standards are further illustrated. As an example, the UTP task management request list may be further stored in one area of the host memory 130 , and as an example, the task management request UPIU and the task management response UPIU may be stored in one area of the host memory 130 . Also, the task management request list may be stored in the host memory 130 through the UTP task management request stored in the register 111 . In addition, the register 111 further shows other components defined in the JEDEC UFS standards, such as Host Controller Capabilities, Interrupt and host status, UFS Interconnect (UIC) commands. (UIC Command) and vendor specific values (Vendor Specific) may be stored in the register 111 .

In order for the operating system to store data stored in the data buffer of the host memory 130 in the storage device ( FIGS. 1 and 200 ), a UTP transmission request descriptor is generated in the host memory 130 , and a UTP transmission request is performed. By creating it can initiate the host controller interface (FIG. 2, 190).

The host controller interface 190 may access one space of the host memory 130 corresponding to the UTP transmission request, read the UTP transmission request descriptor, and transmit the corresponding command UPIU to the storage device 200 .

The storage device 200 receiving the command UPIU may transmit a Ready To Transfer (RTT) UPIU containing the size and offset information to be transmitted to the host controller interface 190, and the host controller interface 190 is the RTT UPIU. By referring to LUN (Logical Unit Number) and TAG (identifier) information inside HEADER (transmission information), access the corresponding UTP transmission request descriptor location, search for PRDT information, and finally know the address of the data buffer and start data transmission can do.

12 is a block diagram comparing the frequency of access to a host memory according to an embodiment of the present disclosure with a general case. 12 illustrates an example in which the host performs an operation according to a packet transmitted from the storage device.

12 shows an example of processing a packet according to a general format. Referring to FIG. 12 , one or more UTP transfer requests are stored in the register 111 in the host controller ( FIGS. 2 and 110 ). As an example, a first transfer request (Transfer Request 0) corresponds to a data write request and a third The transfer request (Transfer Request 2) may correspond to a data read request. The host controller 110 may receive the RTT UPIU from the storage device ( FIGS. 1 and 200 ) in response to the first transfer request 0 . Also, the host controller 110 may receive the DATA_IN UPIU from the storage device 200 in response to the third transfer request (Transfer Request 2 ).

A packet (PACKET) transmitted from the storage device 200 may include a header area in which header information is stored, and the header information of the RTT UPIU includes size and offset information of data to be transmitted for a data write operation. can The host controller 110 may perform a processing operation using at least some information values in header information of the RTT UPIU. For example, the host controller 110 accesses the host memory 130 to check the corresponding UTP transmission request descriptor by referring to logical unit number (LUN) and identifier (TAG) information in header information of the RTT UPIU. In addition, the host controller checks the information of the PRDT by accessing the host memory 130 at the location determined through the UTP transmission request descriptor. Also, a data buffer may be accessed through the checked PRDT information (eg, a buffer address), and data stored in the data buffer may be transmitted to the storage device 200 .

On the other hand, when the DATA_IN UPIU is received, the host controller 110 accesses the host memory 130 to check the corresponding UTP transmission request descriptor from the header information of the DATA_IN UPIU, and also checks the PRDT information corresponding thereto. to access the host memory 130 . And, the read data included in the DATA_IN UPIU may be stored in a data buffer corresponding to the checked PRDT information.

13 is a diagram illustrating an implementation example of a data read operation and a packet according to a UFS interface.

Referring to FIG. 13 , a command UPIU (CMD UPIU) for a data read request is transmitted from the host device 100 to the storage device 200, and a buffer address (or a physical data buffer) is transmitted to the CMD UPIU for a data read request. address PA) may be included. The storage device 200 reads data from the memory core in response to the command UPIU for the data read request, and transmits the DATA_IN UPIU including the read data together with the physical address PA parsed from the command UPIU to the host. . In addition, the storage device 200 may transmit a response UPIU (Response UPIU) indicating that the operation corresponding to the command UPIU has been completed to the host device 100 . According to the above-described embodiments, the host device 100 may store read data in a data buffer at a location indicated by the physical address PA parsed from the DATA_IN UPIU. Meanwhile, the packet structures of the aforementioned command UPIU and DATA_IN UPIU may be implemented as shown in FIGS. 14A and 14B below.

14A and 14B are diagrams illustrating the structure of a packet according to an exemplary embodiment of the present disclosure.

14A and 14B show an example in which a buffer address is included in an existing header area. FIG. 14A shows the structure of a command UPIU, and FIG. 14B shows the structure of a DATA_IN UPIU.

Referring to FIG. 14A , the header area of the command UPIU includes a reserved area, and a part of the reserved area may include a buffer address according to embodiments of the present disclosure and information related thereto. As an example, information CWA indicating that the buffer address is included in the command UPIU, the size of the area (or the buffer Information (CWA_LENGTH) indicating the size of an area in which an address and related information are stored) may be further included in the spare area.

The configuration of the command packet (PACKET_C) transmitted from the host device 100 adopting the UFS standard to the storage device 200 includes a submission queue ID (SQ_ID), a completion queue ID (CQ_ID), and a response credit (CR_RESP). may include

A submission queue ID (SQ_ID) indicating which submission queue-related command from among the plurality of submission queues is transmitted, and a commutation queue indicating which command related to which of the plurality of completion queues is transmitted The partition queue ID (CQ_ID) is transmitted from the host device 100 to the storage device 200 .

In an exemplary embodiment, initialization of the host device 100 may be performed using a reserve command (Reserved CMD).

Referring to FIG. 14B , the DATA_IN UPIU may include a payload area including a header area and a data area, and the header area may include a reserved area. Also, at least a part of the spare area may include a buffer address of the host memory 130 and information related thereto.

The configuration of the response packet (PACKET_R) transmitted from the storage device 200 adopting the UFS standard to the host device 100 includes a submission queue ID (SQ_ID), a completion queue ID (CQ_ID), and a command credit (CR_CMD). may include

Since information included in the spare area shown in FIG. 14B is the same as or similar to that shown in FIG. 14A , a detailed description thereof will be omitted.

15 is a diagram illustrating a system 1000 to which a storage device according to an exemplary embodiment of the present disclosure is applied.

The system 1000 of FIG. 15 is basically a mobile phone such as a mobile phone, a smart phone, a tablet personal computer, a wearable device, a healthcare device, or an Internet of things (IOT) device. (mobile) system. However, the system 1000 of FIG. 15 is not necessarily limited to a mobile system, and is for a vehicle such as a personal computer, a laptop computer, a server, a media player, or a navigation system. It may be an automotive device or the like.

Referring to FIG. 15 , the system 1000 may include a main processor 1100 , memories 1200a and 1200b , and storage devices 1300a and 1300b , and additionally an image capturing device. 1410 , user input device 1420 , sensor 1430 , communication device 1440 , display 1450 , speaker 1460 , power supplying device 1470 and connection may include one or more of a connecting interface 1480 .

The main processor 1100 may control the overall operation of the system 1000 , and more specifically, the operation of other components constituting the system 1000 . The main processor 1100 may be implemented as a general-purpose processor, a dedicated processor, or an application processor.

The main processor 1100 may include one or more CPU cores 1110 and may further include a controller 1120 for controlling the memories 1200a and 1200b and/or the storage devices 1300a and 1300b. According to an embodiment, the main processor 1100 may further include an accelerator 1130 that is a dedicated circuit for high-speed data operation such as artificial intelligence (AI) data operation. The accelerator 1130 may include a graphics processing unit (GPU), a neural processing unit (NPU), and/or a data processing unit (DPU), and is physically independent from other components of the main processor 1100 . It may be implemented as a separate chip.

The memories 1200a and 1200b may be used as the main memory device of the system 1000 and may include volatile memories such as SRAM and/or DRAM, but may include non-volatile memories such as flash memory, PRAM and/or RRAM. may be The memories 1200a and 1200b may be implemented in the same package as the main processor 1100 .

The storage devices 1300a and 1300b may function as non-volatile storage devices that store data regardless of whether power is supplied or not, and may have a relatively larger storage capacity than the memories 1200a and 1200b. The storage devices 1300a and 1300b may include storage controllers 1310a and 1310b and non-volatile memory (NVM) 1320a and 1320b for storing data under the control of the storage controllers 1310a and 1310b. can The nonvolatile memories 1320a and 1320b may include a flash memory having a 2D (2-dimensional) structure or a 3D (3-dimensional) V-NAND (Vertical NAND) structure, but may include other types of memory such as PRAM and/or RRAM. It may include non-volatile memory.

The storage devices 1300a and 1300b may be included in the system 1000 in a state physically separated from the main processor 1100 , or may be implemented in the same package as the main processor 1100 . In addition, the storage devices 1300a and 1300b have the same shape as a solid state device (SSD) or a memory card, and thus other components of the system 1000 through an interface such as a connection interface 1480 to be described later. They may be coupled to be detachably attached. Such storage devices 1300a and 1300b may be devices to which standard protocols such as UFS (Universal Flash Storage), eMMC (embedded multi-media card), or NVMe (non-volatile memory express) are applied, but are not necessarily limited thereto. it's not

The photographing device 1410 may photograph a still image or a moving image, and may be a camera, a camcorder, and/or a webcam.

The user input device 1420 may receive various types of data input from a user of the system 1000 , and may include a touch pad, a keypad, a keyboard, a mouse, and/or It may be a microphone or the like.

The sensor 1430 may detect various types of physical quantities that may be acquired from the outside of the system 1000 , and may convert the sensed physical quantities into electrical signals. Such a sensor 1430 may be a temperature sensor, a pressure sensor, an illuminance sensor, a position sensor, an acceleration sensor, a biosensor and/or a gyroscope sensor.

The communication device 1440 may transmit and receive signals between other devices outside the system 1000 according to various communication protocols. Such a communication device 1440 may be implemented including an antenna, a transceiver, and/or a modem (MODEM).

The display 1450 and the speaker 1460 may function as output devices that respectively output visual information and auditory information to the user of the system 1000 .

The power supply device 1470 may appropriately convert power supplied from a battery (not shown) built into the system 1000 and/or an external power source and supply it to each component of the system 1000 .

The connection interface 1480 may provide a connection between the system 1000 and an external device that is connected to the system 1000 and can exchange data with the system 1000. The connection interface 1480 is an ATA (Advanced Technology) Attachment), SATA (Serial ATA), e-SATA (external SATA), SCSI (Small Computer Small Interface), SAS (Serial Attached SCSI), PCI (Peripheral Component Interconnection), PCIe (PCI express), NVMe, IEEE 1394, It can be implemented in various interface methods such as USB (universal serial bus), SD (secure digital) card, MMC (multi-media card), eMMC, UFS, eUFS (embedded universal flash storage), CF (compact flash) card interface, etc. have.

16 is a diagram for explaining a UFS system 2000 according to an exemplary embodiment of the present disclosure.

The UFS system 2000 is a system conforming to the UFS standard announced by the Joint Electron Device Engineering Council (JEDEC), and may include a UFS host 2100 , a UFS device 2200 , and a UFS interface 2300 . The above description of the system 1000 of FIG. 15 may also be applied to the UFS system 2000 of FIG. 16 to the extent that it does not conflict with the description below with respect to FIG. 16 .

Referring to FIG. 16 , a UFS host 2100 and a UFS device 2200 may be interconnected through a UFS interface 2300 . When the main processor 1100 of FIG. 1 is an application processor, the UFS host 2100 may be implemented as a part of the corresponding application processor. The UFS host controller 2110 and the host memory 2140 may correspond to the controller 1120 and the memories 1200a and 1200b of the main processor 1100 of FIG. 1 , respectively. The UFS device 2200 may correspond to the storage devices 1300a and 1300b of FIG. 1 , and the UFS device controller 2210 and the nonvolatile memory 2220 include the storage controllers 1310a and 1310b and the nonvolatile memory of FIG. 1 . It may correspond to (1320a, 1320b), respectively.

The UFS host 2100 may include a UFS host controller 2110 , an application 2120 , a UFS driver 2130 , a host memory 2140 , and a UFS interconnect (UIC) layer 2150 . The UFS device 2200 may include a UFS device controller 2210 , a non-volatile memory 2220 , a storage interface 2230 , a device memory 2240 , a UIC layer 2250 , and a regulator 2260 . The nonvolatile memory 2220 may include a plurality of memory units 2221 , and the memory unit 2221 may include a V-NAND flash memory having a 2D structure or a 3D structure, but PRAM and/or RRAM It may include other types of non-volatile memory such as The UFS device controller 2210 and the nonvolatile memory 2220 may be connected to each other through the storage interface 2230 . The storage interface 2230 may be implemented to comply with a standard protocol such as toggle or ONFI.

The application 2120 may mean a program that wants to communicate with the UFS device 2200 in order to use the function of the UFS device 2200 . The application 2120 may transmit an input-output request (IOR) to the UFS driver 2130 for input/output to the UFS device 2200 . The input/output request (IOR) may mean a read request, a write request, and/or a discard/erase request of data, but is not necessarily limited thereto.

The UFS driver 2130 may manage the UFS host controller 2110 through a UFS-HCI (host controller interface). The UFS driver 2130 may convert an input/output request generated by the application 2120 into a UFS command defined by the UFS standard, and transmit the converted UFS command to the UFS host controller 2110 . One I/O request can be converted into multiple UFS commands. A UFS command may be basically a command defined by the SCSI standard, but it may also be a command dedicated to the UFS standard.

The UFS host controller 2110 may transmit the UFS command converted by the UFS driver 2130 to the UIC layer 2250 of the UFS device 2200 through the UIC layer 2150 and the UFS interface 2300 . In this process, the UFS host register 2111 of the UFS host controller 2110 may serve as a command queue (CQ).

The UIC layer 2150 on the UFS host 2100 side may include MIPI M-PHY 2151 and MIPI UniPro 2152, and the UIC layer 2250 on the UFS device 2200 side also MIPI M-PHY ( 2251) and MIPI UniPro (2252).

The UFS interface 2300 includes a line for transmitting a reference clock REF_CLK, a line for transmitting a hardware reset signal RESET_n for the UFS device 2200, and a pair of lines for transmitting a differential input signal pair DIN_t and DIN_c. and a pair of lines for transmitting the differential output signal pair DOUT_t and DOUT_c.

The frequency value of the reference clock REF_CLK provided from the UFS host 2100 to the UFS device 2200 may be one of four values of 19.2 MHz, 26 MHz, 38.4 MHz, and 52 MHz, but is not limited thereto. The UFS host 2100 may change the frequency value of the reference clock REF_CLK during operation, that is, while data transmission/reception is performed between the UFS host 2100 and the UFS device 2200 . The UFS device 2200 may generate clocks of various frequencies from the reference clock REF_CLK provided from the UFS host 2100 using a phase-locked loop (PLL) or the like. Also, the UFS host 2100 may set a data rate value between the UFS host 2100 and the UFS device 2200 through the frequency value of the reference clock REF_CLK. That is, the value of the data rate may be determined depending on the frequency value of the reference clock REF_CLK.

The UFS interface 2300 may support multiple lanes, and each lane may be implemented as a differential line pair. For example, the UFS interface 2300 may include one or more receive lanes and one or more transmit lanes. In FIG. 16 , a pair of lines for transmitting a differential input signal pair (DIN_T and DIN_C) may constitute a receive lane, and a pair of lines for transmitting a differential output signal pair (DOUT_T and DOUT_C) may constitute a transmit lane, respectively. . 16 illustrates one transmission lane and one reception lane, the number of transmission lanes and reception lanes may be changed.

The reception lane and the transmission lane may transmit data in a serial communication method, and a full-duplex between the UFS host 2100 and the UFS device 2200 by a structure in which the reception and transmission lanes are separated. communication is possible. That is, the UFS device 2200 may transmit data to the UFS host 2100 through the transmission lane while receiving data from the UFS host 2100 through the reception lane. In addition, control data such as commands from the UFS host 2100 to the UFS device 2200, and the UFS host 2100 to be stored in the non-volatile memory 2220 of the UFS device 2200 or from the non-volatile memory 2220 User data to be read may be transmitted through the same lane. Accordingly, there is no need to further provide a separate lane for data transmission between the UFS host 2100 and the UFS device 2200 in addition to the pair of reception lanes and the pair of transmission lanes.

The UFS device controller 2210 of the UFS device 2200 may control overall operations of the UFS device 2200 . The UFS device controller 2210 may manage the nonvolatile memory 2220 through a logical unit (LU) 2211 which is a logical data storage unit. The number of LUs 2211 may be 8, but is not limited thereto. The UFS device controller 2210 may include a flash translation layer (FTL), and a logical data address transmitted from the UFS host 2100 using address mapping information of the FTL, for example, LBA. (logical block address) may be converted into a physical data address, for example, into a physical block address (PBA). A logical block for storing user data in the UFS system 2000 may have a size within a predetermined range. For example, the minimum size of the logical block may be set to 4Kbyte.

When a command from the UFS host 2100 is input to the UFS device 2200 through the UIC layer 2250, the UFS device controller 2210 performs an operation according to the input command, and when the operation is completed, a completion response is returned. It can be transmitted to the UFS host 2100 .

As an example, when the UFS host 2100 intends to store user data in the UFS device 2200 , the UFS host 2100 may transmit a data storage command to the UFS device 2200 . When a response indicating that the user data is ready-to-transfer is received from the UFS device 2200 , the UFS host 2100 may transmit the user data to the UFS device 2200 . The UFS device controller 2210 temporarily stores the received user data in the device memory 2240 and transfers the user data temporarily stored in the device memory 2240 based on the address mapping information of the FTL to the nonvolatile memory 2220. You can save it to a location of your choice.

As another example, when the UFS host 2100 wants to read user data stored in the UFS device 2200 , the UFS host 2100 may transmit a data read command to the UFS device 2200 . Upon receiving the command, the UFS device controller 2210 may read user data from the nonvolatile memory 2220 based on the data read command and temporarily store the read user data in the device memory 2240 . In this reading process, the UFS device controller 2210 may detect and correct an error in the read user data using a built-in error correction code (ECC) engine (not shown). More specifically, the ECC engine may generate parity bits for write data to be written into the non-volatile memory 2220 , and the generated parity bits are stored in the non-volatile memory 2220 together with the write data. can be saved. When reading data from the non-volatile memory 2220, the ECC engine corrects an error in the read data using parity bits read from the non-volatile memory 2220 together with the read data, and outputs the error-corrected read data. can

In addition, the UFS device controller 2210 may transmit user data temporarily stored in the device memory 2240 to the UFS host 2100 . In addition, the UFS device controller 2210 may further include an advanced encryption standard (AES) engine (not shown). The AES engine may perform at least one of an encryption operation and a decryption operation on data input to the UFS device controller 2210 using a symmetric-key algorithm.

The UFS host 2100 may sequentially store commands to be transmitted to the UFS device 2200 in the UFS host register 2111, which may function as a command queue, and may transmit the commands to the UFS device 2200 in this order. . At this time, even if the previously transmitted command is still being processed by the UFS device 2200, that is, even before the UFS host 2100 receives a notification that the previously transmitted command has been processed by the UFS device 2200 The next command waiting in the command queue may be transmitted to the UFS device 2200 , and accordingly, the UFS device 2200 may also receive the next command from the UFS host 2100 while processing the previously transmitted command. The maximum number of commands (queue depth) that can be stored in such a command queue may be, for example, 32. In addition, the command queue may be implemented as a circular queue type indicating the start and end of the command sequence stored in the queue, respectively, through a head pointer and a tail pointer.

Each of the plurality of memory units 2221 may include a memory cell array (not shown) and a control circuit (not shown) for controlling an operation of the memory cell array. The memory cell array may include a two-dimensional memory cell array or a three-dimensional memory cell array. The memory cell array includes a plurality of memory cells, and each memory cell may be a cell (single level cell, SLC) storing one bit of information, but a multi level cell (MLC), a triple level cell (TLC), It may be a cell that stores information of 2 bits or more, such as a quadruple level cell (QLC). The three-dimensional memory cell array may include vertical NAND strings that are vertically oriented such that at least one memory cell is positioned on top of another memory cell.

VCC, VCCQ, VCCQ2, etc. may be input to the UFS device 2200 as a power voltage. VCC is a main power voltage for the UFS device 2200 and may have a value of 2.4 to 3.6V. VCCQ is a power supply voltage for supplying a low-range voltage, and is mainly for the UFS device controller 2210 . It can have a value of 1.14 to 1.26V. VCCQ2 is a power supply voltage for supplying a voltage lower than VCC but higher than VCCQ, mainly for an input/output interface such as the MIPI M-PHY 2251, and may have a value of 1.7 to 1.95V. The power voltages may be supplied for each component of the UFS device 2200 through the regulator 2260 . The regulator 2260 may be implemented as a set of unit regulators respectively connected to different ones of the above-described power voltages.

17A to 17C are diagrams for explaining a form factor of a UFS card according to an exemplary embodiment of the present disclosure.

When the UFS device 2200 described with reference to FIG. 16 is implemented in the form of the UFS card 4000 , the outer shape of the UFS card 4000 may be as shown in FIGS. 17A to 17C .

17A exemplarily shows a top view of the UFS card 4000 . Referring to FIG. 17A , it can be seen that the UFS card 4000 follows a shark-shaped design as a whole. Referring to FIG. 17A , the UFS card 4000 may have dimension values as exemplarily shown in Table 1 below.

Item Dimensions (mm) T1 9.70 T2 15.00 T3 11.00 T4 9.70 T5 5.15 T6 0.25 T7 0.60 T8 0.75 T9 R0.80

17B exemplarily shows a side view of the UFS card 4000 . Referring to FIG. 17B , the UFS card 4000 may have dimension values as exemplarily shown in Table 2 below.

Item Dimensions (mm) S1 0.74±0.06 S2 0.30 S3 0.52 S4 1.20 S5 1.05 S6 1.00

17C exemplarily shows a bottom view of the UFS card 4000 . Referring to FIG. 17C , a plurality of pins for electrical contact with the UFS slot may be formed on the bottom surface of the UFS card 4000 , and the function of each pin will be described later. Based on the symmetry between the top and bottom surfaces of the UFS card 4000, some of the information regarding the dimensions described with reference to FIG. 17A and Table 1 (eg, T1 to T5 and T9) is a UFS card as shown in FIG. 17C It can also be applied to the bottom view of 4000. A plurality of pins may be formed on the bottom of the UFS card 4000 for electrical connection with the UFS host, and according to FIG. 17C , the number of pins may be 12 in total. Each pin may have a rectangular shape, and a signal name corresponding to the pin is as shown in FIG. 17C . For schematic information on each pin, reference may be made to Table 3 below, and the above description in relation to FIG. 16 may also be referred to.

number signal name Explanation Dimensions (mm) One vss Ground (GND) 3.00 × 0.72±0.05 2 DIN_C Differential input signal input from host to UFS card (4000) (DIN_C is negative node, DIN_T is positive node) 1.50 × 0.72±0.05 3 DIN_T 4 vss same as 1 3.00 × 0.72±0.05 5 DOUT_C Differential output signal output from the UFS card (4000) to the host (DOUT_C is a negative node, DOUT_T is a positive node) 1.50 × 0.72±0.05 6 DOUT_T 7 vss same as 1 3.00 × 0.72±0.05 8 REF_CLK Reference clock provided from host to UFS card (4000) 1.50 × 0.72±0.05 9 VCCQ2 A supply voltage with a relatively low value relative to Vcc, mainly provided for a PHY interface or controller. 3.00 × 0.72±0.05 10 C/D (GND) Signals for Card Detection 1.50 × 0.72±0.05 11 vss same as 1 3.00 × 0.80±0.05 12 Vcc mains voltage

18A is a block diagram illustrating a host-storage system 10 according to an exemplary embodiment of the present disclosure, and FIGS. 18B to 18E are detailed block diagrams of the configurations of FIG. 18A . Referring to FIG. 18A , host-storage The system 10 may include a host device 100 and a storage device 200 . Also, the storage device 200 may include a storage controller 210 and a non-volatile memory (NVM) 230 . Also, according to an exemplary embodiment of the present disclosure, the host device 100 may include a host controller 110 and a host memory 130 . The host memory 130 may function as a buffer memory for temporarily storing data to be transmitted to the storage device 200 or data transmitted from the storage device 200 .

The storage device 200 may include storage media for storing data according to a request from the host device 100 . As an example, the storage device 200 may include at least one of a solid state drive (SSD), an embedded memory, and a removable external memory. When the storage device 200 is an SSD, the storage device 200 may be a device conforming to a non-volatile memory express (NVMe) standard. When the storage device 200 is an embedded memory or an external memory, the storage device 200 may be a device conforming to a universal flash storage (UFS) or an embedded multi-media card (eMMC) standard. The host device 100 and the storage device 200 may generate and transmit a packet according to an adopted standard protocol, respectively.

When the nonvolatile memory 230 of the storage device 200 includes a flash memory, the flash memory may include a 2D NAND memory array or a 3D (or vertical) NAND (VNAND) memory array. As another example, the storage device 200 may include other various types of non-volatile memories. For example, the storage device 200 includes a magnetic RAM (MRAM), a spin-transfer torque MRAM (MRAM), a conductive bridging RAM (CBRAM), a ferroelectric RAM (FeRAM), a phase RAM (PRAM), a resistive memory ( Resistive RAM) and various other types of memory may be applied.

According to an embodiment, the host controller 110 and the host memory 130 may be implemented as separate semiconductor chips. Alternatively, in some embodiments, the host controller 110 and the host memory 130 may be integrated on the same semiconductor chip. As an example, the host controller 110 may be any one of a plurality of modules included in an application processor, and the application processor may be implemented as a system on chip (SoC). In addition, the host memory 130 may be an embedded memory provided in the application processor or a non-volatile memory or a memory module disposed outside the application processor.

The host controller 110 stores data (eg, write data) of the buffer region of the host memory 130 in the non-volatile memory 230 , or stores data (eg, read data) of the non-volatile memory 230 in the buffer region You can manage the action to be saved to .

The storage controller 210 may include a host interface 211 , a memory interface 216 , and a central processing unit (CPU) 212 . In addition, the storage controller 210 includes a Flash Translation Layer (FTL) 213 , a packet manager 214 , a buffer memory 215 , an error correction code (ECC) 217 engine, and an advanced encryption standard (AES). ) may further include an engine 218 . The storage controller 210 may further include a working memory (not shown) into which the flash translation layer (FTL) 214 is loaded, and the non-volatile memory 230 by the central processing unit 212 executing the flash layer. ) data writing and reading operations can be controlled.

The host interface 211 may transmit/receive packets to and from the host device 100 . A packet transmitted from the host device 100 to the host interface 211 may include a command or data to be written to the nonvolatile memory 230 , and is transmitted from the host interface 211 to the host device 100 . The transmitted packet may include a response to a command or data read from the nonvolatile memory 230 . The memory interface 216 may transmit data to be written to the nonvolatile memory 230 to the nonvolatile memory 230 or receive data read from the nonvolatile memory 230 . The memory interface 216 may be implemented to comply with a standard protocol such as Toggle or Open NAND Flash Interface (ONFI).

The flash translation layer 213 may perform various functions such as address mapping, wear-leveling, and garbage collection. The address mapping operation is an operation of changing a logical address received from the host device 100 into a physical address used to actually store data in the nonvolatile memory 230 . Wear-leveling is a technique for preventing excessive degradation of a specific block by ensuring that blocks in the non-volatile memory 230 are used uniformly, for example, a firmware technique for balancing erase counts of physical blocks can be implemented through Garbage collection is a technique for securing usable capacity in the nonvolatile memory 230 by copying valid data of a block to a new block and then erasing an existing block.

The packet manager 214 may generate a packet (PACKET) according to a protocol of an interface negotiated with the host device 100 or parse various types of information from a packet (PACKET) received from the host device 100 . Also, the buffer manager 215 may temporarily store data to be written to or read from the nonvolatile memory 230 in a buffer. The buffer may be provided in the storage controller 210 , but may be disposed outside the storage controller 210 .

The ECC engine 217 may perform an error detection and correction function on read data read from the nonvolatile memory 230 . More specifically, the ECC engine 217 may generate parity bits for write data to be written in the non-volatile memory 230 , and the generated parity bits are used together with the write data in the non-volatile memory ( 230) may be stored in When reading data from the non-volatile memory 230 , the ECC engine 217 corrects an error of the read data using parity bits read from the non-volatile memory 230 together with the read data, and the error-corrected read data can be printed out.

The AES engine 218 may perform at least one of an encryption operation and a decryption operation on data input to the storage controller 210 using a symmetric-key algorithm. .

18B is a diagram for explaining the ECC engine 217 of FIG. 18A in more detail. Referring to FIG. 18B , the ECC engine 217 may include an ECC encoding circuit 510 and an ECC decoding circuit 520 . The ECC encoding circuit 510 transmits parity bits ECCP[0:7] to the write data WData[0:63] to be written to the memory cells of the memory cell array 221 in response to the ECC control signal ECC_CON. ) can be created. The parity bits ECCP[0:7] may be stored in the ECC cell array 223 . According to an embodiment, the ECC encoding circuit 510 responds to the ECC control signal ECC_CON with respect to write data WData[0:63] to be written to memory cells including defective cells of the memory cell array 221 . Parity bits (ECCP[0:7]) may be generated.

The ECC decoding circuit 520 receives the read data RData[0:63] read from the memory cells of the memory cell array 221 in response to the ECC control signal ECC_CON and the parity bit reads out from the ECC cell array 223 . It is possible to correct the error bit data using the ECCP[0:7] and output the error-corrected data Data[0:63]. According to an embodiment, the ECC decoding circuit 520 receives read data RData[0:63] and ECC read from memory cells including defective cells of the memory cell array 221 in response to the ECC control signal ECC_CON. The error bit data may be corrected using the parity bits ECCP[0:7] read from the cell array 223 and the error-corrected data Data[0:63] may be output.

18C is a diagram for explaining the ECC encoding circuit 510 of FIG. 18B.

Referring to FIG. 18C , the ECC encoding circuit 510 receives 64-bit write data (WData[0:63]) and basis bits (Basis Bit, B[0:7]) in response to the ECC control signal ECC_CON. and a parity generator 511 that generates parity bits ECCP[0:7] using an XOR array operation. The basis bits (B[0:7]) are bits for generating parity bits (ECCP[0:7]) for the 64-bit write data (WData[0:63]), for example, b'00000000 bits can be composed of The basis bits (B[0:7]) may use other specific bits instead of the b'00000000 bits.

18D is a diagram for explaining the ECC decoding circuit 520 of FIG. 18B.

Referring to FIG. 18D , the ECC decoding circuit 520 includes a syndrome generator 521 , a coefficient calculator 522 , a 1-bit error position detector 523 , and an error corrector 524 . The syndrome generator 521 receives 64-bit read data and 8-bit parity bits ECCP[0:7] in response to the ECC control signal ECC_CON, and uses the XOR array operation to receive the syndrome data S[0: 7]) may occur. The coefficient calculator 522 may calculate the coefficient of the error location equation by using the syndrome data S[0:7]. The error position equation is an equation based on the reciprocal of the error bit. The 1-bit error position detector 523 may calculate the position of the 1-bit error using the calculated error position equation. The error corrector 524 may determine the 1-bit error position based on the detection result of the 1-bit error position detector 523 . The error corrector 524 corrects the error by inverting the logic value of the bit in which the error occurred among the 64-bit read data RData[0:63] according to the determined 1-bit error position information, and corrects the error, and the error-corrected 64-bit data ( Data[0:63]) can be output.

18E is a diagram for explaining the AES engine 218 of FIG. 18A in more detail.

The AES engine 218 may perform encryption and decryption of data using an advanced encryption standard (AES) algorithm, and may include an encryption module 218a and a decryption module 218b. Although FIG. 18E shows the encryption module 218a and the decryption module 218b implemented as separate modules, unlike this, one module capable of performing both encryption and decryption is implemented in the AES engine 218. It is possible. The buffer memory 215 may be a volatile memory serving as a buffer, but may also be a non-volatile memory.

The AES engine 218 may receive the first data transmitted from the buffer memory 215 . The encryption module 218a may generate the second data by encrypting the first data transmitted from the buffer memory 215 using an encryption key. The second data may be transmitted from the AES engine 218 to the buffer memory 215 and stored in the buffer memory 215 .

Also, the AES engine 218 may receive the third data transmitted from the buffer memory 215 . The third data may be data encrypted with the same encryption key used to encrypt the first data. The decryption module 218b may generate fourth data by decrypting the third data transmitted from the buffer memory 215 with the same encryption key as the encryption key used to encrypt the first data. The fourth data may be transmitted from the AES engine 218 to the buffer memory 215 and stored in the buffer memory 215 .

19 is a block diagram illustrating a memory system 15 according to an exemplary embodiment of the present disclosure.

Referring to FIG. 19 , the memory system 15 may include a memory device 17 and a memory controller 16 . The memory system 15 may support a plurality of channels CH1 to CHm, and the memory device 17 and the memory controller 16 may be connected through the plurality of channels CH1 to CHm. For example, the memory system 15 may be implemented as a storage device such as a solid state drive (SSD).

The memory device 17 may include a plurality of nonvolatile memory devices NVM11 to NVMmn. Each of the nonvolatile memory devices NVM11 to NVMmn may be connected to one of the plurality of channels CH1 to CHm through a corresponding way. For example, the nonvolatile memory devices NVM11 to NVM1n are connected to the first channel CH1 through the ways W11 to W1n, and the nonvolatile memory devices NVM21 to NVM2n are the ways W21 to W2n) may be connected to the second channel CH2. In an exemplary embodiment, each of the nonvolatile memory devices NVM11 to NVMmn may be implemented as an arbitrary memory unit capable of operating according to an individual command from the memory controller 16 . For example, each of the nonvolatile memory devices NVM11 to NVMmn may be implemented as a chip or a die, but the present disclosure is not limited thereto.

The memory controller 16 may transmit/receive signals to and from the memory device 17 through the plurality of channels CH1 to CHm. For example, the memory controller 16 stores commands CMDa to CMDm, addresses ADDRa to ADDRm, and data DATAa to DATAm to the memory device 17 through channels CH1 to CHm. The data DATAa to DATAm may be transmitted to the device 17 or received from the memory device 17 .

The memory controller 16 may select one of the nonvolatile memory devices NVM11 to NVMmn connected to the corresponding channel through each channel, and transmit/receive signals to/from the selected nonvolatile memory device. For example, the memory controller 16 may select the nonvolatile memory device NVM11 from among the nonvolatile memory devices NVM11 to NVM1n connected to the first channel CH1 . The memory controller 16 transmits the command CMDa, the address ADDRa, and the data DATAa to the selected nonvolatile memory device NVM11 through the first channel CH1 or the selected nonvolatile memory device NVM11 It is possible to receive data DATAa from

The memory controller 16 may transmit/receive signals to and from the memory device 17 in parallel through different channels. For example, the memory controller 16 transmits the command CMDb to the memory device 17 through the second channel CH2 while transmitting the command CMDa to the memory device 17 through the first channel CH1 . can be transmitted. For example, the memory controller 16 receives data DATAb from the memory device 17 through the second channel CH2 while receiving the data DATAa from the memory device 17 through the first channel CH1 . can receive

The memory controller 16 may control the overall operation of the memory device 17 . The memory controller 16 may transmit signals to the channels CH1 to CHm to control each of the nonvolatile memory devices NVM11 to NVMmn connected to the channels CH1 to CHm. For example, the memory controller 16 may transmit a command CMDa and an address ADDRa to the first channel CH1 to control a selected one of the nonvolatile memory devices NVM11 to NVM1n.

Each of the nonvolatile memory devices NVM11 to NVMmn may operate under the control of the memory controller 16 . For example, the nonvolatile memory device NVM11 may program the data DATAa according to the command CMDa and the address ADDRa provided to the first channel CH1 . For example, the nonvolatile memory device NVM21 reads the data DATAb according to the command CMDb and the address ADDRb provided to the second channel CH2, and transfers the read data DATAb to the memory controller 16) can be transmitted.

19 shows that the memory device 17 communicates with the memory controller 16 through m channels, and the memory device 17 includes n non-volatile memory devices corresponding to each channel. The number and the number of nonvolatile memory devices connected to one channel may be variously changed.

20 is a block diagram illustrating a memory system according to an exemplary embodiment of the present disclosure.

Referring to FIG. 20 , the memory system may include a memory device 300 and a memory controller 400 . The storage device 200 of FIG. 1 may be applied to the memory system of FIG. 20 . The memory device 300 may correspond to one of the nonvolatile memory devices NVM11 to NVMmn that communicates with the memory controller 400 based on one of the plurality of channels CH1 to CHm of FIG. 19 . The memory controller 400 may correspond to the memory controller 16 of FIG. 19 .

The memory device 300 may include first to eighth pins P11 to P18 , a memory interface circuit 310 , a control logic circuit 320 , and a memory cell array 330 .

The memory interface circuit 310 may receive the chip enable signal nCE from the memory controller 400 through the first pin P11 . The memory interface circuit 310 may transmit/receive signals to and from the memory controller 400 through the second to eighth pins P12 to P18 according to the chip enable signal nCE. For example, when the chip enable signal nCE is in an enable state (eg, a low level), the memory interface circuit 310 may be configured to operate the memory controller 400 through the second to eighth pins P12 to P18. ) and can transmit and receive signals.

The memory interface circuit 310 receives a command latch enable signal CLE, an address latch enable signal ALE, and a write enable signal from the memory controller 400 through the second to fourth pins P12 to P14. nWE) can be received. The memory interface circuit 310 may receive the data signal DQ from the memory controller 400 through the seventh pin P17 or may transmit the data signal DQ to the memory controller 400 . A command CMD, an address ADDR, and data DATA may be transmitted through the data signal DQ. For example, the data signal DQ may be transmitted through a plurality of data signal lines. In this case, the seventh pin P17 may include a plurality of pins corresponding to the plurality of data signals DQ.

The memory interface circuit 310 may generate a data signal DQ received in an enable period (eg, a high level state) of the command latch enable signal CLE based on the toggle timings of the write enable signal nWE. A command (CMD) can be obtained from The memory interface circuit 310 may generate a data signal DQ received in an enable period (eg, a high level state) of the address latch enable signal ALE based on the toggle timings of the write enable signal nWE. The address ADDR can be obtained from

In an exemplary embodiment, the write enable signal nWE may be toggled between a high level and a low level while maintaining a static state (eg, a high level or a low level). have. For example, the write enable signal nWE may be toggled during a period in which the command CMD or the address ADDR is transmitted. Accordingly, the memory interface circuit 310 may acquire the command CMD or the address ADDR based on the toggle timings of the write enable signal nWE.

The memory interface circuit 310 may receive the read enable signal nRE from the memory controller 400 through the fifth pin P15 . The memory interface circuit 310 may receive the data strobe signal DQS from the memory controller 400 through the sixth pin P16 or transmit the data strobe signal DQS to the memory controller 400 .

In the data output operation of the memory device 300 , the memory interface circuit 310 may receive the read enable signal nRE toggling through the fifth pin P15 before outputting the data DATA. have. The memory interface circuit 310 may generate the toggling data strobe signal DQS based on the toggling of the read enable signal nRE. For example, the memory interface circuit 310 generates a data strobe signal DQS that starts toggling after a predetermined delay (eg, tDQSRE) based on a toggling start time of the read enable signal nRE. can do. The memory interface circuit 310 may transmit the data signal DQ including the data DATA based on the toggle timing of the data strobe signal DQS. Accordingly, the data DATA may be aligned with the toggle timing of the data strobe signal DQS and transmitted to the memory controller 400 .

In the data input operation of the memory device 300 , when the data signal DQ including the data DATA is received from the memory controller 400 , the memory interface circuit 310 receives the data from the memory controller 400 . A data strobe signal DQS toggling together with the data DATA may be received. The memory interface circuit 310 may acquire the data DATA from the data signal DQ based on the toggle timing of the data strobe signal DQS. For example, the memory interface circuit 310 may acquire the data DATA by sampling the data signal DQ at rising edges and falling edges of the data strobe signal DQS.

The memory interface circuit 310 may transmit the ready/busy output signal nR/B to the memory controller 400 through the eighth pin P18 . The memory interface circuit 310 may transmit state information of the memory device 300 to the memory controller 400 through the ready/busy output signal nR/B. When the memory device 300 is in a busy state (that is, when internal operations of the memory device 300 are being performed), the memory interface circuit 310 transmits a ready/busy output signal nR/B indicating the busy state to the memory controller (400). When the memory device 300 is in the ready state (ie, when internal operations of the memory device 300 are not performed or completed), the memory interface circuit 310 outputs a ready/busy output signal nR/B indicating the ready state. may be transmitted to the memory controller 400 . For example, while the memory device 300 reads data DATA from the memory cell array 330 in response to a page read command, the memory interface circuit 310 is in a busy state (eg, low level). A ready/busy output signal nR/B indicating nR/B may be transmitted to the memory controller 400 . For example, while the memory device 300 programs data DATA into the memory cell array 330 in response to a program command, the memory interface circuit 310 provides a ready/busy output signal nR/ B) may be transmitted to the memory controller 400 .

The control logic circuit 320 may generally control various operations of the memory device 300 . The control logic circuit 320 may receive the command/address CMD/ADDR obtained from the memory interface circuit 310 . The control logic circuit 320 may generate control signals for controlling other components of the memory device 300 according to the received command/address CMD/ADDR. For example, the control logic circuit 320 may generate various control signals for programming data DATA in the memory cell array 330 or reading data DATA from the memory cell array 330 . .

The memory cell array 330 may store data DATA obtained from the memory interface circuit 310 under the control of the control logic circuit 320 . The memory cell array 330 may output the stored data DATA to the memory interface circuit 310 under the control of the control logic circuit 320 .

The memory cell array 330 may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. However, the present disclosure is not limited thereto, and the memory cells include a resistive random access memory (RRAM) cell, a ferroelectric random access memory (FRAM) cell, a phase change random access memory (PRAM) cell, a thyristor random access memory (TRAM) cell, They may be Magnetic Random Access Memory (MRAM) cells. Hereinafter, embodiments of the present disclosure will be described focusing on an embodiment in which the memory cells are NAND flash memory cells.

The memory controller 400 may include first to eighth pins P21 to P28 and a controller interface circuit 410 . The first to eighth pins P21 to P28 may correspond to the first to eighth pins P11 to P18 of the memory device 300 .

The controller interface circuit 410 may transmit the chip enable signal nCE to the memory device 300 through the first pin P21 . The controller interface circuit 410 may transmit/receive signals to and from the memory device 300 selected through the chip enable signal nCE and the second to eighth pins P22 to P28.

The controller interface circuit 410 transmits the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE to the memory device through the second to fourth pins P22 to P24. 300) can be transmitted. The controller interface circuit 410 may transmit the data signal DQ to the memory device 300 or receive the data signal DQ from the memory device 300 through the seventh pin P27 .

The controller interface circuit 410 may transmit the data signal DQ including the command CMD or the address ADDR together with the toggling write enable signal nWE to the memory device 300 . The controller interface circuit 410 transmits the data signal DQ including the command CMD to the memory device 300 as the command latch enable signal CLE having an enable state is transmitted, and sets the enable state to the memory device 300 . As the branch transmits the address latch enable signal ALE, the data signal DQ including the address ADDR may be transmitted to the memory device 300 .

The controller interface circuit 410 may transmit the read enable signal nRE to the memory device 300 through the fifth pin P25 . The controller interface circuit 410 may receive the data strobe signal DQS from the memory device 300 through the sixth pin P26 or transmit the data strobe signal DQS to the memory device 300 .

In the data output operation of the memory device 300 , the controller interface circuit 410 may generate a toggling read enable signal nRE and transmit the read enable signal nRE to the memory device 300 . have. For example, the controller interface circuit 410 may generate a read enable signal nRE that is changed from a fixed state (eg, a high level or a low level) to a toggle state before the data DATA is output. have. Accordingly, the data strobe signal DQS toggling based on the read enable signal nRE in the memory device 300 may be generated. The controller interface circuit 410 may receive the data signal DQ including the data DATA together with the toggling data strobe signal DQS from the memory device 300 . The controller interface circuit 410 may acquire the data DATA from the data signal DQ based on the toggle timing of the data strobe signal DQS.

In a data input operation of the memory device 300 , the controller interface circuit 410 may generate a toggle data strobe signal DQS. For example, the controller interface circuit 410 may generate a data strobe signal DQS that is changed from a fixed state (eg, a high level or a low level) to a toggle state before transmitting the data DATA. . The controller interface circuit 410 may transmit the data signal DQ including the data DATA to the memory device 300 based on the toggle timings of the data strobe signal DQS.

The controller interface circuit 410 may receive the ready/busy output signal nR/B from the memory device 300 through the eighth pin P28 . The controller interface circuit 410 may determine the state information of the memory device 300 based on the ready/busy output signal nR/B.

21 is a block diagram illustrating a memory device 300 according to an exemplary embodiment of the present disclosure.

Referring to FIG. 21 , the memory device 300 may include a control logic circuit 320 , a memory cell array 330 , a page buffer 340 , a voltage generator 350 , and a row decoder 360 . Although not shown in FIG. 21 , the memory device 300 may further include the memory interface circuit 310 shown in FIG. 21 , and further include column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, and the like. may include

The control logic circuit 320 may generally control various operations in the memory device 300 . The control logic circuit 320 may output various control signals in response to a command CMD and/or an address ADDR from the memory interface circuit 310 . For example, the control logic circuit 320 may output a voltage control signal CTRL_vol, a row address X-ADDR, and a column address Y-ADDR.

The memory cell array 330 may include a plurality of memory blocks BLK1 to BLKz (z is a positive integer), and each of the plurality of memory blocks BLK1 to BLKz may include a plurality of memory cells. have. The memory cell array 330 may be connected to the page buffer 340 through bit lines BL, and through word lines WL, string select lines SSL, and ground select lines GSL. It may be connected to the row decoder 360 .

In an exemplary embodiment, the memory cell array 330 may include a 3D memory cell array, and the 3D memory cell array may include a plurality of NAND strings. Each NAND string may include memory cells respectively connected to word lines stacked vertically on the substrate. U.S. Patent Publication No. 7,679,133, U.S. Patent Publication No. 8,553,466, U.S. Patent Publication No. 8,654,587, U.S. Patent Publication No. 8,559,235, and U.S. Patent Application Publication No. 2011/0233648 are incorporated herein by reference in their entirety. are combined In an exemplary embodiment, the memory cell array 330 may include a two-dimensional memory cell array, and the two-dimensional memory cell array may include a plurality of NAND strings arranged along row and column directions.

The page buffer 340 may include a plurality of page buffers PB1 to PBn (n is an integer greater than or equal to 3), and the plurality of page buffers PB1 to PBn are connected through a plurality of bit lines BL. Each of the memory cells may be connected. The page buffer 340 may select at least one bit line among the bit lines BL in response to the column address Y-ADDR. The page buffer 340 may operate as a write driver or a sense amplifier according to an operation mode. For example, during a program operation, the page buffer 340 may apply a bit line voltage corresponding to data to be programmed to a selected bit line. During a read operation, the page buffer 340 may sense data stored in the memory cell by sensing the current or voltage of the selected bit line.

The voltage generator 350 may generate various types of voltages for performing program, read, and erase operations based on the voltage control signal CTRL_vol. For example, the voltage generator 350 may generate a program voltage, a read voltage, a program verify voltage, an erase voltage, etc. as the word line voltage VWL.

The row decoder 360 may select one of the plurality of word lines WL in response to the row address X-ADDR and may select one of the plurality of string selection lines SSL. For example, during a program operation, the row decoder 360 may apply a program voltage and a program verify voltage to a selected word line, and during a read operation, apply a read voltage to the selected word line.

22 is a diagram for explaining a 3D V-NAND structure applicable to a UFS device according to an exemplary embodiment of the present disclosure.

When the storage module of the UFS device is implemented as a 3D V-NAND type flash memory, each of a plurality of memory blocks constituting the storage module may be represented by an equivalent circuit as shown in FIG. 22 .

The memory block BLKi illustrated in FIG. 22 represents a three-dimensional memory block formed on a substrate in a three-dimensional structure. For example, a plurality of memory NAND strings included in the memory block BLKi may be formed in a direction perpendicular to the substrate.

Referring to FIG. 22 , the memory block BLKi may include a plurality of memory NAND strings NS11 to NS33 connected between the bit lines BL1 , BL2 , and BL3 and the common source line CSL. Each of the plurality of memory NAND strings NS11 to NS33 may include a string select transistor SST, a plurality of memory cells MC1 , MC2 , ..., MC8 , and a ground select transistor GST. 22 , each of the plurality of memory NAND strings NS11 to NS33 includes eight memory cells MC1 , MC2 , ..., MC8 , but is not limited thereto.

The string select transistor SST may be connected to the corresponding string select lines SSL1 , SSL2 , and SSL3 . The plurality of memory cells MC1 , MC2 , ..., MC8 may be respectively connected to corresponding gate lines GTL1 , GTL2 , ..., GTL8 . The gate lines GTL1, GTL2, ..., GTL8 may correspond to word lines, and some of the gate lines GTL1, GTL2, ..., GTL8 may correspond to dummy word lines. The ground select transistor GST may be connected to the corresponding ground select lines GSL1 , GSL2 , and GSL3 . The string select transistor SST may be connected to the corresponding bit lines BL1 , BL2 , and BL3 , and the ground select transistor GST may be connected to the common source line CSL.

Word lines of the same height (eg, WL1 ) may be commonly connected, and the ground selection lines GSL1 , GSL2 , and GSL3 and the string selection lines SSL1 , SSL2 , and SSL3 may be separated from each other. 22 shows that the memory block BLK is connected to eight gate lines GTL1, GTL2, ..., GTL8 and three bit lines BL1, BL2, BL3, but is not necessarily limited thereto. no.

23 is a cross-sectional view illustrating a memory device 600 according to an exemplary embodiment of the present disclosure. The nonvolatile memory 230 of FIG. 1 may be applied to the memory device 600 of FIG. 23 .

Referring to FIG. 23 , the memory device 600 may have a chip to chip (C2C) structure. In the C2C structure, an upper chip including a cell region CELL is fabricated on a first wafer, a lower chip including a peripheral circuit region PERI is fabricated on a second wafer different from the first wafer, and then the upper chip It may mean connecting the chip and the lower chip to each other by a bonding method. For example, the bonding method may refer to a method of electrically connecting the bonding metal formed in the uppermost metal layer of the upper chip and the bonding metal formed in the uppermost metal layer of the lower chip to each other. For example, when the bonding metal is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method, and the bonding metal may be formed of aluminum or tungsten.

Each of the peripheral circuit area PERI and the cell area CELL of the memory device 600 may include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA. The peripheral circuit region PERI includes a first substrate 710 , an interlayer insulating layer 715 , a plurality of circuit elements 720a , 720b , and 720c formed on the first substrate 710 , and a plurality of circuit elements 720a . , 720b, 720c) connected to each of the first metal layers 730a, 730b, 730c, and the second metal layers 740a, 740b, 740c formed on the first metal layers 730a, 730b, 730c. can In an embodiment, the first metal layers 730a, 730b, and 730c may be formed of tungsten having a relatively high resistance, and the second metal layers 740a, 740b, and 740c may be formed of copper having a relatively low resistance. can

In the present specification, only the first metal layers 730a, 730b, 730c and the second metal layers 740a, 740b, and 740c are shown and described, but the present invention is not limited thereto. At least one or more metal layers may be further formed. At least some of the one or more metal layers formed on the second metal layers 740a, 740b, and 740c are formed of aluminum having a lower resistance than copper forming the second metal layers 740a, 740b, and 740c. can be

The interlayer insulating layer 715 is a first substrate to cover the plurality of circuit elements 720a, 720b, and 720c, the first metal layers 730a, 730b, and 730c, and the second metal layers 740a, 740b, and 740c. It is disposed on the 710 and may include an insulating material such as silicon oxide, silicon nitride, or the like.

Lower bonding metals 771b and 772b may be formed on the second metal layer 740b of the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 771b and 772b of the peripheral circuit area PERI may be electrically connected to the upper bonding metals 871b and 872b of the cell area CELL by a bonding method. , the lower bonding metals 771b and 772b and the upper bonding metals 871b and 872b may be formed of aluminum, copper, tungsten, or the like. The upper bonding metals 871b and 872b of the cell region CELL may be referred to as first metal pads, and the lower bonding metals 771b and 772b of the peripheral circuit area PERI may be referred to as second metal pads. can

The cell region CELL may provide at least one memory block. The cell region CELL may include a second substrate 810 and a common source line 820 . A plurality of word lines 831 - 838 ( 830 ) may be stacked on the second substrate 810 in a direction (Z-axis direction) perpendicular to the top surface of the second substrate 810 . String select lines and ground select lines may be disposed above and below the word lines 830 , respectively, and a plurality of word lines 830 may be disposed between the string select lines and the ground select line.

In the bit line bonding area BLBA, the channel structure CH may extend in a direction perpendicular to the top surface of the second substrate 810 to pass through the word lines 830 , the string selection lines, and the ground selection line. have. The channel structure CH may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer may be electrically connected to the first metal layer 850c and the second metal layer 860c. For example, the first metal layer 850c may be a bit line contact, and the second metal layer 860c may be a bit line. In an embodiment, the bit line may extend in a first direction (Y-axis direction) parallel to the top surface of the second substrate 810 .

23 , an area in which the channel structure CH and the bit line are disposed may be defined as the bit line bonding area BLBA. The bit line may be electrically connected to the circuit elements 720c providing the page buffer 893 in the peripheral circuit area PERI in the bit line bonding area BLBA. As an example, the bit line is connected to the upper bonding metals 871c and 872c in the peripheral circuit region PERI, and the upper bonding metals 871c and 872c are connected to the circuit elements 720c of the page buffer 893. It may be connected to the lower bonding metals 771c and 772c.

In the word line bonding area WLBA, the word lines 830 may extend in a second direction (X-axis direction) parallel to the top surface of the second substrate 810 , and include a plurality of cell contact plugs 841 . -847; 840). The word lines 830 and the cell contact plugs 840 may be connected to each other through pads provided by at least some of the word lines 830 extending to different lengths along the second direction (X-axis direction). have. A first metal layer 850b and a second metal layer 860b may be sequentially connected to the upper portions of the cell contact plugs 840 connected to the word lines 830 . The cell contact plugs 840 are formed in the word line bonding area WLBA through the upper bonding metals 871b and 872b of the cell area CELL and the lower bonding metals 771b and 772b of the peripheral circuit area PERI through a peripheral circuit. It may be connected to the region PERI.

The cell contact plugs 840 may be electrically connected to circuit elements 720b providing the row decoder 894 in the peripheral circuit region PERI. In an embodiment, the operating voltages of the circuit elements 720b providing the row decoder 894 may be different from the operating voltages of the circuit elements 720c providing the page buffer 893 . For example, the operating voltages of the circuit elements 720c providing the page buffer 893 may be greater than the operating voltages of the circuit elements 720b providing the row decoder 894 .

A common source line contact plug 880 may be disposed in the external pad bonding area PA. The common source line contact plug 880 may be formed of a metal, a metal compound, or a conductive material such as polysilicon, and may be electrically connected to the common source line 820 . A first metal layer 850a and a second metal layer 860a may be sequentially stacked on the common source line contact plug 880 . For example, an area in which the common source line contact plug 880 , the first metal layer 850a , and the second metal layer 860a are disposed may be defined as an external pad bonding area PA.

Meanwhile, input/output pads 705 and 805 may be disposed in the external pad bonding area PA. Referring to FIG. 23 , a lower insulating film 701 covering the lower surface of the first substrate 710 may be formed under the first substrate 710 , and first input/output pads 705 on the lower insulating film 701 . can be formed. The first input/output pad 705 is connected to at least one of the plurality of circuit elements 720a, 720b, and 720c disposed in the peripheral circuit region PERI through the first input/output contact plug 703 and the lower insulating layer 701 ) may be separated from the first substrate 710 by the In addition, a side insulating layer may be disposed between the first input/output contact plug 703 and the first substrate 710 to electrically separate the first input/output contact plug 703 from the first substrate 710 .

Referring to FIG. 23 , an upper insulating layer 801 covering the upper surface of the second substrate 810 may be formed on the second substrate 810 , and second input/output pads 805 on the upper insulating layer 801 . can be placed. The second input/output pad 805 may be connected to at least one of the plurality of circuit elements 720a , 720b , and 720c disposed in the peripheral circuit area PERI through the second input/output contact plug 803 .

In some embodiments, the second substrate 810 and the common source line 820 may not be disposed in the region where the second input/output contact plug 803 is disposed. Also, the second input/output pad 805 may not overlap the word lines 830 in the third direction (Z-axis direction). Referring to FIG. 23 , the second input/output contact plug 803 is separated from the second substrate 810 in a direction parallel to the top surface of the second substrate 810 , and an interlayer insulating layer 815 of the cell region CELL. may pass through and be connected to the second input/output pad 805 .

In some embodiments, the first input/output pad 705 and the second input/output pad 805 may be selectively formed. For example, the memory device 600 includes only the first input/output pad 705 disposed on the first substrate 710 , or the second input/output pad 805 disposed on the second substrate 810 . can contain only Alternatively, the memory device 600 may include both the first input/output pad 705 and the second input/output pad 805 .

In each of the external pad bonding area PA and the bit line bonding area BLBA included in each of the cell area CELL and the peripheral circuit area PERI, the metal pattern of the uppermost metal layer exists as a dummy pattern, or The uppermost metal layer may be empty.

In the external pad bonding area PA, the memory device 600 corresponds to the upper metal pattern 872a formed on the uppermost metal layer of the cell area CELL in the uppermost metal layer of the peripheral circuit area PERI. ), a lower metal pattern 773a having the same shape as the upper metal pattern 872a may be formed. The lower metal pattern 773a formed on the uppermost metal layer of the peripheral circuit region PERI may not be connected to a separate contact in the peripheral circuit region PERI. Similarly, in the external pad bonding area PA, the lower metal pattern of the peripheral circuit area PERI corresponds to the lower metal pattern formed on the uppermost metal layer of the peripheral circuit area PERI on the upper metal layer of the cell area CELL. An upper metal pattern having the same shape as the above may be formed.

Lower bonding metals 771b and 772b may be formed on the second metal layer 740b of the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 771b and 772b of the peripheral circuit area PERI may be electrically connected to the upper bonding metals 871b and 872b of the cell area CELL by a bonding method. .

In addition, in the bit line bonding area BLBA, the lower part of the peripheral circuit area PERI is located on the uppermost metal layer of the cell area CELL corresponding to the lower metal pattern 752 formed on the uppermost metal layer of the peripheral circuit area PERI. An upper metal pattern 892 having the same shape as the metal pattern 752 may be formed. In an exemplary embodiment, a contact may not be formed on the upper metal pattern 892 formed on the uppermost metal layer of the cell region CELL.

In the exemplary embodiment, corresponding to the metal pattern formed on the uppermost metal layer of one of the cell region CELL and the peripheral circuit region PERI, the uppermost metal layer of the other one of the cell region CELL and the peripheral circuit region PERI A reinforced metal pattern having the same cross-sectional shape as the formed metal pattern may be formed. Contacts may not be formed in the reinforced metal pattern.

24 is a diagram illustrating a data center to which the host storage system ( FIGS. 1 and 10 ) according to an exemplary embodiment of the present disclosure is applied.

Referring to FIG. 24 , a data center 3000 is a facility that collects various types of data and provides services, and may also be referred to as a data storage center. The data center 3000 may be a system for operating a search engine and a database, and may be a computing system used in a business such as a bank or a government institution. The data center 3000 may include application servers 3100 to 3100n and storage servers 3200 to 3200m. The number of application servers 3100 to 3100n and the number of storage servers 3200 to 3200m may be variously selected according to an embodiment, and the number of application servers 3100 to 3100n and the number of storage servers 3200 to 3200m 3200m) may be different.

The application server 3100 or the storage server 3200 may include at least one of processors 3110 and 3210 and memories 3120 and 3220 . If the storage server 3200 is described as an example, the processor 3210 may control the overall operation of the storage server 3200 , and access the memory 3220 to execute instructions and/or data loaded into the memory 3220 . can run Memory 3220 may include DDR Double Data Rate Synchronous DRAM (SDRAM), High Bandwidth Memory (HBM), Hybrid Memory Cube (HMC), Dual In-line Memory Module (DIMM), Optane DIMM, and/or Non-Volatile DIMM (NVMDIMM). ) can be According to an embodiment, the number of processors 3210 and the number of memories 3220 included in the storage server 3200 may be variously selected. In one embodiment, processor 3210 and memory 3220 may provide a processor-memory pair. In one embodiment, the number of processors 3210 and the number of memories 3220 may be different from each other. The processor 3210 may include a single-core processor or a multi-core processor. The above description of the storage server 3200 may be similarly applied to the application server 3100 . According to an embodiment, the application server 3100 may not include the storage device 3150 . The storage server 3200 may include at least one or more storage devices 3250 . The number of storage devices 3250 included in the storage server 3200 may be variously selected according to embodiments.

The application servers 3100 to 3100n and the storage servers 3200 to 3200m may communicate with each other through the network 3300 . The network 3300 may be implemented using Fiber Channel (FC) or Ethernet. In this case, FC is a medium used for relatively high-speed data transmission, and an optical switch providing high performance/high availability may be used. Depending on the access method of the network 3300 , the storage servers 3200 to 3200m may be provided as file storage, block storage, or object storage.

In one embodiment, network 3300 may be a storage-only network, such as a storage area network (SAN). For example, the SAN may be an FC-SAN that uses an FC network and is implemented according to FC Protocol (FCP). As another example, the SAN may be an IP-SAN that uses a TCP/IP network and is implemented according to the iSCSI (SCSI over TCP/IP or Internet SCSI) protocol. In other embodiments, network 3300 may be a generic network, such as a TCP/IP network. For example, the network 3300 may be implemented according to protocols such as FC over Ethernet (FCoE), Network Attached Storage (NAS), and NVMe over Fabrics (NVMe-oF).

Hereinafter, the application server 3100 and the storage server 3200 will be mainly described. A description of the application server 3100 may be applied to other application servers 3100n, and a description of the storage server 3200 may also be applied to other storage servers 3200m.

The application server 3100 may store data requested to be stored by a user or a client in one of the storage servers 3200 to 3200m through the network 3300 . Also, the application server 3100 may obtain data read requested by the user or the client from one of the storage servers 3200 to 3200m through the network 3300 . For example, the application server 3100 may be implemented as a web server or DBMS (Database Management System).

The application server 3100 may access the memory 3120n or the storage device 3150n included in another application server 3100n through the network 3300, or the storage servers 3200- through the network 3300 3200m) may access the memories 3220-3220m or the storage device 3250-3250m. Accordingly, the application server 3100 may perform various operations on data stored in the application servers 3100-3100n and/or the storage servers 3200-3200m. For example, the application server 3100 may execute a command for moving or copying data between the application servers 3100-3100n and/or the storage servers 3200-3200m. At this time, data is transferred from the storage device 3250-3250m of the storage servers 3200-3200m via the memories 3220-3220m of the storage servers 3200-3200m, or directly to the application servers 3100-3100n. may be moved to the memory 3120-3120n of Data moving through the network 3300 may be encrypted data for security or privacy.

Taking the storage server 3200 as an example, the interface 3254 may provide a physical connection between the processor 3210 and the controller 3251 and a physical connection between the Network InterConnect (NIC) 3240 and the controller 3251 . . For example, the interface 3254 may be implemented in a DAS (Direct Attached Storage) method for directly connecting the storage device 3250 with a dedicated cable. Also, for example, the interface 3254 may be an Advanced Technology Attachment (ATA), Serial ATA (SATA), external SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral (PCI) Component Interconnection), PCIe (PCI express), NVMe (NVM express), IEEE 1394, USB (universal serial bus), SD (secure digital) card, MMC (multi-media card), eMMC (embedded multi-media card), It may be implemented in various interface methods, such as a universal flash storage (UFS), an embedded universal flash storage (eUFS), and/or a compact flash (CF) card interface.

The storage server 3200 may further include a switch 3230 and a NIC 3240 . The switch 3230 may selectively connect the processor 3210 and the storage device 3250 or the NIC 3240 and the storage device 3250 under the control of the processor 3210 .

In one embodiment, the NIC 3240 may include a network interface card, a network adapter, and the like. The NIC 3240 may be connected to the network 3300 by a wired interface, a wireless interface, a Bluetooth interface, an optical interface, or the like. The NIC 3240 may include an internal memory, a digital signal processor (DSP), a host bus interface, and the like, and may be connected to the processor 3210 and/or the switch 3230 through the host bus interface. The host bus interface may be implemented as one of the examples of interface 3254 described above. In an embodiment, the NIC 3240 may be integrated with at least one of the processor 3210 , the switch 3230 , and the storage device 3250 .

In the storage servers 3200-3200m or the application servers 3100-3100n, the processor sends a command to the storage devices 3150-3150n and 3250-3250m or the memory 3120-3120n, 3220-3220m to program the data. or lead. In this case, the data may be error-corrected data through an ECC (Error Correction Code) engine. The data is data processed by Data Bus Inversion (DBI) or Data Masking (DM), and may include Cyclic Redundancy Code (CRC) information. The data may be encrypted data for security or privacy.

The storage devices 3150-3150n and 3250-3250m may transmit a control signal and a command/address signal to the NAND flash memory devices 3252-3252m in response to a read command received from the processor. Accordingly, when data is read from the NAND flash memory device 3252-3252m, a read enable (RE) signal may be input as a data output control signal to output data to the DQ bus. A data strobe (DQS) may be generated using the RE signal. The command and address signals may be latched in the page buffer according to a rising edge or a falling edge of a write enable (WE) signal.

The controller 3251 may control overall operations of the storage device 3250 . In one embodiment, the controller 3251 may include static random access memory (SRAM). The controller 3251 may write data to the NAND flash 3252 in response to a write command, or may read data from the NAND flash 3252 in response to a read command. For example, write commands and/or read commands may be from processor 3210 in storage server 3200, processor 3210m in another storage server 3200m, or processors 3110, 3110n in application servers 3100, 3100n. can be provided. The DRAM 3253 may temporarily store (buffer) data to be written to the NAND flash 3252 or data read from the NAND flash 3252 . Also, the DRAM 3253 may store metadata. Here, the metadata is user data or data generated by the controller 3251 to manage the NAND flash 3252 . The storage device 3250 may include a Secure Element (SE) for security or privacy.

Exemplary embodiments have been disclosed in the drawings and specification as described above. Although the embodiments have been described using specific terms in the present specification, these are used only for the purpose of explaining the technical spirit of the present disclosure, and not used to limit the meaning or the scope of the present disclosure described in the claims. Therefore, it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the true technical protection scope of the present disclosure should be defined by the technical spirit of the appended claims.

Claims (20)

A host controller interface configured to provide interfacing between a host device and a storage device, the host controller interface comprising:
a doorbell register configured to store a head pointer and a tail pointer of at least one cue;
an entry buffer configured to store a first command or a first response included in the at least one queue;
an arbiter configured to arbitrate the order of the at least one queue;
a first router configured to route the first command to be stored in the entry buffer in order; and
and a second router configured to route the first response to be stored in the doorbell register. According to claim 1,
the at least one queue,
A host controller interface characterized in that it is a plurality of circular queues. According to claim 1,
the at least one queue,
including a submission queue and a completion queue;
The doorbell register is
a first head pointer and a first tail pointer to the submission queue, and
and storing a second head pointer and a second tail pointer for the completion queue. 4. The method of claim 3,
The first head pointer is
The host controller interface of claim 1, wherein the first command is updated as it is stored in the entry buffer. 4. The method of claim 3,
The second tail pointer is
and the first response is updated as the first response is stored in the completion queue. According to claim 1,
The host controller interface further comprising a bitmap doorbell register configured to indicate whether the entry buffer can be stored using a bitmap. 7. The method of claim 6,
The bitmap doorbell register,
Based on the storage of the first command or the first response in the entry buffer, bit information corresponding to a data area in which the first command or the first response is stored is changed from bit 0 to bit 1. Host controller interface. According to claim 1,
The host device,
a first core for processing the first submission queue and the first completion queue; and
a second core for processing a second submission queue and a second completion queue;
The mediator is
The host controller interface of claim 1, wherein a queue having a higher priority among the first submission queue and the second submission queue is processed first. 9. The method of claim 8,
The priority is
In the first submission queue or the second submission queue, according to whether a priority flag is attached, whether it is input first, whether there is insufficient empty space, whether the weight is high, or whether it is predetermined with high priority A host controller interface, characterized in that determined. A storage system comprising a host device and a storage device, the storage system comprising:
The host device transmitting a command to the storage device,
a host memory for storing at least one queue; and
a host controller comprising at least one core configured to process the at least one queue, and a host controller interface configured to provide interfacing with the host memory;
The storage device is
providing a response that is a result of performing a memory operation based on the command to the host device;
The host controller interface comprises:
and a doorbell register configured to store a head pointer and a tail pointer for the at least one queue. 11. The method of claim 10,
the at least one queue,
including a submission queue and a completion queue;
The doorbell register is
a first head pointer and a first tail pointer to the submission queue, and
and storing a second head pointer and a second tail pointer for the completion queue. 12. The method of claim 11,
The first head pointer is
The storage system is updated as the command is stored in an entry buffer included in the host controller. 12. The method of claim 11,
The second tail pointer is
The storage system of claim 1, wherein the response is updated as the response is stored in the completion queue. 11. The method of claim 10,
The host controller interface comprises:
an entry buffer configured to store the command or the response;
an arbiter configured to arbitrate the order of the at least one queue;
a first router configured to route the commands such that they can be stored in the entry buffer in an orderly manner; and
and a second router configured to route the response to be stored in the doorbell register. 15. The method of claim 14,
the at least one core,
a first core for processing the first submission queue and the first completion queue; and
a second core for processing a second submission queue and a second completion queue;
The mediator is
The storage system of claim 1 , wherein a queue having a higher priority among the first submission queue and the second submission queue is processed first. A method of operating a host controller interface configured to provide interfacing between a host device and a storage device using at least one queue comprising at least one command, the method comprising:
arbitrating an order of a plurality of commands including a first command included in the first queue;
storing the first command in an entry buffer;
updating a first head pointer of the first queue;
storing a second command in the entry buffer;
updating a second head pointer of a second queue including the second command; and
and sequentially providing the first command and the second command to the storage device. 17. The method of claim 16,
Arbitrating the order of the plurality of commands comprises:
and processing a queue having a higher priority among the first queue and the second queue first. 18. The method of claim 17,
The step of processing the high-priority queue first is,
determining whether a priority flag is attached among the first queue and the second queue;
determining a first input queue among the first queue and the second queue; and
and determining a queue having insufficient empty space among the first queue and the second queue. 18. The method of claim 17,
The step of processing the high-priority queue first is,
and processing the queues for a uniform time sequentially in an input order. 18. The method of claim 17,
The step of processing the high-priority queue first is,
checking a weight per queue given according to importance; and
and processing the queues in order of increasing the weight.

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