KR20210148009A - Semiconductor device and method for fabricating the same - Google Patents

Abstract

Provided is a semiconductor device with improved reliability. The semiconductor device comprises: a substrate; a laminated stacked structure including a plurality of gate electrodes alternately laminated on the substrate in a first direction; a source conductive layer disposed between the substrate and the laminated structure and including a first etch stop hole; a first channel hole passing through the laminated structure and connected to the first etch stop hole and a channel insulating layer sequentially formed in the first channel hole along a profile of the first channel hole; and a first channel structure including a channel film and a channel filling film. A portion of the channel insulating layer is disposed in the first etch stop hole.

Description

Semiconductor device and method for manufacturing the same

The present invention relates to a semiconductor device and a method for manufacturing the same.

In an electronic system that requires data storage, a semiconductor device capable of storing high-capacity data is in demand. Accordingly, a method for increasing the data storage capacity of a semiconductor device is being studied. For example, as a method for increasing the data storage capacity of a semiconductor device, a semiconductor device including memory cells arranged three-dimensionally instead of two-dimensionally arranged memory cells has been proposed.

SUMMARY The technical problem to be solved by the present invention is to provide a semiconductor device with improved reliability.

Another technical problem to be solved by the present invention is to provide a method of manufacturing a semiconductor device capable of manufacturing a semiconductor device with improved reliability.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

A semiconductor device according to some embodiments of the present invention for achieving the above technical object includes a substrate, a stacked structure including a plurality of gate electrodes alternately stacked on the substrate in a first direction, and disposed between the substrate and the stacked structure, , a source conductive layer including a first etch stop hole, a first channel hole passing through the stacked structure, connected to the first etch stop hole, and a channel insulating film sequentially formed along the profile of the first channel hole in the first channel hole, It includes a first channel structure including a channel layer and a channel filling layer, and a portion of the channel insulating layer is disposed in the first etch stop hole.

In a semiconductor device manufacturing method according to some embodiments of the present invention for achieving the above technical problem, a source conductive layer is formed on a substrate, an etch stop hole is formed in the source conductive layer, a metal is filled in the etch stop hole, A mold structure in which a mold insulating layer and a sacrificial insulating layer are alternately stacked on the source conductive layer is formed, a vertical channel hole passing through the mold structure is formed on the etch stop hole, the metal in the etch stop hole is removed, and the vertical channel hole passing through the mold structure is formed. and forming a channel insulating layer in the channel hole and the etch stop hole.

The details of other embodiments are included in the detailed description and drawings.

1 is a block diagram illustrating a semiconductor device according to some example embodiments.
2 is a perspective view schematically illustrating a semiconductor device according to some example embodiments.
3 is a circuit diagram illustrating one memory cell block among a plurality of memory cell blocks included in a semiconductor device according to some embodiments.
4 is a plan view illustrating one stacked structure among stacked structures included in a semiconductor device according to some embodiments.
FIG. 5 is an enlarged view illustrating part B of FIG. 4 .
6 and 7 are cross-sectional views taken along line AA of FIG. 4 .
8 and 9 are enlarged views illustrating a portion P of FIG. 6 .
10 is an enlarged view illustrating a portion Q of FIG. 8 .
11 to 13 are enlarged views illustrating a portion R of FIG. 10 .
14 to 22 are diagrams for explaining a method of manufacturing a semiconductor device according to some embodiments.

Hereinafter, embodiments according to the technical spirit of the present invention will be described with reference to the accompanying drawings.

1 is a block diagram illustrating a semiconductor device according to some example embodiments. Referring to FIG. 1 , a semiconductor device 10 according to some embodiments may include a memory cell array 20 and a peripheral circuit 30 .

The memory cell array 20 may include a plurality of memory cell blocks BLK1 to BLKn. Each of the memory cell blocks BLK1 to BLKn may include a plurality of memory cells. The memory cell blocks BLK1 to BLKn are connected to the peripheral circuit 30 through bit lines BL, word lines WL, at least one string selection line SSL, and at least one ground selection line GSL. can be connected to

Specifically, the memory cell blocks BLK1 to BLKn may be connected to the row decoder 33 through word lines WL, at least one string select line SSL, and at least one ground select line GSL. . Also, the memory cell blocks BLK1 to BLKn may be connected to the page buffer 35 through the bit lines BL.

The peripheral circuit 30 may receive an address ADDR, a command CMD, and a control signal CTRL from the outside of the semiconductor device 10 , and transmit data DATA from an external device of the semiconductor device 10 . can transmit and receive. The peripheral circuit 30 may include a control logic 37 , a row decoder 33 , and a page buffer 35 .

Although not shown, the peripheral circuit 30 is an input/output circuit, a voltage generator circuit for generating various voltages necessary for the operation of the semiconductor device 10 , and an error in data DATA read from the memory cell array 20 . Various sub-circuits, such as an error correction circuit for

The control logic 37 may be connected to the row decoder 33 , the voltage generator, and the input/output circuit. The control logic 37 may control the overall operation of the semiconductor device 10 . The control logic 37 may generate various internal control signals used in the semiconductor device 10 in response to the control signal CTRL.

For example, the control logic 37 may adjust the voltage level provided to the word lines WL and the bit lines BL when a memory operation such as a program operation or an erase operation is performed.

The row decoder 33 may select at least one of the plurality of memory cell blocks BLK1 to BLKn in response to the address ADDR, and at least one word line WL of the selected memory cell blocks BLK1 to BLKn. , at least one string selection line SSL and at least one ground selection line GSL may be selected. The row decoder 33 may transmit a voltage for performing a memory operation to the word line WL of the selected memory cell blocks BLK1 to BLKn.

The page buffer 35 may be connected to the memory cell array 20 through bit lines BL. The page buffer 35 may operate as a write driver or a sense amplifier. Specifically, during a program operation, the page buffer 35 operates as a write driver to apply a voltage according to the data DATA to be stored in the memory cell array 20 to the bit lines BL. Meanwhile, during a read operation, the page buffer 35 may operate as a sense amplifier to sense data DATA stored in the memory cell array 20 .

2 is a perspective view schematically illustrating a semiconductor device according to some example embodiments. Referring to FIG. 2 , a semiconductor memory device according to some embodiments may include a peripheral logic structure PS and a cell stack structure ST.

The cell stack structure ST may be stacked on the peripheral logic structure PS. That is, the peripheral logic structure PS and the cell stack structure ST may overlap in a plan view. The semiconductor memory device according to some embodiments may have a COP (Cell Over Peri) structure. However, the technical idea of the present application is not limited to the COP structure, and unlike FIG. 2 , the peripheral logic structures PS may not overlap in a plan view.

For example, the cell stack structure ST may include the memory cell array 20 of FIG. 1 . The peripheral logic structure PS may include the peripheral circuit 30 of FIG. 1 .

The cell stack structure ST may include a plurality of memory cell blocks BLK1 to BLKn disposed on the peripheral logic structure PS.

3 is a circuit diagram illustrating one memory cell block among a plurality of memory cell blocks included in a semiconductor device according to some embodiments.

Referring to FIG. 3 , a memory cell block according to some embodiments may include a common source line CSL, a plurality of bit lines BL, and a plurality of common source lines CSL and bit lines BL disposed between the common source line CSL and the bit lines BL. may include cell strings (CSTR) of

A plurality of cell strings CSTR may be connected in parallel to each of the bit lines BL0 - BL2 . The plurality of cell strings CSTR may be commonly connected to a common source line CSL. That is, a plurality of cell strings CSTR may be disposed between the plurality of bit lines BL0 - BL2 and one common source line CSL. A plurality of common source lines CSL may be two-dimensionally arranged. Here, the same voltage may be applied to the common source line CSL, or each of the common source lines CSL may be electrically controlled.

For example, each of the cell strings CSTR may include series-connected string select transistors SST, series-connected memory cells MCT, and a ground select transistor GST. In addition, each of the memory cells MCT includes a data storage element.

For example, each of the cell strings CSTR may include a string selection transistor SST connected in series with the bit lines BL0 - BL2. The ground select transistor GST may be connected to the common source line CSL. The memory cells MCT may be connected in series between the string select transistor SST and the ground select transistor GST.

Furthermore, each of the cell strings CSTR may further include a dummy cell DMCT connected between the string select transistor SST and the memory cell MCT.

Although not shown in the drawing, the dummy cell DMCT may also be connected between the ground selection transistor GST and the memory cell MCT. As another example, the ground selection transistor GST in each of the cell strings CSTR may be configured of a plurality of MOS transistors connected in series. As another example, each of the cell strings CSTR may include a plurality of string selection transistors connected in series. As another example, each of the cell strings CSTR may further include an erase control transistor disposed between the bit lines BL0 - BL2 and the string select transistor SST. The erase control transistor may be connected in series with the string select transistor SST.

According to some embodiments, the string select transistor SST may be controlled by the string select line SSL. The memory cells MCT may be controlled by a plurality of word lines WL0 - WLn, and the dummy cells DMCT may be controlled by a dummy word line DWL. Also, the ground select transistor GST may be controlled by the ground select line GSL. The common source line CSL may be commonly connected to sources of the ground select transistors GST.

One cell string CSTR may include a plurality of memory cells MCT having different distances from the common source lines CSL. In addition, a plurality of word lines WL0 - WLn and DWL may be disposed between the common source lines CSL and the bit lines BL0 - BL2 .

Gate electrodes of the memory cells MCT, which are disposed at substantially the same distance from the common source lines CSL, may be in an equipotential state by being commonly connected to one of the word lines WLO-WLn and DWL. Alternatively, although the gate electrodes of the memory cells MCT are disposed at substantially the same level from the common source lines CSL, the gate electrodes disposed in different rows or columns may be independently controlled.

The ground selection lines GSL0 - GSL2 and the string selection lines SSL may extend in the same direction as the word lines WL0 - WLn and DWL, for example. The ground selection lines GSL0 - GSL2 and the string selection line SSL disposed at substantially the same level from the common source lines CSL may be electrically separated from each other.

Although not shown in the drawings, when the cell string CSTR includes an erase control transistor, the erase control transistors may be controlled by a common erase control line. The erase control transistors generate gate induced drain leakage (GIDL) during an erase operation of the memory cell array. That is, the erase control transistors may be GIDL transistors.

4 is a plan view illustrating one stacked structure among stacked structures included in a semiconductor device according to some embodiments. FIG. 5 is an enlarged view illustrating part B of FIG. 4 . 6 and 7 are cross-sectional views taken along line A-A of FIG. 4 . 8 and 9 are enlarged views illustrating a portion P of FIG. 6 . 10 is an enlarged view illustrating a portion Q of FIG. 8 . 11 to 13 are enlarged views illustrating a portion R of FIG. 10 .

For reference, FIG. 5 illustrates a cross-section of a lowermost portion of the channel hole CH and a cross-section of an uppermost portion of the etch stop hole 330 .

4, 6, and 7 , the cell stack structure ST may include a second cell extension area CER2 extending in the first direction X from the cell area CR. Also, the cell stack structure ST may include a cell region CR and a first cell extension region CER1 extending from the cell region CR in the second direction Y.

The plurality of electrode separation regions ESR may be disposed in the cell stack structure ST. Each electrode separation region ESR may extend in the first direction X. A plurality of channel structures CS passing through the cell stack structure ST may be disposed between the adjacent electrode separation regions ESR.

The cell stack structure ST may include a plurality of gate electrode layers 210 that are metal layers stacked in the third direction Z and a plurality of insulating layers 250 . The plurality of gate electrode layers 210 may be disposed between the plurality of insulating layers 250 . The plurality of gate electrode layers 210 and the plurality of insulating layers 250 may be alternately and repeatedly stacked on the substrate 101 .

Referring to FIG. 5 , the channel hole CH and the etch stop hole 330 may overlap. The channel hole CH may be disposed on the etch stop hole 330 . The cross-section of the uppermost portion of the channel hole CH and the cross-section of the uppermost portion of the etch stop hole 330 may be the same. A cross-section of the lowermost portion of the channel hole CH may be smaller than a cross-section of the uppermost portion of the etch stop hole 330 .

6 to 11 , the semiconductor device according to some embodiments may include a peripheral circuit region PERI and a cell region CELL.

The peripheral circuit region PERI includes the first substrate 100 , the interlayer insulating layer 150 , the plurality of circuit elements TR1 , TR2 , TR3 , 220a , and 220b formed on the first substrate 100 , and a plurality of circuit elements. The first metal layers 244, 230a, 230b connected to each of the TR1, TR2, TR3, 220a, and 220b, and the second metal layer 240 formed on the first metal layers 244, 230a, 230b, 240a, 240b) may be included. The peripheral circuit region PERI may include the peripheral circuit 30 of FIG. 1 and the peripheral logic structure PS of FIG. 2 .

In some embodiments, the first to third circuit elements TR1 , TR2 , and TR3 may provide a decoder circuit in the peripheral circuit region PERI. In some embodiments, the fourth circuit element 220a may provide a logic circuit in the peripheral circuit region PERI. In some embodiments, the fifth circuit element 220b may provide a page buffer in the peripheral circuit region PERI.

6 and 7, only the first metal layers 244, 230a, 230b and the second metal layers 240, 240a, 204b are illustrated, but the present invention is not limited thereto, and the second metal layers 240, 240a, 240b). At least one metal layer may be further formed thereon. At least a portion of the one or more metal layers formed on the second metal layers 240 , 240a and 240b may be formed of aluminum or the like.

In some embodiments, the first metal layers 244 , 230a , and 230b and the second metal layers 240 , 240a , and 240b may be formed of tungsten or copper having a relatively low resistance.

The interlayer insulating layer 150 is formed to cover the plurality of circuit elements TR1, TR2, TR3, 220a, 220b, the first metal layers 244, 230a, 230b, and the second metal layers 240, 240a, 240b. 1 may be disposed on the substrate 100 .

The cell region CELL may provide at least one memory block. The cell region CELL may be disposed on the peripheral circuit region PERI. The cell region CELL may include a source conductive layer 310 , a support layer 320 , a stack structure 200 , and a channel structure CS.

The source conductive layer 310 may be disposed on the substrate. The source conductive layer 310 may be a common source plate. The source conductive layer 310 may serve as a common source line (CSL of FIG. 3 ).

The source conductive layer 310 may include at least one of a conductive semiconductor layer, a metal silicide layer, and a metal layer. When the source conductive layer 310 includes a conductive semiconductor film, the source conductive layer 310 is, for example, silicon (Si), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), or indium gallium. It may include at least one of arsenic (InGaAs), aluminum gallium arsenide (AlGaAs), or a combination thereof. The source conductive layer 310 may have a crystal structure including at least one selected from single crystal, amorphous, and polycrystalline. The source conductive layer 310 may include at least one of p-type impurities, n-type impurities, and carbon included in the semiconductor layer.

The source conductive layer 310 may include an etch stop hole 330 and a dummy etch stop layer 335 . The etch stop hole 330 and the dummy etch stop layer 335 may include recesses recessed from the top surface to the bottom surface of the source conductive layer 310 . The top surface of the etch stop hole 330 and the dummy etch stop layer 335 may be the same as the top surface of the source conductive layer 310 . The etch stop hole 330 may be connected to the channel hole CH.

The etch stop hole 330 may include a channel insulating layer 110 or a channel layer 120 extending from the channel hole CH.

The dummy etch stop layer 335 may not contact the channel hole CH. The dummy etch stop layer 335 may include a metal material. In some embodiments, the dummy etch stop layer 335 may include tungsten (W).

Although the side surface of the etch stop hole 330 is not inclined and is perpendicular to the upper surface of the source conductive layer 310 in FIGS. 6 to 10 , the embodiment is not limited thereto. For example, the side surface of the etch stop hole 330 may have a slope like the side surface of the channel hole CH. That is, the width of the upper portion of the etch stop hole 330 may be greater than the width of the lower portion of the etch stop hole 330 .

The support layer 320 may be disposed on the source conductive layer 310 . The support layer 320 may be disposed on the etch stop hole 330 and the dummy etch stop layer 335 . The support layer 320 may include, for example, a semiconductor material such as silicon (Si), germanium (Ge), or a mixture thereof.

The stacked structure 200 may include a plurality of gate electrode layers 210 and a plurality of insulating layers 250 that are alternately stacked.

A plurality of word lines may be stacked on the support layer 320 in the third direction Z crossing the top surface of the support layer 320 . The plurality of word lines may correspond to the plurality of gate electrode layers 210 . A string select line and a ground select line may be disposed above and below the word lines, respectively.

Referring to FIG. 9 , the channel hole CH may extend in the third direction Z to pass through the word lines, the string selection lines, and the ground selection line. The channel hole CH may pass through the stack structure 200 in the third direction Z. The first channel hole CH1 may pass through the stack structure 200 and the support layer 320 in the third direction Z to be connected to the etch stop hole 330 in the source conductive layer 310 . The second channel hole CH2 may not completely penetrate the stack structure 200 and may not be connected to the etch stop hole 330 . The second channel hole CH2 may overlap the dummy etch stop layer 335 . The second channel hole CH2 may be disposed on the dummy etch stop layer 335 .

The channel hole CH may be formed as a multi-stack as shown in FIG. 6 or as a single stack as shown in FIG. 7 .

The channel structure CS may be electrically connected to the first metal layer 350c and the second metal layer 360c. For example, the first metal layer 350c may be a bit line contact, and the second metal layer 360c may be a bit line. In some embodiments, the second metal layer 360c may extend in one direction (eg, the second direction Y) parallel to the top surface of the source conductive layer 310 . In some embodiments, the second metal layer 360c may be electrically connected to the fifth circuit element 230b providing a page buffer in the peripheral circuit region PERI.

The channel structure CS may be disposed on the etch stop hole 330 disposed in the source conductive layer 310 . The channel structure CS may be connected to the etch stop hole 330 disposed in the source conductive layer 310 .

The channel structure CS may be disposed in the channel hole CH. The channel structure CS may penetrate the stack structure 200 . The channel structure CS may extend in the third direction Z. The channel structure CS includes the channel insulating layer 110 sequentially formed along the profile of the channel hole CH, the channel layer 120 on the channel insulating layer 110 , and the channel layer 120 on the channel layer 120 to fill the channel hole CH. A channel filling layer 130 may be included.

The channel layer 120 may pass through the stacked structure 200 to cross the plurality of gate layers LCL1 to LCLN and UCL1 to UCLN. Although the channel film 120 is illustrated as having a cup shape, this is only exemplary. For example, the channel film 120 may have various shapes, such as a cylindrical shape, a rectangular cylindrical shape, and a hollow filler shape. The channel film 120 may be connected to the support layer 320 . A lower end of a side surface of the channel film 120 may be exposed to contact the support layer 320 .

The channel layer 120 may include, for example, a semiconductor material such as single crystal silicon, polycrystalline silicon, an organic semiconductor material, and a carbon nanostructure, but is not limited thereto.

The channel insulating layer 110 may be interposed between the channel layer 120 and the plurality of gate layers LCL1 to LCLN and UCL1 to UCLN. The channel insulating layer 110 may extend along a side surface of the channel layer 120 .

The channel insulating layer 110 may include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, and a high-k material having a dielectric constant greater than that of silicon oxide. The high-k material is, for example, aluminum oxide, hafnium oxide, lanthanum oxide, tantalum oxide, titanium oxide, lanthanum hafnium oxide), lanthanum aluminum oxide, dysprosium scandium oxide, and combinations thereof.

In some embodiments, the channel insulating layer 110 may include a plurality of layers. For example, the channel insulating layer 110 may include a blocking insulating layer 111 , a charge storage layer 112 , and a tunnel insulating layer 113 sequentially disposed along the profile of the channel hole CH.

The blocking insulating layer 111 may include, for example, silicon oxide or a high-k material having a higher dielectric constant than silicon oxide (eg, aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ )). The charge storage layer 112 may include, for example, silicon nitride. The tunnel insulating layer 113 may include, for example, silicon oxide or a high-k material having a higher dielectric constant than silicon oxide (eg, aluminum oxide (Al ₂ O ₃ ), hafnium oxide (HfO ₂ )).

The blocking insulating layer 111 , the charge storage layer 112 , and the tunnel insulating layer 113 may be separated from the lower portion of the channel structure CS. The support layer 320 may be disposed between the separated blocking insulating layer 111 , the charge storage layer 112 , and the tunnel insulating layer 113 . The support layer 320 may electrically connect the source conductive layer 310 and the channel layer 120 to each other.

The channel filling layer 130 may be formed to fill the inside of the channel layer 120 . The channel film 120 may extend along the side surface and the bottom surface of the channel filling film 130 . The channel filling layer 130 may include, for example, silicon oxide, but is not limited thereto.

The channel insulating layer 110 may extend in the third direction Z along the profile of the channel hole CH, and may extend to the etch stop hole 330 . A portion of the channel insulating layer 110 may be disposed in the etch stop hole 330 .

Specifically, the blocking insulating layer 111 may include an upper blocking insulating layer 111a disposed in the channel hole CH and a lower blocking insulating layer 111b disposed in the etch stop hole 330 . The charge storage layer 112 may include an upper charge storage layer 112a disposed in the channel hole CH and a lower charge storage layer 112b disposed in the etch stop hole 330 . Similarly, the tunnel insulating layer 113 may include an upper tunnel insulating layer 113a disposed in the channel hole CH and a lower tunnel insulating layer 113b disposed in the etch stop hole 330 .

The lower blocking insulating layer 111b may be formed in the etch stop hole 330 along the profile of the etch stop hole 330 . The lower charge storage layer 112b may be formed on the lower blocking insulating layer 111b. That is, the lower blocking insulating layer 111b and the lower charge storage layer 112b may be sequentially disposed along the profile of the etch stop hole 330 .

The lower tunnel insulating layer 113b may be disposed on the lower charge storage layer 112b and may fill the etch stop hole 330 . The lower tunnel insulating layer 113b may be disposed under the channel layer 120 .

The channel layer 120 may extend in the third direction Z along the profile of the channel hole CH and the channel insulating layer 110 , and may extend to the etch stop hole 330 . A portion of the channel insulating layer 110 may be disposed in the etch stop hole 330 . The channel film 120 may pass through the support layer 320 , and a lower end of the channel film 120 may be disposed in the etch stop hole 330 . The channel layer 120 may contact the lower tunnel insulating layer 113b in the etch stop hole 330 .

The channel filling layer 130 may not extend to the etch stop hole 330 . For example, the lower surface of the channel filling layer 130 may be on the same plane as the upper surface of the etch stop hole 330 . For another example, the lower surface of the channel filling layer 130 may be disposed above the upper surface of the etch stop hole 330 .

In some embodiments, a cross-section of an uppermost portion of the channel hole CH may be the same as a cross-section of an uppermost portion of the etch stop hole 330 . Specifically, the first width W1 that is the width of the uppermost portion of the channel hole CH in the first direction X is the second width W2 that is the width of the uppermost portion of the etch stop hole 330 in the first direction X. ) can be the same as However, the embodiment is not limited thereto, and the first width W1 and the second width W2 may be different. For example, the first width W1 may be smaller than the second width W2 .

In some embodiments, a cross-section of a lowermost portion of the channel hole CH may be smaller than a cross-section of an uppermost portion of the etch stop hole 330 . Specifically, the third width W3 that is the width of the lowermost portion of the channel hole CH in the first direction X is the second width W2 that is the width of the uppermost portion of the etch stop hole 330 in the first direction X. ) can be smaller than The third width W3 , which is the width of the lowermost portion of the channel hole CH in the first direction X, may refer to the width in the first direction X of the channel hole CH in contact with the upper surface of the support layer 320 . can The second width W2, which is the width of the uppermost portion of the etch stop hole 330 in the first direction (X), is the width of the etch stop hole 330 in contact with the lower surface of the support layer 320 in the first direction (X). can be referred to

Referring to FIG. 12 , an air gap 337 may be disposed inside the etch stop hole 330 . A lower blocking insulating layer 111b, a lower charge storage layer 112b, and a lower tunnel insulating layer 113b are sequentially formed along the profile of the etch stop hole 330, and an air gap 337 is formed on the lower tunnel insulating layer 113b. can be formed in The air gap 337 may be formed when the lower tunnel insulating layer 113b conforms to the profile of the lower charge storage layer 112b and does not completely fill the etch stop hole 330 .

The air gap 337 may not be connected to the channel layer 120 . The channel layer 120 may penetrate the support layer 320 , extend to the etch stop hole 330 , and be connected to the lower tunnel insulating layer 113b. The channel layer 120 may extend to the lower tunnel insulating layer 113b and may not extend to the air gap 337 .

Referring to FIG. 13 , the second support layer 322 may pass through the etch stop hole 330 . Specifically, the second support layer 322 may not be disposed on the source conductive layer 310 , but may extend from the source conductive layer 310 under the etch stop hole 330 into the etch stop hole 330 . . The second support layer 322 may be formed from the source conductive layer 310 by a selective epitaxial growth (SEG) process.

The second support layer 322 may pass through the lower blocking insulating layer 111b, the lower charge storage layer 112b, and the lower tunnel insulating layer 113b in the etch stop hole 330 , and may be connected to the channel layer 120 . In the etch stop hole 330 , the second support layer 322 may be surrounded by a lower blocking insulating layer 111b , a lower charge storage layer 112b , and a lower tunnel insulating layer 113b .

The etch stop hole 330 may be disposed under the stack structure 200 . The top surface of the etch stop hole 330 may be the same as the top surface of the source conductive layer 310 . The upper surface of the etch stop hole 330 may be disposed on the same plane as the lower surface of the stack structure 200 . A second width W2 in the first direction X of the etch stop hole 330 on the top surface of the source conductive layer 310 is in the first direction of the channel hole CH on the top surface of the source conductive layer 310 . It may be larger than the fourth width W4 in (X).

14 to 22 are diagrams for explaining a method of manufacturing a semiconductor device according to some embodiments.

14 and 15 , a source conductive layer 310 may be formed, and a mask may be formed on the source conductive layer 310 . An etch stop hole 330 may be formed using a mask formed on the source conductive layer 310 . The etch stop hole 330 may have a recessed structure recessed from the top surface of the source conductive layer 310 .

Referring to FIG. 16 , a preliminary etch stop layer 330p may be formed on the etch stop hole 330 and the source conductive layer 310 . The preliminary etch stop layer 330p may include a metal material. For example, the preliminary etch stop layer 330p may include tungsten. The preliminary etch stop layer 330p may fill the etch stop hole 330 .

Referring to FIG. 17 , the preliminary etch stop layer 330p formed on the source conductive layer 310 is removed to form an etch stop layer 335a disposed in the etch stop hole 330 , and the source conductive layer 310 . A replacement insulating layer 320p may be formed thereon. Subsequently, a lower mold structure 200a in which a plurality of insulating layers 250 and a plurality of sacrificial layers 210a are alternately disposed may be formed on the replacement insulating layer 320p.

Referring to FIG. 18 , a channel hole CH is formed to overlap the etch stop layer 335a in the lower mold structure 200a , and a sacrificial layer 110a filling the channel hole CH may be formed.

Referring to FIG. 19 , an upper mold structure 200b in which a plurality of insulating layers 250a and a plurality of sacrificial layers 210a are alternately disposed may be formed on the lower mold structure 200a.

Referring to FIG. 20 , a channel hole is formed in the upper mold structure 200b to overlap the channel hole passing through the lower mold structure 200a, and a sacrificial film 110a in the channel hole passing through the lower mold structure 200a is formed. The etch stop layer 335a in the etch stop hole 330 may be removed. As the sacrificial layer 110a is removed, a channel hole CH in which a channel hole passing through the lower mold structure 200a and a channel hole passing through the upper mold structure 200b are connected may be formed.

8 and 21 , the channel insulating layer 110 extending along the profile of the channel hole CH and the etch stop hole 330 , the channel layer 120 on the channel insulating layer 110 , and the channel layer ( By forming the channel filling layer 130 on the 120 , the channel structure CS may be formed.

Referring to FIG. 22 , the replacement insulating layer 320p is removed, and the support layer 320 may be formed in the space where the replacement insulating layer 320p is removed. In this case, the channel insulating layer 110 under the channel structure CS may be removed to expose the channel layer 120 . The channel insulating film 110 under the channel structure CS is removed, and a lower poly layer is formed in the portion where the channel film 120 is exposed, and the channel film 120 is formed without removing the lower channel insulating film 110 . An upper support layer may be formed on the unexposed portion. The support layer 320 including the lower poly layer formed in the space from which the channel insulating layer 110 is removed may electrically connect the channel layer 120 and the source conductive layer 310 .

Subsequently, the plurality of sacrificial layers 210a of the first mold structure 200a and the second mold structure 200b may be removed. The gate electrode layer 210 may be formed in a space from which the plurality of sacrificial layers 210a are removed. Specifically, through a replacement metal gate process, the plurality of sacrificial layers 210a of the first mold structure 200a and the second mold structure 200b are replaced with the gate electrode layer 210, and the stacked structure (200) may be formed.

18 to 22 , all of the five channel holes CH pass through the lower mold structure 200a and are connected to the etch stop layer 335a, and the 5 etch stop holes are removed by removing the 5 etch stop layers 335a. Although 330 is shown to be formed, the embodiment is not limited thereto. For example, when one or more channel holes CH do not completely penetrate the lower mold structure 200a and are not connected to the etch stop layer 335a, the etch stop layer 335a is not connected to the channel hole CH. ) may not be removed. Accordingly, as shown in FIG. 9 , a dummy etch stop layer 335 may be formed.

The embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, but may be manufactured in various different forms, and those of ordinary skill in the art to which the present invention pertains. It will be understood by those skilled in the art that the present invention may be embodied in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive.

100: first substrate 110: channel insulating film
310: source conductive layer 320: support layer
330: etch stop hole 335: dummy etch stop film
CH: channel hole

Claims (10)

Board;
a stacked structure including a plurality of gate electrodes alternately stacked on the substrate in a first direction;
a source conductive layer disposed between the substrate and the stacked structure and including a first etch stop hole;
a first channel hole passing through the stack structure and connected to the first etch stop hole; and
and a first channel structure including a channel insulating film, a channel film, and a channel filling film sequentially formed in the first channel hole along a profile of the first channel hole,
A portion of the channel insulating layer is disposed in the first etch stop hole. The method of claim 1,
The first etch stop hole further includes an air gap formed on the channel insulating layer. The method of claim 1,
The width of the top surface of the first channel hole in the second direction and the width of the top surface of the first etch stop hole in the second direction are the same. The method of claim 1,
On the upper surface of the source conductive layer, the width of the first etch stop hole in the second direction is,
On the upper surface of the source conductive layer, a width of the first channel hole in the second direction is larger than that of the semiconductor device. The method of claim 1,
The channel insulating film,
A semiconductor device comprising: a blocking layer; a charge storage layer on the blocking layer; and a tunnel insulating layer on the charge storage layer. 6. The method of claim 5,
In the first etch stop hole,
The blocking layer and the charge storage layer are sequentially disposed along the profile of the first etch stop hole,
The tunnel insulating layer fills the first etch stop hole on the charge storage layer. The method of claim 1,
The semiconductor device of claim 1, further comprising a support layer disposed between the source conductive layer and the stacked structure and in direct contact with the channel layer through the channel insulating layer. The method of claim 1,
The source conductive layer further includes a second etch stop hole,
On the second etch stop hole, further comprising a second channel hole not in contact with the second etch stop hole,
The second etch stop hole includes a metal material. forming a source conductive layer on the substrate;
forming an etch stop hole in the source conductive layer;
Filling the metal in the etch stop hole,
forming a mold structure in which a mold insulating layer and a sacrificial insulating layer are alternately stacked on the source conductive layer;
A vertical channel hole passing through the mold structure is formed on the etch stop hole,
removing the metal in the etch stop hole,
and forming a channel insulating layer in the vertical channel hole and the etch stop hole. 10. The method of claim 9,
On the upper surface of the source conductive layer, the width of the etch stop hole is,
On the upper surface of the source conductive layer, the width of the vertical channel hole is larger than the semiconductor device manufacturing method.

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