KR20210137663A - Apparatus and method for learning a spiking neural network - Google Patents

Abstract

The present invention provides an apparatus and a method for training a spiking neural network. The apparatus comprises: a counter for receiving and counting a clock signal and outputting a shift signal in units of a predetermined time interval; a plurality of input shift registers which have a number corresponding to the number of a plurality of input neurons and a size corresponding to the number and size of a plurality of quantization intervals, which are time intervals divided by a quantization STDP function, and add a predetermined value to an input spike when the input spike is applied to a corresponding input neuron; a plurality of output shift registers which have a number corresponding to the number of a plurality of output neurons and a size corresponding to the number and size of the plurality of quantization sections, and add a predetermined value to an output spike when the output spike occurs in a corresponding output neuron; and a weight update unit which receives the values stored in the plurality of input shift registers and the plurality of output shift registers as accumulated weight change amounts and adds or subtracts the values from the weights stored in a plurality of synapses to update weights. Therefore, the apparatus can be easily implemented as hardware with a small size and at a low cost, and the size of a learning window can be easily varied.

Description

Spiking neural network learning apparatus and method {APPARATUS AND METHOD FOR LEARNING A SPIKING NEURAL NETWORK}

The present invention relates to a learning apparatus for a spiking neural network, and to a learning apparatus for a spiking neural network that implements spike timing dependent plasticity in hardware using a shift accumulator.

Neuromorphic technology is a technology to mimic the human neural structure in hardware. It is proposed to overcome the limitations that the existing computing architecture is very low in efficiency and consumes a lot of power compared to humans in performing cognitive processing functions. became

A typical example of neuromorphic technology is a spiking neural network (SNN). SNN is a neural network designed by mimicking the characteristics that the human brain has a neuron-synapse structure, and a synapse between neurons transmits information as a spike-type electrical signal. These SNNs process information based on the timing difference at which the spikes are transmitted.

1 is a diagram for explaining an operation concept of a spiking neural network.

As shown in (b) of Figure 1, the SNN is a plurality of input neurons (I1 ~ I3), a plurality of output neurons (O1 ~ O3), and a plurality of input neurons (I1 ~ I3) and a plurality of output neurons (O1 ~) O3) contains multiple synapses that connect each other. And each of the plurality of synapses has a weight obtained by learning. In FIG. 1, as an example, weights W12, W22, and W32 of three synapses connecting three input neurons (I1 to I3) and one output neuron (O2) are illustrated.

An input spike signal is applied to a plurality of input neurons (I1 to I3) at different timings (T1, T2, T4) as shown in (a). The input spike is a signal obtained in the form of a spike train by encoding input data in a predetermined manner. And the input neurons (I1 ~ I3) to which the input spike is applied transmit the spike to a number of output neurons (O1 ~ O3) along the synapse. At this time, the weight of each synapse is weighted and transmitted to the input spike, and each of the multiple output neurons (O1 to O3) to which the weighted input spike is transmitted is based on the timing at which the input spike is transmitted and the weight assigned to the synapse. , when the intensity of spikes accumulated with different sizes is equal to _{or greater than a predetermined firing threshold (V th} ), an output spike signal is output.

Referring to FIG. 1C , the weights (W12, W32) of the synapses to the input spikes applied to the first and third input neurons (I1, I3) at the first timing (T1) and the second timing (T2), respectively is weighted and transmitted to the second output neuron O2, and the second output neuron O2 is weighted with weights W12, W32 and the accumulated voltage of the input spike is equal to or greater than the _{firing threshold V th , so the third} Output an output spike at timing T3.

In such an SNN, a Leaky-Integrate and Fire (LIF) neuron model that mimics the operation characteristics of a human neural network is mainly used. The LIF neuron model accumulates weights according to input spikes, and when the accumulated weights are above a predetermined reference level, it fires and generates a new input spike to be transmitted to the next neuron, and the input spike is not transmitted. Otherwise, the accumulated strength of the input spike is leaked and the model is configured to gradually weaken as time goes by.

On the other hand, since SNN is also a kind of artificial neural network, learning to update the weights of synapses connecting neurons must be performed. Hereinafter, STDP) technique is used.

The STDP technique learns by increasing or decreasing the weight of the corresponding synapse by a predetermined weight change amount (Δw) according to the time difference (Δt) between the timing at which the output spike occurs and the timing at which the input spike is transmitted through the synapse. method to do it.

However, when the STDP technique is implemented in hardware, the input spice signal is sent to each of a plurality of input neurons for a predetermined period in order to calculate the time difference (Δt) between the timing at which the output spike is generated and the timing at which the input spike is transmitted. A plurality of input history registers for storing the input spike history, which is the time information to which ? was requested In addition, a separate change amount register for storing the accumulated weight change amount (∑Δw) calculated from the input spike history and the output spike history stored in the plurality of input history registers and the plurality of output history registers was required.

At this time, the input history register and the output history register should be implemented with a size corresponding to a predetermined time interval and provided with the number corresponding to the number of input neurons and the number of output neurons. It should be provided in the number corresponding to each number.

Therefore, when the STDP technique is to be implemented in hardware, the number of required registers is very large, which has a disadvantage in that hardware consumption is large. That is, it is difficult to implement in hardware, and there is a problem in that the manufacturing cost is greatly increased.

Korean Patent Publication No. 10-2018-0062934 (published on June 11, 2018)

An object of the present invention is to provide an apparatus and method for learning a spiking neural network that can be easily implemented in hardware at a low cost and small size.

Another object of the present invention is to provide an apparatus and method for learning a spiking neural network that can easily change the size of a learning window when learning is performed according to the STDP technique.

A spiking neural network learning apparatus according to an embodiment of the present invention for achieving the above object is a learning apparatus for learning a spiking neural network including a plurality of input neurons, a plurality of output neurons, and a plurality of synapses in which weights are stored, respectively. a counter for receiving and counting a clock signal and outputting a shift signal in units of a predetermined time interval; It has a number corresponding to the number of the plurality of input neurons and a size corresponding to the number and size of a plurality of quantization sections that are time sections separated by the quantization STDP function, and when an input spike is applied to the corresponding input neuron, a predetermined a plurality of input shift registers for adding values; A plurality of output shift registers having a number corresponding to the number of the plurality of output neurons and a size corresponding to the number and size of the plurality of quantization sections, and adding a predetermined value when an output spike occurs in the corresponding output neuron ; and a weight update unit that receives the values stored in the plurality of input shift registers and the plurality of output shift registers as cumulative weight change amounts, and updates the weights by adding or subtracting the values stored in the plurality of synapses.

The counter may output the shift signal in units of time intervals corresponding to time intervals of the plurality of quantization intervals.

Each of the plurality of input shift registers and the plurality of output registers may have a size in which a predetermined number of bits is added to the number of the plurality of quantization sections.

Each of the plurality of input shift registers and the plurality of output registers may shift the stored value in the least significant bit direction in units of one bit when the shift signal is applied.

Each of the plurality of input shift registers may add a value of 1 to a bit position corresponding to the number of the plurality of quantization sections when an input spike is applied to a corresponding input neuron.

Each of the plurality of input shift registers may output a stored value to the weight updater as an input cumulative weight change amount when an output spike occurs in at least one output neuron among the plurality of output neurons.

Each of the plurality of output shift registers may add a value of 1 to a bit position corresponding to the number of the plurality of quantization sections when an output spike is generated from a corresponding output neuron.

Each of the plurality of output shift registers may output a stored value to the weight updater as an output cumulative weight change amount when an input spike is applied to at least one input neuron among the plurality of input neurons.

The weight update unit receives the values stored in each of the plurality of input shift registers, adds them to the weights of synapses connected to the output neurons that generated output spikes among the plurality of synapses, and applies the values stored in each of the plurality of output shift registers In response, the weight of the synapse connected to the input neuron to which the input spike is applied among the plurality of synapses may be subtracted.

A spiking neural network learning method according to another embodiment of the present invention for achieving the above other object is a learning method for learning a spiking neural network including a plurality of input neurons, a plurality of output neurons, and a plurality of synapses in which weights are stored, respectively. The method of claim 1 , further comprising: receiving a clock signal, counting it, and outputting a shift signal in units of a predetermined time interval; When an input spike is applied to a corresponding input neuron, an input shift register having a number corresponding to the number of the plurality of input neurons and a size corresponding to the number and size of a plurality of quantization sections, which are time sections divided by the quantization STDP function adding a predetermined value to ; adding a predetermined value to an output shift register having a number corresponding to the number of the plurality of output neurons and a size corresponding to the number and size of the plurality of quantization sections when an output spike is generated from a corresponding output neuron; and updating the weights by receiving the values stored in the plurality of input shift registers and the plurality of output shift registers as cumulative weight changes and adding or subtracting the values stored in the plurality of synapses to the weights.

Therefore, the spiking neural network learning apparatus and method according to an embodiment of the present invention do not require an input history register and an output history register, and update the weight of the synapse by calculating the cumulative weight change amount, making it easy to use hardware with a small size and low cost. can be implemented, and the size of the learning window can be easily changed.

1 is a diagram for explaining an operation concept of a spiking neural network.
2 is a diagram for explaining a learning concept of a spiking neural network using the STDP technique.
3 to 5 show an example of an SNN that is learned using a quantized STDP function.
6 shows a schematic structure of a spiking neural network according to an embodiment of the present invention.
FIG. 7 shows a detailed configuration of the weight learning unit of FIG. 6 .
FIG. 8 is a diagram for explaining an operation of an input shift register in the weight learning unit of FIG. 7 .
9 is a diagram for explaining a relationship between the size of a learning window and the number of quantization sections and the size of a shift register.
10 shows a spiking neural network learning method according to an embodiment of the present invention.

In order to fully understand the present invention, the operational advantages of the present invention, and the objects achieved by the practice of the present invention, reference should be made to the accompanying drawings illustrating preferred embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, the present invention will be described in detail by describing preferred embodiments of the present invention with reference to the accompanying drawings. However, the present invention may be embodied in various different forms, and is not limited to the described embodiments. In addition, in order to clearly describe the present invention, parts irrelevant to the description are omitted, and the same reference numerals in the drawings indicate the same members.

Throughout the specification, when a part "includes" a certain component, it means that other components may be further included, rather than excluding other components unless otherwise stated. In addition, terms such as "... unit", "... group", "module", and "block" described in the specification mean a unit that processes at least one function or operation, which is hardware, software, or hardware. and a combination of software.

2 is a diagram for explaining a learning concept of a spiking neural network using the STDP technique.

In FIG. 2, similarly to FIG. 1, (a) shows the timing when the input spike is applied to a plurality of input neurons (I1 to I3), (b) is a plurality of input neurons (I1 to I3) and one output neuron (O2) represents the weights (W12, W22, W32) of synapses connected between represents the weight change amount (Δw) updated in the synapse.

As shown in the graph in (c), in the STDP technique, according to the predetermined STDP function, the synapse that the output neuron (O2) delivered the input spike before generating the output spike is judged to be highly related to the occurrence of the output spike and weighted ( Long Term Potentiation (LTP), which increases W) (Δw > 0), and the synapse that transmits the input spike after the occurrence of the output spike are judged to have low relevance to the occurrence of the output spike and decrease the weight (W) ( Δw < 0) and may consist of Long Term Depression (LTD). _{Here, the absolute value (|Δw|) of the weight change amount Δw} is the absolute value (|Δt = t outputspike - t) of the timing difference Δt between the output spike and the input spike, as shown in FIG. 2(c). _{The smaller the inputspike} |) is, the bigger it is. That is, based on the third timing T3 at which the output spike is generated in the second output neuron O2, the third input is greater than the timing difference from the first timing T1 at which the input spike is applied to the first input neuron I1. Since the timing difference from the second timing T2 at which the input spike is applied to the neuron I3 is smaller, it can be seen that the absolute value of the weight change amount Δw is larger. Also, since the input spike is applied to the second input neuron I2 at the fourth timing after the output spike is generated, it can be seen that the weight change amount Δw is negative.

However, since it is very difficult to implement the weight change amount Δw according to the continuous STDP function as it is in hardware as shown in FIG. 2C , a quantized STDP function is generally applied.

3 to 5 show an example of an SNN that is learned using a quantized STDP function.

3 shows an SNN including 784 input neurons (I1 to I784) and 784 output neurons (O1 to O784) and synapses connecting the input neurons (I1 to I784) and output neurons (O1 to O784), respectively. did. And for SNN learning, the number of input history registers corresponding to the number of input neurons (I1 to I784) and the number of output history registers corresponding to the number of output neurons (O1 to O784) are input history registers (Input history registers) ) is further provided. The input history register is a register for storing the timing at which the input spike is applied for a predetermined time period, and the output history register is a register for storing the timing at which the output spike is generated for the predetermined time period. In addition, the input history register and the output history register are implemented as shift registers to shift an applied input spike or a generated output spike in units of a predetermined time interval (here, in units of clocks or cycles).

4 shows the STDP function quantized into two quantization sections so that the STDP function has different weight change amounts (Δw) based on 20 clocks and 40 clocks. In this case, the input history register and the output history register each have an input spike. It should be able to store up to 40 clocks the timing at which is applied or the timing at which the output spike is generated. That is, the input history register and the output history register must have sizes corresponding to the time interval specified by the quantized STDP function.

In FIG. 4, based on the position where the time difference (Δt) is 0, the weight change amount (Δw) is 0 in the LTP having a positive value until the weight change amount (Δw) becomes 0, or in the LTD having a negative value, the weight change amount (Δw) is 0 Each period is called a learning window. In FIG. 4, as an example, each of the LTP learning window and the LTD learning window is shown as being divided into two quantization sections in units of 20 clocks. The weight change amount Δw may be adjusted.

And as shown in FIG. 5A, the input spike timing stored in the plurality of input history registers is based on the LTP of the quantized STDP function of FIG. 4 when an output spike occurs in a specific output neuron among the plurality of output neurons. Thus, the weight change amount Δw applied differently depending on the timing is added and stored in the input change amount register. Here, the input change amount register is provided in a number corresponding to each of the plurality of input history registers, and the accumulated weight change amount (∑Δw) is obtained by adding the weight change amount (Δw) according to the input spike timing stored in the corresponding input history register. The synapse weight (w+∑Δw) is updated by adding the accumulated weight change amount (∑Δw) to the corresponding synapse weight (w).

Also, as shown in FIG. 5B, the output spike timing stored in the plurality of output history registers is based on the LTD of the quantized STDP function of FIG. 4 when an input spike is applied from a specific input neuron among the plurality of input neurons. Accordingly, the weight change amount Δw applied differently depending on the timing is added and stored in the output change amount register. The output change amount register is also provided in a number corresponding to each of the plurality of output history registers, and the accumulated weight change amount (∑Δw) is obtained by adding the weight change amount (Δw) according to the output spike timing stored in the corresponding output history register. The synapse weight (w+∑Δw) is updated by adding the accumulated weight change amount (∑Δw) to the corresponding synapse weight (w).

As a result, in Figs. 3 to 5, not only the input history register and the output history register with a predetermined size are required in numbers corresponding to each of the plurality of input neurons and the plurality of output neurons, but also the input change register and the output change register are input The number of neurons and output neurons is required. Therefore, when implementing this in hardware, a large number of registers are required.

6 shows a schematic structure of a spiking neural network according to an embodiment of the present invention.

Referring to FIG. 6 , the SNN includes an input neuron unit 100 , a weighted synapse unit 200 , an output neuron unit 300 , and a weight learning unit 400 .

The input neuron unit 100 includes a plurality of input neurons (not shown), and when input data is applied, it encodes the applied input data according to a predetermined method and converts it into an input spike in the form of a spike train. to the corresponding input neuron.

In this case, the input neuron unit 100 may encode input data according to a Poisson encoding technique and convert it into an input spike. Poisson encoding is an encoding technique mainly used to transform input data in SNN, and may be generated with sparse input spikes generated with a time difference, based on a probability according to a Poisson distribution. For example, the input neuron unit 100 may receive the pixel values of each pixel corresponding to the image as input data, and may output an input spike generated with a time difference according to the applied pixel value.

Here, it is assumed that the input neuron unit 100 generates an input spike in the form of binary data. For example, it may be set to output a value of 1 when an input spike occurs, and output a value of 0 when no input spike occurs.

Also, the input neuron unit 100 may be configured to receive a plurality of input spikes in a binary data format. In this case, the input neuron unit 100 may be implemented as a buffer that buffers and outputs the plurality of input spikes.

In addition, each of the plurality of input neurons to which the input spike is applied transmits the applied input spike to the corresponding synapse of the weighted synapse unit 200 .

The weight synapse unit 200 is configured to imitate brain synapses in SNN, and may have a structure similar to a memory array storing a plurality of weights. For example, the weight synapse unit 200 may be implemented as a static random access memory (SRAM) or the like.

Each of the plurality of synapses of the weighted synapse unit 200 stores a corresponding weight, and when an input spike is applied from the input neuron unit 100 , a weight corresponding to the applied input spike is outputted to the output neuron unit 300 . . Here, a plurality of weights stored in the weight synapse unit 200 are updated by the weight learning unit 400 .

Each of the plurality of synapses of the weighted synaptic unit 200 repeatedly outputs a corresponding weight in response to each of a plurality of input spikes generated and applied with a time difference from the input neuron unit 100. The corresponding output of the neuron unit 300 transmitted to neurons. That is, whenever an input spike occurs in the input neuron unit 100 , a corresponding weight among the stored weights is output to the output neuron unit 300 .

Each of the plurality of output neurons of the output neuron unit 300 generates a plurality of output spikes based on the cumulative sum of weights output from the weighted synaptic unit 200 . A plurality of output neurons may be constructed based on the above-described LIF neuron model.

Each of the plurality of output neurons sums all the weights w applied from the corresponding synaptic units whenever at least one input spike occurs, and further adds the previously obtained cumulative spike to the sum of the weighted input spikes. At this time, the output neuron unit 300 does not add the previously acquired cumulative spike to the sum of the input spikes as it is, but in order to implement the leakage of the LIF technique, a leakage factor (λ) predetermined to the previously acquired cumulative spike (where 0 < A cumulative spike may be obtained by adding the leakage cumulative spike weighted by λ < 1).

And when the voltage level of the accumulated spike is higher than the predetermined ignition threshold (V _th ), the output spike is ignited and output.

The weight learning unit 400 learns synapses by updating the weights for each of a plurality of synapses of the weighted synapse unit 200 according to the above-described STDP technique as a configuration corresponding to a learning apparatus for learning the SNN. The weight learning unit 400 for learning the weights according to the STDP technique is the time information when the input spike is input from the input neuron unit 100 to the weight synapse unit 200 for a previously predetermined period based on the time when the output spike is generated. weights are increased based on On the other hand, the weight learning unit 400, when an input spike is input from the input neuron unit 100 to the weight synapse unit 200, weights based on the time information at which the output spike occurred during the previous predetermined period when the input spike was input. reduces the That is, the weight learning unit 400 increases or decreases the weight based on the generation time of the applied input spike and the output spike.

At this time, as described above, the weight learning unit 400 may learn the synapse by adjusting the weight change amount Δw of the weight w based on the quantization STDP function and updating the weight.

FIG. 7 shows the detailed configuration of the weight learning unit of FIG. 6 , and FIG. 8 is a diagram for explaining the operation of the input shift register in the weight learning unit of FIG. 7 .

Referring to FIG. 7 , the weight learning unit 400 may include a counter 410 , an input shift register unit 420 , an output shift register unit 430 , and a weight update unit 440 .

The counter 410 receives and counts the clock signal clk, and when the counted number of clock signals reaches a predetermined number, the counter 410 transmits the shift signal sf to the input shift register unit 420 and the output shift register unit 430 . ) is output.

Here, the counter 410 may be set to output the shift signal sf by counting the number of clocks according to a time interval specified by the quantization STDP function. For example, as shown in FIG. 4 , when the quantization STDP function varies the weight change amount Δw in units of 20 clocks (20clk), the counter 410 outputs a shift signal sf every 20 clocks (20clk). may be set, and when the quantization STDP function varies the weight change amount Δw in units of 40 clocks (40clk), the counter 410 may be configured to output the shift signal sf every 40 clocks (40clk).

The input shift register unit 420 and the output shift register unit 430 correspond to the number of input shift registers corresponding to the number of input neurons of the input neuron unit 100 and the number of output neurons of the output neuron unit 300, respectively. It contains a number of output shift registers. In addition, each of the input shift register and the output shift register has a size corresponding to the size of the learning window specified in the quantization STDP function and the number of quantization sections in which the weight change amount Δw is divided within the learning window.

In the present invention, the input shift register and the output shift register may be implemented to have the number of bits corresponding to the sum of the number of quantization sections included in the learning window and a predetermined number of bits (eg, 2 bits). Here, the predetermined number of bits may be adjusted according to the size of the quantization section in the learning window.

As an example, as shown in FIG. 4 , it is assumed that a learning window having a size of 40 clocks is divided into two quantization sections having two different weight change amounts Δw. In this case, the input shift register and the output shift register may be implemented as shift registers each having a size of 4 (= 2+2) bits. However, if the learning window has a clock size of 60 and is divided into three quantization sections, the input shift register and the output shift register may be implemented as shift registers each having a size of 5 (= 3+2) bits. In addition, when the learning window has a size of 1000 clocks and is divided into two quantization sections, the input shift register and the output shift register may be implemented as shift registers each having a size of 5 (= 2+3) bits.

The relationship between the size of the learning window, the number of quantization intervals, and the sizes of the input shift register and the output shift register will be described later.

Each of the plurality of input shift registers adds a value of 1 to a predetermined bit position of the input shift register when an input spike IS is applied to the corresponding neuron. That is, a predetermined value is added to the position stored in the input shift register. The input shift register adds the weight change amount (Δw) based on the LTP in the quantization STDP function, and the position where the time difference (Δt) is 0 among a plurality of quantization sections dividing the learning window to the weight change amount corresponding to the initial quantization section (Δw) is added to the previously stored value. Since the input shift register unit 420 adds the same value whenever the input spike IS is applied, 1 is added to the same bit position each time. And whenever the shift signal sf is applied from the counter 410, the stored value is shifted in a designated direction.

In FIG. 8, (a) shows an example of an input shift register, and (b) shows a value stored in the input shift register according to the timing at which the input spike is applied. In FIG. 8 , it is assumed that the input shift register unit 420 includes 784 input shift registers corresponding to the number of input neurons. Also in FIG. 8 , it is assumed that the input shift register operates based on the quantization STDP function of FIG. 4 .

In the example of FIG. 4 , since the weight change amount Δw in the initial quantization section is +2, the input shift register adds a value of 1 to the bit position corresponding to 2 when the input spike IS is applied. Accordingly, in response to the input spike applied at the first timing (T = t1) in FIG. 8B , the input shift register is 1 at the first left bit position from the right least significant bit (LSB) position. was added.

And when the shift signal sf is applied from the counter 410 at the second timing (T = t2), the input shift register shifts the value stored at each bit position by one bit in the least significant bit direction. Shifting one bit in the least significant bit direction in the shift register is mathematically similar to performing a division by two operation on the value stored in the shift register, so the value stored in the input shift register is decremented by 1.

Meanwhile, when the input spikes are applied again at the third timing (T = t3) and the fourth timing (T = t4), respectively, the input shift register responds to the input spikes applied at the third and fourth timings (t3 and t4), respectively So, +2 is added continuously.

In this way, the input shift register adds a predetermined value whenever an input spike is applied, and performs a bit shift so that an operation of dividing the stored value by 2 is performed whenever a shift signal sf is applied from the counter 410. . This is to implement LTP that increases the weight (W) by determining that the synapse that delivered the input spike before the output spike is highly related to the occurrence of the output spike, and always stores the accumulated weight change (∑Δw) in the input shift register It can be seen as doing

In addition, when an output spike OS occurs in at least one output neuron among the plurality of output neurons, the input shift register outputs the currently stored accumulated weight change amount ∑Δw.

On the other hand, although not shown, the output shift register, similar to the input shift register, adds a predetermined value each time an output spike is applied, and each time a shift signal sf is applied from the counter 410, the stored value is 2 A bit shift is performed so that the division by . And this operation implements an LTD that decreases the weight (W) by determining that the synapse that delivered the input spike after the output spike has occurred has low relevance to the occurrence of the output spike. It can be seen that Δw) is being stored.

However, in the case of the output shift register, the absolute value (|∑Δw |) of the cumulative weight change (∑Δw) must be stored according to the quantization STDP function. have. And when the input spike IS is applied to at least one input neuron among the plurality of input neurons, the input shift register outputs the currently stored cumulative weight change amount ∑Δw.

Here, for convenience of explanation, the cumulative weight change amount (∑Δw) stored in the input shift register is divided into the input cumulative weight change amount, and the cumulative weight change amount (∑Δw) stored in the output shift register is divided into the output cumulative weight change amount. .

The weight update unit 440 receives the current weight (w(t)) of a plurality of synapses connected to the output neuron in which the output spike OS is generated when the input cumulative weight change amount (∑Δw) is applied from the input shift register. , an update weight w(t+1) is obtained by adding the weight change amount Δw to the applied weight w(t).

On the other hand, when the output cumulative weight change amount (∑Δw) is applied from the output shift register, the current weight (w(t)) of a plurality of synapses connected to the input neuron where the input spike (IS) is generated is applied, and the applied weight ( An update weight w(t+1) is obtained by subtracting the weight change amount Δw from w(t)).

Then, the weight is updated by replacing the obtained update weight w(t+1) with the current weight w(t) of the corresponding synapse and storing it. That is, the SNN is trained.

As described above, in the present embodiment, the LTP and LTD are respectively implemented even though the plurality of input shift registers of the input shift register unit 420 and the plurality of output shift registers of the output shift register unit 430 are implemented as small-sized shift registers. Since the accumulated weight change amount is always stored for this purpose, when an input spike is applied or an output spike occurs, the accumulated weight change amount (∑Δw) is immediately transmitted to the weight update unit 440 to update the weight of the corresponding synapse in real time. .

However, each of the input shift register and the output shift register does not store the exact timing at which the input spike IS is applied and the exact timing at which the output spike OS is generated, but does not store the shift signal sf applied from the counter 410. Accordingly, an error in the accumulated weight change amount ∑Δw due to the decrease of the stored accumulated weight change amount ∑Δw may be partially generated. However, as described above, since the input spike (IS) generated according to Poisson encoding and the output spike (OS) generated in response to the input spike (IS) are generated with a very low probability, stored according to the shift signal sf The error caused by reducing the cumulative weight change amount (∑Δw) does not occur significantly. In general, during the learning window period of the quantization STDP function in SNN, the case where an input spike (IS) is generated according to Poisson encoding is less than 10%. That is, there is less than one input spike IS in most of the learning window sections. This is similar to the output spike (OS). Therefore, the error caused by reducing the accumulated weight change amount (∑Δw) stored according to the shift signal sf does not significantly affect the learning of the synapse.

On the other hand, when the accumulated weight change amount ∑Δw is obtained using the input shift register and the output shift register, the size of the required register can be significantly reduced compared to FIG. 3 .

Table 1 shows the size of a register required when the weight learning unit 400 is implemented in the manner of FIGS. 5 and 8 . In Table 1, it is assumed that the number of input neurons is 784 and the number of output neurons is 256. In this case, when the weight learning unit 400 is implemented as shown in FIG. 5 , input history registers and output history registers implemented as shift registers are provided as many as the number of input neurons and output neurons, respectively, and the size of each learning window. It should have a size corresponding to (40 clk). In addition, the input change amount register and the output change amount register must have a size that can store the accumulated weight change amount (∑Δw). Accordingly, when the method of FIG. 5 is used, the weight learning unit 400 requires a register having a total size of 46800. On the other hand, as shown in FIG. 8 , when the weight learning unit 400 is configured using the input shift register and the output shift register, a total size of 4160 registers is required. That is, the size of the register required for the weight learning unit 400 can be reduced by 91.1%.

9 is a diagram for explaining a relationship between the size of a learning window and the number of quantization sections and the size of a shift register.

As described above, the sizes of the input shift register and the output shift register may be adjusted according to the size of the learning window and the number of quantization sections in which the weight change amount Δw in the learning window is divided. As shown in (a) of FIG. 9 , when both and a section are divided into two within the learning window and the total size of the learning window is 40 clocks (40 clk), the input shift register and the output shift register receive input spikes. or an output spike occurs, a value of 1 should be stored in the first bit position on the left of the least significant bit (LSB) as shown in (b). However, as shown in (c), when the quantum and section are divided into two in the learning window and the total size of the learning window is 40 clocks (40 clk), as shown in (d), 1 at the left second bit position of the least significant bit (LSB) value should be stored. That is, as the number of quantization sections increases in the learning window, the sizes of the input shift register and the output shift register should increase. In addition, the remaining number of bits excluding the number of bits corresponding to the number of quantization intervals should be able to represent all the number of input spikes or output spikes generated within the quantization interval. For example, in (b) and (d) of FIG. 9 , 2 bits and 3 bits are allocated as the number of bits corresponding to the quantization period, respectively, so the remaining number of bits is 2 bits. And the maximum number that can be expressed with 2 bits is 3. Therefore, when four or more input or output spikes are generated in both the input shift register and the output shift register shown in (b) and (d) of FIG. .

As described above, in the case of Poisson encoding, even the probability that one input spike or output spike will occur in one quantization interval is low, so in general, the probability that four or more input spikes or output spikes occur within the quantum and interval is extremely slim. it can be seen that Accordingly, in this embodiment, it is assumed that the input shift register and the output shift register are implemented as shift registers having the number of bits corresponding to the sum of the number of quantization sections and the predetermined number of bits (here, 2 bits). Nevertheless, although the possibility of application in SNN is very low, if the size of each quantization interval is very large (for example, 100 clk), an error is generated in the cumulative weight change amount (∑Δw) by increasing the predetermined number of bits. can be easily prevented.

As such, the weight learning unit 400 according to the present embodiment can easily respond by increasing the size of the input shift register and the output shift register to a very small size even when the size of the learning window and the number of quantization sections in the learning window are adjusted. .

10 shows a spiking neural network learning method according to an embodiment of the present invention.

6 to 9, the SNN learning method of FIG. 10 is described. First, each of a plurality of input shift registers configured to have a predetermined number of bits corresponding to the number of quantization sections constituting the learning window of the quantization STDP function is input. It is determined whether the input spike IS is applied to a corresponding input neuron among a plurality of input neurons of the neuron unit 100 (S11). If it is determined that the input spike IS is applied, a value corresponding to the number of quantization sections constituting the learning window of the quantization STDP function is added to the pre-stored value (S12). In this case, the input shift register may add a value corresponding to the number of quantization sections by adding 1 to a bit position corresponding to the number of quantization sections.

Meanwhile, each of the plurality of output shift registers having the number of bits corresponding to the input shift register acquires a pre-stored value as an output cumulative weight change amount in response to the input spike IS (S13).

Then, the weight of each synapse is updated by subtracting the acquired output cumulative weight change (∑Δw) from the current weight w of each of a plurality of synapses connected to the output neuron corresponding to the output shift register (S14).

In addition, each of the plurality of output shift registers determines whether an output spike OS occurs in a corresponding output neuron among a plurality of output neurons of the output neuron unit 300 ( S15 ). If the output spike OS occurs, a value corresponding to the number of quantization sections constituting the learning window of the quantization STDP function is added to the pre-stored value (S16). In this case, the output shift register may also add 1 to a bit position corresponding to the number of quantization sections to add a value corresponding to the number of quantization sections.

Meanwhile, each of the plurality of input shift registers acquires a pre-stored value as an input cumulative weight change amount in response to an output spike ( S17 ).

Then, the weight of each synapse is updated by adding the acquired output cumulative weight change amount (∑Δw) to the current weight w of each of the plurality of synapses connected to the input neuron corresponding to the input shift register (S18).

Also, the counter 410 determines whether a shift signal sf generated at a cycle corresponding to a predetermined number of clocks is applied (S19). If the shift signal sf is applied, each of the plurality of input shift registers and the plurality of output shift registers shifts the stored value by one bit in the least significant bit direction, so that the input cumulative weight change amount ?w and the output cumulative weight change amount ? Δw) is decreased (S20).

The method according to the present invention may be implemented as a computer program stored in a medium for execution by a computer. Here, the computer-readable medium may be any available medium that can be accessed by a computer, and may include all computer storage media. Computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, and read dedicated memory), RAM (Random Access Memory), CD (Compact Disk)-ROM, DVD (Digital Video Disk)-ROM, magnetic tape, floppy disk, optical data storage, and the like.

Although the present invention has been described with reference to the embodiment shown in the drawings, which is merely exemplary, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom.

Accordingly, the true technical protection scope of the present invention should be defined by the technical spirit of the appended claims.

100: input neuron unit 200: weighted synaptic unit
300: output neuron unit 400: weight learning unit
410: counter 420: input shift register unit
430: output shift register unit 440: weight update unit

Claims (18)

A learning apparatus for learning a spiking neural network including a plurality of input neurons, a plurality of output neurons, and a plurality of synapses in which weights are stored, respectively,
a counter for receiving and counting a clock signal and outputting a shift signal in units of a predetermined time interval;
It has a number corresponding to the number of the plurality of input neurons and a size corresponding to the number and size of a plurality of quantization sections that are time sections separated by the quantization STDP function, and when an input spike is applied to the corresponding input neuron, a predetermined a plurality of input shift registers for adding values;
A plurality of output shift registers having a number corresponding to the number of the plurality of output neurons and a size corresponding to the number and size of the plurality of quantization sections, and adding a predetermined value when an output spike occurs in the corresponding output neuron ; and
and a weight update unit configured to receive the values stored in the plurality of input shift registers and the plurality of output shift registers as cumulative weight changes, and add or subtract weights stored in the plurality of synapses to update the weights. The method of claim 1, wherein the counter
A spiking neural network learning apparatus for outputting the shift signal in units of time intervals corresponding to time intervals of the plurality of quantization intervals. 2. The method of claim 1, wherein each of the plurality of input shift registers and the plurality of output registers comprises:
A spiking neural network learning apparatus having a size in which a predetermined number of bits is added to the number of the plurality of quantization sections. 4. The method of claim 3, wherein each of the plurality of input shift registers and the plurality of output registers comprises:
When the shift signal is applied, the spiking neural network learning apparatus shifts the stored value in the least significant bit direction by one bit. 5. The method of claim 4, wherein each of the plurality of input shift registers comprises:
A spiking neural network learning apparatus for adding a value of 1 to bit positions corresponding to the number of the plurality of quantization sections when an input spike is applied to a corresponding input neuron. 6. The method of claim 5, wherein each of the plurality of input shift registers comprises:
When an output spike occurs in at least one output neuron among the plurality of output neurons, the spiking neural network learning apparatus outputs a stored value as an input cumulative weight change amount to the weight update unit. 7. The method of claim 6, wherein each of the plurality of output shift registers comprises:
When an output spike is generated from a corresponding output neuron, a spiking neural network learning apparatus for adding a value of 1 to bit positions corresponding to the number of the plurality of quantization sections. 8. The method of claim 7, wherein each of the plurality of output shift registers comprises:
When an input spike is applied to at least one input neuron among the plurality of input neurons, the spiking neural network learning apparatus outputs a stored value as an output cumulative weight change amount to the weight updater. The method of claim 8, wherein the weight update unit
receiving the value stored in each of the plurality of input shift registers, and adding an output spike among the plurality of synapses to the weight of the synapse connected to the output neuron,
A spiking neural network learning apparatus for receiving a value stored in each of the plurality of output shift registers, and subtracting a weight of a synapse connected to an input neuron to which an input spike is applied among the plurality of synapses. A learning method for learning a spiking neural network including a plurality of input neurons, a plurality of output neurons, and a plurality of synapses in which weights are stored, respectively,
receiving and counting the clock signal and outputting a shift signal in units of a predetermined time interval;
When an input spike is applied to a corresponding input neuron, an input shift register having a number corresponding to the number of the plurality of input neurons and a size corresponding to the number and size of a plurality of quantization sections, which are time sections divided by the quantization STDP function adding a predetermined value to ;
adding a predetermined value to an output shift register having a number corresponding to the number of the plurality of output neurons and a size corresponding to the number and size of the plurality of quantization sections when an output spike is generated from a corresponding output neuron; and
and updating the weights by receiving the values stored in the plurality of input shift registers and the plurality of output shift registers as cumulative weight changes and adding or subtracting the values stored in the plurality of synapses to the weights. The method of claim 10, wherein outputting the shift signal comprises:
A spiking neural network learning method for outputting the shift signal in units of time intervals corresponding to time sections of the plurality of quantization sections. 11. The method of claim 10, wherein each of the plurality of input shift registers and the plurality of output registers comprises:
A spiking neural network learning method having a size in which a predetermined number of bits is added to the number of the plurality of quantization sections. The method of claim 12, wherein the spiking neural network learning method is
When the shift signal is applied, the spiking neural network learning method further comprising the step of shifting the values stored in each of the plurality of input shift registers and the plurality of output registers in the least significant bit direction by one bit. 14. The method of claim 13, wherein adding a predetermined value to the input shift register comprises:
When an input spike is applied to a corresponding input neuron, a spiking neural network learning method for adding a value of 1 to bit positions corresponding to the number of the plurality of quantization sections. 15. The method of claim 14, wherein the spiking neural network learning method is
and outputting a value stored in the plurality of input shift registers as an input cumulative weight change amount when an output spike occurs in at least one output neuron among the plurality of output neurons. 16. The method of claim 15, wherein adding a predetermined value to the output shift register comprises:
When an output spike is generated from a corresponding output neuron, a spiking neural network learning method for adding a value of 1 to bit positions corresponding to the number of the plurality of quantization sections. The method of claim 16, wherein the spiking neural network learning method is
When an input spike is applied to at least one input neuron among the plurality of input neurons, outputting a stored value as an output cumulative weight change amount. 18. The method of claim 17, wherein updating the weight comprises:
receiving a value stored in each of the plurality of input shift registers and adding an output spike among the plurality of synapses to a weight of a synapse connected to an output neuron; and
and subtracting a weight of a synapse connected to an input neuron to which an input spike is applied among the plurality of synapses by receiving a value stored in each of the plurality of output shift registers.

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