KR20210132569A - Link startup method of storage device - Google Patents

Abstract

Disclosed are a storage device for performing high-speed link startup and a storage system including the same. According to the technical idea of the present disclosure, the link startup method of a storage device receives a line-reset signal from a host through a line connected to an input signal pin of the storage device, compares the length of the received line-reset signal with a first reference time, and performs a link startup operation, according to the comparison result, between the storage device and the host, in a high-speed mode or a low-speed mode.

Description

Link startup method of storage device

The technical idea of the present disclosure relates to a memory device, and more particularly, to a link startup method of a storage device and a storage device for performing high-speed link startup.

A storage system consists of a host and a storage device. The host and the storage device are connected through various standard interfaces such as universal flash storage (UFS), serial ATA (SATA), small computer small interface (SCSI), serial attached SCSI (SAS), and embedded MMC (eMMC). When a storage system is used in a mobile device, high-speed operation between the host and the storage device is very important, and a fast link-up between the host and the storage device is required.

The technical idea of the present disclosure provides a storage device capable of performing link startup in a high-speed mode between a host and a storage device, a storage system including the same, and a link startup method of the storage device.

A link start-up method of a storage device according to the technical concept of the present disclosure includes receiving a line-reset signal from a host through a line connected to an input signal pin of the storage device, and determining the length of the received line-reset signal. Comparing with 1 reference time, and performing a link start-up operation between the storage device and the host in a high-speed mode or a low-speed mode according to the comparison result.

In addition, the link start-up method of the storage device according to the technical concept of the present disclosure includes the steps of determining whether a line-reset signal is received from the host through a line connected to an input signal pin of the storage device, from the host performing a fast mode link startup operation between the storage device and the host when the line-reset signal is received; and when the line-reset signal is not received from the host, between the storage device and the host and performing a slow mode link startup operation.

In addition, the link start-up method of the storage device according to the technical idea of the present disclosure includes the steps of performing a high-speed mode link startup operation between the storage device and a host, and determining whether the high-speed mode link startup operation is complete. , determining whether the link-up between the storage device and the host has passed when the high-speed mode link start-up operation is completed; and performing a mode link startup operation.

According to the technical idea of the present disclosure, since the storage device may perform a link start-up operation in a high-speed mode or a low-speed mode according to the length of the line-reset signal or the presence or absence of the line-reset signal from the host, the link between the host and the storage device The time required for startup operation can be reduced. Accordingly, the host and the storage device can be quickly set to a link-up state, thereby improving the performance of the storage system.

In addition, according to the technical idea of the present disclosure, the storage device and the host perform a link start-up operation in the high-speed mode first, and when the link-up is not completed, the link start-up is performed in the low-speed mode, so that the storage device enters the high-speed mode. A link startup operation can be performed whether or not it supports it. Accordingly, a time required for a link start-up operation between the host and the storage device may be further reduced, and performance of the storage system may be further improved.

1 is a block diagram illustrating a storage system according to an embodiment of the present disclosure.
2 illustrates an interface between a host and a storage device according to an embodiment of the present disclosure.
3 is a timing diagram illustrating a line-reset signal according to an embodiment of the present disclosure.
4 is a table illustrating line-reset parameters and line-reset high-speed link-up parameters according to an embodiment of the present disclosure.
5 is a block diagram illustrating a storage system according to an embodiment of the present disclosure.
6 is a block diagram illustrating a line-reset detector according to an embodiment of the present disclosure.
7 is a timing diagram exemplarily illustrating a detection operation of the line-reset detector of FIG. 6 , according to an embodiment of the present disclosure.
8 is a block diagram illustrating a line-reset detector according to an embodiment of the present disclosure.
9 is a block diagram illustrating a line-reset detector according to an embodiment of the present disclosure.
FIG. 10 is a timing diagram exemplarily illustrating a detection operation of the line-reset detector of FIG. 9 , according to an embodiment of the present disclosure.
11 is a flowchart illustrating a method of operating a storage device according to an embodiment of the present disclosure.
12 is a flowchart illustrating an operation between a host and a storage device according to an embodiment of the present disclosure.
13 is a flowchart illustrating a method of operating a storage device according to an embodiment of the present disclosure.
14 is a flowchart exemplarily illustrating a fast mode initialization sequence between a UFS host and a UFS device according to an embodiment of the present disclosure.
15 is a flowchart illustrating a link startup operation between a host and a storage device according to an embodiment of the present disclosure.
16 to 18 are flowcharts each illustrating a link startup method of a storage device according to some embodiments of the present disclosure.
19 is a flowchart illustrating a link startup operation between a host and a storage device according to an embodiment of the present disclosure.
20 and 21 are flowcharts each illustrating a link startup method of a storage device according to some embodiments of the present disclosure.
22 is a flowchart illustrating an operation between a host and a storage device according to an embodiment of the present disclosure.
23 and 24 are flowcharts each illustrating a link startup method of a storage device according to some embodiments of the present disclosure.
25 is a diagram for explaining a UFS system according to an embodiment of the present invention.
26A to 26C are diagrams for explaining a form factor of a UFS card.
27 is a block diagram illustrating a memory system according to an embodiment of the present disclosure.
28 is a diagram for explaining a 3D VNAND structure applicable to a UFS device according to an embodiment of the present disclosure.
29 is a diagram for explaining a BVNAND structure applicable to a UFS device according to an embodiment of the present disclosure.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a storage system 10 according to an embodiment of the present disclosure.

Referring to FIG. 1 , a storage system 10 includes a storage device 100 and a host 200 . For example, the storage device 100 and the host 200 may be connected according to an interface protocol defined in a UFS (Universal Flash Storage) standard, and accordingly, the storage device 100 may be a UFS device, and , the host 200 may be a UFS host. However, the present invention is not limited thereto, and the storage device 100 and the host 200 may be connected according to various standard interfaces.

The host 200 may include an interconnect unit 210 and a host controller 220 . The host 200 may control a data processing operation for the storage device 100 , for example, a data read operation or a data write operation. The host 200 may refer to a data processing device capable of processing data, such as a central processing unit (CPU), a processor, a microprocessor, or an application processor (AP). The host 200 may execute an operating system (OS) and/or various applications. In an embodiment, the storage system 10 may be included in a mobile device, and the host 200 may be implemented as an application processor (AP). In an embodiment, the host 200 may be implemented as a system-on-a-chip (SoC), and accordingly, may be embedded in an electronic device.

The storage device 100 may include an interconnect unit 110 , a device controller 120 , and a nonvolatile memory 130 . The device controller 120 controls the nonvolatile memory 130 to write data to the nonvolatile memory 130 in response to a write request from the host 200 , or in response to a read request from the host 200 . The nonvolatile memory 130 may be controlled to read data stored in the nonvolatile memory 130 . The nonvolatile memory 130 may include a plurality of memory cells, for example, the plurality of memory cells may be flash memory cells. In an embodiment, the plurality of memory cells may be NAND flash memory cells. However, the present invention is not limited thereto, and in another embodiment, the plurality of memory cells may be resistive memory cells such as resistive RAM (ReRAM), phase change RAM (PRAM), or magnetic RAM (MRAM).

In addition, although the interconnect unit 110 and the device controller 120 are illustrated as being distinct from each other in FIG. 1 , the device controller 120 may be a concept including the interconnect unit 110 . The same applies to other drawings other than FIG. 1 to be described later. For example, when the device controller 120 is implemented as a single package chip, the interconnect unit 110 may also be implemented in the package chip.

The host 200 may further include first pins P1a' and P1b', and the storage device 100 includes first pins P1a and P1b configured to be respectively connected to the first pins P1a' and P1b'. ) may be further included. The storage device 100 may receive an input signal, for example, a differential input signal DIN_t and DIN_c, from the host 200 through the first pins P1a and P1b. Accordingly, the first pins P1a and P1b may be referred to as “input signal pins”, and signal lines through which the differential input signals DIN_t and DIN_c are transmitted may constitute a reception lane. For example, the first pin P1a may be referred to as a “positive input signal pin” and the first pin P1b may be referred to as a “negative input signal pin”.

In addition, the host 200 may further include second pins P2a' and P2b', and the storage device 100 has second pins P2a configured to be respectively connected to the second pins P2a' and P2b'. , P2b) may be further included. The storage device 100 may transmit an output signal, for example, the differential output signals DOUT_t and DOUT_c, to the host 200 through the second pins P2a and P2b. Accordingly, the second pins P2a and P2b may be referred to as “output signal pins”, and signal lines to which the differential output signals DOUT_t and DOUT_c are transmitted may constitute a transmission lane. For example, the second pin P2a may be referred to as a “positive output signal pin” and the second pin P2b may be referred to as a “negative output signal pin”.

The storage device 100 may further include a line-reset detector 140 . In FIG. 1 , the device controller 120 is illustrated as including the line-reset detector 140 , but the present invention is not limited thereto. The line-reset detector 140 receives the line-reset signal LINE-RESET from the host 200 and detects the length of the received line-reset signal LINE-RESET, that is, the length of the line-reset section. can do. The device controller 120 may perform link start-up in a high-speed mode or a low-speed mode (eg, PWM mode) based on the detected length of the line-reset signal LINE-RESET. The line-reset signal LINE-RESET will be described in more detail with reference to FIGS. 3 and 4 . A detailed operation of the line-reset detector 140 will be described in more detail with reference to FIGS. 5 to 10 .

The interconnect units 110 and 210 may provide an interface for exchanging data between the host 200 and the storage device 100 . In an embodiment, the interconnect unit 110 may include a physical layer (PL) 111 and a link layer (LL) 115 , and the physical layer 111 includes first and second layers. It may be connected to the 2 pins P1a, P1b, P2a, and P2b. Similarly, the interconnect unit 210 may also include a physical layer 211 and a link layer 215, and the physical layer 211 includes first and second pins P1a', P1b', P2a', P2b'. can be connected to Each of the physical layers 111 and 211 may include physical components for exchanging data between the host 200 and the storage device 100 , for example, at least one transmitter and at least one receiver. (receiver) and the like. Each of the link layers 115 and 215 may manage data transmission and composition, and may manage data integrity and error.

In one embodiment, where storage system 10 is a mobile device, link layers 115 and 215 may be defined by the “UniPro” specification, and physical layers 111 and 211 may be “M-PHY”. It can be defined by the specification. UniPro and M-PHY are interface protocols proposed by the Mobile Industry Processor Interface (MIPI) Alliance. In this case, the link layers 115 and 215 may include a Physical Adapted Layer, respectively. The physical adaptation layer may control the physical layers 111 and 211, such as managing data symbols or managing power. Hereinafter, an interface between the host 200 and the storage device 100 will be described in detail with reference to FIG. 2 .

2 illustrates an interface 20 between a host and a storage device according to an embodiment of the present disclosure.

Referring to FIG. 2 , the interface 20 may include a link 300 between the host controller 220 and the device controller 120 , and the link 300 includes a plurality of lanes (lanes). 310, 320, 330). The link 300 may include at least one lane corresponding to each direction, and the number of lanes in each direction need not be symmetrical. For example, the link 300 includes two lanes 310 and 320 corresponding to a first direction from the host controller 220 to the device controller 120 and a second direction from the device controller 120 to the host controller 220 . One lane 330 corresponding to two directions may be included, but the present invention is not limited thereto. For example, two lanes 310 and 320 corresponding to the first direction may constitute a first sub-link, and one lane 330 corresponding to the second direction may constitute a second sub-link. .

Each of the lanes 310 , 320 , and 330 is a unidirectional, single-signal, and a transmission channel carrying information. For example, the lane 320 may be composed of a transmitter TX1 , a receiver RX1 , and a line LINE for point-to-point interconnection between the transmitter TX1 and the receiver RX1 . For example, the transmitter TX1 may be connected to a pin TXDP corresponding to a positive node of the differential signal and a pin TXDN corresponding to a negative node of the differential signal, and the receiver RX1 may be connected to a positive node of the differential signal. It may be connected to a corresponding pin RXDP and a pin RXDN corresponding to the negative node of the differential signal. Line LINE consists of two differentially routed wires connecting the pins TXDP and RXDP, TXDN and RXDN of transmitter TX1 and receiver RX1, these wires can correspond to transmission lines have.

The link 300 may further include lane managers 340 and 350 that provide a bidirectional data transmission function. Although FIG. 2 illustrates that the lane manager 350 and the host controller 220 are separated, the present invention is not limited thereto, and the lane manager 350 may be included in the host controller 220 . Similarly, although FIG. 2 illustrates that the lane manager 340 and the device controller 120 are separated, the present invention is not limited thereto, and the lane manager 340 may be included in the device controller 120 .

1 and 2 together, the transmitter included in the interconnect part 210 of the host 200 and the receiver included in the interconnect part 110 of the storage device 100 form one lane. However, the number of transmitters and receivers included in the interconnect unit 210 of the host 200 may be different from the number of transmitters and receivers included in the interconnect unit 110 of the storage device 100 . Also, the capability of the host 200 may be different from that of the storage device 100 .

Accordingly, the host 200 and the storage device 100 recognize a physically connected lane and perform a process for receiving information from the counterpart device. Accordingly, the host 200 and the storage device 100 perform a link startup process before exchanging data. By performing the link startup process, the host 200 and the storage device 100 exchange and recognize information on the number of transmitters and receivers, information on physically connected lanes, information on the performance of the counterpart device, etc. can After the link start-up process is completed, the host 200 and the storage device 100 are set to a linkup state in which data can be stably exchanged with each other.

The link startup process may be performed during an initialization operation performed when the storage system 10 is used for the first time or a boot operation of the storage system 10 . Furthermore, the link start-up process may be performed during an operation of recovering an error in the link-up state. However, since the link startup process requires the exchange of a lot of information about the host 200 and the storage device 100 , it may take a long time. performance may be degraded.

However, according to an embodiment of the present disclosure, the host 200 performs the storage device 100 through a differential input signal line through which the differential input signals DIN_t and DIN_c are transmitted during an initialization operation or a booting operation of the storage system 10 . ) may provide a line-reset signal LINE-RESET having a specific length, and the storage device 100 processes link startup in a high-speed mode by detecting the length of the received line-reset signal LINE-RESET. can be performed. Accordingly, the time required for the link start-up process may be reduced, and thus the performance of the storage system 10 may be improved.

Also, according to an embodiment of the present disclosure, the storage device 100 may perform a link startup process in a high speed mode or a low speed mode based on the presence of the line-reset signal LINE-RESET. In addition, according to an embodiment of the present disclosure, after power-up or hardware reset, the storage device 100 first performs a link start-up process in a high-speed mode, and links-up between the host 200 and the storage device 100 . If this is not passed, link start-up processing may be performed in the low-speed mode.

In addition, according to some embodiments of the present disclosure, the condition for determining the operation mode of the link startup process is not limited to the length or existence of the line-reset signal LINE-RESET. For example, link startup processing may be performed in high-speed mode or low-speed mode based on other characteristics such as the number of times toggling between logic low and logic high in the line-reset signal LINE-RESET. have.

In addition, according to some embodiments of the present disclosure, the signal used to determine the operation mode of the link startup process is not limited to the line-reset signal LINE-RESET. For example, other signals that may be transmitted between the host 200 and the storage device 100 before the link startup process is performed may be used instead of the line-reset signal, and based on the other signals, the high-speed mode or Link startup processing can be performed in low speed mode.

In some embodiments, the storage device 100 may be implemented as a DRAMless device, and the DRAMless device may refer to a device that does not include a DRAM cache. In this case, the device controller 120 may not include a DRAM controller. For example, the storage device 100 may use a partial area of the nonvolatile memory 130 as a buffer memory.

In some embodiments, the storage device 100 may be an internal memory embedded in an electronic device. For example, the storage device 100 may be an embedded UFS memory device, an embedded Multi-Media Card (eMMC), or a solid state drive (SSD). However, the present invention is not limited thereto, and the storage device 100 includes a nonvolatile memory (eg, One Time Programmable ROM (OTPROM), Programmable ROM (PROM), Erasable and Programmable ROM (EPROM), and Electrically Erasable ROM (EEPROM)). and Programmable ROM), Mask ROM, Flash ROM, etc.). In some embodiments, the storage device 100 may be an external memory that is detachable from the electronic device. For example, the storage device 100 may include a UFS memory card, Compact Flash (CF), Secure Digital (SD), Micro Secure Digital (Micro-SD), Mini Secure Digital (Mini-SD), Extreme Digital (xD) and It may include at least one of "Memory Stick".

The storage system 10 is, for example, a personal computer (PC), a laptop computer, a mobile phone, a smartphone, a tablet PC, a personal digital assistant (PDA), an enterprise digital assistant (EDA). ), digital still camera, digital video camera, audio device, PMP (portable multimedia player), PND (personal navigation device or portable navigation device), MP3 player, portable game It may be implemented as an electronic device such as a handheld game console or an e-book. Also, the storage system 10 may be implemented as various types of electronic devices, such as a wrist watch or a wearable device such as a head-mounted display (HMD).

3 is a timing diagram illustrating a line-reset signal LINE-RESET according to an embodiment of the present disclosure.

1 to 3 together, voltage 30 on line LINE is in a DIF-P state with a positive differential line voltage, a DIF-N state with a negative differential line voltage, or a DIF with a near zero differential line voltage. Can be driven in -Z state. Although not shown, the line LINE may have a DIF-Q state indicating a high impedance state, or a DIF-X state that is neither DIF-N nor DIF-P. Here, the differential line voltage may be defined as a value obtained by subtracting the voltage of the line connected to the negative node from the voltage of the line connected to the positive node.

The line LINE may correspond to any line included in the interface 20, for example, the line LINE may correspond to a differential input signal line through which the differential input signals DIN_t and DIN_c of FIG. 1 are transmitted. have. For example, when the voltage level of the first pin P1a to which the positive input signal DIN_t is applied is higher than the voltage level of the first pin P1b to which the negative input signal DIN_c is applied, the line LINE is It can be in DIF-P state or logic high. For example, when the voltage level of the first pin P1a to which the positive input signal DIN_t is applied is lower than the voltage level of the first pin P1b to which the negative input signal DIN_c is applied, the line LINE is It can be DIF-N state or logic low. For example, when the voltage level of the first pin P1a to which the positive input signal DIN_t is applied is substantially the same as the voltage level of the first pin P1b to which the negative input signal DIN_c is applied, the line LINE ) may be DIF-Z state or ground state.

_{In the activation period T ACTIVATE} between t0 and t1 , the line LINE may be driven by DIF-N. _{For example, during the activation period T ACTIVATE} , the host 200 sends a signal (eg, For example, the activation signal) can be driven to the DIF-N state. The storage device 100 may exit the power saving state (eg, the HIBERN8 state) in response to the activation signal. In an embodiment, the physical layer 111 or the link layer 115 of the interconnect unit 110 of the storage device 100 may be preset based on the length of the _{activation period T ACTIVATE .} In an embodiment, a link startup operation between the host 200 and the storage device 100 may be performed in a high speed mode or a low speed mode based on the length of the activation period _{T ACTIVATE .}

In the line-reset period T _LINE-RESET between t1 and t3, the line LINE may be driven in the DIF-P state. _{For example, during the line-reset period T LINE-RESET} , the host 200 transmits a signal (eg, the line-reset signal LINE-RESET ) transmitted through the line LINE to instruct the line-reset operation. )) can be driven to the DIF-P state. The storage device 100 may perform a line-reset for resetting the physical layer 111 of the interconnect unit 110 in response to the line-reset signal LINE-RESET. "Line-reset" is a reset mechanism for resetting the physical layer 111 of the interconnect unit 110 through the line LINE during operation in a malfunctioning situation.

In the line-reset high-speed link-up period T _{LINE-RESET-HS-LINKUP} between t1 and t2, the line LINE may be driven to a DIF-P state. For example, during the line-reset high-speed link-up period (T _{LINE-RESET-HS-LINKUP} ), the host 200 transmits a signal (eg, The line-reset signal LINE-RESET) may be driven to the DIF-P state. The storage device 100 may perform a link startup process between the host 200 and the storage device 100 in a high-speed mode by performing a high-speed link startup sequence in response to the line-reset signal LINE-RESET. have.

4 is a table 40 illustrating line-reset parameters and line-reset high-speed link-up parameters according to an embodiment of the present disclosure.

_{1, 3, and 4 together, the line-reset period T LINE-RESET} for the host 200 to instruct the line-reset operation of the storage device 100 may be defined as at least 3.1 ms. have. Accordingly, in order to reset the physical layer 111 of the interconnect unit 110 of the storage device 100 , the host 200 drives the voltage of the line LINE to the DIF-P state for about 3.1 ms or more. can In other words, the line-reset period T _LINE-RESET may correspond to the line-reset parameter of the transmitter.

_{The minimum value of the line-reset detection period T LINE-RESET-DETECT} for the storage device 100 to perform the line-reset operation may be 1 ms, and the maximum value may be defined as 3 ms. Accordingly, when the length of the period in which the voltage of the line LINE is driven by the DIF-P is between about 1 ms and 3 ms, the storage device 100 resets the physical layer 111 of the interconnect unit 110 . - A reset operation can be performed. In other words, the line-reset detection period T _{LINE-RESET-DETECT} may correspond to the line-reset parameter of the receiver.

_{The minimum value of the line-reset high-speed link-up period (T LINE-RESET-HS-LINKUP} ) for the host 200 to instruct the high-speed link start-up operation of the storage device 100 is 300 μs, and the maximum value is 500 μs can be defined as Accordingly, the host 200 may drive the voltage of the line LINE in the DIF-P state for a time between about 300 μs and 500 μs to perform the high-speed link startup. In other words, the line-reset high-speed link-up period T _{LINE-RESET-HS-LINKUP} may correspond to the line-reset high-speed link-up parameter of the transmitting end.

_{The minimum value of the line-reset high-speed link-up detection period (T LINE-RESET-HS-LINKUP-DETECT} ) for the storage device 100 to perform a high-speed link start-up operation is 200 μs, and the maximum value is defined as 300 μs can be Accordingly, the storage device 100 may perform the high-speed link start-up sequence when the length of the period in which the voltage of the line LINE is driven in the DIF-P state is between about 200 μs and 300 μs. Meanwhile, the storage device 100 may perform a low-speed link start-up sequence when the length of the period in which the voltage of the line LINE is driven in the DIF-P state is longer than about 300 μs. In other words, the line-reset high-speed link-up detection section T _{LINE-RESET-DETECT-HS-LINKUP-DETECT} may correspond to the line-reset high-speed link-up parameter of the receiving end.

5 is a block diagram illustrating a storage system 10A according to an embodiment of the present disclosure.

Referring to FIG. 5 , the storage system 10A includes a storage device 100A and a host 200A, and the storage device 100A includes an interconnect unit 110a, a device controller 120a, and a non-volatile memory 130 . The host 200A may include an interconnect unit 210a and a host controller 220a. The storage system 10A corresponds to a modified example of the storage system 10 of FIG. 1 , and the contents described above with reference to FIGS. 1 to 4 may also be applied to the present embodiment. In the present embodiment, the line-reset detector 140 may be included in the interconnect unit 110a, for example, the line-reset detector 140 may include a physical layer (eg, FIG. 1 ) of the interconnect unit 110a. 111) may be included.

6 is a block diagram illustrating a line-reset detector 140a according to an embodiment of the present disclosure. 7 is a timing diagram exemplarily illustrating a detection operation of the line-reset detector 140a of FIG. 6 according to an embodiment of the present disclosure.

1, 6, and 7 together, the line-reset detector 140a may include a comparator 141, a system clock counter 142, and a line-reset length determiner 143, as shown in FIG. may correspond to an example of the line-reset detector 140 of . Here, the positive input signal DIN_t may be received from the host 200 through the first pin P1a, and the negative input signal DIN_c may be received from the host 200 through the first pin P1b. have. The system clock SYS_CLK may correspond to an internal clock signal generated by the storage device 100 .

The comparator 141 may generate a differential line voltage DIF by comparing the positive input signal DIN_t and the negative input signal DIN_c. The system clock counter 142 may generate a system clock count value SYS_CNT by counting the number of clocks from the system clock SYS_CLK. The line-reset length determiner 143 may determine the line-reset length based on the differential line voltage DIF and the system clock count value SYS_CNT. For example, the system clock SYS_CLK may be toggled according to the first frequency, and during a period in which the differential line voltage DIF maintains a logic high level, that is, during a period in which it is DIF-P, the system clock count value (SYS_CNT) may be created with X, for example. Accordingly, the line-reset determiner 143 may determine the line-reset length from the first frequency and the system clock count value SYS_CNT.

8 is a block diagram illustrating a line-reset detector 140b according to an embodiment of the present disclosure.

1 and 8 together, the line-reset detector 140b may include a comparator 141 and an RC filter 144, and may correspond to an example of the line-reset detector 140 of FIG. have. In an embodiment, the RC filter 144 may be included in the physical layer 111 of the interconnect unit 110 . In an embodiment, the RC filter 144 may be included in the device controller 120 .

The comparator 141 may generate a differential line voltage DIF by comparing the positive input signal DIN_t and the negative input signal DIN_c. The RC filter 144 may include a resistor R and a capacitor C, and may generate an output voltage Vout from the received differential line voltage DIF as the input voltage Vin. The line-reset detector 140b may detect the line-reset length based on the output voltage Vout1. Specifically, the RC filter 144 may detect the output voltage Vout corresponding to the differential line voltage DIF at a first time point (eg, t1 of FIG. 10 ), for example, at the first time point. may correspond to a time constant based on the resistance value of the resistor R and the capacitance of the capacitor C.

9 is a block diagram illustrating a line-reset detector 140c according to an embodiment of the present disclosure.

Referring to FIG. 9 , the line-reset detector 140c may include a comparator 141 , an RC filter 144 , and a trigger signal generator 145 . The line-reset detector 140c may correspond to a modified example of the line-reset detector 140b of FIG. 8 , and the contents described above with reference to FIGS. 1 and 8 may also be applied to this embodiment. The trigger signal generator 145 may generate the trigger signal TS from the output voltage Vout. For example, the trigger signal generator 145 may be implemented as a pulse generator, and the trigger signal TS may be generated as a pulse waveform. The line-reset detector 140c may detect a line-reset length from the trigger signal TS.

10 is a timing diagram exemplarily illustrating a detection operation of the line-reset detector 140c of FIG. 9 according to an embodiment of the present disclosure.

9 and 10 together, the differential line voltage DIF may transition from a logic low to a logic high at t0, and accordingly, the voltage level of the output voltage Vout may increase. At t1, the RC filter 144 may detect an output voltage Vout corresponding to the differential line voltage DIF, and the trigger signal generator 145 is a trigger enabled according to the voltage level of the output voltage Vout. A signal TS may be generated. When the voltage level of the output voltage Vout is higher than the reference voltage level, the trigger signal generator 145 may generate a trigger signal. When the voltage level of the output voltage Vout is lower than the reference voltage level, the trigger signal generator 145 may not generate a trigger signal. In an embodiment, the RC filter 144 may include an internal switch, and when the trigger signal TS is generated, the internal switch of the RC filter 144 may be turned off. Accordingly, after t1 , the differential line voltage DIF may not be applied to the RC filter 144 , and accordingly, the voltage level of the output voltage Vout may decrease.

For example, the reference time T1 from t0 to t1 may correspond to the maximum value (eg, 300 μs) of the _{line-reset high-speed link-up detection period T LINE-RESET-HS-LINKUP-DETECT.} . In this case, the time constant of the RC filter 144 may correspond to the first reference time T1. When the trigger signal TS is generated, the line-reset detector 140c determines that the length of the line-reset signal is longer than the maximum value _{of the line-reset high-speed link-up detection section T LINE-RESET-HS-LINKUP-DETECT} In this case, the host 200 and the storage device 100 may perform link startup in a low speed mode. On the other hand, when the line-reset detector 140c does not generate the trigger signal TS, the length of the line-reset signal is greater than the maximum value _{of the line-reset high-speed link-up detection section T LINE-RESET-HS-LINKUP-DETECT .} It may be determined to be short, and in this case, the host 200 and the storage device 100 may perform link startup in a high-speed mode.

In some embodiments, the line-reset detector 140c may include a plurality of RC filters corresponding to the number of the number of detection points. For example, the line-reset detector 140c may include _{the minimum and maximum values of the line-reset detection period T LINE-RESET-DETECT} illustrated in FIG. 4 , and the line-reset high-speed link-up detection period T _{LINE. -RESET-HS-LINKUP-DETECT} ) may include four RC filters for detecting the minimum and maximum values. At this time, the time constants of the four RC filters are _{the minimum and maximum values of the line-reset detection section (T LINE-RESET-DETECT} ), and the line-reset high-speed link-up detection section (T _{LINE-RESET-HS-LINKUP- DETECT} ) may correspond to a minimum value and a maximum value, respectively.

11 is a flowchart illustrating a method of operating a storage device according to an embodiment of the present disclosure. Referring to FIG. 11 , the method of operating the storage device according to the present embodiment corresponds to the method of operating the link startup of the storage device, for example, in time series in the storage devices 100 and 100A of FIG. 1 or FIG. 5 . It may include the steps performed. The contents described above with reference to FIGS. 1 to 10 may be applied to the present embodiment, and redundant description will be omitted.

In step S110 , the storage device 100 receives a line-reset signal LINE-RESET. For example, the storage device 100 may receive the line-reset signal LINE-RESET from the host 200 through the first pins P1a and P1b. For example, when power is applied to the storage system 10 , the storage device 100 may receive a line-reset signal LINE-RESET from the host 200 .

In operation S130 , the storage device 100 compares the line-reset length corresponding to the length of the received line-reset signal LINE-RESET with the first reference time. For example, the first reference time may correspond to the maximum value (eg, 300 μs) of the line-reset high-speed link-up detection period T _{LINE-RESET-HS-LINKUP-DETECT of FIG. 4 .} For example, the line-reset detector 140a may detect the line-reset length based on the DIF-P section of the differential line voltage DIF and the system clock count value SYS_CNT, and the detected line-reset length may be compared with the first reference time. For example, the line-reset detector 140b or 140c may detect a line-reset length based on an output voltage corresponding to the differential line voltage DIF at a time point corresponding to the first reference time, and the detected line - The reset length may be compared with the first reference time.

In step S150 , the storage device 100 performs link startup in a high speed mode or a low speed mode. In an embodiment, if the line-reset length is shorter than the first reference time, the storage device 100 performs link startup in the high-speed mode, and if the line-reset length is longer than the first reference time, the storage device 100 can perform link start-up in low-speed mode. However, the present invention is not limited thereto, and in one embodiment, when the line-reset length is shorter than the first reference time, the storage device 100 performs link startup in the low speed mode, and the line-reset length is the first If longer than the reference time, the storage device 100 may perform link start-up in a high-speed mode.

12 is a flowchart illustrating an operation between the host 200 and the storage device 100 according to an embodiment of the present disclosure.

Referring to FIG. 12 , in operation S210 , power may be applied to the storage system 10 , and accordingly, the host 200 transmits power to the storage device 100 . In step S220 , the host 200 generates a line-reset signal LINE-RESET. Specifically, in order to instruct the high-speed link start-up operation of the storage device 100 , the host 200 sets the length of the line-reset section in which the line LINE is in the DIF-P state, for example, about 300 μs to 500 μs. It can be issued in ㎲.

In step S230 , the host 200 transmits a line-reset signal LINE-RESET to the storage device 100 through a differential input signal line through which the positive input signal DIN_t and the negative input signal DIN_c are transmitted. . Specifically, the host 200 may drive the differential input signal line to the DIF-P state according to the length of the line-reset section issued in step S220. In operation S240 , the storage device 100 detects the line-reset signal LINE-RESET received from the host 200 and compares the length of the line-reset signal LINE-RESET with a first reference time. Steps S220 to S240 may correspond to HS MODE STANDBY (HS_SB).

In step S250, the host 200 performs a link start-up operation in a high-speed mode. In step S260 , the storage device 100 performs a link start-up operation in a high-speed mode. Steps S250 and S260 may be performed substantially simultaneously. For example, steps S250 and S260 may correspond to step S150 of FIG. 11 . In an embodiment, the link startup operation may include an initialization operation of the physical layers 111 and 211 and the link layers 115 and 215 . The link startup operation may further include an information exchange operation between the host 200 and the storage device 100 . In step S270 , when the link start-up operation is completed, the host 200 and the storage device 100 may be set to a link-up state, and the host 200 and the storage device 100 may stably transmit and receive data. have. Steps S250 to S270 may be performed in the high-speed mode HS_MD.

13 is a flowchart illustrating a method of operating a storage device according to an embodiment of the present disclosure. Referring to FIG. 13 , the operating method of the storage device according to the present embodiment corresponds to the link startup operating method of the storage device, and the operating method of FIG. 11 may correspond to a modified example. The contents described above with reference to FIG. 11 may also be applied to the present embodiment, and below, differences from FIG. 11 will be mainly described.

In step S110 , the storage device 100 receives a line-reset signal LINE-RESET. In operation S130 , the storage device 100 compares the line-reset length corresponding to the length of the received line-reset signal LINE-RESET with the first reference time. In step S140 , the storage device 100 sets a physical layer or a link layer of the interconnect layer according to the comparison result of the line-reset length and the first reference time. For example, the device controller 120 may set the physical layer 111 of the interconnect unit 110 according to a result of comparing the line-reset length and the first reference time. For example, the device controller 120 may transmit information on a result of comparing the line-reset length and the first reference time to the link layer 115 of the interconnect unit 110 . For example, the storage device 100 may initialize the physical layer 111 and the link layer 115 according to the comparison result of the line-reset length and the first reference time. In step S150 , the storage device 100 performs link startup in a high speed mode or a low speed mode.

14 is a flowchart exemplarily illustrating a fast mode initialization sequence between the UFS host 200a and the UFS device 100a according to an embodiment of the present disclosure.

Referring to FIG. 14 , the UFS host 200a may be an example of the host 200 of FIG. 1 , and the UFS device 100a may be an example of the storage device 100 of FIG. 1 . When power is applied to the UFS host 200a and the UFS device 100a, in the high-speed mode standby (HS_SB) phase, the UFS device 100a receives a line-reset signal LINE-RESET from the UFS host 200a and , it is possible to determine the length of the received line-reset signal LINE-RESET. When the length of the line-reset signal LINE-RESET is determined, the UFS host 200a and the USF device 100a may perform a link start-up operation in the high-speed mode. Specifically, the UFS host 200a and the USF device 100a may perform an M-PHY/UniPro initialization (S310) and perform a link startup sequence (S320) by exchanging information. In this case, the UFS host 200a and the UFS device 100a may simultaneously perform a read operation and a write operation in parallel through a full duplex LVDS serial interface.

15 is a flowchart illustrating a link startup operation between the host 200 and the storage device 100 according to an embodiment of the present disclosure.

1, 1 and 15 together, in step S410, the host 200 generates a line-reset signal LINE-RESET, resets transmitters of connected lanes, and provides information indicating that the transmitters are reset. may be transmitted to the storage device 100 . Also, in operation S410 , the storage device 100 may receive the line-reset signal LINE-RESET, reset receivers of connected lanes, and transmit information indicating that the receivers are reset to the host 200 . Through this line-reset operation, all attributes of the physical layers 111 and 211 of the interconnects 110 and 210 may be reset to default values. The host 200 and the storage device 100 may exchange line-reset information with each other. Step S410 may be referred to as a line-reset step. After the line-reset step is performed, a link startup sequence including steps S420 to S460 may be started.

Steps S420 to S460 may correspond to a link startup sequence. The link startup sequence is performed in a multi-phase handshake manner, exchanging UniPro trigger events to establish initial link communication in both directions, between the host 200 and the storage device 100 . can be A link startup sequence may be defined as predetermined phases, a trigger event may be used for each phase, and each trigger event may be transmitted multiple times.

In the first step S420 of the link startup sequence, connected lanes may be discovered between the host 200 and the storage device 100 . In step S420 , the host 200 may send a first trigger event TRG_UPR0 on all available TX Lanes. The host 200 may continue to transmit the first trigger event TRG_UPR0 until it receives the first trigger event message from the storage device 100 . The first trigger event TRG_UPR0 transmitted from the host 200 may include a physical lane number of a transmission lane of the host 200 through which the corresponding trigger is transmitted.

Also, in the first step S420 , the storage device 100 may transmit a first trigger event TRG_UPR0 in all available transmission lanes. The storage device 100 may continuously transmit the first trigger event TRG_UPR0 until it receives the first trigger event message from the host 200 . The first trigger event TRG_UPR0 transmitted from the storage device 100 may include a physical lane number of a transmission lane of the storage device 100 through which the corresponding trigger is transmitted.

In the second step ( S430 ) of the link startup sequence, lanes may be realigned. In step S430 , the host 200 may transmit a second trigger event TRG_UPR1 in all available transmission lanes. The host 200 may continuously transmit the second trigger event TRG_UPR1 until it receives the second trigger event message from the storage device 100 . The second trigger event TRG_UPR1 transmitted from the host 200 may include information on transmission lanes connected to the host 200 .

Also, in the second step S430 , the storage device 100 may transmit a second trigger event TRG_UPR1 in all available transmission lanes. The storage device 100 may continuously transmit the second trigger event TRG_UPR1 until it receives the second trigger event message from the host 200 . The second trigger event TRG_UPR1 transmitted from the storage device 100 may include information on transmission lanes connected to the storage device 100 .

In the third step (S440) of the link startup sequence, the physical layers ( 111, 211) can be reflected. In step S440 , the host 200 may transmit a third trigger event TRG_UPR2 in all available transmission lanes. The host 200 may continuously transmit the third trigger event TRG_UPR2 until a message corresponding to the third trigger event TRG_UPR2 is received from the storage device 100 . The third trigger event TRG_UPR2 transmitted from the host 200 may include logical lane numbers for transmission lanes connected to the host 200 .

Also, in step S440 , the storage device 100 may transmit a third trigger event TRG_UPR2 in all available transmission lanes. The storage device 100 may continue to transmit the third trigger event TRG_UPR2 until it receives a third trigger event message corresponding to the third trigger event TRG_UPR2 from the host 200 . The third trigger event TRG_UPR2 transmitted from the storage device 100 may include logical lane numbers related to transmission lanes connected to the storage device 100 .

As the third step S430 of the link startup sequence is performed, the host 200 and the storage device 100 may have identical logical lane numbers for available lanes. At this point, the host 200 and the storage device 100 may terminate the link startup sequence and perform capability exchange.

In step S450 , the host 200 and the storage device 100 may exchange and recognize the performance information CAP of the counterpart device in order to communicate architectural requirements of the interconnect units 210 and 110 . Architectural requirements of interconnects 210 , 110 may include, for example, bandwidth, timers, speed gear, termination/untermination, scrambling, and the like. Step S450 may be referred to as a performance exchange step. As the performance exchange step S450 is performed, information on the performance of the counterpart device CAP is collected in the interconnects 210 and 110, and the physical properties of the interconnects 210 and 110 are collected according to the collected performance information CAP. The properties of the layers may be set.

In operation S460 , the host 200 and the storage device 100 may exchange a control frame (AFC) with each other in order to provide a reliable data link. To this end, the host 200 and the storage device 100 may send an initial data frame to the counterpart device, and the device receiving the data frame sends back a control frame (AFC) to the device transmitting the data frame. can do. The control frame (AFC) may be configured differently from the data frame, and may be used to notify the transmission device that it has been correctly received and to inform the buffer space of the available data link layer. In step S470, when the link start-up operation is completed, the host 200 and the storage device 100 may be set to a link-up state, and the host 200 and the storage device 100 may stably transmit and receive data. have.

16 is a flowchart illustrating a link startup method of a storage device according to an embodiment of the present disclosure. Referring to FIG. 16 , the link startup method of the storage device according to the present embodiment may correspond to an implementation example of the link startup method of FIG. 11 , and the steps performed in time series in the storage device 100 of FIG. 1 . may include Hereinafter, a link startup method will be described with reference to FIGS. 1, 3, 4 and 16 together.

In operation S540 , the storage device 100 determines whether the line-reset length is longer than the first reference time T1 . For example, the first reference time T1 may correspond to the maximum value (eg, 300 μs) of the line-reset high-speed link-up detection period T _{LINE-RESET-HS-LINKUP-DETECT .} Here, the line-reset length may correspond to the length of the line-reset signal, for example, the length of a section in which the differential line voltage DIF is driven in the DIF-P state. For example, the differential line voltage DIF may correspond to a voltage level difference between the positive input signal DIN_t and the negative input signal DIN_c respectively received at the first pins P1a and P1b of FIG. 1 . For example, step S540 may correspond to step S420 of FIG. 15 .

As a result of the determination, if the line-reset length is not longer than the first reference time T1 , in step S560 , the storage device 100 performs a fast mode link startup sequence. For example, steps S430 to S460 of FIG. 15 may be performed in a high-speed mode. Meanwhile, if the line-reset length is longer than the first reference time T1 , the storage device 100 performs a low-speed mode link startup sequence. For example, steps S430 to S460 of FIG. 15 may be performed in a low speed mode, that is, a PWM mode.

In the low-speed link startup performed by the PWM method, when information required for link startup is exchanged between the storage device 100 and the host 200 through a lane (transmission lane or reception lane), it is necessary for link startup Bits for representing information are expressed through a pulse width of a signal transmitted through a lane. In the low-speed mode link start-up of the PWM method, the RZ (return to zero) method in which a logic low section must exist between each logic high section of a signal transmitted through a lane. applies.

In contrast, in the high-speed mode link startup, bits representing information necessary for link startup are expressed through the logic level of the signal transmitted through the lane, and even if the logic high interval is continuous, there is a logic low interval between the intervals. A non-return to zero (NRZ) method that does not need to exist is applied. Accordingly, the high-speed mode link start-up operation may be performed at a higher speed than the low-speed mode link start-up operation.

17 is a flowchart illustrating a link startup method of a storage device according to an embodiment of the present disclosure. Referring to FIG. 17 , the link startup method of the storage device according to the present embodiment may correspond to a modified example of the link startup method of FIG. 16 , and a redundant description will be omitted.

In operation S530 , the storage device 100 determines whether the line-reset length is longer than the second reference time T2 . For example, the second reference time T2 may correspond to the minimum value (eg, 200 μs) of the line-reset high-speed link-up detection period T _{LINE-RESET-HS-LINKUP-DETECT of FIG. 4 .} . As a result of the determination, if the line-reset length is longer than the second reference time T2 , in operation S540 , the storage device 100 determines whether the line-reset length is longer than the first reference time T1 . According to the present embodiment, even if the line-reset length is shorter than the first reference time T1, if it is not longer than the second reference time T2, the link startup sequence may not be performed.

18 is a flowchart illustrating a link startup method of a storage device according to an embodiment of the present disclosure. Referring to FIG. 18 , the link start-up method of the storage device according to the present embodiment may correspond to a modified example of the link start-up method of FIG. 16 , and a duplicate description will be omitted.

In operation S510 , the storage device 100 determines whether _{the length of the activation period} T ACTIVATE is shorter than the third reference time T3 . For example, the third reference time T3 may be 0.9 ms. As a result of the determination, if _{the length of the activation period} T ACTIVATE is shorter than the third reference time T3 , in step S520 , the storage device 100 sets a physical layer or a link layer of the interconnect layer. For example, the device controller 120 may preset the physical layer 111 to perform a high-speed link startup sequence. For example, the device controller 120 may preset the link layer 115 of the interconnect unit 110 to perform a high-speed link startup sequence. For example, the storage device 100 may initialize the physical layer 111 and the link layer 115 to perform a high-speed link startup sequence. Meanwhile, if _{the length of the activation period} T ACTIVATE is not shorter than the third reference time T3 , step S540 is directly performed.

In operation S540 , the storage device 100 determines whether the line-reset length is longer than the first reference time T1 . As a result of the determination, if the line-reset length is not longer than the first reference time T1 , in step S560 , the storage device 100 performs a fast mode link startup sequence. Meanwhile, if the line-reset length is longer than the first reference time T1 , the storage device 100 performs a low-speed mode link startup sequence. As such, according to the present embodiment, in order to determine the operation mode for performing the link start-up sequence, _{the length of the activation period T ACTIVATE} is determined, and then the line-reset length is determined two-step determination method can be used.

19 is a flowchart illustrating a link startup operation between the host 200 and the storage device 100 according to an embodiment of the present disclosure. Referring to FIG. 19 , the link start-up operation according to the present embodiment may correspond to a modified example of the link start-up operation of FIG. 15 , and a redundant description will be omitted. Step S400 may correspond to the HIBERN8 escape step. In step S400 , the host 200 generates a signal (eg, an activate signal) instructing exit of the power saving mode, that is, the hibernate state (HIBERN8), and sends the generated signal to the storage device 100 . send. Specifically, the host 200 may transition the line LINE to the DIF-N state and exit the hibernate state HIBERN8. Also, in step S400 , the storage device 100 may transmit information indicating that it has escaped from the hibernate state HIBERN8 to the host 200 . Steps S410 to S470 may be performed according to the description described above with reference to FIG. 15, and thus redundant description will be omitted.

20 is a flowchart illustrating a link startup method of a storage device according to an embodiment of the present disclosure.

1, 3, and 20 together, in step S500, the storage device 100 exits the hibernate state HIBERN8. For example, when the differential line voltage DIF transitions from the DIF-Z state to the DIF-N state, the storage device 100 _{determines that the activation period T ACTIVATE} has entered, and the hibernate state HIBERN8 . can escape In operation S540 , the storage device 100 determines whether the line-reset length is longer than the first reference time T1 . As a result of the determination, if the line-reset length is not longer than the first reference time T1 , in step S560 , the storage device 100 performs a fast mode link startup sequence. Meanwhile, if the line-reset length is longer than the first reference time T1 , the storage device 100 performs a low-speed mode link startup sequence.

21 is a flowchart illustrating a link startup method of a storage device according to an embodiment of the present disclosure. Referring to FIG. 21 , the link startup method of the storage device according to the present embodiment may correspond to an implementation example of the link startup method of FIG. 11 , and the steps performed in time series in the storage device 100 of FIG. 1 . may include

In step S620 , the storage device 100 determines whether a line-reset exists. Specifically, the storage device 100 determines whether a line-reset signal LINE-RESET is received from the host 200 . In an embodiment, the storage device 100 may determine whether there is a line-reset period in which the line LINE has a positive differential line voltage. In an embodiment, the storage device 100 may determine whether the line LINE transitions from a negative differential line voltage to a positive differential line voltage. For example, the line-reset detector 140a of FIG. 6 may detect whether the line-reset signal LINE-RESET is received using the system clock SYS_CLK. For example, the line-reset detector ( 140b of FIG. 8 and 140c of FIG. 9 ) may detect whether the line-reset signal LINE-RESET is received by using the RC filter.

As a result of the determination, if the line-reset signal LINE-RESET exists, in step S640 , the storage device 100 performs a fast mode link startup sequence. In this case, the storage device 100 may omit the line-reset operation. Meanwhile, when the line-reset signal LINE-RESET does not exist, the storage device 100 performs a low-speed mode link startup sequence.

The various embodiments described above with reference to FIGS. 11 to 20 may also be applied to this embodiment. In some embodiments, after step S620 , the storage device 100 performs a physical layer 111 or link layer 115 of the interconnect unit 110 to perform a high-speed mode link startup operation or a low-speed mode link startup operation. ) can be set. Also, in some embodiments, before step S620, the storage device 100 compares the activation period in which the line LINE has a negative differential line voltage with a reference time, and when the activation period is shorter than the reference time, The physical layer 111 or the link layer 115 of the interconnect unit 110 may be configured. Also, in some embodiments, before step S620 , the storage device 100 may exit the hibernate state HIBERN8 that is the power saving state.

22 is a flowchart illustrating an operation between the host 200 and the storage device 100 according to an embodiment of the present disclosure.

Referring to FIG. 22 , in step S710 , the host 200 generates a line-reset signal LINE-RESET. In operation S720 , the host 200 transmits a line-reset signal LINE-RESET to the storage device 100 through a differential input signal line through which the positive input signal DIN_t and the negative input signal DIN_c are transmitted. . Steps S710 and S720 may correspond to the high-speed mode standby (HS_SB).

In step S730, the host 200 performs a link start-up operation in a high-speed mode. In step S740 , the storage device 100 performs a link start-up operation in a high-speed mode. Steps S730 and S740 may be performed substantially simultaneously. For example, steps S730 and S740 may correspond to steps S250 and S260 of FIG. 12 , respectively. In step S750 , when the link start-up operation is completed, the host 200 and the storage device 100 may be set to a link-up state, and the host 200 and the storage device 100 may stably transmit and receive data. have. Steps S730 to S750 may be performed in the high-speed mode HS_MD.

The various embodiments described above with reference to FIGS. 11 to 20 may also be applied to this embodiment. In some embodiments, before step S820 , the storage device 100 may configure the interconnect unit 110 to perform a fast mode link startup operation. Also, in some embodiments, the storage device 100 may configure the interconnect unit 110 to perform a low-speed link startup operation before step S880.

Further, in some embodiments, in step S820 , between the storage device 100 and the host 200 , a first trigger event of exchanging physical lane numbers of a transmission lane and a reception lane is performed, and information of the transmission lane and A second trigger event for exchanging information on a reception lane may be performed, and a third trigger event for exchanging logical lane information on a transmission lane and a reception lane may be performed. In addition, in some embodiments, in step S820 , after performing the third trigger event, performance information is exchanged and recognized between the storage device 100 and the host 200 , and the transmitted initial data frame is correctly received It is possible to exchange and recognize the control frame indicating that the

23 is a flowchart illustrating a link startup method of a storage device according to an embodiment of the present disclosure. Referring to FIG. 23 , the link startup method of the storage device according to the present embodiment may correspond to an implementation example of the link startup method of FIG. 11 , and the steps performed in time series in the storage device 100 of FIG. 1 . may include

In step S820 , the storage device 100 performs a fast mode link startup sequence. In step S840, the storage device 100 determines whether the high-speed link-up is completed. As a result of the determination, when the high-speed link-up is completed, in step S860, the storage device 100 determines whether a link-up pass is made. As a result of the determination, when the link-up is passed, the link-up method is terminated. On the other hand, if the link-up is not passed, in step S880, the storage device 100 performs a low-speed mode link startup sequence.

In the initial stage, since the host 200 does not know whether the storage device 100 supports the high-speed mode, the host 200 may preferentially perform the high-speed mode link startup sequence. When the link-up is passed as a result of performing the high-speed mode link start-up sequence, the host 200 may determine that the storage device 100 is a device supporting the high-speed mode. Meanwhile, when the link-up is not passed as a result of performing the high-speed mode link startup sequence, the host 200 determines that the storage device 100 is a device that does not support the high-speed mode, and performs the low-speed mode link startup sequence. can do.

As described above, according to the present embodiment, when power is applied to the storage system 10 , the host 200 and the storage device 100 may first perform a high-speed mode link startup sequence. Accordingly, when the storage device 100 is a device supporting the high-speed mode, the high-speed mode link start-up sequence can be directly performed without performing an operation such as line-reset presence or line-reset length detection. The time required for startup processing can be further reduced.

24 is a flowchart illustrating a link startup method of a storage device according to an embodiment of the present disclosure. Referring to FIG. 24 , the link startup method of the storage device according to the present embodiment may correspond to an implementation example of the link startup method of FIG. 23 , and the steps performed in time series in the storage device 100 of FIG. 1 . may include

In step S820 , the storage device 100 performs a fast mode link startup sequence. In step S840a, the storage device 100 determines whether the execution time (t) of the fast mode link startup sequence has elapsed a threshold time (Tth). Specifically, the storage device 100 may determine whether the threshold time Tth has elapsed from the start time of the fast mode link startup sequence. The threshold time Tth may be defined as a link timeout value. For example, the threshold time Tth may be about 10 ms.

If the execution time t has passed the threshold time Tth, in step S840a , the storage device 100 determines whether performance information (eg, PACP_CAP_ind) has been received from the host 200 . When the storage device 100 receives the performance information from the host 200 , it may be determined that the link-up has passed. Meanwhile, when the storage device 100 does not receive the performance information from the host 200 , it is determined that the link-up has not been passed. If the link-up is not passed, in step S880, the storage device 100 performs a low-speed mode link startup sequence.

25 is a diagram for explaining the UFS system 1000 according to an embodiment of the present invention. The UFS system 1000 is a system conforming to the UFS standard published by the Joint Electron Device Engineering Council (JEDEC), and may include a UFS host 1100 , a UFS device 1200 , and a UFS interface 1300 . The above description of the storage systems 10 and 10A of FIGS. 1 and 5 may also be applied to the UFS system 1000 of FIG. 25 within the scope not in conflict with the following description of FIG. 25 .

Referring to FIG. 25 , a UFS host 1100 and a UFS device 1200 may be interconnected through a UFS interface 1300 . When the host 200 of FIG. 1 is an application processor, the UFS host 1100 may be implemented as a part of the corresponding application processor. The UFS host controller 1110 may respectively correspond to the host controller 220 of FIG. 1 . The UFS device 1200 may correspond to the storage device 100 of FIG. 1 , and the UFS device controller 1210 and the non-volatile memory 1220 are connected to the device controller 120 and the non-volatile memory 130 of FIG. 1 . Each can be matched.

The UFS host 1100 may include a UFS host controller 1110 , an application 1120 , a UFS driver 1130 , a host memory 1140 , and a UFS interconnect (UIC) layer 1150 . The UFS device 1200 may include a UFS device controller 1210 , a non-volatile memory 1220 , a storage interface 1230 , a device memory 1240 , a UIC layer 1250 , and a regulator 1260 . The nonvolatile memory 1220 may include a plurality of memory units 1221 , and the memory unit 1221 may include a V-NAND flash memory having a 2D structure or a 3D structure, but PRAM and/or RRAM It may include other types of non-volatile memory such as The UFS device controller 1210 and the nonvolatile memory 1220 may be connected to each other through the storage interface 1230 . The storage interface 1230 may be implemented to comply with a standard protocol such as toggle or ONFI.

The application 1120 may mean a program that wants to communicate with the UFS device 1200 in order to use the function of the UFS device 1200 . The application 1120 may transmit an input-output request (IOR) to the UFS driver 1130 for input/output to the UFS device 1200 . The input/output request (IOR) may mean a read request, a write request, and/or a discard request of data, but is not limited thereto.

The UFS driver 1130 may manage the UFS host controller 1110 through a UFS-HCI (host controller interface). The UFS driver 1130 may convert an input/output request generated by the application 1120 into a UFS command defined by the UFS standard, and transmit the converted UFS command to the UFS host controller 1110 . One I/O request can be converted into multiple UFS commands. A UFS command may be basically a command defined by the SCSI standard, but it may also be a command dedicated to the UFS standard.

The UFS host controller 1110 may transmit the UFS command converted by the UFS driver 1130 to the UIC layer 1250 of the UFS device 1200 through the UIC layer 1150 and the UFS interface 1300 . In this process, the UFS host register 1111 of the UFS host controller 1110 may serve as a command queue (CQ).

The UIC layer 1150 on the UFS host 1100 side may include MIPI M-PHY 1151 and MIPI UniPro 1152 , and the UIC layer 1250 on the UFS device 1200 side also MIPI M-PHY ( 1251) and MIPI UniPro (1252).

The UFS interface 1300 includes a line for transmitting a reference clock REF_CLK, a line for transmitting a hardware reset signal RESET_n for the UFS device 1200, and a pair of lines for transmitting a differential input signal pair DIN_t and DIN_c. and a pair of lines for transmitting the differential output signal pair DOUT_t and DOUT_c.

The frequency value of the reference clock provided from the UFS host 1100 to the UFS device 1200 may be one of four values of 19.2 MHz, 26 MHz, 38.4 MHz, and 52 MHz, but is not limited thereto. The UFS host 1100 may change the frequency value of the reference clock during operation, that is, while data transmission/reception is performed between the UFS host 1100 and the UFS device 1200 . The UFS device 1200 may generate clocks of various frequencies from the reference clock provided from the UFS host 1100 using a phase-locked loop (PLL) or the like. Also, the UFS host 1100 may set a data rate value between the UFS host 1100 and the UFS device 1200 through the frequency value of the reference clock. That is, the value of the data rate may be determined depending on the frequency value of the reference clock.

The UFS interface 1300 may support multiple lanes, and each lane may be implemented as a differential pair. For example, the UFS interface may include one or more receive lanes and one or more transmit lanes. In FIG. 25 , a pair of lines for transmitting a differential input signal pair (DIN_T and DIN_C) may constitute a receive lane, and a pair of lines for transmitting a differential output signal pair (DOUT_T and DOUT_C) may constitute a transmit lane, respectively. . Although one transmission lane and one reception lane are illustrated in FIG. 25, the number of transmission lanes and reception lanes may be changed.

The reception lane and the transmission lane may transmit data in a serial communication method, and a full-duplex between the UFS host 1100 and the UFS device 1200 by a structure in which the reception and transmission lanes are separated. method of communication is possible. That is, the UFS device 1200 may transmit data to the UFS host 1100 through the transmission lane while receiving data from the UFS host 1100 through the reception lane. In addition, control data such as a command from the UFS host 1100 to the UFS device 1200, and the UFS host 1100 to be stored in the nonvolatile memory 1220 of the UFS device 1200 or from the nonvolatile memory 1220 User data to be read may be transmitted through the same lane. Accordingly, between the UFS host 1100 and the UFS device 1200, there is no need to further provide a separate lane for data transmission in addition to the pair of reception lanes and the pair of transmission lanes.

The UFS device controller 1210 of the UFS device 1200 may control overall operation of the UFS device 1200 . The UFS device controller 1210 may manage the nonvolatile memory 1220 through a logical unit (LU) 1211 which is a logical data storage unit. The number of LUs 1211 may be 8, but is not limited thereto. The UFS device controller 1210 may include a flash translation layer (FTL), and a logical data address transmitted from the UFS host 1100 using address mapping information of the FTL, for example, an LBA. (logical block address) may be converted into a physical data address, for example, into a physical block address (PBA). A logical block for storing user data in the UFS system 1000 may have a size within a predetermined range. For example, the minimum size of the logical block may be set to 4Kbyte.

When a command from the UFS host 1100 is input to the UFS device 1200 through the UIC layer 1250, the UFS device controller 1210 performs an operation according to the input command, and when the operation is completed, a completion response is returned. It can be transmitted to the UFS host 1100 .

As an example, when the UFS host 1100 intends to store user data in the UFS device 1200 , the UFS host 1100 may transmit a data storage command to the UFS device 1200 . When a response indicating that the user data is ready-to-transfer is received from the UFS device 1200 , the UFS host 1100 may transmit the user data to the UFS device 1200 . The UFS device controller 1210 temporarily stores the received user data in the device memory 1240 , and transfers the user data temporarily stored in the device memory 1240 based on the address mapping information of the FTL to the nonvolatile memory 1220 . You can save it to a location of your choice.

As another example, when the UFS host 1100 wants to read user data stored in the UFS device 1200 , the UFS host 1100 may transmit a data read command to the UFS device 1200 . Upon receiving the command, the UFS device controller 1210 may read user data from the nonvolatile memory 1220 based on the data read command and temporarily store the read user data in the device memory 1240 . In this reading process, the UFS device controller 1210 may detect and correct an error in the read user data using a built-in error correction code (ECC) engine (not shown). More specifically, the ECC engine may generate parity bits for write data to be written into the non-volatile memory 1220 , and the generated parity bits are stored in the non-volatile memory 1220 together with the write data. can be saved. When reading data from the non-volatile memory 1220, the ECC engine corrects an error in the read data using parity bits read from the non-volatile memory 1220 together with the read data, and outputs the error-corrected read data. can

In addition, the UFS device controller 1210 may transmit user data temporarily stored in the device memory 1240 to the UFS host 1100 . In addition, the UFS device controller 1210 may further include an advanced encryption standard (AES) engine (not shown). The AES engine may perform at least one of an encryption operation and a decryption operation on data input to the UFS device controller 1210 using a symmetric-key algorithm.

The UFS host 1100 may sequentially store commands to be transmitted to the UFS device 1200 in the UFS host register 1111, which may function as a command queue, and may transmit the commands to the UFS device 1200 in this order. . At this time, even when the previously transmitted command is still being processed by the UFS device 1200 , that is, even before the UFS host 1100 receives a notification that the previously transmitted command has been processed by the UFS device 1200 . The next command waiting in the command queue may be transmitted to the UFS device 1200 , and accordingly, the UFS device 1200 may also receive the next command from the UFS host 1100 while processing the previously transmitted command. The maximum number of commands that can be stored in such a command queue (queue depth) may be, for example, 32. In addition, the command queue may be implemented as a circular queue type indicating the start and end of the command sequence stored in the queue, respectively, through a head pointer and a tail pointer.

Each of the plurality of memory units 1221 may include a memory cell array (not shown) and a control circuit (not shown) for controlling an operation of the memory cell array. The memory cell array may include a two-dimensional memory cell array or a three-dimensional memory cell array. The memory cell array includes a plurality of memory cells, and each memory cell may be a cell (single level cell, SLC) storing one bit of information, but a multi level cell (MLC), a triple level cell (TLC), It may be a cell that stores information of 2 bits or more, such as a quadruple level cell (QLC). The three-dimensional memory cell array may include vertical NAND strings that are vertically oriented such that at least one memory cell is positioned on top of another memory cell.

VCC, VCCQ, VCCQ2, etc. may be input to the UFS device 1200 as a power voltage. VCC is a main power voltage for the UFS device 1200 and may have a value of 2.4 to 3.6V. VCCQ is a power supply voltage for supplying a low-range voltage, mainly for the UFS device controller 1210 . It can have a value of 1.14 to 1.26V. VCCQ2 is a power supply voltage for supplying a voltage in a range lower than VCC but higher than VCCQ, mainly for an input/output interface such as the MIPI M-PHY 1251, and may have a value of 1.7 to 1.95V. The power voltages may be supplied for each component of the UFS device 1200 through the regulator 1260 . The regulator 1260 may be implemented as a set of unit regulators respectively connected to different ones of the above-described power voltages.

26A to 25C are diagrams for explaining a form factor of a UFS card. When the UFS device 1200 described with reference to FIG. 25 is implemented in the form of the UFS card 2000, the appearance of the UFS card 2000 may be as shown in FIGS. 26A to 26C.

26A exemplarily shows a top view of the UFS card 2000 . Referring to FIG. 26A , it can be seen that the UFS card 2000 follows a shark-shaped design as a whole. Referring to FIG. 26A , the UFS card 2000 may have dimension values as exemplarily shown in Table 1 below.

item Dimensions (mm) T1 9.70 T2 15.00 T3 11.00 T4 9.70 T5 5.15 T6 0.25 T7 0.60 T8 0.75 T9 R0.80

26B exemplarily shows a side view of the UFS card 2000 . Referring to FIG. 26B , the UFS card 2000 may have dimension values as exemplarily shown in Table 2 below.

item Dimensions (mm) S1 0.74±0.06 S2 0.30 S3 0.52 S4 1.20 S5 1.05 S6 1.00

26C exemplarily shows a bottom view of the UFS card 2000 . Referring to FIG. 26C , a plurality of pins for electrical contact with the UFS slot may be formed on the bottom surface of the UFS card 2000 , and the function of each pin will be described later. Based on the symmetry between the top and bottom surfaces of the UFS card 2000, some of the information regarding dimensions described with reference to FIG. 26A and Table 1 (eg, T1 to T5 and T9) is a UFS card as shown in FIG. 26C (2000). A plurality of pins may be formed on the bottom of the UFS card 2000 for electrical connection with the UFS host, and according to FIG. 26C, the total number of pins may be 12. Each pin may have a rectangular shape, and a signal name corresponding to the pin is as shown in FIG. 26C . For schematic information on each pin, refer to Table 3 below.

number signal name Explanation Dimensions (mm) One VSS Ground (GND) 3.00 × 0.72±0.05 2 DIN_C Differential input signal input from the host to the UFS card (2000) (DIN_C is a negative node, DIN_T is a positive node) 1.50 × 0.72±0.05 3 DIN_T 4 VSS same as 1 3.00 × 0.72±0.05 5 DOUT_C A differential output signal output from the UFS card 2000 to the host (DOUT_C is a negative node, DOUT_T is a positive node) 1.50 × 0.72±0.05 6 DOUT_T 7 VSS same as 1 3.00 × 0.72±0.05 8 REF_CLK Reference clock provided from host to UFS card (2000) 1.50 × 0.72±0.05 9 VCCQ2 A supply voltage with a relatively low value relative to Vcc, mainly provided for the PHY interface or controller. 3.00 × 0.72±0.05 10 C/D (GND) Signals for Card Detection 1.50 × 0.72±0.05 11 VSS same as 1 3.00 × 0.80±0.05 12 Vcc mains voltage

27 is a block diagram illustrating a memory system 3000 according to an embodiment of the present disclosure. Referring to FIG. 27 , the memory system 3000 may include a memory device 3200 and a memory controller 3100 . The memory device 3200 may correspond to one of the nonvolatile memory devices communicating with the memory controller 3100 based on one of a plurality of channels. For example, the memory device 3200 may correspond to the nonvolatile memory 130 of FIG. 1 , and the memory controller 3100 may correspond to the device controller 120 of FIG. 1 .

The memory device 3200 may include first to eighth pins P11 to P18 , a memory interface circuit 3210 , a control logic circuit 3220 , and a memory cell array 3230 . The memory interface circuit 3210 may receive the chip enable signal nCE from the memory controller 3100 through the first pin P11 . The memory interface circuit 3210 may transmit/receive signals to and from the memory controller 3100 through the second to eighth pins P12 to P18 according to the chip enable signal nCE. For example, when the chip enable signal nCE is in an enable state (eg, a low level), the memory interface circuit 3310 operates the memory controller 3100 through the second to eighth pins P12 to P18. ) and can transmit and receive signals.

The memory interface circuit 3210 receives a command latch enable signal CLE, an address latch enable signal ALE, and a write enable signal from the memory controller 3100 through the second to fourth pins P12 to P14. nWE) can be received. The memory interface circuit 3210 may receive the data signal DQ from the memory controller 3100 through the seventh pin P17 or transmit the data signal DQ to the memory controller 3100 . The command CMD, the address ADDR, and the data DATA may be transmitted through the data signal DQ. For example, the data signal DQ may be transmitted through a plurality of data signal lines. In this case, the seventh pin P17 may include a plurality of pins corresponding to a plurality of data signals.

The memory interface circuit 3210 receives the data signal DQ in the enable period (eg, high level state) of the command latch enable signal CLE based on the toggle timings of the write enable signal nWE. A command (CMD) can be obtained from The memory interface circuit 3210 receives the data signal DQ in the enable period (eg, high level state) of the address latch enable signal ALE based on the toggle timings of the write enable signal nWE. The address ADDR can be obtained from

In an exemplary embodiment, the write enable signal nWE may be toggled between a high level and a low level while maintaining a static state (eg, a high level or a low level). have. For example, the write enable signal nWE may be toggled in a period in which the command CMD or the address ADDR is transmitted. Accordingly, the memory interface circuit 3210 may acquire the command CMD or the address ADDR based on the toggle timings of the write enable signal nWE.

The memory interface circuit 3210 may receive the read enable signal nRE from the memory controller 3100 through the fifth pin P15 . The memory interface circuit 3210 may receive the data strobe signal DQS from the memory controller 3100 through the sixth pin P16 or transmit the data strobe signal DQS to the memory controller 3100 .

In the data output operation of the memory device 3200 , the memory interface circuit 3210 may receive the read enable signal nRE toggling through the fifth pin P15 before outputting the data DATA. have. The memory interface circuit 3210 may generate a toggling data strobe signal DQS based on the toggling of the read enable signal nRE. For example, the memory interface circuit 3210 generates a data strobe signal DQS that starts toggling after a predetermined delay (eg, tDQSRE) based on a toggling start time of the read enable signal nRE. can do. The memory interface circuit 310 may transmit the data signal DQ including the data DATA based on the toggle timing of the data strobe signal DQS. Accordingly, the data DATA may be aligned with the toggle timing of the data strobe signal DQS and transmitted to the memory controller 3100 .

In the data input operation of the memory device 3200 , when the data signal DQ including the data DATA is received from the memory controller 3100 , the memory interface circuit 3210 receives the data from the memory controller 3100 . A data strobe signal DQS toggling together with the data DATA may be received. The memory interface circuit 3210 may acquire the data DATA from the data signal DQ based on the toggle timing of the data strobe signal DQS. For example, the memory interface circuit 3210 may acquire the data DATA by sampling the data signal DQ at a rising edge and a falling edge of the data strobe signal DQS.

The memory interface circuit 3210 may transmit the ready/busy output signal nR/B to the memory controller 3100 through the eighth pin P18 . The memory interface circuit 3210 may transmit state information of the memory device 3200 to the memory controller 3100 through the ready/busy output signal nR/B. When the memory device 3200 is in a busy state (ie, when internal operations of the memory device 3200 are being performed), the memory interface circuit 3210 transmits a ready/busy output signal nR/B indicating the busy state to the memory controller. It can be transmitted to (3100). When the memory device 3200 is in the ready state (that is, when internal operations of the memory device 3200 are not performed or completed), the memory interface circuit 3210 outputs a ready/busy output signal nR/B indicating the ready state. may be transmitted to the memory controller 3100 . For example, while the memory device 3200 reads data DATA from the memory cell array 3230 in response to a page read command, the memory interface circuit 3210 may be in a busy state (eg, a low level). A ready/busy output signal nR/B indicating , may be transmitted to the memory controller 3100 . For example, while the memory device 3200 programs data DATA into the memory cell array 3230 in response to a program command, the memory interface circuit 3210 generates a ready/busy output signal nR/ B) may be transmitted to the memory controller 3100 .

The control logic circuit 3220 may generally control various operations of the memory device 3200 . The control logic circuit 3220 may receive the command/address CMD/ADDR obtained from the memory interface circuit 3210 . The control logic circuit 3220 may generate control signals for controlling other components of the memory device 3200 according to the received command/address CMD/ADDR. For example, the control logic circuit 3220 may generate various control signals for programming data DATA in the memory cell array 3230 or reading data DATA from the memory cell array 3230 . .

The memory cell array 3230 may store data DATA obtained from the memory interface circuit 3210 under the control of the control logic circuit 3220 . The memory cell array 3230 may output the stored data DATA to the memory interface circuit 3210 under the control of the control logic circuit 3220 .

The memory cell array 3230 may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. However, the present invention is not limited thereto, and the memory cells include a resistive random access memory (RRAM) cell, a ferroelectric random access memory (FRAM) cell, a phase change random access memory (PRAM) cell, a thyristor random access memory (TRAM) cell, They may be Magnetic Random Access Memory (MRAM) cells. Hereinafter, embodiments of the present invention will be described focusing on an embodiment in which the memory cells are NAND flash memory cells.

The memory controller 3100 may include first to eighth pins P21 to P28 and a controller interface circuit 3110 . The first to eighth pins P21 to P28 may correspond to the first to eighth pins P11 to P18 of the memory device 3200 . The controller interface circuit 3110 may transmit the chip enable signal nCE to the memory device 3200 through the first pin P21 . The controller interface circuit 3110 may transmit/receive signals to and from the memory device 3200 selected through the chip enable signal nCE and the second to eighth pins P22 to P28.

The controller interface circuit 3110 transmits the command latch enable signal CLE, the address latch enable signal ALE, and the write enable signal nWE to the memory device through the second to fourth pins P22 to P24. 3200) can be transmitted. The controller interface circuit 3110 may transmit the data signal DQ to the memory device 3200 or receive the data signal DQ from the memory device 3200 through the seventh pin P27 .

The controller interface circuit 3110 may transmit the data signal DQ including the command CMD or the address ADDR together with the toggling write enable signal nWE to the memory device 3200 . The controller interface circuit 3110 transmits the data signal DQ including the command CMD to the memory device 3200 as the command latch enable signal CLE having an enable state is transmitted, and sets the enable state to the memory device 3200 . As the branch transmits the address latch enable signal ALE, the data signal DQ including the address ADDR may be transmitted to the memory device 3200 .

The controller interface circuit 3110 may transmit the read enable signal nRE to the memory device 3200 through the fifth pin P25 . The controller interface circuit 3110 may receive the data strobe signal DQS from the memory device 3200 through the sixth pin P26 or transmit the data strobe signal DQS to the memory device 3200 .

In the data output operation of the memory device 3200 , the controller interface circuit 3110 may generate a toggle read enable signal nRE and transmit the read enable signal nRE to the memory device 3200 . have. For example, the controller interface circuit 3110 may generate a read enable signal nRE that is changed from a fixed state (eg, a high level or a low level) to a toggle state before the data DATA is output. have. Accordingly, the data strobe signal DQS toggling based on the read enable signal nRE in the memory device 3200 may be generated. The controller interface circuit 3110 may receive the data signal DQ including the data DATA together with the toggling data strobe signal DQS from the memory device 3200 . The controller interface circuit 3110 may acquire the data DATA from the data signal DQ based on the toggle timing of the data strobe signal DQS.

In a data input operation of the memory device 3200 , the controller interface circuit 3110 may generate a toggle data strobe signal DQS. For example, the controller interface circuit 3110 may generate a data strobe signal DQS that is changed from a fixed state (eg, a high level or a low level) to a toggle state before transmitting the data DATA. . The controller interface circuit 3110 may transmit the data signal DQ including the data DATA to the memory device 3200 based on the toggle timings of the data strobe signal DQS.

The controller interface circuit 3110 may receive the ready/busy output signal nR/B from the memory device 3200 through the eighth pin P28 . The controller interface circuit 3110 may determine state information of the memory device 3200 based on the ready/busy output signal nR/B.

28 is a diagram for explaining a 3D VNAND structure applicable to a UFS device according to an embodiment of the present invention. When the storage module of the UFS device is implemented as a 3D VNAND (Vertical NAND) type flash memory, each of a plurality of memory blocks constituting the storage module may be represented by an equivalent circuit as shown in FIG. 28 . The memory block BLKi illustrated in FIG. 28 represents a three-dimensional memory block formed on a substrate in a three-dimensional structure. For example, a plurality of memory NAND strings included in the memory block BLKi may be formed in a direction perpendicular to the substrate.

Referring to FIG. 28 , the memory block BLKi may include a plurality of memory NAND strings NS11 to NS33 connected between the bit lines BL1 , BL2 , and BL3 and the common source line CSL. Each of the plurality of memory NAND strings NS11 to NS33 may include a string select transistor SST, a plurality of memory cells MC1 , MC2 , ..., MC8 , and a ground select transistor GST. 28 , each of the plurality of memory NAND strings NS11 to NS33 includes eight memory cells MC1 , MC2 , ..., MC8 , but is not limited thereto.

The string select transistor SST may be connected to the corresponding string select lines SSL1 , SSL2 , and SSL3 . The plurality of memory cells MC1 , MC2 , ..., MC8 may be respectively connected to corresponding gate lines GTL1 , GTL2 , ..., GTL8 . The gate lines GTL1, GTL2, ..., GTL8 may correspond to word lines, and some of the gate lines GTL1, GTL2, ..., GTL8 may correspond to dummy word lines. The ground select transistor GST may be connected to the corresponding ground select lines GSL1 , GSL2 , and GSL3 . The string select transistor SST may be connected to the corresponding bit lines BL1 , BL2 , and BL3 , and the ground select transistor GST may be connected to the common source line CSL.

Word lines of the same height (eg, WL1 ) may be commonly connected, and the ground selection lines GSL1 , GSL2 , and GSL3 and the string selection lines SSL1 , SSL2 , and SSL3 may be separated from each other. 28 , the memory block BLK is illustrated as being connected to eight gate lines GTL1, GTL2, ..., GTL8 and three bit lines BL1, BL2, BL3, but is not necessarily limited thereto. no.

29 is a diagram for explaining a B-VNAND structure applicable to a UFS device according to an embodiment of the present invention. When the nonvolatile memory included in the UFS device is implemented as a B-VNAND (Bonding Vertical NAND) type flash memory, the nonvolatile memory may have the structure shown in FIG. 29 .

Referring to FIG. 29 , the memory device 4000 may have a chip to chip (C2C) structure. In the C2C structure, an upper chip including a cell region (CELL) is fabricated on a first wafer, a lower chip including a peripheral circuit region (PERI) is fabricated on a second wafer different from the first wafer, and then the upper chip is fabricated. It may mean connecting the chip and the lower chip to each other by a bonding method. For example, the bonding method may refer to a method of electrically connecting the bonding metal formed in the uppermost metal layer of the upper chip and the bonding metal formed in the uppermost metal layer of the lower chip to each other. For example, when the bonding metal is formed of copper (Cu), the bonding method may be a Cu-Cu bonding method, and the bonding metal may be formed of aluminum or tungsten.

Each of the peripheral circuit area PERI and the cell area CELL of the memory device 4000 may include an external pad bonding area PA, a word line bonding area WLBA, and a bit line bonding area BLBA.

The peripheral circuit region PERI includes a first substrate 4110 , an interlayer insulating layer 4115 , a plurality of circuit elements 4120a , 4120b , and 4120c formed on the first substrate 4110 , and a plurality of circuit elements 4120a . , 4120b, 4120c) The first metal layer (4130a, 4130b, 4130c) connected to each, the second metal layer (4140a, 4140b, 4140c) formed on the first metal layer (4130a, 4130b, 4130c) to be included can In one embodiment, the first metal layers 4130a, 4130b, and 4130c may be formed of tungsten having a relatively high resistance, and the second metal layers 4140a, 4140b, and 4140c may be formed of copper having a relatively low resistance. can

In this specification, only the first metal layers 4130a, 4130b, 4130c and the second metal layers 4140a, 4140b, 4140c are shown and described, but not limited thereto, and the second metal layers 4140a, 4140b, 4140c At least one metal layer may be further formed on the . At least some of the one or more metal layers formed on the second metal layers 4140a, 4140b, and 4140c are formed of aluminum having a lower resistance than copper forming the second metal layers 4140a, 4140b, and 4140c. can be

The interlayer insulating layer 4115 is a first substrate to cover the plurality of circuit elements 4120a, 4120b, and 4120c, the first metal layers 4130a, 4130b, and 4130c, and the second metal layers 4140a, 4140b, and 4140c. It is disposed on the 4110 and may include an insulating material such as silicon oxide, silicon nitride, or the like.

Lower bonding metals 4171b and 4172b may be formed on the second metal layer 4140b of the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 4171b and 4172b of the peripheral circuit area PERI may be electrically connected to the upper bonding metals 4271b and 4272b of the cell area CELL by a bonding method. , the lower bonding metals 4171b and 4172b and the upper bonding metals 4271b and 4272b may be formed of aluminum, copper, tungsten, or the like.

The cell region CELL may provide at least one memory block. The cell region CELL may include a second substrate 4210 and a common source line 4220 . A plurality of word lines 4231-4238; 4230 may be stacked on the second substrate 4210 in a direction perpendicular to the top surface of the second substrate 4210 (Z-axis direction). String select lines and a ground select line may be disposed above and below the word lines 4230 , respectively, and a plurality of word lines 4230 may be disposed between the string select lines and the ground select line.

In the bit line bonding area BLBA, the channel structure CH may extend in a direction perpendicular to the top surface of the second substrate 4210 to pass through the word lines 4230 , the string selection lines, and the ground selection line. have. The channel structure CH may include a data storage layer, a channel layer, and a buried insulating layer, and the channel layer may be electrically connected to the first metal layer 4250c and the second metal layer 4260c. For example, the first metal layer 4250c may be a bit line contact, and the second metal layer 4260c may be a bit line. In an embodiment, the bit line 4260c may extend along a first direction (Y-axis direction) parallel to the top surface of the second substrate 4210 .

In the exemplary embodiment illustrated in FIG. 29 , a region in which the channel structure CH and the bit line 4260c are disposed may be defined as the bit line bonding area BLBA. The bit line 4260c may be electrically connected to the circuit elements 4120c providing the page buffer 4293 in the peripheral circuit area PERI in the bit line bonding area BLBA. For example, the bit line 4260c is connected to the upper bonding metals 4271c and 4272c in the peripheral circuit region PERI, and the upper bonding metals 4271c and 4272c are connected to the circuit elements 4120c of the page buffer 4293. It may be connected to the lower bonding metals 4171c and 4172c to be connected.

In the word line bonding area WLBA, the word lines 4230 may extend in a second direction (X-axis direction) parallel to the top surface of the second substrate 4210 , and include a plurality of cell contact plugs 4241 . -4247; 4240). The word lines 4230 and the cell contact plugs 4240 may be connected to each other through pads provided by at least some of the word lines 4230 extending in different lengths along the second direction. A first metal layer 4250b and a second metal layer 4260b may be sequentially connected to the upper portions of the cell contact plugs 4240 connected to the word lines 4230 . In the word line bonding area WLBA, the cell contact plugs 4240 are connected to a peripheral circuit through upper bonding metals 4271b and 4272b of the cell area CELL and lower bonding metals 4171b and 4172b of the peripheral circuit area PERI. It may be connected to the region PERI.

The cell contact plugs 4240 may be electrically connected to the circuit elements 4120b providing the row decoder 4294 in the peripheral circuit region PERI. In an embodiment, the operating voltages of the circuit elements 4120b providing the row decoder 4294 may be different from the operating voltages of the circuit elements 4120c providing the page buffer 4293 . For example, the operating voltages of the circuit elements 4120c providing the page buffer 4293 may be greater than the operating voltages of the circuit elements 4120b providing the row decoder 4294 .

A common source line contact plug 4280 may be disposed in the external pad bonding area PA. The common source line contact plug 4280 may be formed of a metal, a metal compound, or a conductive material such as polysilicon, and may be electrically connected to the common source line 4220 . A first metal layer 4250a and a second metal layer 4260a may be sequentially stacked on the common source line contact plug 4280 . For example, an area in which the common source line contact plug 4280 , the first metal layer 4250a , and the second metal layer 4260a are disposed may be defined as the external pad bonding area PA.

Meanwhile, input/output pads 4105 and 4205 may be disposed in the external pad bonding area PA. Referring to FIG. 29 , a lower insulating layer 4101 covering the lower surface of the first substrate 4110 may be formed under the first substrate 4110 , and the first input/output pads 4105 on the lower insulating layer 4101 . can be formed. The first input/output pad 4105 is connected to at least one of the plurality of circuit elements 4120a, 4120b, and 4120c disposed in the peripheral circuit region PERI through the first input/output contact plug 4103 , and the lower insulating layer 4101 ) may be separated from the first substrate 4110 by the In addition, a side insulating layer may be disposed between the first input/output contact plug 4103 and the first substrate 4110 to electrically separate the first input/output contact plug 4103 from the first substrate 4110 .

Referring to FIG. 29 , an upper insulating film 4201 covering the upper surface of the second substrate 4210 may be formed on the second substrate 4210 , and second input/output pads 4205 on the upper insulating film 4201 . can be placed. The second input/output pad 4205 may be connected to at least one of the plurality of circuit elements 4120a , 4120b , and 4120c disposed in the peripheral circuit area PERI through the second input/output contact plug 4203 .

In some embodiments, the second substrate 4210 and the common source line 4220 may not be disposed in the region where the second input/output contact plug 4203 is disposed. Also, the second input/output pad 4205 may not overlap the word lines 4230 in the third direction (Z-axis direction). Referring to FIG. 29 , the second input/output contact plug 4203 is separated from the second substrate 4210 in a direction parallel to the top surface of the second substrate 4210 , and an interlayer insulating layer 4215 of the cell region CELL. may be connected to the second input/output pad 4205 through the .

In some embodiments, the first input/output pad 4105 and the second input/output pad 4205 may be selectively formed. For example, the memory device 4000 includes only the first input/output pad 4105 disposed on the first substrate 4110 , or the second input/output pad 4205 disposed on the second substrate 4210 . can contain only Alternatively, the memory device 4000 may include both the first input/output pad 4105 and the second input/output pad 4205 .

In each of the external pad bonding area PA and the bit line bonding area BLBA included in the cell area CELL and the peripheral circuit area PERI, the metal pattern of the uppermost metal layer exists as a dummy pattern, or The uppermost metal layer may be empty.

In the external pad bonding area PA, the memory device 4000 corresponds to the upper metal pattern 4272a formed on the uppermost metal layer of the cell area CELL in the uppermost metal layer of the peripheral circuit area PERI. ), a lower metal pattern 4176a having the same shape as the upper metal pattern 4272a may be formed. The lower metal pattern 4176a formed on the uppermost metal layer of the peripheral circuit region PERI may not be connected to a separate contact in the peripheral circuit region PERI. Similarly, in the outer pad bonding area PA, the lower metal pattern of the peripheral circuit area PERI corresponds to the lower metal pattern formed on the uppermost metal layer of the peripheral circuit area PERI on the upper metal layer of the cell area CELL. An upper metal pattern having the same shape as the above may be formed.

Lower bonding metals 4171b and 4172b may be formed on the second metal layer 4140b of the word line bonding area WLBA. In the word line bonding area WLBA, the lower bonding metals 4171b and 4172b of the peripheral circuit area PERI may be electrically connected to the upper bonding metals 4271b and 4272b of the cell area CELL by a bonding method. .

In addition, in the bit line bonding area BLBA, the lower part of the peripheral circuit area PERI is formed on the uppermost metal layer of the cell area CELL corresponding to the lower metal pattern 4152 formed on the uppermost metal layer of the peripheral circuit area PERI. An upper metal pattern 4292 having the same shape as the metal pattern 4152 may be formed. A contact may not be formed on the upper metal pattern 4292 formed on the uppermost metal layer of the cell region CELL.

Exemplary embodiments have been disclosed in the drawings and specification as described above. Although the embodiments have been described using specific terms in the present specification, these are used only for the purpose of explaining the technical spirit of the present disclosure and are not used to limit the meaning or the scope of the present disclosure described in the claims. . Therefore, it will be understood by those skilled in the art that various modifications and equivalent other embodiments are possible therefrom. Accordingly, the true technical protection scope of the present disclosure should be defined by the technical spirit of the appended claims.

Claims (20)

A method for link startup of a storage device, comprising:
receiving a line-reset signal from a host through a line connected to an input signal pin of the storage device;
comparing the length of the received line-reset signal with a first reference time; and
and performing a link startup operation between the storage device and the host in a high-speed mode or a low-speed mode according to the comparison result. The method of claim 1, wherein performing the link start-up operation comprises:
performing the link start-up operation in the high-speed mode when the length of the line-reset signal is shorter than the first reference time; and
and performing the link startup operation in the low speed mode when the length of the line-reset signal is not shorter than the first reference time. The method of claim 1, wherein the receiving of the line-reset signal comprises:
receiving, from the host, the line-reset signal where the line has a positive differential line voltage;
Comparing the length of the line-reset signal with the first reference time comprises:
and comparing the length of a line-reset period in which the line has the positive differential line voltage to the first reference time. 4. The method of claim 3,
the input signal pin comprises a positive input signal pin configured to receive a positive input signal and a negative input signal pin configured to receive a negative input signal;
the line comprises a positive line connected to the positive input signal pin and a negative line connected to the negative input signal pin;
The receiving of the line-reset signal comprises receiving the line-reset signal, wherein a voltage of the positive line is higher than a voltage of the negative line. 5. The method of claim 4,
Comparing the length of the line-reset signal with the first reference time comprises:
generating a differential line voltage by comparing the voltage of the positive line and the voltage of the negative line;
generating a system clock count value by counting the number of clocks from the system clock; and
and determining the line-reset length based on the differential line voltage and the system clock count value. According to claim 1,
Comparing the length of the line-reset signal with the first reference time comprises:
detecting an output voltage corresponding to the differential line voltage of the line at a first time point using an RC filter having a time constant corresponding to the first reference time; and
and generating a trigger signal based on the sensed output voltage. According to claim 1,
and the first reference time is about 300 μs. According to claim 1,
Before comparing the length of the line-reset signal with the first reference time, the method further comprising: comparing the received length of the line-reset signal with a second reference time that is smaller than the first reference time . The method of claim 8, wherein performing the link startup operation comprises:
performing the link start-up operation in the high-speed mode when the length of the line-reset signal is longer than the second reference time and shorter than the first reference time; and
and performing the link startup operation in the low speed mode when the length of the line-reset signal is not shorter than the first reference time. 9. The method of claim 8,
and the second reference time is about 200 μs. According to claim 1,
The storage device includes an interconnect configured to transmit and receive data to and from the host;
The method is
The method of claim 1, further comprising: setting a physical layer or a link layer of the interconnect unit according to the comparison result. The method of claim 1, wherein the receiving of the line-reset signal comprises:
and the line transitioning from a negative differential line voltage to a positive differential line voltage. 13. The method of claim 12,
The storage device includes an interconnect configured to transmit and receive data to and from the host;
The method is
before comparing the length of the line-reset signal with the first reference time, comparing an active period in which the line has the negative differential line voltage with a third reference time; and
When the activation period is shorter than the third reference time, the method further comprising the step of setting a physical layer or a link layer of the interconnect unit. According to claim 1,
and prior to receiving the line-reset signal, exiting the hibernate state (HIBERN8), which is a power saving state. According to claim 1,
The storage device is a UFS device interconnected with the host through a UFS (Universal Flash Storage) standard. A method for link startup of a storage device, comprising:
determining whether a line-reset signal is received from the host through a line connected to an input signal pin of the storage device;
performing a fast mode link start-up operation between the storage device and the host when the line-reset signal is received from the host; and
and when the line-reset signal is not received from the host, performing a low-speed link startup operation between the storage device and the host. 17. The method of claim 16,
Determining whether the line-reset signal is received comprises:
and determining whether there is a line-reset section in which the line has a positive differential line voltage. A method for link startup of a storage device, comprising:
performing a fast mode link start-up operation between the storage device and the host;
determining whether the fast mode link start-up operation is completed;
determining whether the link-up between the storage device and the host has passed when the high-speed mode link start-up operation is completed; and
and performing a slow mode link start-up operation between the storage device and the host when the link-up is not passed. 19. The method of claim 18,
The step of determining whether the high-speed mode link start-up operation is complete,
and determining whether a threshold time has elapsed from the start time of the fast mode link startup operation. 19. The method of claim 18,
The step of determining whether the link-up has been passed comprises:
and determining whether capability information has been received from the host.

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