KR20210132264A - Operation method of nonvolatile memory device - Google Patents

Abstract

An objective of the present invention is to provide an operating method of a nonvolatile memory device which has improved reliability. According to an embodiment of the present invention, the nonvolatile memory device includes a memory block connected to a plurality of word lines. The operating method of the nonvolatile memory device comprises: a step of using a zeroth erase voltage to perform an erase operation on the memory block; a step of using a zeroth erase verification voltage to perform a block verification operation on the memory block; a step of using a first erase verification voltage different from the zeroth erase verification voltage to perform a delta verification operation on the memory block if a result of the block verification operation is a pass; and a step of outputting information on an erase result for the memory block based on the result of the block verification operation or a result of the delta verification operation. The plurality of word lines can be divided into a plurality of word line groups. The delta verification operation includes a step of using the first erase voltage to generate a plurality of delta counting values corresponding to the plurality of word line groups, a step of generating a delta value based on the plurality of delta counting values, and a step of comparing the delta value and a first reference value.

Description

OPERATION METHOD OF NONVOLATILE MEMORY DEVICE

The present invention relates to a semiconductor memory, and more particularly, to a method of operating a nonvolatile memory device.

Semiconductor memories, such as SRAM, DRAM, etc., are volatile memory devices that lose their stored data when the power supply is cut off, flash memory devices, PRAM, MRAM, RRAM, FRAM, etc. It is classified as a volatile memory device.

Flash memory is widely used as a mass storage medium. The flash memory may erase the memory blocks by using the erase voltage to lower the threshold voltage of the memory cells. Reliability of data programmed in flash memory cells may vary according to an erase state of the flash memory. That is, a means for verifying the erase state of the flash memory is required.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method of operating a nonvolatile memory device having improved reliability.

A nonvolatile memory device according to an embodiment of the present invention may include a memory block connected to a plurality of word lines. The method of operating the nonvolatile memory device may include: performing an erase operation on the memory block using a zeroth erase voltage; performing a block verify operation on the memory block using a zeroth erase verify voltage; performing a delta verify operation on the memory block using a first erase verify voltage different from the zeroth erase verify voltage when a result of the block verify operation is a pass; and outputting information on an erase result of the memory block based on a result of the block verify operation or a result of the delta verify operation. The plurality of word lines may be divided into a plurality of word line groups. The delta verification operation may include generating a plurality of delta counting values respectively corresponding to the plurality of word line groups by using the first erase verification voltage; generating a delta value based on the plurality of delta counting values; and comparing the delta value and the first reference value.

A nonvolatile memory device according to an embodiment of the present invention may include a memory block connected to a plurality of word lines. The method of operating the nonvolatile memory device includes: performing an erase operation on the memory block; performing a block verify operation on the memory block using a zeroth erase verify voltage; performing a partial verification operation on the memory block using a first erase verification voltage when a result of the block verification operation is a pass; performing a delta verification operation on the memory block using a second erase verification voltage different from the zeroth and first erase verification voltages when a result of the partial verification operation is a pass; and outputting information on an erase result of the memory block based on the result of the block verify operation, the result of the partial verify operation, or the result of the delta verify operation. The block verification operation may refer to an operation of generating a block counting value in units of blocks using the 0th erase verification voltage and comparing the block counting value with a first reference value. The partial verification operation may refer to an operation of generating a plurality of partial counting values for each word line group using the first erase verification voltage and comparing each of the plurality of partial counting values with a second reference value. In the delta verification operation, a plurality of delta counting values generated in units of the word line group are generated using the second erase verification voltage, a delta value is generated based on the plurality of delta counting values, and the delta value is It may refer to an operation of comparing with the third reference value.

A nonvolatile memory device according to an embodiment of the present invention may include a memory block connected to a plurality of word lines divided into a plurality of word line groups. The erase verification method of the nonvolatile memory device may include generating a plurality of delta counting values respectively corresponding to the plurality of word line groups by using a first erase verification voltage; generating a delta value based on the plurality of delta counting values; comparing the delta value to a first reference value; and outputting information on an erase result of the memory block based on the comparison result.

According to the present invention, when the memory block is erased, the nonvolatile memory device may detect a soft defect in the memory block based on a difference in fail bits in units of word line groups. Accordingly, a method of operating a nonvolatile memory device having improved reliability is provided.

1 is a block diagram exemplarily showing a storage device according to an embodiment of the present invention.
FIG. 2 is a block diagram exemplarily illustrating the memory controller of FIG. 1 .
FIG. 3 is a block diagram exemplarily illustrating the nonvolatile memory device of FIG. 1 .
FIG. 4A is a circuit diagram exemplarily illustrating one memory block BLK of a plurality of memory blocks included in the memory cell array of FIG. 3 .
FIG. 4B is a diagram for explaining a word line group for the memory block of FIG. 4A.
5 is a flowchart illustrating an erase operation of the nonvolatile memory device of FIG. 3 .
FIG. 6 is a distribution diagram exemplarily illustrating a threshold voltage distribution of memory cells included in the memory block of FIG. 4A .
7 is a flowchart exemplarily illustrating step S110 of FIG. 5 , that is, a block verification operation.
8A to 8C are diagrams for explaining a block verification operation of the flowchart of FIG. 7 .
9 is a flowchart exemplarily illustrating the operation of step S120 of FIG. 5 , that is, a partial verification operation.
10A and 10B are diagrams for explaining the partial verification operation of FIG. 9 .
11 is a block diagram exemplarily illustrating the operation of step S130 of FIG. 5 , that is, the delta verification operation.
12A and 12B are diagrams for explaining a delta verification operation according to the flowchart of FIG. 11 .
13A is a block diagram illustrating an erase delta verification logic circuit of a nonvolatile memory device configured to perform the delta verification operation described with reference to FIGS. 11 to 12C .
13B is a block diagram exemplarily showing the delta operator of FIG. 13A .
14 is a flowchart exemplarily illustrating an operation of the nonvolatile memory device of FIG. 3 .
15 is a flowchart illustrating an operation of the nonvolatile memory device of FIG. 3 .
16 is a flowchart exemplarily illustrating the operation of step S340 of FIG. 15 , that is, the word line verification operation.
17A and 17B are diagrams for explaining a word line verification operation according to the flowchart of FIG. 16 .
18 is a flowchart exemplarily illustrating a word line verification operation in step S340 of FIG. 15 .
19 is a flowchart illustrating an exemplary operation of the nonvolatile memory device of FIG. 3 .
20 and 21 are diagrams for explaining a word line group for a memory block.
22A and 22B are diagrams exemplarily illustrating memory blocks included in the memory cell array of FIG. 3 .
23A and 23B are diagrams for explaining a word line group for the first multi-stack memory block of FIG. 22A.
24 is a flowchart illustrating an exemplary operation of the memory controller of FIG. 2 .
25 is a block diagram exemplarily illustrating a storage device according to an embodiment of the present invention.
26 is a block diagram exemplarily showing a test system according to an embodiment of the present invention.
27 is a block diagram illustrating an SSD system to which a nonvolatile memory device according to the present invention is applied.
28 is a block diagram illustrating an electronic device to which a storage system according to the present invention is applied.

Hereinafter, embodiments of the present invention will be described clearly and in detail to the extent that those skilled in the art can easily practice the present invention.

1 is a block diagram exemplarily showing a storage device according to an embodiment of the present invention. Referring to FIG. 1 , the storage device 100 may include a memory controller 110 and a nonvolatile memory device 120 . The memory controller 110 stores data in the nonvolatile memory device 120 or stores data in the nonvolatile memory device 120 according to a request or control of an external device (eg, an external host device, CPU, AP, etc.) Stored data can be read.

The nonvolatile memory device 120 may store data or provide stored data to the memory controller 110 under the control of the memory controller 110 . In an exemplary embodiment, the nonvolatile memory device 120 may be a NAND flash memory device, but the scope of the present invention is not limited thereto.

The nonvolatile memory device 120 may include a plurality of memory blocks. The nonvolatile memory device 120 may perform an erase operation on the plurality of memory blocks by itself or under the control of the memory controller 110 . For example, the nonvolatile memory device 120 may perform an erase operation on a selected memory block among a plurality of memory blocks. The erase operation may be performed based on an increment step pulse erase (ISPE) method. For example, an erase operation may include a plurality of erase loops. Each of the plurality of erase loops may include an erase step of lowering a threshold voltage distribution of the memory cells of the selected memory block and a verify step of verifying the erase state of the memory cells of the selected memory block. When it is determined that the erase operation of the memory block selected in the verification step is a fail after all of the plurality of erase loops have been performed, the nonvolatile memory device 120 transmits information on the memory block that is an erase fail to the memory controller 110 . ) can be provided. The memory controller 110 may manage the erase-failed memory block as a bad block based on information on the erase-failed memory block.

In an exemplary embodiment, the nonvolatile memory device 120 according to an embodiment of the present invention may include an erase delta verification logic circuit 121 . For example, during an erase operation on the selected memory block, even if it is determined that the verification result by the predetermined erase verification voltage is a pass, a soft defect may occur in a specific word line of the selected memory block. A soft defect for a specific word line may cause an error in data stored in the specific word line. That is, when a soft defect for a specific word line occurs, data reliability may be deteriorated.

The erase delta verification logic circuit 121 may verify a soft defect with respect to a specific word line of the selected memory block by performing delta verification on the selected memory block. When it is determined that a soft defect has occurred for a specific word line, it may be determined that an erase operation for a memory block (ie, a selected memory block) including a specific word line is a fail.

In an exemplary embodiment, the delta verification may refer to a verification operation of verifying a soft defect for a specific word line by comparing a difference in the number of fail bits per word line group for a plurality of word lines of a selected memory block. The configuration of the erase delta verification logic circuit 121 and the operation of the delta verification will be described in more detail with reference to the following drawings.

As described above, the nonvolatile memory device 120 according to an embodiment of the present invention may perform delta verification on the selected memory block during an erase operation on the selected memory block. In this case, even if a soft defect for a specific word line occurs in a memory block determined to be a pass through the conventional erase verification operation, since the soft defect can be verified or detected through the delta verification, the nonvolatile memory device 120 ) can be improved.

FIG. 2 is a block diagram exemplarily illustrating the memory controller of FIG. 1 . 1 and 2 , the memory controller 110 includes a processor 111 , a memory 112 , an error correction code engine (ECC) 113 , a nonvolatile memory manager 114 , and a host. It may include an interface circuit 115 , and a flash interface circuit 116 .

The processor 111 may control overall operations of the memory controller 110 . The memory 112 may be used as an operating memory, a buffer memory, or a system memory of the memory controller 110 . In an exemplary embodiment, the memory 112 may be a volatile memory such as SRAM, DRAM, or the like. The processor 111 may process information stored in the memory 112 or execute various firmware or program codes stored in the memory 112 .

The ECC engine 113 may be configured to detect and correct errors in data read from the nonvolatile memory device 120 . For example, the ECC engine 113 may generate an error correction code for data to be stored in the nonvolatile memory device 120 . The generated error correction code may be stored in the nonvolatile memory device 120 together with the corresponding data. Thereafter, the error correction code and corresponding data may be read from the nonvolatile memory device 120 , and the ECC engine 113 uses the error correction code to generate an error on the data read from the nonvolatile memory device 120 . can be configured to correct In an exemplary embodiment, the ECC engine 113 may have an error correction capability of a predetermined size.

The nonvolatile memory manager 114 may perform various management operations on the nonvolatile memory device 120 . For example, the nonvolatile memory device 114 may perform a mapping table management operation for managing mapping information between a physical address of the nonvolatile memory device 120 and a logical address for stored data, and a bad operation of the nonvolatile memory device 120 . Various maintenance operations are performed, such as a bad block management operation for managing blocks, a wear leveling operation for managing the wear level of the nonvolatile memory device 120 , and a garbage collection operation for securing free memory blocks of the nonvolatile memory device 120 . can do. In an exemplary embodiment, the nonvolatile memory manager 114 may be a flash translation layer (FTL) configured to perform a maintenance operation on the nonvolatile memory device 120 . In an exemplary embodiment, the nonvolatile memory manager 114 may be implemented in the form of software, firmware, hardware, or a combination thereof. The nonvolatile memory manager 114 implemented in the form of software or firmware may be stored in the memory 112 , and the nonvolatile memory manager 114 stored in the memory 112 may be executed by the processor 111 .

The memory controller 110 may communicate with an external host through the host interface circuit 115 . The host interface circuit 115 may be implemented based on a predetermined interface protocol. In an exemplary embodiment, the predetermined interface protocol includes a Peripheral Component Interconnect express (PCI-express) interface, a nonvolatile memory express (NVMe) interface, a Serial ATA (SATA) interface, a Serial Attached SCSI (SAS) interface, and a Universal Flash Storage (UFS) interface. ) may include at least one of various interface conventions such as an interface, but the scope of the present invention is not limited thereto.

The memory controller 110 may communicate with the nonvolatile memory device 120 through the flash interface circuit 116 . In an exemplary embodiment, the flash interface circuit 116 may be implemented based on a NAND interface, a toggle interface, or an ONFI interface. In an exemplary embodiment, the flash interface circuit 116 includes a flash memory controller (FMC) configured to control each of the plurality of nonvolatile memories included in the nonvolatile memory device 122 . can do.

FIG. 3 is a block diagram exemplarily illustrating the nonvolatile memory device of FIG. 1 . 1 and 3 , the nonvolatile memory device 120 includes an erase delta verification logic circuit 121 , a memory cell array 122 , an address decoder 123 , a page buffer 124 , and an input/output circuit 125 . , and a control logic and voltage generation circuit 126 .

The erase delta verification logic circuit 121 may be configured to perform delta verification on a memory block selected for erase. The delta verification operation and configuration of the erase delta verification logic circuit 121 will be described in more detail with reference to the drawings below.

The memory cell array 122 may include a plurality of memory blocks. Each of the plurality of memory blocks may include a plurality of memory cells. The configuration of the memory block will be described in more detail with reference to FIG. 4 .

The address decoder 123 may be connected to the memory cell array 122 through string select lines SSL, word lines WL, and ground select lines GSL. The address decoder 123 decodes the address ADDR received from the memory controller 110 , and based on the decoding result, the string selection lines SSL, the word lines WL, and the ground selection lines GSL. can be controlled.

The page buffer 124 may be connected to the memory cell array 122 through bit lines BL. The page buffer 124 may temporarily store data stored in memory cells of the memory cell array 122 through the bit lines BL. Alternatively, the page buffer 124 may control the levels of the bit lines BL based on data received from the input/output circuit 125 through the data line DL.

The input/output circuit 125 may receive data from the page buffer 124 through the data line DL and transmit the received data to the memory controller 110 . Alternatively, the input/output circuit 125 may transfer data received from the memory controller 110 to the page buffer 124 through the data line DL.

The control logic and voltage generation circuit 126 (hereinafter, referred to as a “control logic circuit”) responds to the command CMD and the control signal CTRL from the memory controller 110 , and the nonvolatile memory device 120 . components can be controlled. The control logic circuit 126 may generate various voltages required for the nonvolatile memory device 120 to operate. For example, the control logic circuit 126 may generate various voltages such as a plurality of program voltages, a plurality of program verify voltages, a plurality of read voltages, a plurality of erase voltages, a plurality of erase verify voltages, and the like. have. Hereinafter, various voltages (eg, an erase voltage or an erase verify voltage, etc.) to be described are generated by the control logic circuit 126 and provided to a corresponding word line through the address decoder 123 , or not. It may serve as a substrate on which the volatile memory device 120 is formed.

FIG. 4A is a circuit diagram exemplarily illustrating one memory block BLK of a plurality of memory blocks included in the memory cell array of FIG. 3 . Although one memory block BLK is described with reference to FIG. 4A , the scope of the present invention is not limited thereto. The plurality of memory blocks included in the memory cell array 121 may have the same or similar structure to the memory block BLK of FIG. 4A . 3 and 4A , the memory block BLK may include a plurality of cell strings CS11, CS12, CS21, and CS22. Each of the plurality of cell strings CS11, CS12, CS21, and CS22 may be arranged in a row direction and a column direction.

Cell strings positioned in the same column among the plurality of cell strings CS11, CS12, CS21, and CS22 may be connected to the same bit line. For example, the cell strings CS11 and CS21 may be connected to the first bit line BL1 , and the cell strings CS12 and CS22 may be connected to the second bit line BL2 . Each of the plurality of cell strings CS11 , CS12 , CS21 , and CS22 may include a plurality of cell transistors. Each of the plurality of cell transistors may be a charge trap flash (CTF) memory cell, but the scope of the present invention is not limited thereto. The plurality of cell transistors may be stacked in a height direction that is perpendicular to a plane (eg, a semiconductor substrate (not shown)) formed by the row direction and the column direction.

The plurality of cell transistors may be connected in series between a corresponding bit line (eg, BL1 or BL2 ) and a common source line CSL. For example, the plurality of cell transistors may include string select transistors SSTb and SSTa, dummy memory cells DMC1 and DMC2, memory cells MC1 to MC8, and ground select transistors GSTa and GSTb. have. The series-connected string select transistors SSTb and SSTa may be provided or connected between the series-connected memory cells MC1 to MC8 and a corresponding bit line (eg, BL1 or BL2). The series-connected ground select transistors GSTa and GSTb may be provided or connected between the series-connected memory cells MC1 to MC8 and the common source line CSL. In an exemplary embodiment, a second dummy memory cell DMC2 may be provided between the series-connected string select transistors SSTb and SSTa and the series-connected memory cells MC1 to MC8, and the series-connected memory cells MC1 to MC1 to A first dummy memory cell DMC1 may be provided between MC8 and the series-connected ground select transistors GSTb and GSTa.

Memory cells located at the same height among the memory cells MC1 to MC8 of each of the plurality of cell strings CS11, CS12, CS21, and CS22 may share the same word line. For example, the first memory cells MC1 of each of the plurality of cell strings CS11, CS12, CS21, and CS22 may be positioned at the same height from the substrate (not shown) and connect the first word line WL1 to each other. can share The second memory cells MC2 of each of the plurality of cell strings CS11, CS12, CS21, and CS22 may be positioned at the same height from the substrate (not shown) and may share the second word line WL2. . Similarly, each of the third to eighth memory cells MC3 to MC8 of each of the plurality of cell strings CS11, CS12, CS21, and CS22 may be positioned at the same height from the substrate (not shown), and the third to third memory cells MC3 to MC8 may be positioned at the same height from the substrate (not shown). Eight word lines WL3 to WL8 may be shared, respectively.

Among the dummy memory cells DMC1 and DMC2 of each of the plurality of cell strings CS11, CS12, CS21, and CS22, the dummy memory cells located at the same height may share the same dummy word line. For example, the first dummy memory cells DMC1 of each of the plurality of cell strings CS11, CS12, CS21, and CS22 may share the first dummy word line DWL1, and the plurality of cell strings CS11 The second dummy memory cells DMC2 of each of , CS12 , CS21 , and CS22 may share a second dummy word line DWL2 .

Among the string select transistors SSTa and SSTb of each of the cell strings CS11, CS12, CS21, and CS22, string select transistors located in the same row and the same height may be connected to the same string select line. For example, the string select transistors SSTb of the cell strings CS11 and CS12 may be connected to the string select line SSL1b, and the string select transistors SSTa of the cell strings CS11 and CS12 may be It may be connected to the selection line SSL1a. The string select transistors SSTb of the cell strings CS21 and CS22 may be connected to the string select line SSL2b, and the string select transistors SSTa of the cell strings CS21 and CS22 are connected to the string select line SSL2a. ) can be associated with

Although not shown in the drawing, the string select transistors located in the same row among the string select transistors SSTb and SSTa of each of the plurality of cell strings CS11, CS12, CS21, and CS22 may share the same string select line. have. For example, the string select transistors SSTb and SSTa of the cell strings CS11 and CS12 may share a first string select line, and the string select transistors SSTb, SSTa) may share a second string selection line different from the first string selection line.

Among the ground selection transistors GSTb and GSTa of each of the cell strings CS11, CS12, CS21, and CS22, the ground selection transistors located in the same row and the same height may be connected to the same ground selection line. For example, the ground select transistors GSTb of the cell strings CS11 and CS12 may be connected to the ground select line GSL1b, and the ground select transistors GSLa of the cell strings CS11 and CS12 may be grounded. It may be connected to the selection line GST1a. The ground selection transistors GSTb of the cell strings CS21 and CS22 may be connected to the ground selection line GSL2b, and the ground selection transistors GSLa of the cell strings CS21 and CS22 may be connected to the ground selection line GST2a. ) can be associated with

Although not shown in the drawings, the ground selection transistors GST1b and GST1a of each of the plurality of cell strings CS11, CS12, CS21, and CS22 may share the same ground selection line with each other. Alternatively, the ground selection transistors of the same height among the ground selection transistors GSTb and GSTa of each of the plurality of cell strings CS11, CS12, CS21, and CS22 may share the same ground selection line. Alternatively, the ground selection transistors located in the same row among the ground selection transistors GSTb and GSTa of each of the plurality of cell strings CS11, CS12, CS21, and CS22 may share the same ground selection line.

In an exemplary embodiment, although not shown in the drawings, each of the plurality of cell strings CS11 , CS12 , CS21 , and CS22 of the memory block BLK may further include an erase control transistor ECT. The erase control transistor ECT of each of the plurality of cell strings CS11, CS12, CS21, and CS22 may be positioned at the same height from the substrate and may be connected to the same erase control line ECL. have. For example, the erase control transistor ECT may be positioned between the common source line CSL and the ground selection transistor GSTa in each of the plurality of cell strings CS11 , CS12 , CS21 , and CS22 . Alternatively, the erase control transistor ECT may be positioned between the bit lines BL1 and BL2 and the string select transistors SSTb. However, the scope of the present invention is not limited thereto.

In an exemplary embodiment, the memory block BLK illustrated in FIG. 4A is exemplary, and the number of cell strings may be increased or decreased, and the number of rows and columns constituting the cell string may vary according to the number of cell strings. may be increased or decreased. Also, the number of cell transistors GST, MC, DMC, SST, etc. of the memory block BLK may be increased or decreased, respectively, and the height of the memory block BLK may increase or decrease according to the number of cell transistors. can do. Also, the number of lines (GSL, WL, DWL, SSL, etc.) connected to the cell transistors may be increased or decreased according to the number of cell transistors.

FIG. 4B is a diagram for explaining a word line group for the memory block of FIG. 4A. Hereinafter, in order to easily describe the technical idea of the present invention, the term “wordline group” is used. One word line group may include at least two word lines connected to a plurality of memory blocks.

For example, referring to FIG. 4B , the memory block BLK may include first to eighth word lines WL1 to WL8. The first to eighth word lines WL1 to WL8 may be divided into first to fourth word line groups WG1 to WG4 . For example, the first word line group WG1 may include first and fifth word lines WL1 and WL5 , and the second word line group WG2 includes second and sixth word lines ( WG2 ). may include WL2 and WL6 , the third word line group WG3 may include third and seventh word lines WL3 and WL7 , and the fourth word line group WG4 may include fourth and seventh word lines WL3 and WL7 . It may include eighth word lines WL4 and WL8. In a partial verification operation or a delta verification operation to be described below, the first to eighth word lines WL1 to WL8 may be controlled in units of word line groups.

5 is a flowchart illustrating an erase operation of the nonvolatile memory device of FIG. 3 . For convenience of description, it is assumed that the nonvolatile memory device 120 performs an erase operation on one memory block (hereinafter, referred to as a selected memory block). However, the scope of the present invention is not limited thereto, and the nonvolatile memory device 120 may perform an erase operation in various units such as a word line unit, a sub-block unit, a memory block unit, and a super block unit.

Hereinafter, it is assumed that the memory block selected for erasing is the memory block BLK described with reference to FIGS. 4A and 4B . For example, the selected memory block BLK may include or be connected to the first to eighth word lines WL1 to WL8. The first to eighth word lines WL1 to WL8 may be divided into first to fourth word line groups WG1 to WG4 as described with reference to FIG. 4B .

Hereinafter, for the sake of brevity and convenience of description, the erase operation of step S100, the block verification operation (BV) of step S110, the partial verification operation (PV) of step S120, and the delta verification operation (DV) of step S130 are performed. Although separated into separate operations, the scope of the present invention is not limited thereto. For example, erasing of the selected memory block may be performed based on an incremental step pulse erase (ISPE) method. One erase according to the ISPE method may include a plurality of erase loops. Each of the plurality of erase loops may include an erase operation and a verify operation. In this case, the erase operation may include the erase operation of step S100, and the verification operation includes the block verification operation (BV) of step S110, the partial verification operation (PV) of step S120, or the delta verification operation (DV) of step S130. may include That is, when the verification result of step S110 , S120 , or S130 is FAIL, the nonvolatile memory device 120 may perform the erase operation of step S100 again for a predetermined number of erase loops.

Hereinafter, for convenience of explanation, the fact that the verification result of step S110, S120, or S130 is FAIL means that the final verification result is FAIL after a predetermined number of erase loops are all performed. can mean That is, hereinafter, when the verification result of step S110, step S120, or step S130 is FAIL, it is assumed that the erase operation of step S100 is not performed again. However, the scope of the present invention is not limited thereto, and as described above, the erase operation in step S100 may be re-performed for a predetermined number of erase loops. As the erase loop progresses, the level of the erase voltage used in the erase operation may increase in stages. It will be understood that the above contents are merely for easily explaining the technical spirit of the present invention, and the scope of the present invention is not limited thereto.

3 to 5 , in step S100 , the nonvolatile memory device 120 may perform an erase operation on the selected memory block BLK. For example, the nonvolatile memory device 120 may perform an erase operation on the selected memory block BLK by applying an erase voltage to the substrate (not shown). In an exemplary embodiment, the nonvolatile memory device 120 may perform the erase operation of step S100 in response to a program command for the selected memory block from the memory controller 110 . Alternatively, the nonvolatile memory device 120 may perform the erase operation of step S100 in response to an erase command (eg, a trim command, a sanitize command, etc.) from the memory controller 110 .

In operation S110 , the nonvolatile memory device 120 may perform a block verification operation (BV). For example, the nonvolatile memory device 120 applies the zeroth erase verification voltage EV0 to the word lines connected to the selected memory block to determine the threshold voltage distribution or erase state of the memory cells included in the selected memory blocks. can be verified. The block verify operation (BV) is described in more detail with reference to FIGS. 7-8C .

When the result of the block verify operation BV is FAIL, in step S142 , the nonvolatile memory device 120 may determine that the erase of the selected memory block is FAIL.

When the result of the block verification operation BV is PASS, in step S120 , the nonvolatile memory device 120 may perform a partial verification operation (PV). For example, the nonvolatile memory device 120 counts the number of fail bits for each of the plurality of word line groups using the zeroth erase verification voltage EV0, and sets each of the counted number of fail bits as a reference value. can be compared with The partial verification operation PV is described in more detail with reference to FIGS. 9 to 10B .

When the result of the partial verification operation PV is FAIL, in operation S142 , the nonvolatile memory device 120 may determine that the erase of the selected memory block is FAIL.

When the result of the partial verification operation PV is PASS, in step S130 , the nonvolatile memory device 120 may perform a delta verification operation (DV). For example, the nonvolatile memory device 120 may count the number of fail bits for each of the plurality of word line groups using the first erase verification voltage EV1 . The nonvolatile memory device 120 may determine whether to pass or fail based on a difference or distribution of the counted number of fail bits. In an exemplary embodiment, the level of the first erase verify voltage EV1 used in the delta verify operation DV is the zeroth erase verify voltage EV0 used in the block verify operation BV or the partial verify operation PV. may be lower. In an exemplary embodiment, it may be determined whether a word line having a soft defect is included in the selected memory block through the delta verification operation DV. The delta verify operation (DV) is described in more detail with reference to FIGS. 11-13B .

When the result of the delta verification operation DV is FAIL, in step S142 , the nonvolatile memory device 120 may determine that the erase of the selected memory block is FAIL.

When the result of the delta verification operation (DV) is PASS (that is, when the results of the block verify operation (BV), the partial verification operation (PV), and the delta verification operation (DV) are all PASS) , S141 , the nonvolatile memory device 120 may determine that the erase of the selected memory block is PASS.

In an exemplary embodiment, the nonvolatile memory device 120 may provide information on an erase result (ie, pass or fail) of the selected memory block to the memory controller 110 . Alternatively, when an erase result of the selected memory block is a pass, the nonvolatile memory device 120 may perform an additional subsequent operation (eg, a program operation on the erase-passed memory block).

As described above, the nonvolatile memory device 120 according to an embodiment of the present invention detects whether a word line having a soft defect is included in the selected memory block by performing a delta verification operation (DV) on the selected memory block. can do. Accordingly, the reliability of the nonvolatile memory device 120 may be improved.

The block verify operation BV, the partial verify operation PV, and the delta verify operation DV of the nonvolatile memory device 120 will be described in more detail with reference to the drawings below.

FIG. 6 is a distribution diagram exemplarily illustrating a threshold voltage distribution of memory cells included in the memory block of FIG. 4A . In the scatter plots of FIG. 6 , horizontal axes indicate threshold voltages of memory cells, and vertical axes indicate the number of memory cells. Referring to FIG. 6 , step S100 of FIG. 5 , that is, an erase operation will be described. For convenience of description, it is assumed that the memory block BLK is a selected memory block, and each of the memory cells included in the memory block BLK is a triple level cell (TLC) configured to store 3-bits per cell. However, the scope of the present invention is not limited thereto, and each of the memory cells may be a multi-level memory cell configured to store at least two or more bits per cell.

4A and 6 , the memory cells of the memory block BLK may each have an erase state E and a corresponding one of the first to seventh program states P1 to P7 . During an erase operation on the memory block BLK, the memory cells of the memory block BLK may be erased to have a threshold voltage distribution of the erase state E. For example, the nonvolatile memory device 120 applies an erase voltage to the substrate on which the memory block BLK is located, and applies a word line erase voltage (eg, 0V) to the word lines connected to the memory block BLK. By applying the application, an erase operation may be performed on the memory block BLK. However, the scope of the present invention is not limited thereto, and the erase operation may be performed through various methods.

In an exemplary embodiment, the upper limit of the threshold voltage distribution of the erase state E may be lower than the zeroth erase verification voltage EV0. In an exemplary embodiment, the zeroth erase verification voltage EV0 may be a predetermined level based on physical characteristics, end of life (EOL) characteristics, and the like of the nonvolatile memory device 120 . The zeroth erase verification voltage EV0 will be described in more detail with reference to FIG. 8A .

7 is a flowchart exemplarily illustrating step S110 of FIG. 5 , that is, a block verification operation. 3 to 7 , the block verification operation BV of step S110 may include the operations of steps S111 through S113.

In operation S111 , the nonvolatile memory device 120 may apply the zeroth erase verification voltage EV0 to the word lines WL1 to WL8 of the selected memory block BLK.

In step S112 , the nonvolatile memory device 120 counts fail bits from the selected memory block BLK, and a fail bit counting value for the memory block (hereinafter, for brevity, referred to as a “block counting value”). ) (CV_B) can be created. For example, as shown in FIG. 6 , when the memory cells of the memory block BLK are normally erased (ie, when the memory cells have the erase state E), the threshold voltages of the memory cells are zeroth erased. It will be lower than the verify voltage EV0.

On the other hand, when the memory cells of the memory block BLK are not normally erased (ie, the memory cells do not have the erase state E, or have a threshold voltage higher than the threshold voltage distribution of the erase state E, Alternatively, when the threshold voltage is higher than the zeroth erase verification voltage EV0), the threshold voltages of specific memory cells may be higher than the zeroth erase verification voltage EV0. In this case, memory cells having threshold voltages higher than the zeroth erase voltage EV0 may not be turned on by the zeroth erase voltage EV0. In this case, the nonvolatile memory device 120 sets the number of fail bits for the memory block BLK based on the number of non-turned-on memory cells (or the number of bit lines corresponding to the non-turned-on memory cells). A block counting value (CV_B) may be generated by counting .

In operation S113 , the nonvolatile memory device 120 may compare the block counting value CV_B with the first reference value REF1 . In an exemplary embodiment, the first reference value REF1 may be a value corresponding to the error correction capability of the ECC engine 113 described with reference to FIG. 2 . Alternatively, the first reference value REF1 may be a value corresponding to the number of recoverable errors through a separate error correction operation or a data restoration operation.

That is, if the block counting value CV_B is greater than or equal to the first reference value REF1, more errors than the first reference value REF1 may occur in data stored in the memory block BLK or data to be programmed later. means That is, when the block counting value CV_B is greater than or equal to the first reference value REF1 , it may be determined that the result of the block verify operation BV on the memory block BLK is fail. In this case, the nonvolatile memory device 120 performs the operation of step S142.

The fact that the block counting value CV_B is smaller than the first reference value REF1 means that the probability of generating more errors than the first reference value REF1 in data stored in the memory block BLK or data to be programmed thereafter is low. do. That is, when the block counting value CV_B is less than the first reference value REF1 , the result of the block verify operation on the memory block BLK may be determined to be a pass. In this case, the nonvolatile memory device 120 may perform the operation of step S120 .

8A to 8C are diagrams for explaining a block verification operation of the flowchart of FIG. 7 . For brevity of the drawing, scatter diagrams for the erase state E of the memory cells of the memory block BLK are shown. For convenience of description, reference signs of “” are used. “X_B” means that a component corresponding to the reference symbol X corresponds to a memory block. For example, a reference symbol of “ ” may indicate an erase state E of memory cells included in the memory block BLK. However, these descriptions are merely examples for explaining the configuration of the present invention, and the scope of the present invention is not limited thereto.

First, referring to FIG. 8A , as the lifetime of the nonvolatile memory device 120 elapses (eg, the number of program and erase cycles increases), the threshold voltage distribution corresponding to the erase state of the memory block BLK may change. can For example, memory cells of the memory block BLK in an initial state may have a block erase state E_B0', and memory cells of the memory block BLK in an end of life (EOL) state may have a block erase state E_B0. ') can have. The width of the threshold voltage distribution of E_B0 may be ΔV_B0, and the width of the threshold voltage distribution of E_B0' may be ΔV_B0'. In this case, ΔV_B0' may be wider than ΔV_B0. That is, as the lifespan of the nonvolatile memory device 120 elapses, the threshold voltage distribution of the memory cells may spread widely.

In an exemplary embodiment, the zeroth erase verification voltage EV0 used in the block verify operation BV may be determined in consideration of the EOL state of the nonvolatile memory device 120 . For example, as shown in FIG. 8A , the zeroth erase verification voltage EV0 may be determined based on the upper limit value of the threshold voltage distribution of the block erase state E_B0' of the memory block BLK in the EOL state. .

This may be to prevent the memory block BLK in the EOL state from being determined as a bad block. For example, when the erase verify voltage is determined based on the block erase state E_B0 of the memory block in the initial state, the block verify operation for the memory block in the EOL state will fail. That is, even though the memory block in the EOL state can be used as a normal block, the erase verification voltage is determined based on the block erase state E_B0 of the memory block in the initial state, so that the memory block in the EOL state can be managed as a bad block. can In this case, the utility or lifespan of the nonvolatile memory device 120 may be shortened. Accordingly, the zeroth erase verification voltage EV0 is determined in consideration of the EOL state of the nonvolatile memory device 120 , so that the utility or lifespan of the nonvolatile memory device 120 may be maintained or improved.

Next, referring to FIG. 8B , during block verification of the memory block BLK, the zeroth erase verification voltage EV0 may be applied to the plurality of word lines WL1 to WL8 connected to the memory block BLK. have. In this case, as described above, when the threshold voltage of the specific memory cell is higher than the zeroth erase verification voltage EV0, the specific memory cell is turned off. When the threshold voltage of the specific memory cell is higher than the zeroth erase verification voltage EV0, it may mean that a fail bit occurs or is highly likely to occur from the specific memory cell. The nonvolatile memory device 120 may generate a block counting value CV_B by counting the number of turned-off specific memory cells or the number of bit lines corresponding to the turned-off specific memory cells.

Next, referring to FIG. 8C , block erase states E_B1 to E_B3 of the first to third memory blocks BLK1 to BLK3 are illustrated. Memory cells of the first memory block BLK1 may have a first block erase state E_B1 . In this case, the width of the threshold voltage distribution of the first block erase state E_B1 may be ΔV_B1 , and the upper limit value may be lower than the zeroth erase verification voltage EV0 . That is, in the block verify operation BV for the first memory block BLK1 , the fail bit for the first memory block BLK1 may not be counted. In this case, the block for the first memory block BLK1 A result of the verify operation BV may be determined to be a pass.

Memory cells of the second memory block BLK2 may have a second block erase state E_B2 . In this case, the width of the threshold voltage distribution of the second block erase state E_B2 may be ΔV_B2 , and the upper limit value may be higher than the zeroth erase verification voltage EV0 . In the block verify operation BV for the second memory block BLK2 , the number of fail bits for the second memory block BLK2 may be the second block counting value CV_B2 . In an exemplary embodiment, the second block counting value CV2 may correspond to the number of memory cells having a threshold voltage higher than the zeroth erase verification voltage EV0 among the memory cells of the second memory block BLK2 . The second block counting value CV_B2 may be smaller than the first reference value REF1 . This may mean that errors occurring in the memory cells of the second memory block BLK2 may be corrected through the ECC engine 123 or other error correction operation. In this case, the result of the block verify operation BV on the second memory block BLK2 may be determined to be a pass.

Memory cells of the third memory block BLK3 may have a third block erase state E_B3 . In this case, the width of the threshold voltage distribution of the third block erase state E_B3 may be ΔV_B3 , and the upper limit value may be higher than the zeroth erase verification voltage EV0 . In the block verify operation BV for the third memory block BLK3 , the number of fail bits for the third memory block BLK3 may be the third block counting value CV_B3 . In this case, the third block counting value CV_B3 may be greater than the first reference value REF1 . This may mean that errors occurring in the memory cells of the third memory block BLK3 cannot be corrected through the ECC engine 123 or other error correction operations. In this case, the result of the block verify operation BV for the third memory block BLK3 may be determined to be a fail.

As described above, the nonvolatile memory device 120 performs an erase operation on the selected memory block BLK (ie, an operation for lowering threshold voltages of memory cells of the selected memory block BLK), and then the selected memory A block verify operation BV may be performed on the block BLK. When the result of the block verify operation BV is FAIL, it is determined that the erase of the selected memory block BLK is a failure, or the selected memory block BLK is managed as a bad block by the memory controller 110 . can be

When the result of the block verify operation BV is PASS, the nonvolatile memory device 120 may perform the partial verification operation PV described below with reference to FIGS. 9 to 10B .

9 is a flowchart exemplarily illustrating the operation of step S120 of FIG. 5 , that is, a partial verification operation. 10A and 10B are diagrams for explaining the partial verification operation of FIG. 9 . 5 and 9 to 10B , when the result of the block verification operation BV of step S110 is PASS, the partial verification operation PV of step S120 may be performed. The partial verification operation PV of step S120 may include the operations of steps S121 to S126.

In step S121 , the variable k may be set to 1. In an exemplary embodiment, the variable k is used to describe the repetition of fail bit counting for a wordline group, and does not limit the scope of the present invention.

In operation S122 , the nonvolatile memory device 120 applies a 0 th erase verification voltage EV0 to the word lines of the k th word line group among the word line groups of the selected memory block BLK, and the remaining word line groups. The pass voltage VPASS may be applied to the word lines. In step S123 , the nonvolatile memory device 120 counts the number of fail bits, and a fail bit counting value for the kth word line group (hereinafter, referred to as a kth partial counting value for convenience of description). (CV_Pk) can be created.

For example, as shown in FIG. 10A , the nonvolatile memory device 120 applies the zeroth erase verification voltage EV0 to the word lines (ie, WL1 and WL5) of the first word line group WG1. The pass voltage VPASS may be applied to the word lines WL2, WL3, WL4, WL6, WL7, and WL8 of the remaining word line groups WG2, WG3, and WG4.

The pass voltage VPASS may be a high voltage capable of turning on the memory cells regardless of their state (ie, an erase state or a program state). That is, the memory cells connected to the word lines WL2, WL3, WL4, WL6, WL7, and WL8 of the remaining word line groups WG2, WG3, and WG4 may be turned on by the pass voltage VPASS. On the other hand, among the memory cells connected to the word lines (ie, WL1 and WL5) of the first word line group WG1 , the memory cells having a threshold voltage higher than the zeroth erase verification voltage EV0 are turned off. The nonvolatile memory device 120 has turned-off memory cells among memory cells connected to the word lines (ie, WL1 and WL5) of the first word line group WG1 or a bit line corresponding to the turned-off memory cells. A first partial counting value CV_P1 may be generated based on .

That is, the kth partial counting value CV_Pk is the number of memory cells having a higher threshold voltage than the 0th erase verification voltage EV0 or the 0th erase verification voltage among the memory cells connected to the wordlines of the kth word line group. It may correspond to the number of bit lines associated with memory cells having a threshold voltage higher than (EV0).

Hereinafter, for convenience of explanation, it will be described that the erase verification voltage used in the partial verification operation PV is the zeroth erase verification voltage EV0 (ie, the erase verification voltage used in the block verification operation BV). , the scope of the present invention is not limited thereto. For example, the erase verify voltage used in the partial verify operation PV may be equal to or less than the zeroth erase verify voltage EV0.

In operation S124 , the nonvolatile memory device 120 may compare the kth partial counting value CV_Pk with the second reference value REF2 . In an exemplary embodiment, the second reference value REF2 may be smaller than the first reference value REF1 used in the block verify operation BV described with reference to FIG. 7 . In an exemplary embodiment, the second reference value REF2 may be a value corresponding to an error correction command of the ECC engine 123 or another error correction operation.

That is, when the k-th partial counting value CV_Pk is greater than or equal to the second reference value REF2, an error with respect to data read from memory cells connected to the word lines of the k-th word line group occurs in the ECC engine 123 . Or it may mean that it may not be cured by other error correction operations. In this case, it is determined that the result of the partial verification operation PV is FAIL, and the nonvolatile memory device 120 may perform the operation S142 .

On the other hand, when the k-th partial counting value CV_Pk is smaller than the second reference value REF2, an error does not occur with respect to data read from memory cells connected to the word lines of the k word line group or occurs This may mean that the error may not be corrected by the ECC engine 123 or other error correction operations. In this case, the nonvolatile memory device 120 may perform the operation of step S125.

In step S125, it is determined whether the variable k is the maximum. If the variable k is not the maximum, in step S126, the variable k is increased by one. Thereafter, the nonvolatile memory device 120 may perform the operation of step S122 . The nonvolatile memory device 120 may repeatedly perform a partial verification operation PV on each of all word line groups of the selected memory block BLK. When the results of the partial verification operation PV for each of all word line groups are all PASS (ie, Yes in step S125), the partial verification operation PV for the selected memory block BLK is determined to be PASS, and the nonvolatile memory device 120 may perform the operation of step S130 .

As a more detailed example, as shown in FIG. 10B , the memory cells of the second memory block BLK2 may have a second block erase state E_B2 , and the second memory cells generated through the block verify operation BV may be in the second block erase state E_B2 . The block counting value CV_B2 may be smaller than the first reference value REF1. That is, the second memory block BLK2 may be a memory block passed in the block verify operation BV.

As described above, the nonvolatile memory device 120 may perform the partial verification operation PV on the second memory block BLK2 passed in the block verification operation BV. For example, memory cells corresponding to the first word line group WG1 of the second memory block BLK2 may have a first group erase state E_G1 and corresponding to the second word line group WG2 . The memory cells may have a second group erase state E_G2 , memory cells corresponding to the third word line group WG3 may have a third group erase state E_G3 , and the fourth word line group WG4 may have a third group erase state E_G3 . ) may have a fourth group erase state E_G4. Widths of threshold voltage distributions in each of the first to fourth group erase states E_G1 to E_G4 may be ΔV_G1, ΔV_G2, ΔV_G3, and ΔV_G14.

The nonvolatile memory device 120 counts the fail bits of the first word line group WG1 of the second memory block BLK2 using the zeroth erase verification voltage EV0 to obtain a first partial counting value ( CV_P1 may be generated, and a third partial counting value CV_P3 may be generated by counting the fail bit in the third word line group WG3 . Since the upper limit value of the threshold voltage distribution of the second and fourth group erase states E_G2 and E_G4 is lower than the zeroth erase verification voltage EV0, the second and fourth word line groups WG2 and WG4 are Fail bits may not be counted.

In this case, the first partial counting value CV_P1 may be smaller than the second reference value REF2. That is, among the memory cells corresponding to the first word line group WG1 , there is a fail memory cell having a threshold voltage higher than the zeroth erase verification voltage EV0 , but an error due to the fail memory cell is caused by the ECC engine 123 or another error. It can be cured by corrective action. On the other hand, the third partial counting value CV_P3 may be greater than the second reference value REF2 . That is, an error caused by a fail memory cell having a threshold voltage higher than the zeroth erase verification voltage EV0 among the memory cells corresponding to the first word line group WG1 is not cured by the ECC engine 123 or other error correction operation. can The nonvolatile memory device 120 detects that a hard defect has occurred in the third word line group WG3 in response to the third partial counting value CV_P3 being greater than the second reference value REF2 . can do. The nonvolatile memory device 120 may determine the partial verification operation PV of the memory block (ie, BLK2 ) including the word line group in which the hard defect has occurred as a FAIL.

In an exemplary embodiment, the number of failed bits detected based on the zeroth erase verification voltage EV0 is a reference value (eg, REF1 ) for a hard defect for a memory block, a word line group, or a word line. , REF2, etc.). That is, when a hard defect occurs in a specific memory block, a specific word line group, or a specific word line, an error may occur in data stored in a specific memory block, a specific word line group, or a specific word line, and the generated error is It may not be corrected by the error correction means. As described above, the nonvolatile memory device 120 detects a hard defect for a memory block or a specific word line group through a block verify operation (BV) or a partial verify operation (PV), and based on the detected hard defect Erasing the corresponding memory block may be determined as FAIL.

When it is determined that the result of the partial verification operation PV is PASS, the nonvolatile memory device 120 may perform the delta verification operation DV described with reference to FIGS. 11 to 13B below.

11 is a block diagram exemplarily illustrating the operation of step S130 of FIG. 5 , that is, the delta verification operation. 12A and 12B are diagrams for explaining a delta verification operation according to the flowchart of FIG. 11 . 5 and 11 to 12C , when the partial verification operation PV of step S120 is PASS, the nonvolatile memory device 120 may perform the delta verification operation DV of step S130. have. The delta verification operation DV of step S130 may include the operations of steps S131 to S137.

In step S131, the variable k is set to 1. The variable k is used to describe the iteration for fail bit counting for a group of word lines, and does not limit the scope of the present invention.

In operation S132 , the nonvolatile memory device 120 applies the first erase verification voltage EV1 to the word lines of the k-th word line group among the word line groups of the selected memory block BLK, and the remaining word line groups. The pass voltage VPASS may be applied to the word lines. In step S133, the nonvolatile memory device 120 counts the number of fail bits, and a fail bit counting value for the kth word line group (hereinafter, referred to as a kth delta counting value for convenience of description). (CV_Dk) can be created.

In an exemplary embodiment, the operations of steps S132 and S133 of the delta verification operation DV are compared with steps S122 and S123 of the partial verification operation PV described with reference to FIGS. 9 to 10B , and the erase verification voltage Except for this difference, since other operating methods are similar, a description thereof will be omitted. In an exemplary embodiment, the first erase verification voltage EV1 used in the delta verification operation DV may be lower than the zeroth erase verification voltage EV0 used in the partial verification operation PV.

In step S134, it is determined whether the variable k is maximum. If the variable k is not the maximum, in step S135, the variable k is increased by one. Thereafter, the nonvolatile memory device 120 performs step S132. That is, the nonvolatile memory device 120 may generate a delta counting value for each of the word line groups of the selected memory block BLK by using the first erase verification voltage EV1 .

When the determination result of step S134 indicates that the variable k is the maximum, in step S136 , the nonvolatile memory device 120 may generate a delta value DLT based on the generated delta counting values CV_Ds. For example, the delta value DLT may indicate a difference, distribution, or variance between the generated delta counting values CV_Ds. Alternatively, the delta value DLT may indicate a difference between a maximum value and a minimum value among the generated delta counting values CV_Ds. Alternatively, the delta value DLT may indicate a difference between a maximum value and an intermediate value among the generated delta counting values CV_Ds. The delta value DLT may indicate a difference between a maximum value and an average value among the generated delta counting values CV_Ds. However, the scope of the present invention is not limited thereto.

In operation S137 , the nonvolatile memory device 120 may compare the delta value DLT with the third reference value REF3 . When the delta value DLT is greater than or equal to the third reference value REF3 , the nonvolatile memory device 120 may perform the operation S142 . That is, when the delta value DLT is greater than or equal to the third reference value REF3 , the nonvolatile memory device 120 may determine to erase the selected memory block BLK as FAIL.

When the delta value DLT is less than the third reference value REF3 , the nonvolatile memory device 120 may perform the operation S141 . That is, when the delta value DLT is smaller than the third reference value REF3 , the nonvolatile memory device 120 may determine the erase of the selected memory block BLK as a pass.

For example, as shown in FIG. 12A , the memory cells of the first memory block BLK1 may have a first block erase state E_B1 . In this case, the width of the threshold voltage distribution of the first block erase state E_B1 may be ΔV_B1 , and the upper limit value of the threshold voltage coral may be lower than the zeroth erase verification voltage EV0 . That is, the result of the block verify operation BV on the first memory block BLK may be a PASS.

Since the result of the block verify operation BV for the first memory block BLK1 is a pass, as described above, the partial verification operation PV for the first memory block BLK1 may be performed. . At this time, as shown in FIG. 12A , the first to fourth word line groups WG1 to WG4 of the first memory block BLK1 may set the first to fourth group erase states E_G1 to E_G4 respectively. can have As illustrated in FIG. 12A , upper limit values of threshold voltage distributions of the first to fourth group erase states E_G1 to E_G4 are all lower than the zeroth erase verification voltage EV0, so that the first memory block BLK1 A result of the partial verification operation PV for ? may be a PASS.

In this case, the widths of the threshold voltage distributions of the first to fourth group erase states E_G1 to E_G4 may be ΔV_G1, ΔV_G2, ΔV_G3, and ΔV_G4. As shown in FIG. 12A , the width of ΔV_G3 may be relatively wider than the other widths ΔV_G1 , ΔV_G2 , and ΔV_G4 . In this case, a soft defect may occur in the third word line group WG3 corresponding to the third group erase state E_G3 having a width of ΔV_G3 . Unlike the hard defect described above, the soft defect may refer to a defect that is not detected by the 0th erase verification voltage EV0 determined in advance based on the physical characteristics and the EOL state of the nonvolatile memory device 120 . That is, as shown in FIG. 12A , although a soft defect exists in the third word line group WG3 , the fail bits may not be counted by the 0 th erase verification voltage EV0 .

When a soft defect occurs in a specific word line group or specific memory cells associated with a specific word line (that is, when the threshold voltage distribution of the erase state of the specific memory cell is relatively wider than the threshold voltage distribution of the erase state of other memory cells) ), an error for a specific memory cell may be induced. These errors may not be cured by the ECC engine. Since a program operation or a read operation for the same memory block is performed through similar parameters, when the deviation of the threshold voltage distribution of an erase state in a specific word line group or a specific word line is relatively larger than others, a specific word line This is because multiple errors may be induced in data stored in a group or a specific word line.

The nonvolatile memory device 120 according to an embodiment of the present invention may detect a soft defect occurring in the selected memory block BLK by performing the delta verification operation DV. For example, as shown in FIG. 12B , results of the block verify operation BV and the partial verification operation PV of the first memory block BLK1 may both be PASS. Since the block verify operation BV and the partial verify operation PV of the first memory block BLK1 illustrated in FIG. 12B have been described with reference to FIG. 12A , a detailed description thereof will be omitted. In this case, the nonvolatile memory device 120 may perform a delta verification operation DV on the first memory block BLK1 .

The nonvolatile memory device 120 applies the first erase verification voltage EV1 to the first word line group WG1 of the first memory block BLK1 , and applies the first erase verification voltage EV1 to the remaining word line groups WG2 , WG3 , and WG4 . By applying the pass voltage VPASS, a fail bit for the first word line group WG1 may be counted to generate a first delta counting value CV_P1 . The first delta counting value CV_P1 is the number of memory cells having a threshold voltage higher than the first erase verification voltage EV1 among the memory cells corresponding to the first word line group WG1 or a bit line corresponding to the memory cells. can correspond to the number of

The nonvolatile memory device 120 may generate delta counting values for each of the second to fourth word line groups WG2 and WG4 , similarly to the operation for the first word line group WG1 . In the embodiment of FIG. 12B , a third delta counting value CV_D3 may be generated for the third word line group WG3 . The upper limit values of the threshold voltage distribution of the second and fourth group erase states E_G2 and E_G4 corresponding to the second and fourth word line groups WG2 and WG4 are all lower than the first erase verification voltage EV1 . Therefore, delta counting values for the second and fourth wordline groups WG2 and WG4 may not be counted.

The nonvolatile memory device 120 may generate a delta value DLT based on the generated counting values CV_D1 and CV_D3. As described above, the delta value DTL may be a value generated by various combinations of the counting values CV_D1 and CV_D3. For convenience of description, it is assumed that the delta value DLT is the difference between the maximum value and the minimum value of the counting values CV_D1 and CV_D3.

In this case, the delta value DLT may be “CV_D3 - CV_D1”, and the calculated delta value DLT may be greater than the third reference value REF3. The fact that the delta value DLT is greater than the third reference value REF3 means that the threshold voltage distribution of a specific word line group among the plurality of word line groups of the selected memory block BLK is greater than the threshold voltage distribution of other word line groups. It can mean wide. This may mean that a soft defect has occurred in a specific word line group. In the embodiment of FIG. 12B , an example in which a soft defect occurs in the third word line group WG3 is illustrated. In an exemplary embodiment, a soft defect may occur in an initial state of the nonvolatile memory device 120 .

In an exemplary embodiment, even if delta counting values for each of the word line groups are detected, when the delta value DLT is less than the third reference value REF3, it may be determined that there is no soft defect. For example, as shown in FIG. 12C , in the delta verification operation DV, a first delta counting value CV_D1 ′ may be generated for the first wordline group WG1 and the second wordline group WG1 . A second delta counting value CV_D2' may be generated for WG2, a third delta counting value CV_D3' may be generated for a third wordline group WG3, and a fourth wordline group A fourth delta counting value (CV_D4') may be generated for (WG4). Compared to the embodiment of FIG. 12B , in the embodiment of FIG. 12C , first to fourth delta counting values CV_D1 ′ to CV_D4 ′ were counted in all word line groups WG1 to WG4 , but the first to fourth Since the delta value DTL based on the 4 delta counting values CV_D1' to CV_D4' is less than the third reference value REF3, it may be determined that there is no soft defect. That is, in the embodiment of FIG. 12C , it may be determined that the result of the delta verification operation DV is PASS.

This is because, since all erase states of the word line groups of the selected memory block are broadly formed, various operation parameters for the selected memory block are equally applied, thereby reducing errors occurring in the memory block. In other words, when the threshold voltage distribution of the erase state of a specific word line group is wider than the threshold voltage distribution of other word line groups as shown in FIG. 12B , many errors occur due to soft defects, whereas all word lines as shown in FIG. 12C When the threshold voltage distribution of the groups is formed widely as a whole, by adjusting other operating parameters, an error may occur relatively less. As a result, when the delta value DTL is smaller than the third reference value REF3 , errors generated from the selected memory block may be recoverable errors.

As described above, in the nonvolatile memory device 120 according to an embodiment of the present invention, the first erase verification voltage EV1 lower than the 0th erase verification voltage EV0 determined in advance based on physical characteristics and EOL state, etc. ), generate delta counting values for each of the wordline groups, and detect a soft defect occurring in a memory block based on a delta value (DLT) based on the difference, variance, or distribution of the generated delta counting values. can do. When a soft defect is detected in a specific memory block through the delta verification operation DV, it may be determined that the specific memory block is erased as FAIL or may be managed as a bad block by the memory controller 110 .

13A is a block diagram illustrating an erase delta verification logic circuit of a nonvolatile memory device configured to perform the delta verification operation described with reference to FIGS. 11 to 12C . 13B is a block diagram exemplarily showing the delta operator of FIG. 13A .

13A and 13B , the erase delta verification logic circuit 121 may include a fail bit counter 121a, a delta operator 121b, and a comparator 121c. The fail bit counter 121a may count fail bits in units of word line groups to generate delta counting values CV_Ds.

The delta operator 121b may generate a delta value DLT based on the delta counting values CV_Ds generated by the fail bit counter 121a. For example, as shown in FIG. 13B , the delta operator 121b may include a maximum value selector and a comparison value selector.

The maximum value selector may select and output the maximum value MAX from among the delta counting values CV_Ds. The comparison value generator may generate the comparison value CMPV based on the delta counting values CV_Ds. In an exemplary embodiment, the comparison value CMPV may indicate a minimum value, a median value, or another specific value (eg, a second largest value, etc.) among the delta counting values CV_Ds. Alternatively, the comparison value CMPV may indicate an average value of the delta counting values CV_Ds. The difference between the maximum value MAX and the comparison value CMPV may be output as a delta value DLT. However, the scope of the present invention is not limited thereto, and the delta value DLT may be calculated as various values indicating a difference, distribution, or variance between the delta counted values CV_Ds.

The comparator 121c may compare the delta value DLT and the third reference value REF3, and may output information about a pass or a fail FAIL as a result of the comparison. For example, when the delta value DTL is smaller than the third reference value REF3, it may mean that a soft defect does not exist in the selected memory block. In this case, the comparator 121c may output information about the pass PASS. On the other hand, if the delta value DTL is greater than or equal to the third reference value REF3, it may mean that a soft defect exists in the selected memory block. In this case, the comparator 121c may output information about a fail (FAIL).

As described above, the nonvolatile memory device 120 according to an embodiment of the present invention may detect a soft defect of a selected memory block to be erased through the delta verification operation DV. The nonvolatile memory device 120 may include an erase delta verification logic circuit 121 configured to perform a delta verification operation DV. That is, a hardware configuration configured to perform the delta verification operation DV may be embedded in the nonvolatile memory device 120 in an on-chip form, thereby providing a nonvolatile memory device having improved reliability.

14 is a flowchart exemplarily illustrating an operation of the nonvolatile memory device of FIG. 3 . For convenience of description, detailed descriptions of the above-described components are omitted. 3 and 14 , the nonvolatile memory device 120 may perform operations S200 and S210 . Since the operations of steps S200 and S210 are similar to those of steps S100 and S110 of FIG. 5 , a detailed description thereof will be omitted.

When the result of the operation of step S210 is FAIL, the nonvolatile memory device 120 may perform the operation of step S242 . When the result of the operation in step S210 is PASS, the nonvolatile memory device 120 may perform the operation in step S230 . When the result of the operation in step S230 is PASS, the nonvolatile memory device 120 may perform the operation in step S241. Since the operations of steps S230, S241, and S242 are similar to the operations of steps S130, S141, and S142 of FIG. 5, a detailed description thereof will be omitted.

In the embodiment of FIG. 14 , unlike the embodiment of FIG. 5 , the partial verification operation PV is omitted. For example, according to the embodiment of FIG. 14 , when the result of the block verify operation BV is PASS, the nonvolatile memory device 120 may perform the delta verification operation DV. That is, since the partial verification operation PV is omitted, the time for the erase verification may be shortened. The embodiment of FIG. 14 is similar to the embodiment of FIG. 5 except that the partial verification operation PV is omitted, and thus a detailed description thereof will be omitted.

In an exemplary embodiment, the nonvolatile memory device 120 according to an embodiment of the present invention may be configured to omit the block verification operation BV and perform the partial verification operation PV and the delta verification operation DV. have. That is, the nonvolatile memory device 120 may be configured to perform a partial verification operation PV after an erase operation and a delta verification operation DV according to a result of the partial verification operation PV. However, the scope of the present invention is not limited thereto.

15 is a flowchart illustrating an operation of the nonvolatile memory device of FIG. 3 . 3 and 15 , the nonvolatile memory device 120 may perform operations S300, S310, S320, S330, S340, S351, and S352. Since the operations of steps S300, S310, S320, S330, S351, and S352 are similar to the operations of steps S100, S110, S120, S130, S141, and S142 of FIG. A detailed description thereof will be omitted.

According to the flowchart of FIG. 15 , when the result of the delta verification operation DV is FAIL, in step S340 , the nonvolatile memory device 120 may perform the word line verification operation WV. The word line verify operation WV may refer to an operation of detecting and verifying fail bits for each of the word lines of the word line group determined as having a soft defect in the delta verify operation DV. When the result of the word line verification operation WV is FAIL, the nonvolatile memory device 120 performs the operation of step S352, and when the result of the word line verification operation WV is PASS, The nonvolatile memory device 120 may perform the operation of step S352. That is, even if the result of the delta verify operation DV is FAIL, the erase of the selected memory block may be determined as a pass according to the result of the word line verify operation WV. The word line verify operation WV will be described in more detail with reference to FIGS. 16 to 18 .

16 is a flowchart exemplarily illustrating the operation of step S340 of FIG. 15 , that is, the word line verification operation. 3, 15, and 16 , when the result of the delta verification operation DV in step S330 is FAIL, the nonvolatile memory device 120 performs the word line verification operation WV, for example. For example, the operation of step S340a may be performed. The operation of step S340a may include the operations of steps S341a, S342a, S343a, S344a, S345a, and S346a.

In operation S341a, the nonvolatile memory device 120 may select one of the word lines of the fail-in word line group, that is, the word line group determined to include a soft defect in the delta verification operation DV.

In operation S342a, the nonvolatile memory device 120 may apply the first erase verification voltage EV1 to one selected word line and apply the pass voltage VPASS to the other word lines. Hereinafter, for convenience of description, it will be described that the word line verification operation WV is performed using the first erase verification voltage EV1 (ie, the erase verification voltage used in the delta verification operation DV). The scope of the invention is not limited thereto. For example, the erase verify voltage used in the word line verify operation WV may be lower than the zeroth erase verify voltage EV0 and may be different from the first erase verify voltage EV1 .

In step S343a, the nonvolatile memory device 120 counts the fail bit for the one selected word line and counts the counting value for the one selected word line (hereinafter, for convenience of description, a “word line counting value”) ) (CV_W) can be created.

In step S344a, the nonvolatile memory device 120 may compare the generated word line counting value CV_W with the fourth reference value REF4.

When the word line counting value CV_W is greater than or equal to the fourth reference value REF4 , the nonvolatile memory device 120 may perform the operation S352 . That is, when the word line counting value CV_W is greater than or equal to the fourth reference value REF4, it is determined that the word line verify operation WV is fail.

When the word line counting value CV_W is smaller than the fourth reference value REF4 , in operation S345a , the nonvolatile memory device 120 may determine whether all word lines included in the fail-in word line group are selected. When an unselected word line remains, in operation S346a , the nonvolatile memory device 120 selects a next word line from among the word lines of the fail-in word line group and performs the operation of operation S342a.

When all the word lines included in the fail-in word line group are selected, the nonvolatile memory device 120 may perform the operation S351a. That is, when all word lines included in the fail-in word line group are selected, it is determined that the word line verify operation WV is PASS.

17A and 17B are diagrams for explaining a word line verification operation according to the flowchart of FIG. 16 . For convenience of description, detailed descriptions of the above-described components are omitted. Referring to FIGS. 17A and 17B , the memory cells of the first memory block BLK1 may have a first block erase state E_B1 , and first to fourth word line groups of the first memory block BLK1 . Each of WG1 to WG4 may have first to fourth group erase states E_G1 to E_G4. Since the first block erase state E_B1 and the first to fourth group erase states E_G1 to E_G4 have been described above, a detailed description thereof will be omitted. As described above, the results of the block verify operation BV and the partial verify operation PV of the first memory block BLK1 may both be PASS, and the result of the delta verify operation DV is fail. (FAIL).

In this case, the nonvolatile memory device 120 may perform a word line verification operation WV on the third word line group WG3 determined to have a soft defect. For example, as described with reference to FIG. 4B , the third word line group WG3 may include third and seventh word lines WL3 and WL7 . The nonvolatile memory device 120 applies the first erase verification voltage EV1 to the third word line WL3 and the pass voltage VPASS to the remaining word lines, thereby forming the third word line WL3 and The number of memory cells (ie, fail bits) having a threshold voltage distribution higher than the first erase verification voltage EV1 among the connected memory cells may be counted. In a similar manner, the nonvolatile memory device 120 may count fail bits for the seventh word line WL7.

Memory cells of the third word line WL3 may have a third word line erased state E_W3 , and memory cells of the seventh word line WL7 may have a seventh word line erased state E_W7 . Widths of threshold voltage distributions of the third and seventh word line erase states E_W3 and E_W7 may be ΔV_W3 and ΔV_W7.

In this case, in the embodiment of FIG. 17A , the fail bit for the third word line WL3 may not be counted (ie, the third word line erase state E_W3) through the word line verify operation WV. The upper limit value is lower than the first erase verification voltage EV1 ) and the fail bit for the seventh word line WL7 may be counted as the seventh word line counting value CV_W7 . At this time, as shown in FIG. 17A , the seventh word line counting value CV_W7 may be greater than the fourth reference value REF4 . This may mean that a soft defect has occurred on the seventh word line WL7. Accordingly, the nonvolatile memory device 120 may determine the result of the word line verify operation WV as FAIL.

On the other hand, in the embodiment of FIG. 17B , the fail bits for the third and seventh word lines WL3 and WL7 may be counted as third and seventh word line counting values CV_W3 and CV_W7. In this case, as shown in FIG. 17B , both of the third and seventh word line counting values CV_W3 and CV_W7 may be smaller than the fourth reference value REF4. This may be because fail bits for the third word line group WG3 are distributed to the third and seventh word lines WL3 and WL7, respectively, in the delta verification operation DV. That is, in the delta verification operation DV, even if a specific word line group is determined to have a soft defect, a soft defect may not occur in each of the plurality of word lines included in the specific word line group. In this case, since the data stored in the memory cells of each word line does not cause an error or the generated error can be corrected through various error correction operations, a specific memory block can be used as a normal block.

In an exemplary embodiment, the partial verification operation PV described above is an operation of comparing the number of fail bits in units of word line groups with respect to the selected memory block using the zeroth erase verification voltage EV0, or FIG. In the word line verify operation WV described with reference to FIGS. 16 to 17B , the number of fail bits per word line for a word line group determined to have a soft defect using the first erase verify voltage EV1 . may be an operation to compare .

18 is a flowchart exemplarily illustrating a word line verification operation in step S340 of FIG. 15 . For convenience of description, detailed descriptions of the above-described components are omitted. 3, 15, and 18 , when the result of the delta verification operation DV in step S330 is FAIL, the nonvolatile memory device 120 performs the word line verification operation WV, for example. For example, the operation of step S340b may be performed. The operation of step S340b may include the operations of steps S341b, S342b, S343b, S344b, S345b, S346b, and S347b.

The nonvolatile memory device 120 may perform the operations of steps S341b to S343b. Since the operations of steps S341b to S343b are similar to the operations of steps S341a to S343a of FIG. 16 , a detailed description thereof will be omitted.

In operation S344b, the nonvolatile memory device 120 may determine whether all word lines included in the fail-in word line group are selected. When an unselected word line remains, in operation S345b , the nonvolatile memory device 120 may select a next word line from among the word lines of the fail-in word line group and perform the operation of operation S342b.

When all the word lines included in the fail-in word line group are selected, in step S346b, the nonvolatile memory device 120 determines a delta value DLT_W (word line delta value for convenience of description) based on the word line counting values. ) can be calculated. Similar to the delta value described above, the wordline delta value DLT_W may be a value indicating a difference, distribution, or variance between wordline counting values. For example, the word line delta value (DLT_W) may indicate the difference between the maximum value and the minimum value, the difference between the maximum value and the middle value, or the difference between the maximum value and the average value among the word line counting values. The scope is not limited thereto.

In operation S347b, the nonvolatile memory device 120 may compare the delta value DLT and the fifth reference value REF5. When the delta value DLT is greater than or equal to the fifth reference value REF5 , the nonvolatile memory device 120 may perform the operation S352 . That is, when the delta value DLT is greater than or equal to the fifth reference value REF5, the result of the word line verify operation WV is FAIL (ie, a soft defect exists in a specific word line). can be identified as When the delta value DLT is less than the fifth reference value REF5 , the nonvolatile memory device 120 may perform the operation S351 . That is, when the delta value DLT is greater than or equal to the fifth reference value REF5, it may be determined that the result of the word line verify operation WV is PASS.

In an exemplary embodiment, the word line verification operation WV described with reference to FIG. 16 is performed except that the verification target is a specific word line group determined to have a soft defect, and the verification unit is a word line unit. , since it may be similar to the delta verification operation (DV) described above, a detailed description thereof will be omitted. In an exemplary embodiment, the word line verify operation WV according to the flowchart of FIG. 18 may be performed by the erase delta verify logic circuit 121 described with reference to FIGS. 13A and 13B .

19 is a flowchart illustrating an exemplary operation of the nonvolatile memory device of FIG. 3 . For convenience of description, detailed descriptions of the above-described components are omitted. 3 and 19 , the nonvolatile memory device 120 may perform operations S400 to S430 . Since the operations of steps S400, S410, and S430 are similar to the operations of steps S200, S210, and S230 of FIG. 14 , a detailed description thereof will be omitted.

When the result of the delta verification operation DV of step S430 is FAIL, the nonvolatile memory device 120 may perform the word line verification operation WV of step S440 . When the result of the delta verification operation of step S430 is PASS or the result of the word line verification operation WV of step S440 is PASS, the nonvolatile memory device 120 performs the operation of step S451. can When the result of the block verify operation BV of step S410 is FAIL or the result of the word line verification operation WV of step S440 is FAIL, the nonvolatile memory device 120 performs the operation of step S452 can be performed. Since the operations of steps S440, S451, and S452 are similar to the operations of steps S340, S351, and S352 of FIG. 15 , a detailed description thereof will be omitted.

The operation according to the flowchart of FIG. 19 may be an operation in which the partial verification operation PV is omitted as compared with the operation according to the flowchart of FIG. 15 . Since this is similar to that described with reference to FIG. 14 , a detailed description thereof will be omitted.

As described above, in the nonvolatile memory device 120 according to an embodiment of the present invention, in erasing the selected memory block, a hard defect ( A hard defect may be detected, and a soft defect of the memory block may be detected through a delta verify operation (DV) or a word line verify operation (WV). In this case, the first erase verify voltage EV1 used in the delta verify operation DV or the word line verify operation WV is the zeroth erase verify voltage EV1 used in the block verify operation BV or the partial verify operation PV. It can be lower than (EV0). Accordingly, since a soft defect for a memory block or a soft defect for one word line, which may occur in an initial operation of the nonvolatile memory device 120 or under a specific condition, may be detected, Reliability can be improved.

The above-described embodiments are exemplary for easily explaining the technical spirit of the present invention, and the scope of the present invention is not limited thereto. For example, whether an erase pass or fail for the selected memory block is determined by various verification operations (eg, a block verification operation, a partial verification operation, a delta verification operation, a word line verification operation, etc.) according to an embodiment of the present invention. can be determined in various ways depending on the result of Alternatively, the order of various verification operations according to an embodiment of the present invention may be modified in various ways different from the illustrated embodiments.

20 and 21 are diagrams for explaining a word line group for a memory block. The word line groups WG1 to WG4 described with reference to FIG. 4B divide the plurality of word lines WL1 to WL8 into a finger type or a cross type. However, the scope of the present invention is not limited thereto. For example, one word line group may be configured to include a plurality of adjacent word lines. As a more detailed example, as shown in FIG. 20 , the memory block BLK may include first to eighth word lines WL1 to WL8. The first to eighth word lines WL1 to WL8 may have a structure in which they are sequentially stacked from a substrate (not shown).

The first and second word lines WL1 and WL2 may form a first word line group WG1 , and the third and fourth word lines WL3 and WL4 may form a second word line group WG2 . may form, the first and second word lines WL5 and WL6 may form a third word line group WG3 , and the first and second word lines WL7 and WL8 may form a fourth A word line group WG4 may be formed. The first and second word lines WL1 and WL2 may be adjacent to each other, the third and fourth word lines WL3 and WL4 may be adjacent to each other, and the fifth and sixth word lines WL5 may be adjacent to each other. , WL6 may be adjacent to each other, and the seventh and eighth word lines WL7 and WL8 may be adjacent to each other.

Alternatively, the word line groups may correspond to the plurality of word lines in various ways. For example, as shown in FIG. 21 , the first to eighth word lines WL1 to WL8 may be connected to the address decoder 121 . The address decoder 121 divides the plurality of word lines WL1 to WL8 into a plurality of word line groups WG1 to WG4 in various ways according to the control of the control logic circuit 126 (refer to FIG. 3 ). can be divided

In an exemplary embodiment, the level of the first erase verify voltage EV1 used in the delta verify operation DV or the word line verify operation WV is determined by a division method for word line groups or a physical location of the word line group. (For example, the height from the substrate of the lowest word line among the word lines included in the word line group) may be variously modified according to the physical characteristics of the word line group.

In an exemplary embodiment, the level of the first erase verification voltage EV1 used in the delta verification operation DV or the word line verification operation WV is the program/erase program for the nonvolatile memory device 120 or the selected memory block. It may be variously modified according to various characteristics such as the number of cycles and the temperature of the nonvolatile memory device 120 .

22A and 22B are diagrams exemplarily illustrating memory blocks included in the memory cell array of FIG. 3 . In an exemplary embodiment, the memory blocks BLK-MS1 and BLK-MS2 having a multi-stack structure will be described with reference to FIGS. 22A and 22B .

Referring to FIG. 22A , the first multi-stack memory block BLK-MS1 may include a first memory structure STR1 and a second memory structure STR2 stacked in a direction perpendicular to the substrate SUB. Each of the first and second memory structures STR1 and STR2 may be a 3D memory cell structure including memory cells stacked in a direction perpendicular to a substrate. The first memory structure STR1 may include a ground select line GSL, a dummy word line DWL11, and a plurality of word lines WL11 to WL14, and a ground select line GSL and a dummy word line DWL11) and the plurality of word lines WL11 to WL14 may be stacked in a direction perpendicular to the substrate SUB. The first memory structure STR1 may include a ground selection line GSL, a dummy word line DWL11, and a first pillar PL1 passing through the plurality of word lines WL11 to WL14.

The second memory structure STR2 may be stacked on the first memory structure STR1 . The second memory structure STR2 may include a plurality of word lines WL21 to WL24, a dummy word line DWL21, and a string selection line SSL, and a plurality of word lines WL21 to WL24; The dummy word line DWL21 and the string selection line SSL may be stacked in a direction perpendicular to the substrate SUB. The second memory structure STR2 may include a plurality of word lines WL21 to WL24 , a dummy word line DWL21 , and a second pillar PL2 passing through the string selection line SSL. The first pillar PL1 of the first memory structure STR1 and the second pillar PL2 of the second memory structure STR2 may be electrically connected to each other.

A bit line BL (or a bit line pad) may be formed on the second memory structure STR2 , and the bit line BL is electrically connected to the second pillar PL2 of the second memory structure STR2 . can be connected

Next, referring to FIG. 22B , the second multi-stack memory block BLK-MS2 may include a first memory structure STR1 and a second memory structure STR2 stacked in a direction perpendicular to the substrate SUB. can Each of the first and second memory structures STR1 and STR2 may be a 3D memory cell structure including memory cells stacked in a direction perpendicular to a substrate. The first memory structure STR1 may include a ground selection line GSL, a plurality of word lines WL11 to WL14, and a string selection line SSL, and a ground selection line GSL and a plurality of words. The lines WL11 to WL14 and the silver substrate SUB may be stacked in a vertical direction. The second memory structure STR2 may include a string select line SSL, a plurality of word lines WL21 to WL24, and a ground select line GSL, the string select line SSL, and a plurality of The word lines WL21 to WL24 and the ground selection line GSL may be stacked in a direction perpendicular to the substrate SUB.

A bit line may be provided on an upper portion of the first memory structure STR1 , and a second memory structure STR2 may be provided on an upper portion of the bit line. That is, unlike the first multi-stack memory block BLK-MS1 of FIG. 22A , in the second multi-stack memory block BLK-MS2 of FIG. 22B , the bit line includes the first and second memory structures STR1 and STR2 . ) can be provided between

The above-described multi-stack memory blocks are exemplary, and the scope of the present invention is not limited thereto. For example, the multi-stack memory blocks BLK-MS1 and BLK-MS2 of FIGS. 22A and 22B are illustrated as having a two-layer stacking structure, but the scope of the present invention is not limited thereto, and n memory structures (provided that n is an integer greater than 2) may have a structure in which they are stacked in a direction perpendicular to the substrate.

Alternatively, the number of word lines, the number of string selection lines, and the number of ground selection lines of each of the plurality of memory structures included in the multi-stack memory block may be variously modified.

23A and 23B are diagrams for explaining a word line group for the first multi-stack memory block of FIG. 22A. For convenience of explanation, division of the first to fourth word line groups WG1 to WG4 is described based on the first multi-stack memory block BLK-MS1, but the scope of the present invention is not limited thereto. no.

22A, 23A, and 23B , the first multi-stack memory block BLK-MS1 may include first and second memory structures STR1 and STR2, and the first memory structure STR1 may include a plurality of word lines WL11 to WL14, and the second memory structure STR2 may include a plurality of word lines WL21 to WL24.

Each of the plurality of word line groups WG1 to WG4 may be configured to group word lines of the same memory structure. For example, as shown in FIG. 23A , the first word line group WG1 may include the word lines WL11 and WL13 of the first memory structure SRT1 and the second word line group WG2 ) may include word lines WL12 and WL14 of the first memory structure STR1 . The third word line group WG3 may include the word lines WL21 and WL23 of the second memory structure STR2 , and the fourth word line group WG4 is a word line of the second memory structure STR2 . These may include WL22 and WL24.

Alternatively, the plurality of word line groups WG1 to WG4 may be configured to group word lines having the same height in each memory structure. For example, the height of the word line WL11 from the bottom of the first memory structure STR1 may be the same as the height of the word line WL21 from the bottom of the second memory structure STR2 . At this time, as shown in FIG. 23B , the word line WL11 of the first memory structure STR1 and the word line WL21 of the second memory structure STR2 may be included in the first word line group WG1 . have. Similarly, the word lines WL12/WL22, WL13/WL23, and WL14/WL24 positioned at the same height in each memory structure may be included in the second to fourth word line groups WG2 to WG4, respectively.

The structure and word line groups of the multi-stack memory block described above are exemplary, and the scope of the present invention is not limited thereto.

In an exemplary embodiment, for the memory blocks having the multi-stack structure as described above, word line groups may be determined based on various methods, and the nonvolatile memory device may be determined based on the word line groups determined based on various methods. may be configured to perform the delta verification operation described with reference to FIGS. 1 to 19 .

24 is a flowchart illustrating an exemplary operation of the memory controller of FIG. 2 . 2 and 24 , in step S1100 , the memory controller 110 may receive information on an erase fail. For example, the nonvolatile memory device 120 performs an erase operation and an erase verify operation (eg, a block verify operation (BV), a partial verify operation (PV) ), a delta verify operation (DV), or a word line verify operation (WV)) may be performed. In the verification operation, when an erase fail occurs, the nonvolatile memory device 120 may provide information on the memory block in which the erase fail occurs to the memory controller 110 .

In operation S1200 , the memory controller 110 may manage a memory block corresponding to the received information as a bad block. For example, the memory controller 110 may manage a memory block in which an erase fail occurs as a bad block, and replace mapping information on the memory block managed as a bad block with another normal block. In an exemplary embodiment, the above-described bad block management operation may be performed by the nonvolatile memory manager 124 (or FTL) described with reference to FIG. 2 .

25 is a block diagram exemplarily illustrating a storage device according to an embodiment of the present invention. Referring to FIG. 25 , the storage device 200 may include a memory controller 210 and a nonvolatile memory device 220 . The erase verification method described with reference to FIGS. 1 to 23B is performed by the nonvolatile memory device 120 or in the erase delta verification logic circuit 121 implemented in an on-chip form in the nonvolatile memory device 120 . can be performed by

On the other hand, in the embodiment of FIG. 25 , the memory controller 210 may perform the delta verification operation DV instead of the nonvolatile memory device 220 . For example, the nonvolatile memory device 220 may perform a delta verification operation DV under the control of the memory controller 210 . In this case, the nonvolatile memory device 220 may provide a delta counting value for each of the word line groups to the memory controller 210 during the delta verification operation DV described with reference to FIGS. 1 to 23B . The memory controller 210 may calculate the delta value DLT as described above based on the delta counting value, and determine whether a soft defect has occurred in the selected memory block based on the calculated delta value DTL. . In an exemplary embodiment, the above-described delta verification operation DV of the memory controller 210 may be performed by the erase verification delta logic 210 included in the memory controller 210 . The erase verify delta logic 210 may be implemented in the form of software, firmware, hardware, or a combination thereof.

26 is a block diagram exemplarily showing a test system according to an embodiment of the present invention. Referring to FIG. 26 , the test system 1000 may include a test device 1100 and a nonvolatile memory device 1200 . The test device 1100 may perform various test operations on the nonvolatile memory device 1200 . In an exemplary embodiment, the test device 1100 may include an erase delta verification logic 1110 . The erase delta verify logic 1110 may be configured to perform the delta verify operation described with reference to FIGS. 1-25 . That is, the test device 1100 performs a delta verification operation on the nonvolatile memory device 1200 to obtain a soft defect (soft defect) occurring in a specific memory block or a specific word line group or a specific word line of the nonvolatile memory device 1200 . defect) can be configured to detect.

27 is a block diagram illustrating an SSD system to which a nonvolatile memory device according to the present invention is applied. Referring to FIG. 27 , the SSD system 2000 includes a host 2100 and a storage device 2200 . The storage device 2200 may exchange a signal SIG with the host 2100 through the signal connector 2201 and receive power PWR through the power connector 2202 . The storage device 2200 may include a solid state drive (SSD) controller 2210 , a plurality of nonvolatile memories 2221 to 222n , an auxiliary power supply 2230 , and a buffer memory 2240 .

The SSD controller 2210 may control the plurality of nonvolatile memories 2221 to 222n in response to the signal SIG received from the host 2100 . The plurality of nonvolatile memories 2221 to 222n may operate under the control of the SSD controller 2210 . The auxiliary power supply 2230 is connected to the host 2100 through the power connector 2002 . The auxiliary power supply 2230 may receive power PWR from the host 2100 and charge it. The auxiliary power supply 2230 may provide power to the SSD 2200 when power supply from the host 2100 is not smooth. The buffer memory 2240 may be used as a buffer memory of the storage device 2200 . In an exemplary embodiment, each of the plurality of nonvolatile memories 2221 to 222n performs the delta verification operation described with reference to FIGS. 1 to 25 or includes an erase delta verification logic circuit configured to perform the delta verification operation can do. Alternatively, the SSD controller 2210 performs the delta verification operation as described with reference to FIGS. 1 to 25 on each of the plurality of nonvolatile memories 2221 to 222n, or an erase delta verification configured to perform the delta verification operation. It may include a logic circuit.

28 is a block diagram illustrating an electronic device to which a storage system according to the present invention is applied. Referring to FIG. 28 , the electronic device 3000 includes a main processor 3100 , a touch panel 3200 , a touch driving circuit 3202 , a display panel 3300 , a display driving circuit 3302 , a system memory 3400 , It may include a storage device 3500 , an audio processor 3600 , a communication block 3700 , and an image processor 3800 . In an exemplary embodiment, the electronic device 3000 includes a personal computer, a laptop computer, a server, a workstation, a mobile communication terminal, a personal digital assistant (PDA), a portable media player (PMP), a digital camera, a smartphone, a tablet computer, It may be one of various electronic devices such as a wearable device.

The main processor 3100 may control overall operations of the electronic device 3000 . The main processor 3100 may control/manage operations of components of the electronic device 3000 . The main processor 3100 may process various calculations to operate the electronic device 3000 . The touch panel 3200 may be configured to sense a touch input from a user under the control of the touch driving circuit 3202 . The display panel 3300 may be configured to display image information under the control of the display driving circuit 3302 .

The system memory 3400 may store data used for the operation of the electronic device 3000 . For example, system memory 3400 may include volatile memory such as static random access memory (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), and/or phase-change RAM (PRAM), magneto-resistive RAM (MRAM), and/or the like. ), a resistive RAM (ReRAM), a non-volatile memory such as a ferro-electric RAM (FRAM), and the like.

The storage device 3500 may store data regardless of power supply. For example, the storage device 3500 may include at least one of various nonvolatile memories such as flash memory, PRAM, MRAM, ReRAM, and FRAM. For example, the storage device 3500 may include an internal memory and/or a removable memory of the electronic device 3000 . In an exemplary embodiment, the storage device 3500 may include a nonvolatile memory and may perform a delta verification operation on the nonvolatile memory.

The audio processor 3600 may process an audio signal using the audio signal processor 3610 . The audio processor 3600 may receive an audio input through the microphone 3620 or provide an audio output through the speaker 3630 . The communication block 3700 may exchange signals with an external device/system through the antenna 3710 . Transceiver 3720 and MODEM (Modulator / Demodulator, 2730) of the communication block 3700 is LTE (Long Term Evolution), WiMax (Worldwide Interoperability for Microwave Access), GSM (Global System for Mobile communication), CDMA (Code Division Multiple) Access), Bluetooth, Near Field Communication (NFC), Wi-Fi (Wireless Fidelity), RFID (Radio Frequency Identification), etc., can process signals exchanged with external devices/systems according to at least one of various wireless communication protocols. have. The image processor 3800 may receive light through the lens 3810 . The image device 3820 and the image signal processor 3830 included in the image processor 3800 may generate image information about an external object based on the received light.

The above are specific embodiments for carrying out the present invention. The present invention will include not only the above-described embodiments, but also simple design changes or easily changeable embodiments. In addition, the present invention will include techniques that can be easily modified and implemented using the embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the claims described below as well as the claims and equivalents of the present invention.

Claims (20)

A method of operating a nonvolatile memory device including a memory block connected to a plurality of word lines, the method comprising:
performing an erase operation on the memory block using a zeroth erase voltage;
performing a block verify operation on the memory block using a zeroth erase verify voltage;
performing a delta verify operation on the memory block using a first erase verify voltage different from the zeroth erase verify voltage when a result of the block verify operation is a pass; and
outputting information on an erase result of the memory block based on a result of the block verify operation or a result of the delta verify operation,
The plurality of word lines are divided into a plurality of word line groups,
The delta verification operation is:
generating a plurality of delta counting values respectively corresponding to the plurality of word line groups by using the first erase verify voltage;
generating a delta value based on the plurality of delta counting values; and
and comparing the delta value and a first reference value. The method of claim 1,
The first erase verify voltage is lower than the zeroth erase verify voltage. The method of claim 1,
The zeroth erase verification voltage is determined based on an end of life (EOL) state of the memory block. The method of claim 1,
The block verification operation is:
generating a block counting value corresponding to the number of memory cells having a threshold voltage higher than the zeroth erase verification voltage among the memory cells of the memory block by using the zeroth erase verification voltage; and
comparing the block counting value with a second reference value;
and when the block counting value is less than the second reference value, it is determined that the result of the block verify operation is a pass. The method of claim 1,
Each of the plurality of delta counting values corresponds to the number of memory cells having a threshold voltage higher than the first erase verification voltage among memory cells included in a corresponding word line group among the plurality of word line groups. The method of claim 1,
The delta value indicates a difference between a comparison value generated based on the plurality of delta counting values and a maximum value among the plurality of delta counting values,
The comparison value is a minimum value, a median value, an average value, or an Nth largest value of the plurality of delta counting values, where N is greater than or equal to 2 and less than the number of the plurality of delta counting values. One way to work. The method of claim 1,
If the delta value is greater than or equal to the first reference value, it is determined that the erase result for the memory block is a fail;
and when the delta value is less than the first reference value, it is determined that the erase result for the memory block is a pass. The method of claim 1,
performing a partial verification operation on the memory block using the second erase verification voltage when a result of the block verification operation is a pass;
When the result of the block verify operation and the result of the partial verify operation are both pass, the delta verify operation is performed on the memory block. 9. The method of claim 8,
The partial verification operation is:
generating a plurality of partial counting values respectively corresponding to the word line groups by using the second erase verification voltage; and
comparing each of the plurality of partial counting values with a third reference value;
and when each of the plurality of partial counting values is less than the third reference value, it is determined that the result of the partial verification operation is a pass. The method of claim 1,
If the result of the delta verify operation is a fail, performing a word line verify operation on one word line group among the plurality of word line groups using the fourth erase verify voltage;
The erase result of the memory block is determined based on the result of the block verify operation, the result of the delta verify operation, and the result of the word line verify operation. 11. The method of claim 10,
The one word line group is a word line group corresponding to a maximum value among the plurality of delta counting values. 11. The method of claim 10,
The word line verification operation includes:
generating a plurality of word line counting values respectively corresponding to the word lines included in the one word line group by using the fourth erase verification voltage; and
comparing each of the plurality of wordline counting values with a fourth reference value;
When each of the plurality of wordline counting values is less than the fourth reference value, it is determined that the result of the wordline verification operation is a pass. 11. The method of claim 10,
The word line verification operation includes:
generating a plurality of word line counting values respectively corresponding to the word lines included in the one word line group by using the fourth erase verification voltage;
generating a wordline delta value based on the plurality of wordline counting values; and
comparing the wordline delta value and a fifth reference value;
and when the wordline delta value is less than the fifth reference value, it is determined that the result of the wordline verify operation is a pass. The method of claim 1,
determining whether the erase operation is performed a predetermined number of times when the result of the block verify operation is a fail; and
and re-performing the erase operation using a first erase voltage higher than the zeroth erase voltage when the erase operation is not performed a predetermined number of times. The method of claim 1,
and performing a program operation on the memory block when an erase result of the memory block is a pass. A method of operating a nonvolatile memory device including a memory block connected to a plurality of word lines, the method comprising:
performing an erase operation on the memory block;
performing a block verify operation on the memory block using a zeroth erase verify voltage;
performing a partial verification operation on the memory block using a first erase verification voltage when a result of the block verification operation is a pass;
performing a delta verification operation on the memory block using a second erase verification voltage different from the zeroth and first erase verification voltages when a result of the partial verification operation is a pass; and
outputting information on an erase result of the memory block based on the result of the block verify operation, the result of the partial verify operation, or the result of the delta verify operation,
The block verification operation refers to an operation of generating a block counting value in block units using the 0th erase verification voltage and comparing the block counting value with a first reference value,
The partial verification operation refers to an operation of generating a plurality of partial counting values for each word line group by using the first erase verification voltage and comparing each of the plurality of partial counting values with a second reference value;
In the delta verification operation, a plurality of delta counting values generated in units of the word line group are generated using the second erase verification voltage, a delta value is generated based on the plurality of delta counting values, and the delta value is A method of operation indicating an operation of comparing with a third reference value. 17. The method of claim 16,
The plurality of word lines are divided into first to fourth word line groups,
The first word line group includes first word lines among the plurality of word lines, the second word line group includes second word lines among the plurality of word lines, and the third word line group includes third wordlines among the plurality of wordlines, and the fourth wordline group includes fourth wordlines among the plurality of wordlines. 18. The method of claim 17,
The plurality of delta counting values include first to fourth delta counting values,
The delta verification operation is:
By applying the second erase verification voltage to the first word lines, the first memory cells connected to the first word lines corresponding to the number of memory cells having a threshold voltage higher than the second erase verification voltage generating a delta counting value;
The second erase verification voltage is applied to the second word lines to correspond to the number of memory cells having a threshold voltage higher than the second erase verification voltage among the memory cells connected to the second word lines. generating a delta counting value;
The third erase verification voltage is applied to the third word lines to correspond to the number of memory cells connected to the third word lines having a threshold voltage higher than the second erase verification voltage. generating a delta counting value;
The fourth erase verification voltage is applied to the fourth word lines to correspond to the number of memory cells connected to the fourth word lines having a threshold voltage higher than the second erase verification voltage. generating a delta counting value;
generating the delta value based on a difference between a comparison value based on the first to fourth delta counting values and a maximum value of the first to fourth delta counting values; and
comparing the delta value and the third reference value;
The comparison value is a minimum value, a median value, an average value, or an Nth largest value of the plurality of delta counting values, where N is greater than or equal to 2 and less than the number of the plurality of delta counting values. is one,
and if the delta value is greater than the third reference value, it is determined that the result of the delta verify operation is a fail. An erase verification method of a nonvolatile memory device comprising a memory block connected to a plurality of word lines divided into a plurality of word line groups, the method comprising:
generating a plurality of delta counting values respectively corresponding to the plurality of word line groups by using a first erase verify voltage;
generating a delta value based on the plurality of delta counting values;
comparing the delta value to a first reference value; and
and outputting information on an erase result of the memory block based on the comparison result. 20. The method of claim 19,
Before generating the plurality of delta counting values:
performing an erase operation on the memory block using a first erase voltage; and
performing a block verify operation on the memory block using a zeroth erase verify voltage;
the zeroth erase voltage is higher than the first erase voltage;
and generating the plurality of delta counting values when a result of the block verify operation is a pass.

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