KR20210129457A - High output power semiconductor device package and manufacturing method thereof - Google Patents

Abstract

The present invention relates to a high output power semiconductor device package and a manufacturing method thereof. The high output power semiconductor device package includes a metal frame having a semiconductor layer stacked on an upper surface thereof and including insulation holes formed on both sides around the semiconductor layer; a semiconductor chip disposed on the semiconductor layer; and an insulating part formed by filling the insulation holes with an organic material or an inorganic material. A source region, a drain region, and a gate region are separated by the insulating part to form an electrode. The source region and the semiconductor chip are electrically connected. The gate region and the semiconductor chip are electrically connected.

Description

High output power semiconductor device package and manufacturing method thereof

The present invention relates to a high output power semiconductor device package technology, and more particularly, to a high output power semiconductor device package capable of improving processability and heat dissipation performance compared to a conventional semiconductor device package and a method of manufacturing the same.

The semiconductor high output power amplifier (SSPA) not only has excellent advantages in terms of lifetime, maintenance and amplifier operation, but also when the power amplifier starts and ends transmission under full output power, the semiconductor high output power Since the heat-up time and cool-down time of the amplifier are much shorter than the heating and cooling time of the traveling wave tube, it is strongly predicted that the semiconductor high-output power amplifier will replace the traveling wave tube.

In addition, semiconductor high-output power amplifiers have advantages such as wideband frequency realization and digital signal processing. Semiconductor high output power amplifier (SSPA) technology includes semiconductor power amplifier device and package technology, semiconductor power amplifier module, and MMIC (Microwave Monolithic Integrated Circuit) technology.

The semiconductor power amplification device technology that must be basically equipped to implement a semiconductor high-power amplifier is a silicon-based LDMOS (Laterally Diffused Metal Oxide Semiconductor) device, a Gallium Arsenide (GaAs)-based HEMT (High Electron Mobility Transistor) device, and gallium nitride. There is a HEMT device technology based on (Gallium Nitride, GaN). Among them, the GaN-based HEMT device (GaN HEMT device) technology is implemented with a GaN material. The GaN material can operate at a high voltage due to a wide energy gap of 3.4 eV, and the carrier concentration using the polarized charge is 10 times higher than that of GaAs. Therefore, high current density and high power density can be obtained, so it is suitable as a high-output, high-efficiency, small-sized power amplifier device.

The semiconductor high-power amplifier device can be implemented by combining individual semiconductor power amplifier devices in an array, or by using an active device and a passive device on a semiconductor substrate at the same time to form an MMIC, or by arraying and combining a power amplifier MMIC. have.

Until now, high-power, high-frequency power semiconductor device packages have been dominated by metal and ceramic packages. In this trend, high-power GaN transistors are also composed of metal and ceramic packages. As a result, metal and ceramic packages improve the excellent heat dissipation characteristics and reliability of high-power GaN transistors, but material and assembly costs are very high to proceed with mass production for supply according to demand, and there is a problem in the limitation of production.

On the other hand, a plastic overmold package can be manufactured at a fraction of the cost, and is limited to low-power applications, so it is not applied to high-power GaN transistors.

1 is a diagram illustrating a stacking state of a high output power semiconductor device package according to the prior art, FIG. 2 is a cross-sectional view illustrating a high output power semiconductor device package according to the prior art, and FIG. 3 is a high output power semiconductor device according to the prior art It is an example diagram explaining the package.

1 to 3 , the high output power semiconductor device package according to the prior art uses a metal-based package to efficiently dissipate heat generated from the semiconductor chip 21 , and the metal-based substrate 11 ) is formed by stacking a three-terminal structure of a gate, a source, and a drain. At this time, in order to form the electrode 13, the insulating layer 12 using ceramic is laminated on the lower side of the electrode, respectively.

The semiconductor chip 21 disposed on the electrode 13 is electrically connected to the source-drain using a silver (Au) alloy bonding wire 22, and then a ceramic cap 23 covering the semiconductor chip 21 is formed on a metal substrate ( 11) is joined. A predetermined space is formed between the ceramic cap 23 and the semiconductor chip 21 .

Conventionally, in order to bond the insulating layer 12 using ceramic to the metal substrate 11, the package is produced by firing at high temperature and high pressure. There is a problem with low fairness.

In addition, although the metal ceramic package structure has a heat dissipation structure in the package itself, there are problems in that the substrate price is high and automatic processing is difficult.

Republic of Korea Patent No. 110-2018-0000105 (Title of the invention: high frequency power transistor package and manufacturing method thereof)

In order to solve the above problems, according to an embodiment of the present invention, a metal-based package is manufactured in order to efficiently dissipate heat generated from a semiconductor chip, and ceramic is used to secure durability and price competitiveness. An object of the present invention is to make it possible to configure three terminals of a source, a gate, and a drain through an insulating structure filled with an organic material or an inorganic material by replacing the insulating layer.

However, the technical task to be achieved by the present embodiment is not limited to the technical task as described above, and other technical tasks may exist.

As a technical means for achieving the above technical problem, the high output power semiconductor device package according to an embodiment of the present invention includes a semiconductor layer stacked on an upper surface, and insulating holes formed on both sides around the semiconductor layer. metal frame; a semiconductor chip disposed on the semiconductor layer; an insulating part formed by filling the insulating hole with an organic material or an inorganic material, wherein a source region, a drain region, and a gate region are separated by the insulating part to form an electrode, and the source region and the semiconductor chip are electrically connected; , electrically connecting the gate region and the semiconductor chip.

The metal frame may be formed of any one of a metal material including aluminum (Al), copper (CU), and Kovar. Meanwhile, a seating groove may be formed in the center of the metal frame, and the semiconductor layer may be stacked in the seating groove.

The insulating hole may be formed to penetrate from an upper surface to a lower surface of the metal frame, and may be formed symmetrically on both sides of the metal frame.

The insulating hole may be formed to penetrate from the upper surface to one side of the metal frame, and may be formed in a symmetrical shape on both sides of the metal frame.

In addition, a method of manufacturing a high output power semiconductor device package according to another embodiment of the present invention includes the steps of selecting a location of an insulating hole for separating a source region, a drain region, and a gate region; creating a metal frame by filling the remaining portions except for the insulating hole with a metal material; forming an insulating part by filling the insulating hole with an organic or inorganic substance; arranging a semiconductor chip by stacking a semiconductor layer on an upper surface of the drain region; and electrically connecting the source region and the semiconductor chip, and electrically connecting the gate region and the semiconductor chip.

The process of forming the insulating part by filling the insulating hole with an organic material or an inorganic material is a method of penetrating from an upper surface to a lower surface of the metal frame, and a method of penetrating from the upper surface to one side of the metal frame. By forming a portion, the insulating portion may serve as a barrier rib separating the source region, the drain region, and the gate region.

According to the problem solving means of the present invention described above, it is possible to provide a new type of miniaturized high output power semiconductor device package of a leadless surface mount type based on a high integration and high heat dissipation substrate, and heat dissipation through a frame based on a metal material Characteristics can be improved and reliability can be secured by maintaining excellent power density and high efficiency through process optimization to minimize loss and yield reduction due to parasitic components caused by internal wire bonding and wiring.

1 is a view for explaining a stacked state of a high output power semiconductor device package according to the prior art.
2 is a cross-sectional view illustrating a high output power semiconductor device package according to the prior art.
3 is an exemplary view illustrating a high output power semiconductor device package according to the prior art.
4 is a cross-sectional view illustrating the configuration of a high output power semiconductor device package according to the first embodiment of the present invention.
5 is a cross-sectional view illustrating a configuration of a high output power semiconductor device package according to a second embodiment of the present invention.
6 is a cross-sectional view illustrating a configuration of a high output power semiconductor device package according to a third embodiment of the present invention.
7 is a cross-sectional view illustrating a configuration of a high output power semiconductor device package according to a fourth embodiment of the present invention.
8 is a flowchart illustrating a method of manufacturing a high output power semiconductor device package according to an embodiment of the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those of ordinary skill in the art can easily implement them. However, the present invention may be embodied in many different forms and is not limited to the embodiments described herein. And in order to clearly explain the present invention in the drawings, parts irrelevant to the description are omitted, and similar reference numerals are attached to similar parts throughout the specification.

Throughout the specification, when a part is "connected" with another part, this includes not only the case of being "directly connected" but also the case of being "electrically connected" with another element interposed therebetween. . Also, when a part "includes" a component, it means that other components may be further included, rather than excluding other components, unless otherwise stated, and one or more other features However, it is to be understood that the existence or addition of numbers, steps, operations, components, parts, or combinations thereof is not precluded in advance.

The following examples are detailed descriptions to help the understanding of the present invention, and do not limit the scope of the present invention. Accordingly, an invention of the same scope performing the same function as the present invention will also fall within the scope of the present invention.

Hereinafter, an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

4 is a cross-sectional view illustrating the configuration of a high output power semiconductor device package according to a first embodiment of the present invention, and FIG. 5 is a cross-sectional view illustrating the configuration of a high output power semiconductor device package according to a second embodiment of the present invention, 6 is a cross-sectional view illustrating a configuration of a high output power semiconductor device package according to a third embodiment of the present invention, and FIG. 7 is a cross-sectional view illustrating a configuration of a high output power semiconductor device package according to a fourth embodiment of the present invention.

4 to 7 , the high output power semiconductor device package 100 includes, but is not limited to, a metal frame 110 , a semiconductor chip, and an insulating part 120 .

The metal frame 110 includes a semiconductor layer 101 stacked on an upper surface, and insulating holes (not shown) formed on both sides of the semiconductor layer 101 as a center. The metal frame 110 is formed of any one of a metal material including aluminum (Al), copper (CU), and Kovar. Here, Kovar is the most widely used metal package, and is an iron, nickel, and cobalt alloy material.

A semiconductor chip (not shown) is disposed on the semiconductor layer 101 , and the insulating part 120 is formed by filling insulating holes formed on both sides of the metal frame 110 with an organic or inorganic substance. The insulating part 120 may apply a combination of organic materials, inorganic materials, organic materials, and inorganic materials.

The insulating part 120 serves as a barrier rib separating the source region 131 , the drain region 133 , and the gate region 132 , and is based on the drain region 133 located under the semiconductor layer 101 . A source region 131 on one side and a gate region 132 on the other side are positioned.

Since the source region 131 , the drain region 133 , and the gate region 132 are separated by the insulating part 130 on the metal frame 110 formed of a metal material, the source region 131 is a source electrode and a gate region. Reference numeral 132 denotes a gate electrode, and a drain region 133 denotes a drain electrode.

The source region 131 is electrically connected to the semiconductor chip using the Au wire 140 , and the gate region 132 is also electrically connected to the semiconductor chip using the Au wire 140 .

The metal frame 110 may be formed in a hexahedral shape as shown in FIG. 4 , and a seating groove 111 is formed in the center of the hexahedral body as shown in FIG. 5 , and a semiconductor in the seating groove 111 . Layer 101 may be laminated. The metal frame 110 may be formed in various sizes and shapes in addition to a rectangular parallelepiped and a cube.

In the metal frame 110 in which the seating groove 111 is formed, since the semiconductor chip is positioned lower than the source and drain, a predetermined space may be formed in the upper portion of the semiconductor chip, thereby more efficiently dissipating heat generated from the semiconductor chip. can do.

') 등 다양한 형태로 형성될 수 있고, 절연용 홀은 반도체층(101)을 중심으로 양측에 대칭적으로 형성된다. On the other hand, the insulating hole is formed in a form penetrating from the upper surface to the lower surface of the metal frame 110, as shown in Figs. form('

'), and the like, and the insulating hole is symmetrically formed on both sides of the semiconductor layer 101 as a center.

The insulating hole may be formed in a shape penetrating from the upper surface to one side of the metal frame 110 , that is, in a 'L' shape.

8 is a flowchart illustrating a method of manufacturing a high output power semiconductor device package according to an embodiment of the present invention.

Referring to FIG. 8 , in the method of manufacturing a high-output power semiconductor device package, a location of an insulating hole serving as a barrier rib is selected to separate the source region 131 , the drain region 133 , and the gate region 132 ( S1 ). ).

The insulating hole is formed in a predetermined region on both sides of the metal frame 110 so that the source region 131 and the gate region 132 are positioned on the other side with respect to the drain region 133 located under the semiconductor layer 101 . can be formed. The insulating hole is formed symmetrically on both sides of the metal frame 110 so that the source region 131 and the gate region 132 have substantially the same area.

In addition, the insulating hole is formed to penetrate from the upper surface to the lower surface of the metal frame 110 or to penetrate from the upper surface to one side of the metal frame 110 to become a barrier rib dividing each region of the source, drain, and gate.

The metal frame 110 is created by filling the remaining portions except for the insulating hole with a metal material (S2). At this time, the metal material is selected in consideration of the thermal characteristics and thermal expansion coefficient between the semiconductor chip and the package.

The insulating part 120 is formed by filling the insulating holes located on both sides of the frame 110 with an organic material, an inorganic material, and a composite of an organic material and an inorganic material (S3).

When the source, drain, and gate are formed by the insulating part 120 , the semiconductor layer 101 is stacked on the upper surface of the drain region 133 to arrange a semiconductor chip ( S4 ). Then, the source region 131 and the semiconductor chip are electrically connected, and the gate region 132 and the semiconductor chip are electrically connected to complete the package (S5).

Meanwhile, steps S1 to S5 of FIG. 8 may be divided into additional steps or combined into fewer steps according to an embodiment of the present invention. Also, some steps may be omitted if necessary, and the order between steps may be changed.

As described above, the method of manufacturing a high-output power semiconductor device package can replace the conventional insulating layer using ceramic by forming the insulating part 120 as a barrier rib that separates the three terminals of the gate, the source, and the drain in the metal frame 110 . Thus, it is possible to improve fairness and heat dissipation performance.

The GaN transistor package manufactured by the method of manufacturing a high-output power device package according to an embodiment of the present invention may be applied to a high-integration module tegration technology for miniaturizing a module for a 5G base station.

In addition, the high output power device package according to an embodiment of the present invention can be used in various fields such as a mobile communication base station, civil and military radar, and can be applied to various circuits and systems such as RF FEM.

The embodiments of the present invention described above may also be implemented in the form of a recording medium including instructions executable by a computer, such as a program module executed by a computer. Such recording media includes computer-readable media, and computer-readable media can be any available media that can be accessed by a computer, and includes both volatile and nonvolatile media, removable and non-removable media. Computer readable media also includes computer storage media, which include volatile and nonvolatile embodied in any method or technology for storage of information, such as computer readable instructions, data structures, program modules, or other data. , both removable and non-removable media.

The above description of the present invention is for illustration, and those of ordinary skill in the art to which the present invention pertains can understand that it can be easily modified into other specific forms without changing the technical spirit or essential features of the present invention. will be. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. For example, each component described as a single type may be implemented in a distributed manner, and likewise components described as distributed may be implemented in a combined form.

The scope of the present invention is indicated by the following claims rather than the above detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present invention. do.

100: high output power semiconductor device package
101: semiconductor layer
110: metal frame
120: insulation
131: source area
132: gate area
133: drain region

Claims (7)

In the high output power semiconductor device package,
a metal frame having a semiconductor layer stacked on an upper surface thereof and including insulating holes formed on both sides around the semiconductor layer;
a semiconductor chip disposed on the semiconductor layer;
Including an insulating portion formed by filling the hole for insulation with an organic material or an inorganic material,
A source region, a drain region, and a gate region are separated by the insulating portion to form an electrode,
and electrically connecting the source region and the semiconductor chip, and electrically connecting the gate region and the semiconductor chip. According to claim 1,
The metal frame, which is formed of any one of a metal material including aluminum (Al), copper (CU), Kovar (Kova), high output power semiconductor device package. According to claim 1,
The metal frame has a seating groove formed in the center, and the semiconductor layer is stacked in the seating groove, a high output power semiconductor device package. According to claim 1,
The insulating hole is formed in a form penetrating from the upper surface to the lower surface of the metal frame, and is formed in a symmetrical form on both sides of the metal frame, a high output power semiconductor device package. According to claim 1,
The insulating hole is formed in a form penetrating from the upper surface to one side of the metal frame, and is formed in a symmetrical form on both sides of the metal frame, high output power semiconductor device package. A method for manufacturing a high output power semiconductor device package, comprising:
a process of selecting a position of an insulating hole for dividing a source region, a drain region, and a gate region;
creating a metal frame by filling the remaining portions except for the insulating hole with a metal material;
forming an insulating part by filling the insulating hole with an organic or inorganic substance;
arranging a semiconductor chip by stacking a semiconductor layer on an upper surface of the drain region; and
and electrically connecting the source region and the semiconductor chip, and electrically connecting the gate region and the semiconductor chip. 7. The method of claim 6,
The process of forming an insulating part by filling the insulating hole with an organic or inorganic substance,
An insulating part is formed in any one of a method of penetrating from the upper surface to the lower surface of the metal frame and penetrating from the upper surface to one side of the metal frame, so that the insulating part separates the source region, the drain region, and the gate region A method of manufacturing a high-output power semiconductor device package that serves as a barrier rib.

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