KR20210124157A - Low density parity check encoder with 64800 length and 4/15 rate, and method using the same - Google Patents

Abstract

Disclosed are an LDPC encoder, a decoder, and an LDPC encoding method. According to an embodiment of the present invention, the LDPC encoder comprises: a first memory for storing an LDPC codeword having a length of 64800 and a code rate of 4/15; a second memory initialized to zero; and a processor configured to generate the LDPC codeword corresponding to information bits by performing accumulation on the second memory by using a sequence corresponding to a parity check matrix.

Description

LDPC encoder with length 64800 and code rate of 4/15 and LDPC encoding method using the same {LOW DENSITY PARITY CHECK ENCODER WITH 64800 LENGTH AND 4/15 RATE, AND METHOD USING THE SAME}

The present invention relates to an LDPC (Low Density Parity Check) code for correcting an error occurring in a wireless channel, and more particularly, to an LDPC code applicable to a digital broadcasting system.

Since the current terrestrial TV broadcasting generates co-channel interference corresponding to three times the service change, the same frequency cannot be reused in an area within three times the service radius. As such, a region where the same frequency cannot be reused is called a white space, and the spectral efficiency is very low due to the occurrence of the white space.

Therefore, there is a need to develop a transmission technology that is easy to remove white space and reuse frequencies with an emphasis on reception robustness to improve spectral efficiency.

Accordingly, in September 2012 IEEE Transactions on Broadcasting, vol. 58, no.3 in the academic literature "Cloud Transmission: A New Spectrum-Reuse Friendly Digital Terrestrial Broadcasting Transmission System", terrestrial cloud that is easy to reuse, does not generate white space, and is easy to build and operate a single frequency network Broadcast technology was proposed.

Using such terrestrial cloud broadcasting technology, broadcasters can transmit the same nationwide or different broadcasting contents for each region through one broadcasting channel. However, for this, the receiver must be able to receive one or more terrestrial cloud broadcasting signals in an area where signals transmitted from different transmitters overlap in a single frequency network, that is, in an overlapping area, and the received terrestrial cloud broadcasting signals can be classified and demodulated. there should be That is, in a situation where co-channel interference exists and timing and frequency synchronization of each transmission signal is not guaranteed, the receiver must be able to demodulate one or more cloud broadcasting signals.

Meanwhile, "LDPC code for terrestrial cloud broadcasting" of Korean Patent Laid-Open No. 2013-0135746 discloses an LDPC code that is optimized for terrestrial cloud broadcasting and shows excellent performance at a low code rate (<0.5).

However, Korean Patent Application Laid-Open No. 2013-0135746 relates to a code length completely different from the LDPC code length used in the DVB broadcasting standard, and is silent about a specific LDPC encoding method.

An object of the present invention is to provide a new LDPC codeword having a codeword length of 64800 and a code rate of 4/15 that can be used universally.

In addition, it is another object of the present invention to efficiently encode LDPC using a sequence having the number of rows corresponding to the value obtained by dividing the sum of 17280, which is the length of the systematic part of the LDPC codeword, and 1800, which is the length of the first parity part, by 360. To provide an LDPC encoding technique capable of performing

An LDPC encoder according to the present invention for achieving the above object includes: a first memory for storing an LDPC codeword having a length of 64800 and a code rate of 4/15; a second memory initialized to zero; and a processor configured to generate the LDPC codeword corresponding to information bits by performing accumulation on the second memory using a sequence corresponding to a parity check matrix. do.

In this case, the accumulation may be performed on parity bit addresses that are updated using a sequence corresponding to a parity check matrix.

In this case, the LDPC codeword corresponds to the information bits and has a length of 17280, a systematic part, a first parity part corresponding to a double diagonal matrix included in the parity check matrix and a length of 1800, and the parity check matrix. A second parity part corresponding to the identity matrix included in , and having a length of 45720 may be included.

At this time, the sequence is the number obtained by adding the value obtained by dividing the length of the systematic part by 17280, which is the length of the systematic part by 360, which is the CPM size corresponding to the parity check matrix, and 1800, the length of the first parity part, divided by the CPM size. It can have rows.

In this case, the sequence may be represented by the following table.

[table]

Line 1: 276 1754 1780 3597 8549 15196 26305 27003 33883 37189 41042 41849 42356

Line 2: 730 873 927 9310 9867 17594 21969 25106 25922 31167 35434 37742 45866

Line 3: 925 1202 1564 2575 2831 2951 5193 13096 18363 20592 33786 34090 40900

Line 4: 973 1045 1071 8545 8980 11983 18649 21323 22789 22843 26821 36720 37856

Line 5: 402 1038 1689 2466 2893 13474 15710 24137 29709 30451 35568 35966 46436

Line 6: 263 271 395 5089 5645 15488 16314 28778 29729 34350 34533 39608 45371

Line 7: 387 1059 1306 1955 6990 20001 24606 28167 33802 35181 38481 38688 45140

Line 8: 53 851 1750 3493 11415 18882 20244 23411 28715 30722 36487 38019 45416

Line 9: 810 1044 1772 3906 5832 16793 17333 17910 23946 29650 34190 40673 45828

Line 10: 97 491 948 12156 13788 24970 33774 37539 39750 39820 41195 46464 46820

Line 11: 192 899 1283 3732 7310 13637 13810 19005 24227 26772 31273 37665 44005

Line 12: 424 531 1300 4860 8983 10137 16323 16888 17933 22458 26917 27835 37931

Line 13: 130 279 731 3024 6378 18838 19746 21007 22825 23109 28644 32048 34667

Line 14: 938 1041 1482 9589 10065 11535 17477 25816 27966 35022 35025 42536

Line 15: 170 454 1312 5326 6765 23408 24090 26072 33037 38088 42985 46413

Line 16: 220 804 843 2921 4841 7760 8303 11259 21058 21276 34346 37604

Line 17: 676 713 832 11937 12006 12309 16329 26438 34214 37471 38179 42420

Line 18: 714 931 1580 6837 9824 11257 15556 26730 32053 34461 35889 45821

Line 19: 28 1097 1340 8767 9406 17253 29558 32857 37856 38593 41781 47101

Line 20: 158 722 754 14489 23851 28160 30371 30579 34963 44216 46462 47463

Line 21: 833 1326 1332 7032 9566 11011 21424 26827 29789 31699 32876 37498

Line 22: 251 504 1075 4470 7736 11242 20397 32719 34453 36571 40344 46341

Line 23: 330 581 868 15168 20265 26354 33624 35134 38609 44965 45209 46909

Line 24: 729 1643 1732 3946 4912 9615 19699 30993 33658 38712 39424 46799

Line 25: 546 982 1274 9264 11017 11868 15674 16277 19204 28606 39063 43331

Line 26: 73 1160 1196 4334 12560 13583 14703 18270 18719 19327 38985 46779

Line 27: 1147 1625 1759 3767 5912 11599 18561 19330 29619 33671 43346 44098

Line 28: 104 1507 1586 9387 17890 23532 27008 27861 30966 33579 35541 39801

Line 29: 1700 1746 1793 4941 7814 13746 20375 27441 30262 30392 35385 42848

Line 30: 183 555 1029 3090 5412 8148 19662 23312 23933 28179 29962 35514

Line 31: 891 908 1127 2827 4077 4376 4570 26923 27456 33699 43431 46071

Line 32: 404 1110 1782 6003 14452 19247 26998 30137 31404 31624 46621 47366

Line 33: 886 1627 1704 8193 8980 9648 10928 16267 19774 35111 38545 44735

Line 34: 268 380 1214 4797 5168 9109 9288 17992 21309 33210 36210 41429

Line 35: 572 1121 1165 6944 7114 20978 23540 25863 26190 26365 41521 44690

Line 36: 18 185 496 5885 6165 20468 23895 24745 31226 33680 37665 38587

Line 37: 289 527 1118 11275 12015 18088 22805 24679 28262 30160 34892 43212

Line 38: 658 926 1589 7634 16231 22193 25320 26057 26512 27498 29472 34219

Line 39: 337 801 1525 2023 3512 16031 26911 32719 35620 39035 43779 44316

Line 40: 248 534 670 6217 11430 24090 26509 28712 33073 33912 38048 39813

Line 41: 82 1556 1575 7879 7892 14714 22404 22773 25531 34170 38203 38254

Line 42: 247 313 1224 3694 14304 24033 26394 28101 37455 37859 38997 41344

Line 43: 790 887 1418 2811 3288 9049 9704 13303 14262 38149 40109 40477

Line 44: 1310 1384 1471 3716 8250 25371 26329 26997 30138 40842 41041 44921

Line 45: 86 288 367 1860 8713 18211 22628 22811 28342 28463 40415 45845

Line 46: 719 1438 1741 8258 10797 29270 29404 32096 34433 34616 36030 45597

Line 47: 215 1182 1364 8146 9949 10498 18603 19304 19803 23685 43304 45121

Line 48: 1243 1496 1537 8484 8851 16589 17665 20152 24283 28993 34274 39795

Line 49: 6320 6785 15841 16309 20512 25804 27421 28941 43871 44647

Line 50: 2207 2713 4450 12217 16506 21188 23933 28789 38099 42392

Line 51: 14064 14307 14599 14866 17540 18881 21065 25823 30341 36963

Line 52: 14259 14396 17037 26769 29219 29319 31689 33013 35631 37319

Line 53: 7798 10495 12868 14298 17221 23344 31908 39809 41001 41965

In this case, the accumulation may be performed while changing the rows of the sequence in units of the CPM size (L) of the parity check matrix.

In addition, an LDPC encoding method according to an embodiment of the present invention includes the steps of: initializing a first memory and a second memory for storing an LDPC codeword; and generating the LDPC codeword corresponding to information bits by performing accumulation on the second memory using a sequence corresponding to a parity check matrix. do.

In this case, the accumulation may be performed on parity bit addresses that are updated using a sequence corresponding to a parity check matrix.

In this case, the LDPC codeword has a systematic part having a length of 17280 corresponding to the information bits, a first parity part corresponding to a double diagonal matrix included in the parity check matrix and having a length of 1800, and the parity check matrix A second parity part corresponding to the identity matrix included in , and having a length of 45720 may be included.

At this time, the sequence is the number obtained by adding the value obtained by dividing the length of the systematic part by 17280, which is the length of the systematic part by 360, which is the CPM size corresponding to the parity check matrix, and 1800, the length of the first parity part, divided by the CPM size. It can have rows.

In this case, the sequence may be represented by the table.

In addition, an LDPC decoder according to an embodiment of the present invention includes: a receiver for receiving a LDPC (Low Density Parity Check) codeword, which is coded using a sequence corresponding to a parity check matrix and represented by the table; and a decoding unit that performs decoding corresponding to the parity check matrix to restore information bits from the received LDPC codeword.

According to the present invention, a new LDPC codeword having a codeword length of 64800 and a code rate of 4/15 that can be used universally is provided.

In addition, the present invention efficiently performs LDPC encoding using a sequence having the number of rows corresponding to a value obtained by dividing the sum of 17280, which is the length of the systematic part of the LDPC codeword, and 1800, which is the length of the first parity part, by 360. can do.

1 is a block diagram illustrating a broadcast signal transmission/reception system according to an embodiment of the present invention.
2 is an operation flowchart illustrating a broadcast signal transmission/reception method according to an embodiment of the present invention.
3 is a diagram illustrating a structure of a parity check matrix corresponding to an LDPC code according to an embodiment of the present invention.
4 is a block diagram illustrating an LDPC encoder according to an embodiment of the present invention.
5 is a block diagram illustrating an LDPC decoder according to an embodiment of the present invention.
6 is a flowchart illustrating an LDPC encoding method according to an embodiment of the present invention.
7 is a graph showing the performance of a QC-LDPC code having a length of 64800 and a code rate of 4/15 _{compared to E b} /N _{o according to an embodiment of the present invention.}

The present invention will be described in detail with reference to the accompanying drawings as follows. Here, repeated descriptions, well-known functions that may unnecessarily obscure the gist of the present invention, and detailed descriptions of configurations will be omitted. The embodiments of the present invention are provided in order to more completely explain the present invention to those of ordinary skill in the art. Accordingly, the shapes and sizes of elements in the drawings may be exaggerated for clearer description.

Hereinafter, preferred embodiments according to the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram illustrating a broadcast signal transmission/reception system according to an embodiment of the present invention.

Referring to FIG. 1 , it can be seen that the transmitter 10 and the receiver 30 communicate via the wireless channel 20 .

The transmitter 10 encodes k-bit information bits 11 in the LDPC encoder 13 to generate an n-bit codeword. The codeword is modulated by a modulator (15) and transmitted via an antenna (17). A signal transmitted through the wireless channel 20 is received through the antenna 31 of the receiver 30 , and the receiver 30 undergoes a reverse process of the process that occurred in the transmitter 10 . That is, the received data may be demodulated by the demodulator 33 and decoded by the LDPC decoder 35 to finally recover information bits.

It is apparent to those skilled in the art that, in addition to the above-described transmission/reception process being described within the minimum range necessary to describe the characteristics of the present invention, many processes necessary for data transmission may be added.

Hereinafter, a specific process of encoding or decoding through the LDPC code in the LDPC encoder 13 or the LDPC decoder 35 and a specific configuration of an encoding or decoding device such as the LDPC encoder 13 or the LDPC decoder 35 will be described. explain about The LDPC encoder 13 shown in FIG. 1 may have the structure shown in FIG. 4 , and the LDPC decoder 35 may have the structure shown in FIG. 5 .

2 is an operation flowchart illustrating a broadcast signal transmission/reception method according to an embodiment of the present invention.

Referring to FIG. 2 , in the method for transmitting/receiving a broadcast signal according to an embodiment of the present invention, input bits are first LDPC-encoded (S210).

That is, in step S210, k-bit information bits are encoded in the LDPC encoder to generate an n-bit codeword.

In this case, step S210 may be performed like the LDPC encoding method shown in FIG. 6 .

In addition, the broadcast signal transmission/reception method modulates the encoded data (S220).

That is, in step S220, the encoded n-bit codeword is modulated by the modulator.

In addition, the broadcast signal transmission/reception method transmits modulated data (S230).

That is, in step S230, the modulated codeword is transmitted to the radio channel through the antenna.

In addition, the broadcast signal transmission/reception method demodulates the received data (S240).

That is, in step S240, a signal transmitted through a radio channel is received through an antenna of a receiver, and the received data is demodulated by a demodulator.

In addition, the broadcast signal transmission/reception method LDPC-decodes demodulated data (S250).

That is, in step S250, the information bits are finally restored by performing LDPC decoding through a demodulator of the receiver.

In this case, step S250 corresponds to the reverse process of the LDPC encoding method illustrated in FIG. 6 and may correspond to the LDPC decoder of FIG. 5 .

The LDPC (Low Density Parity Check) code is known as a code close to the Shannon limit in the AWGN (Additive White Gaussian Noise) channel, and has asymptotically superior performance than the turbo code, parallel decoding, etc. has the advantage of

In general, the LDPC code is defined by a randomly generated low density PCM (parity check matrix). However, the randomly generated LDPC code not only requires a lot of memory to store the PCM, but also takes a lot of time to access the memory. To solve this problem, a quasi-cyclic LDPC (QC-LDPC) code has been proposed, and the QC-LDPC code composed of a zero matrix or CPM (Circulant Permutation Matrix) is expressed by It is defined by the PCM represented by 1.

[Equation 1]

Here, J is a CPM having a size of L x L and is given by Equation 2 below. Hereinafter, L may be 360.

[Equation 2]

In addition, J ⁱ is the L x L identity matrix I(=J ⁰ ) shifted to the right i(0=i<L) times, and J ^∞ is the L x L zero matrix. Accordingly, in the QC-LDPC code, ^{since only the exponent i needs} to be stored to store J i , the memory required to store the PCM is greatly reduced.

3 is a diagram illustrating a structure of a parity check matrix corresponding to an LDPC code according to an embodiment of the present invention.

Referring to FIG. 3 , the sizes of matrices A and C are g x K and (N-K-g) x (K+g), respectively, and are composed of a zero matrix having a size of L x L and a CPM. Also, matrix z is a zero matrix of size gx (NKg), matrix D is an identity matrix of size (NKg) x (NKg), and matrix B is a dual diagonal matrix of size gxg matrix). In this case, the matrix B may be a matrix in which all elements other than the diagonal element and the elements adjacent to the bottom of the diagonal are all 0, or may be defined as in Equation 3 below.

[Equation 3]

Here, I _LxL is an identity matrix of size L x L.

That is, the matrix B may be a bit-wise double diagonal matrix or a block-wise double diagonal matrix using the identity matrix as a block as expressed in Equation 3 above. A general (bit-wise) double diagonal matrix is disclosed in detail in Korean Patent Application Laid-Open No. 2007-0058438 or the like.

In particular, when the matrix B is a bit-wise double diagonal matrix, row permutation or column permutation is applied to the PCM of the structure shown in FIG. 3 including the matrix B. It is apparent to those skilled in the art that conversion to quasi-cyclic is possible.

In this case, N is the length of a codeword, and K is the length of information.

In the present invention, as shown in Table 1 below, a newly designed QC-LDPC code having a code rate of 4/15 and a codeword length of 64800 is proposed. That is, an LDPC code that receives information having a length of 17280 and generates an LDPC codeword having a length of 64800 is proposed.

Table 1 shows the sizes of the A, B, C, D, and Z matrices of the QC-LDPC code of the present invention.

[Table 1]

The newly designed LDPC code may be expressed in the form of a sequence, an equivalent relationship is established between the sequence and the matrix (parity bit check matrix), and the sequence may be expressed as shown in the table below.

[table]

Line 1: 276 1754 1780 3597 8549 15196 26305 27003 33883 37189 41042 41849 42356

Line 2: 730 873 927 9310 9867 17594 21969 25106 25922 31167 35434 37742 45866

Line 3: 925 1202 1564 2575 2831 2951 5193 13096 18363 20592 33786 34090 40900

Line 4: 973 1045 1071 8545 8980 11983 18649 21323 22789 22843 26821 36720 37856

Line 5: 402 1038 1689 2466 2893 13474 15710 24137 29709 30451 35568 35966 46436

Line 6: 263 271 395 5089 5645 15488 16314 28778 29729 34350 34533 39608 45371

Line 7: 387 1059 1306 1955 6990 20001 24606 28167 33802 35181 38481 38688 45140

Line 8: 53 851 1750 3493 11415 18882 20244 23411 28715 30722 36487 38019 45416

Line 9: 810 1044 1772 3906 5832 16793 17333 17910 23946 29650 34190 40673 45828

Line 10: 97 491 948 12156 13788 24970 33774 37539 39750 39820 41195 46464 46820

Line 11: 192 899 1283 3732 7310 13637 13810 19005 24227 26772 31273 37665 44005

Line 12: 424 531 1300 4860 8983 10137 16323 16888 17933 22458 26917 27835 37931

Line 13: 130 279 731 3024 6378 18838 19746 21007 22825 23109 28644 32048 34667

Line 14: 938 1041 1482 9589 10065 11535 17477 25816 27966 35022 35025 42536

Line 15: 170 454 1312 5326 6765 23408 24090 26072 33037 38088 42985 46413

Line 16: 220 804 843 2921 4841 7760 8303 11259 21058 21276 34346 37604

Line 17: 676 713 832 11937 12006 12309 16329 26438 34214 37471 38179 42420

Line 18: 714 931 1580 6837 9824 11257 15556 26730 32053 34461 35889 45821

Line 19: 28 1097 1340 8767 9406 17253 29558 32857 37856 38593 41781 47101

Line 20: 158 722 754 14489 23851 28160 30371 30579 34963 44216 46462 47463

Line 21: 833 1326 1332 7032 9566 11011 21424 26827 29789 31699 32876 37498

Line 22: 251 504 1075 4470 7736 11242 20397 32719 34453 36571 40344 46341

Line 23: 330 581 868 15168 20265 26354 33624 35134 38609 44965 45209 46909

Line 24: 729 1643 1732 3946 4912 9615 19699 30993 33658 38712 39424 46799

Line 25: 546 982 1274 9264 11017 11868 15674 16277 19204 28606 39063 43331

Line 26: 73 1160 1196 4334 12560 13583 14703 18270 18719 19327 38985 46779

Line 27: 1147 1625 1759 3767 5912 11599 18561 19330 29619 33671 43346 44098

Line 28: 104 1507 1586 9387 17890 23532 27008 27861 30966 33579 35541 39801

Line 29: 1700 1746 1793 4941 7814 13746 20375 27441 30262 30392 35385 42848

Line 30: 183 555 1029 3090 5412 8148 19662 23312 23933 28179 29962 35514

Line 31: 891 908 1127 2827 4077 4376 4570 26923 27456 33699 43431 46071

Line 32: 404 1110 1782 6003 14452 19247 26998 30137 31404 31624 46621 47366

Line 33: 886 1627 1704 8193 8980 9648 10928 16267 19774 35111 38545 44735

Line 34: 268 380 1214 4797 5168 9109 9288 17992 21309 33210 36210 41429

Line 35: 572 1121 1165 6944 7114 20978 23540 25863 26190 26365 41521 44690

Line 36: 18 185 496 5885 6165 20468 23895 24745 31226 33680 37665 38587

Line 37: 289 527 1118 11275 12015 18088 22805 24679 28262 30160 34892 43212

Line 38: 658 926 1589 7634 16231 22193 25320 26057 26512 27498 29472 34219

Line 39: 337 801 1525 2023 3512 16031 26911 32719 35620 39035 43779 44316

Line 40: 248 534 670 6217 11430 24090 26509 28712 33073 33912 38048 39813

Line 41: 82 1556 1575 7879 7892 14714 22404 22773 25531 34170 38203 38254

Line 42: 247 313 1224 3694 14304 24033 26394 28101 37455 37859 38997 41344

Line 43: 790 887 1418 2811 3288 9049 9704 13303 14262 38149 40109 40477

Line 44: 1310 1384 1471 3716 8250 25371 26329 26997 30138 40842 41041 44921

Line 45: 86 288 367 1860 8713 18211 22628 22811 28342 28463 40415 45845

Line 46: 719 1438 1741 8258 10797 29270 29404 32096 34433 34616 36030 45597

Line 47: 215 1182 1364 8146 9949 10498 18603 19304 19803 23685 43304 45121

Line 48: 1243 1496 1537 8484 8851 16589 17665 20152 24283 28993 34274 39795

Line 49: 6320 6785 15841 16309 20512 25804 27421 28941 43871 44647

Line 50: 2207 2713 4450 12217 16506 21188 23933 28789 38099 42392

Line 51: 14064 14307 14599 14866 17540 18881 21065 25823 30341 36963

Line 52: 14259 14396 17037 26769 29219 29319 31689 33013 35631 37319

Line 53: 7798 10495 12868 14298 17221 23344 31908 39809 41001 41965

LDPC codes expressed in sequence form are widely used in the DVB standard.

를 생성한다. 여기서, M₁=g, M₂=N-K-g이다. 또한, M₁은 이중 대각행렬(dual diagonal matrix) B에 대응하는 패러티(parity)의 크기이며, M₂는 항등행렬 D에 대응하는 패러티의 크기이다. 부호화 과정은 다음과 같다.According to an embodiment of the present invention, the LDPC code expressed in the form of a sequence is encoded as follows. Assume that an information block having an information size of K S=(s ₀ , s ₁ , ..., s _K-1 ). The LDPC encoder uses an information block S having a size of K to obtain a codeword having _{a size of N=K+M 1} +M ₂

create Here, M ₁ =g, M ₂ =NKg. Also, M ₁ is the size of parity corresponding to the dual diagonal matrix B, and M ₂ is the size of the parity corresponding to the identity matrix D. The encoding process is as follows.

-Initialization:

[Equation 4]

를 상기 테이블의 수열의 제1행에 명시된 패러티 비트 주소들(parity bit addresses)에서 누적(accumulate)한다. 예를 들어, 길이가 64800이며, 부호율이 4/15인 LDPC 부호에서의 누적 과정은 다음과 같다.-First

is accumulated from the parity bit addresses specified in the first row of the sequence of the table. For example, an accumulation process in an LDPC code having a length of 64800 and a code rate of 4/15 is as follows.

)은 GF(2)에서 일어난다.Add here (

) occurs in GF(2).

들에 대해서는, 하기 수학식 5에서 계산된 패러티 비트 주소들에서 누적한다.-Next L-1 information bits, that is,

, are accumulated at the parity bit addresses calculated in Equation 5 below.

[Equation 5]

에 대응되는 패러티 비트 주소들, 즉 상기 테이블의 수열의 제1행에 표기된 패러티 비트 주소들을 나타내며, Q₁ = M₁/L, Q₂ = M₂/L, L = 360이다. 또한, Q₁과 Q₂는 하기 표 2에 정의된다. 예를 들어, 길이가 64800이며, 부호율이 4/15인 LDPC 부호는 M₁ = 1800, Q₁ = 5, M₂ = 45720, Q₂ = 127, L = 360이므로, 두 번째 비트

에 대해서는 상기 수학식 5를 이용하면 다음과 같은 연산이 수행된다.where x is the first bit

Parity bit addresses corresponding to , ie, parity bit addresses indicated in the first row of the sequence of the table, are Q ₁ = M ₁ /L, Q ₂ = M ₂ /L, and L = 360. In addition, Q ₁ and Q ₂ are defined in Table 2 below. For example, an LDPC code with a length of 64800 and a code rate of 4/15 is M ₁ = 1800, Q ₁ = 5, M ₂ = 45720, Q ₂ = 127, L = 360, so the second bit

With respect to Equation 5 above, the following operation is performed.

Table 2 shows the sizes _{of M 1} , M ₂ , Q ₁ , and Q ₂ of the designed QC-LDPC code.

[Table 2]

부터

까지의 새로운 360개의 정보비트들은 상기 수열의 제2행을 이용하여, 상기 수학식 5로부터 패러티 비트 누적기들의 주소를 계산하고, 누적한다.-the next

from

For the new 360 information bits up to, the addresses of the parity bit accumulators are calculated from Equation (5) and accumulated using the second row of the sequence.

- In a similar way, for all groups composed of the new L information bits, the addresses of the parity bit accumulators are calculated and accumulated from Equation 5 using the new row of the sequence.

에서

까지의 모든 정보비트들이 사용된 후, i = 1부터 시작하여 하기 수학식 6의 연산을 순차적으로 수행한다.-

at

After all information bits up to , are used, the operation of Equation 6 below is sequentially performed starting from i = 1.

[Equation 6]

- Next, when parity interleaving is performed as in Equation 7 below, parity generation corresponding to the double diagonal matrix B is completed.

[Equation 7]

)를 이용하여 이중 대각행렬 B에 대응하는 패러티 생성이 완료되면, M₁개의 생성된 패러티(

)을 이용하여, 항등행렬 D에 대응하는 패러티를 생성한다.K information bits (

), when the parity generation corresponding to the double diagonal matrix B is completed, M ₁ generated parity (

) to generate a parity corresponding to the identity matrix D.

에서

까지의 L개의 비트들로 구성된 모든 그룹(group)들에 대해서, 상기 수열들의 새로운 행(이중 대각행렬 B에 대응하는 패러티를 생성할 때 이용한 마지막 행의 바로 다음 행부터 시작)과 상기 수학식 5를 이용하여 패러티 비트 누적기들의 주소를 계산하고, 관련 연산을 수행한다.-

at

For all groups consisting of L bits up to, a new row of the sequence (starting from the row immediately following the last row used to generate the parity corresponding to the double diagonal matrix B) and Equation 5 Calculate the addresses of parity bit accumulators using , and perform related operations.

에서

까지의 모든 비트들이 사용된 후, 하기 수학식 8과 같은 패러티 인터리빙을 수행하면, 항등행렬 D에 대응하는 패러티 생성이 완료된다.-

at

After all bits up to , parity interleaving as in Equation 8 is performed, parity generation corresponding to the identity matrix D is completed.

[Equation 8]

4 is a block diagram illustrating an LDPC encoder according to an embodiment of the present invention.

Referring to FIG. 4 , the LDPC encoder according to an embodiment of the present invention includes memories 310 and 320 and a processor 330 .

The memory 310 is a memory for storing an LDPC codeword having a length of 64800 and a code rate of 4/15.

The memory 320 is a memory initialized to zero.

Memory 310 and memory 320 have λ _i (i=0, 1, ..., N-1) and P _j (j=0, 1, ..., M ₁ +M ₂ -1), respectively. may correspond to

The memory 310 and the memory 320 may correspond to various hardware for storing a set of bits, and may include data structures such as an array, a list, a stack, and a queue ( data structure).

The processor 330 performs accumulation on the memory 320 using a sequence corresponding to a parity check matrix to generate the LDPC codeword corresponding to information bits. create

In this case, the accumulation may be performed on parity bit addresses updated using a sequence of the table.

In this case, the LDPC codeword corresponds to the information bits and is a systematic part (λ ₀ , λ ₁ , ..., λ _K-1 ) having a length of 17280 (=K), included in the parity check matrix. The first parity part (λ _K , λ _K+1 , ..., λ _K+M1-1 ) corresponding to the double diagonal matrix and having a length of 1800 (=M ₁ =g) and the identity included in the parity check matrix It may include a second parity part (λ _K+M1 , λ _K+M1+1 , ..., λ _K+M1+M2-1 ) corresponding to the matrix and having a length of 45720 (=M _{2 ).}

At this time, the sequence is a value obtained by dividing 17280, which is the length of the systematic part, by 360, which is the CPM size (L) corresponding to the parity check matrix, and 1800, which is _{the length of the first parity part (M 1 ) divided by 360.} It may have as many rows as the sum (17280/360+1800/360=53).

As described above, the sequence may be represented by the table.

In this case, the memory 320 may have a size corresponding to the sum (M ₁ +M _{2 ) of the length (M 1} ) of the first parity part and the length (M _{2 ) of the second parity part.}

In this case, the parity bit addresses may be updated based on a result of comparing each of the previous parity bit addresses (x) and the length (M _{1 ) of the first parity part indicated in each row of the sequence.}

That is, the parity bit addresses may be updated according to Equation 5 above. In this case, x is the previous parity bit address, m is an information bit index, an integer greater than 0 and smaller than L, L is the CPM size of the parity check matrix, Q ₁ is M ₁ /L, M ₁ is the first parity part The size of Q ₂ may be M ₂ /L, and M ₂ may be the size of the second parity part.

In this case, as described above, the accumulation may be performed while changing the rows of the sequence in units of the CPM size L=360 of the parity check matrix.

At this time, the first parity part (λ _K , λ _K+1 , ..., λ _K+M1-1 ) uses the memory 310 and the memory 320 as described in Equation 7 above, It may be generated by performing parity interleaving.

In this case, the second parity part (λ _K+M1 , λ _K+M1+1 , ..., λ _K+M1+M2-1 ) is the first parity part (λ _{K ) as described through Equation (8).} , λ _K+1 , ..., λ _K+M1-1 ) After generation of the first parity part (λ _K , λ _K+1 , ..., λ _K+M1-1 ) and the sequence After the accumulation performed by using the , it may be generated by performing parity interleaving using the memory 310 and the memory 320 .

5 is a block diagram illustrating an LDPC decoder according to an embodiment of the present invention.

Referring to FIG. 5 , the LDPC decoder according to an embodiment of the present invention includes a receiver 410 and a decoder 420 .

The receiving unit 410 receives a LDPC (Low Density Parity Check) codeword that corresponds to the parity check matrix and is encoded using a sequence represented by the table.

The decoder 420 reconstructs information bits from the received LDPC codeword by performing decoding corresponding to the parity check matrix.

In this case, the sequence is used to update parity bit addresses of a memory, and the parity bit addresses may be used for accumulation for generating parity bits corresponding to the LDPC codeword.

In this case, the LDPC codeword corresponds to the systematic part (λ ₀ , λ ₁ , ..., λ _K-1 ) corresponding to the information bits, and the first corresponding to the double diagonal matrix included in the parity check matrix. The parity parts (λ _K , λ _K+1 , ..., λ _{K+M1-1 ) and the second parity part (λ K+M1} , λ _{K+M1+ )} corresponding to the identity matrix included in the parity check matrix ₁ , ..., λ _K+M1+M2-1 ).

In this case, the parity bit addresses may be updated based on a result of comparing each of the previous parity bit addresses (x) and the length (M _{1 ) of the first parity part indicated in each row of the sequence.}

That is, the parity bit addresses may be updated according to Equation 5 above. In this case, x is the previous parity bit address, m is an information bit index, an integer greater than 0 and smaller than L, L is the CPM size of the parity check matrix, Q ₁ is M ₁ /L, M ₁ is the first parity part The size of Q ₂ may be M ₂ /L, and M ₂ may be the size of the second parity part.

6 is a flowchart illustrating an LDPC encoding method according to an embodiment of the present invention.

Referring to FIG. 6 , in the LDPC encoding method according to an embodiment of the present invention, a first memory and a second memory for storing an LDPC codeword are initialized ( S510 ).

In this case, step S510 may be performed according to Equation 4 above.

In addition, the LDPC encoding method according to an embodiment of the present invention performs accumulation on the second memory by using a sequence corresponding to a parity check matrix, so that information bits Generates the LDPC codeword corresponding to (S520).

In this case, the accumulation may be performed on parity bit addresses that are updated using a sequence corresponding to a parity check matrix.

In this case, the LDPC codeword corresponds to the information bits and is a systematic part (λ ₀ , λ ₁ , ..., λ _K-1 ) having a length of 17280 (=K), included in the parity check matrix. The first parity part (λ _K , λ _K+1 , ..., λ _K+M1-1 ) corresponding to the double diagonal matrix and having a length of 1800 (=M ₁ =g) and the identity included in the parity check matrix It may include a second parity part (λ _K+M1 , λ _K+M1+1 , ..., λ _K+M1+M2-1 ) corresponding to the matrix and having a length of 45720 (=M _{2 ).}

At this time, the sequence is a value obtained by dividing 17280, which is the length of the systematic part, by 360, which is the CPM size (L) corresponding to the parity check matrix, and 1800, which is _{the length of the first parity part (M 1 ) divided by 360.} It may have as many rows as the sum (17280/360+1800/360=53).

As described above, the sequence may be represented by the table.

In this case, the parity bit addresses may be updated based on a result of comparing each of the previous parity bit addresses (x) and the length (M _{1 ) of the first parity part indicated in each row of the sequence.}

That is, the parity bit addresses may be updated according to Equation 5 above. In this case, x is the previous parity bit address, m is an information bit index, an integer greater than 0 and smaller than L, L is the CPM size of the parity check matrix, Q ₁ is M ₁ /L, M ₁ is the first parity part The size of Q ₂ may be M ₂ /L, and M ₂ may be the size of the second parity part.

In this case, as described above, the accumulation may be performed while changing the rows of the sequence in units of the CPM size L=360 of the parity check matrix.

In this case, the first parity parts λ _K , λ _K+1 , ..., λ _K+M1-1 are parity interleaving using the first memory and the second memory, as described in Equation 7 above. (parity interleaving) may be performed.

In this case, the second parity part (λ _K+M1 , λ _K+M1+1 , ..., λ _K+M1+M2-1 ) is the first parity part (λ _{K ) as described through Equation (8).} , λ _K+1 , ..., λ _K+M1-1 ) After generation of the first parity part (λ _K , λ _K+1 , ..., λ _K+M1-1 ) and the sequence After the accumulation performed by using the , it may be generated by performing parity interleaving using the first memory 310 and the second memory 320 .

7 is a graph showing the performance of a QC-LDPC code having a length of 64800 and a code rate of 4/15 _{compared to E b} /N _{o according to an embodiment of the present invention.}

The graph shown in FIG. 7 is a result of assuming a log-likelihood ratio (LLR)-based sum-product algorithm that performs binary phase shift keying (BPSK) modulation and 50 iterative decoding for a computational experiment. As shown in FIG. 7, it can be seen that the designed code is about 0.5 dB away from the Shannon limit at ^{BER=10 -6.}

As described above, in the LDPC encoder, decoder, and LDPC encoding method according to the present invention, the configuration and method of the above-described embodiments are not limitedly applicable, but the embodiments are each so that various modifications can be made. All or part of the embodiments may be selectively combined and configured.

310, 320: memory
330: processor

Claims (9)

a receiver for receiving a signal corresponding to a LDPC (Low Density Parity Check) codeword having a length of 64800 and a code rate of 4/15, encoded using a sequence corresponding to a parity check matrix; and
A decoding unit that performs decoding on the received signal corresponding to the parity check matrix
LDPC decoder comprising a. The method according to claim 1,
The sequence is represented by the following table.
[table]
Line 1: 276 1754 1780 3597 8549 15196 26305 27003 33883 37189 41042 41849 42356
Line 2: 730 873 927 9310 9867 17594 21969 25106 25922 31167 35434 37742 45866
Line 3: 925 1202 1564 2575 2831 2951 5193 13096 18363 20592 33786 34090 40900
Line 4: 973 1045 1071 8545 8980 11983 18649 21323 22789 22843 26821 36720 37856
Line 5: 402 1038 1689 2466 2893 13474 15710 24137 29709 30451 35568 35966 46436
Line 6: 263 271 395 5089 5645 15488 16314 28778 29729 34350 34533 39608 45371
Line 7: 387 1059 1306 1955 6990 20001 24606 28167 33802 35181 38481 38688 45140
Line 8: 53 851 1750 3493 11415 18882 20244 23411 28715 30722 36487 38019 45416
Line 9: 810 1044 1772 3906 5832 16793 17333 17910 23946 29650 34190 40673 45828
Line 10: 97 491 948 12156 13788 24970 33774 37539 39750 39820 41195 46464 46820
Line 11: 192 899 1283 3732 7310 13637 13810 19005 24227 26772 31273 37665 44005
Line 12: 424 531 1300 4860 8983 10137 16323 16888 17933 22458 26917 27835 37931
Line 13: 130 279 731 3024 6378 18838 19746 21007 22825 23109 28644 32048 34667
Line 14: 938 1041 1482 9589 10065 11535 17477 25816 27966 35022 35025 42536
Line 15: 170 454 1312 5326 6765 23408 24090 26072 33037 38088 42985 46413
Line 16: 220 804 843 2921 4841 7760 8303 11259 21058 21276 34346 37604
Line 17: 676 713 832 11937 12006 12309 16329 26438 34214 37471 38179 42420
Line 18: 714 931 1580 6837 9824 11257 15556 26730 32053 34461 35889 45821
Line 19: 28 1097 1340 8767 9406 17253 29558 32857 37856 38593 41781 47101
Line 20: 158 722 754 14489 23851 28160 30371 30579 34963 44216 46462 47463
Line 21: 833 1326 1332 7032 9566 11011 21424 26827 29789 31699 32876 37498
Line 22: 251 504 1075 4470 7736 11242 20397 32719 34453 36571 40344 46341
Line 23: 330 581 868 15168 20265 26354 33624 35134 38609 44965 45209 46909
Line 24: 729 1643 1732 3946 4912 9615 19699 30993 33658 38712 39424 46799
Line 25: 546 982 1274 9264 11017 11868 15674 16277 19204 28606 39063 43331
Line 26: 73 1160 1196 4334 12560 13583 14703 18270 18719 19327 38985 46779
Line 27: 1147 1625 1759 3767 5912 11599 18561 19330 29619 33671 43346 44098
Line 28: 104 1507 1586 9387 17890 23532 27008 27861 30966 33579 35541 39801
Line 29: 1700 1746 1793 4941 7814 13746 20375 27441 30262 30392 35385 42848
Line 30: 183 555 1029 3090 5412 8148 19662 23312 23933 28179 29962 35514
Line 31: 891 908 1127 2827 4077 4376 4570 26923 27456 33699 43431 46071
Line 32: 404 1110 1782 6003 14452 19247 26998 30137 31404 31624 46621 47366
Line 33: 886 1627 1704 8193 8980 9648 10928 16267 19774 35111 38545 44735
Line 34: 268 380 1214 4797 5168 9109 9288 17992 21309 33210 36210 41429
Line 35: 572 1121 1165 6944 7114 20978 23540 25863 26190 26365 41521 44690
Line 36: 18 185 496 5885 6165 20468 23895 24745 31226 33680 37665 38587
Line 37: 289 527 1118 11275 12015 18088 22805 24679 28262 30160 34892 43212
Line 38: 658 926 1589 7634 16231 22193 25320 26057 26512 27498 29472 34219
Line 39: 337 801 1525 2023 3512 16031 26911 32719 35620 39035 43779 44316
Line 40: 248 534 670 6217 11430 24090 26509 28712 33073 33912 38048 39813
Line 41: 82 1556 1575 7879 7892 14714 22404 22773 25531 34170 38203 38254
Line 42: 247 313 1224 3694 14304 24033 26394 28101 37455 37859 38997 41344
Line 43: 790 887 1418 2811 3288 9049 9704 13303 14262 38149 40109 40477
Line 44: 1310 1384 1471 3716 8250 25371 26329 26997 30138 40842 41041 44921
Line 45: 86 288 367 1860 8713 18211 22628 22811 28342 28463 40415 45845
Line 46: 719 1438 1741 8258 10797 29270 29404 32096 34433 34616 36030 45597
Line 47: 215 1182 1364 8146 9949 10498 18603 19304 19803 23685 43304 45121
Line 48: 1243 1496 1537 8484 8851 16589 17665 20152 24283 28993 34274 39795
Line 49: 6320 6785 15841 16309 20512 25804 27421 28941 43871 44647
Line 50: 2207 2713 4450 12217 16506 21188 23933 28789 38099 42392
Line 51: 14064 14307 14599 14866 17540 18881 21065 25823 30341 36963
Line 52: 14259 14396 17037 26769 29219 29319 31689 33013 35631 37319
Line 53: 7798 10495 12868 14298 17221 23344 31908 39809 41001 41965 3. The method according to claim 2,
The LDPC codeword is
It is generated based on the accumulation performed using the sequence,
The accumulation is a second bit of information bits corresponding to the LDPC codeword.

about

(p _x (0≤x≤47519) is the memory used for the accumulation,

is the addition operator)
An LDPC decoder, characterized in that it is performed using the 13 equations of . 3. The method according to claim 2,
The LDPC codeword is
A systematic part corresponding to information bits and having a length of 17280, a first parity part corresponding to a double diagonal matrix included in the parity check matrix and having a length of 1800, and an identity matrix included in the parity check matrix and a second parity part having a length of 45720. 5. The method according to claim 4,
The sequence is a value obtained by dividing 17280, which is the length of the systematic part, by 360, which is a CPM (Circulant Permutation Matrix) size corresponding to the parity check matrix, plus a value obtained by dividing 1800, which is the length of the first parity part, by the CPM size. An LDPC decoder having as many rows (rows). 4. The method according to claim 3,
The accumulation is
The LDPC decoder, characterized in that it is performed on parity bit addresses updated using the sequence. 7. The method of claim 6,
The accumulation is
The LDPC decoder, characterized in that it is performed while changing the rows of the sequence in units of the CPM size (L) of the parity check matrix. Receiving a signal corresponding to a LDPC (Low Density Parity Check) codeword having a length of 64800 and a code rate of 4/15, encoded using a sequence corresponding to a parity check matrix; and
performing decoding on the received signal corresponding to the parity check matrix,
The sequence is represented by the following table.
[table]
Line 1: 276 1754 1780 3597 8549 15196 26305 27003 33883 37189 41042 41849 42356
Line 2: 730 873 927 9310 9867 17594 21969 25106 25922 31167 35434 37742 45866
Line 3: 925 1202 1564 2575 2831 2951 5193 13096 18363 20592 33786 34090 40900
Line 4: 973 1045 1071 8545 8980 11983 18649 21323 22789 22843 26821 36720 37856
Line 5: 402 1038 1689 2466 2893 13474 15710 24137 29709 30451 35568 35966 46436
Line 6: 263 271 395 5089 5645 15488 16314 28778 29729 34350 34533 39608 45371
Line 7: 387 1059 1306 1955 6990 20001 24606 28167 33802 35181 38481 38688 45140
Line 8: 53 851 1750 3493 11415 18882 20244 23411 28715 30722 36487 38019 45416
Line 9: 810 1044 1772 3906 5832 16793 17333 17910 23946 29650 34190 40673 45828
Line 10: 97 491 948 12156 13788 24970 33774 37539 39750 39820 41195 46464 46820
Line 11: 192 899 1283 3732 7310 13637 13810 19005 24227 26772 31273 37665 44005
Line 12: 424 531 1300 4860 8983 10137 16323 16888 17933 22458 26917 27835 37931
Line 13: 130 279 731 3024 6378 18838 19746 21007 22825 23109 28644 32048 34667
Line 14: 938 1041 1482 9589 10065 11535 17477 25816 27966 35022 35025 42536
Line 15: 170 454 1312 5326 6765 23408 24090 26072 33037 38088 42985 46413
Line 16: 220 804 843 2921 4841 7760 8303 11259 21058 21276 34346 37604
Line 17: 676 713 832 11937 12006 12309 16329 26438 34214 37471 38179 42420
Line 18: 714 931 1580 6837 9824 11257 15556 26730 32053 34461 35889 45821
Line 19: 28 1097 1340 8767 9406 17253 29558 32857 37856 38593 41781 47101
Line 20: 158 722 754 14489 23851 28160 30371 30579 34963 44216 46462 47463
Line 21: 833 1326 1332 7032 9566 11011 21424 26827 29789 31699 32876 37498
Line 22: 251 504 1075 4470 7736 11242 20397 32719 34453 36571 40344 46341
Line 23: 330 581 868 15168 20265 26354 33624 35134 38609 44965 45209 46909
Line 24: 729 1643 1732 3946 4912 9615 19699 30993 33658 38712 39424 46799
Line 25: 546 982 1274 9264 11017 11868 15674 16277 19204 28606 39063 43331
Line 26: 73 1160 1196 4334 12560 13583 14703 18270 18719 19327 38985 46779
Line 27: 1147 1625 1759 3767 5912 11599 18561 19330 29619 33671 43346 44098
Line 28: 104 1507 1586 9387 17890 23532 27008 27861 30966 33579 35541 39801
Line 29: 1700 1746 1793 4941 7814 13746 20375 27441 30262 30392 35385 42848
Line 30: 183 555 1029 3090 5412 8148 19662 23312 23933 28179 29962 35514
Line 31: 891 908 1127 2827 4077 4376 4570 26923 27456 33699 43431 46071
Line 32: 404 1110 1782 6003 14452 19247 26998 30137 31404 31624 46621 47366
Line 33: 886 1627 1704 8193 8980 9648 10928 16267 19774 35111 38545 44735
Line 34: 268 380 1214 4797 5168 9109 9288 17992 21309 33210 36210 41429
Line 35: 572 1121 1165 6944 7114 20978 23540 25863 26190 26365 41521 44690
Line 36: 18 185 496 5885 6165 20468 23895 24745 31226 33680 37665 38587
Line 37: 289 527 1118 11275 12015 18088 22805 24679 28262 30160 34892 43212
Line 38: 658 926 1589 7634 16231 22193 25320 26057 26512 27498 29472 34219
Line 39: 337 801 1525 2023 3512 16031 26911 32719 35620 39035 43779 44316
Line 40: 248 534 670 6217 11430 24090 26509 28712 33073 33912 38048 39813
Line 41: 82 1556 1575 7879 7892 14714 22404 22773 25531 34170 38203 38254
Line 42: 247 313 1224 3694 14304 24033 26394 28101 37455 37859 38997 41344
Line 43: 790 887 1418 2811 3288 9049 9704 13303 14262 38149 40109 40477
Line 44: 1310 1384 1471 3716 8250 25371 26329 26997 30138 40842 41041 44921
Line 45: 86 288 367 1860 8713 18211 22628 22811 28342 28463 40415 45845
Line 46: 719 1438 1741 8258 10797 29270 29404 32096 34433 34616 36030 45597
Line 47: 215 1182 1364 8146 9949 10498 18603 19304 19803 23685 43304 45121
Line 48: 1243 1496 1537 8484 8851 16589 17665 20152 24283 28993 34274 39795
Line 49: 6320 6785 15841 16309 20512 25804 27421 28941 43871 44647
Line 50: 2207 2713 4450 12217 16506 21188 23933 28789 38099 42392
Line 51: 14064 14307 14599 14866 17540 18881 21065 25823 30341 36963
Line 52: 14259 14396 17037 26769 29219 29319 31689 33013 35631 37319
Line 53: 7798 10495 12868 14298 17221 23344 31908 39809 41001 41965 9. The method of claim 8,
The LDPC codeword is
It is generated based on the accumulation performed using the sequence,
The accumulation is a second bit of information bits corresponding to the LDPC codeword.

about

(p _x (0≤x≤47519) is the memory used for the accumulation,

is the addition operator)
LDPC decoding method, characterized in that it is performed using the 13 equations of

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