KR20210118086A - Memory control unit, memory module and information processing system - Google Patents

Abstract

When a memory copy operation is being performed, when an access to the memory is issued, the waiting for the access is suppressed to the necessary minimum. The first storage area of the memory is a copy unit. The second storage area of the memory is a combination of a plurality of first storage areas. In the memory, when a copy operation is performed from the second storage area to another storage area, when an access to the second storage area is issued, the access to the memory is performed using the first storage area as a unit. control is performed. When the copy unit area to be accessed has been copied to another storage area, the address of the area to be accessed is replaced with the copy destination address, and the access is continued.

Description

Memory control unit, memory module and information processing system

The present technology relates to a memory control device. Specifically, it relates to a memory control device, a memory module, and an information processing system for controlling access to a memory.

In a memory, such as a non-volatile memory, in which the number of times of rewriting is limited, a technique called wear leveling in which a physical storage location is moved is used in order to avoid the end of life due to concentration of access to a specific area. In this wear leveling, copying and deletion between areas are performed. On the other hand, in a NAND flash memory or the like, since data cannot be rewritten, it is necessary to copy and delete data even when data is rewritten. In the situation where such a copy process is being performed, when there is an access from the outside, there is a problem that the access from the outside waits until the copy is completed, and the latency increases. On the other hand, in the NAND flash memory, when there is writing from the host in the area being copied, a technique has been proposed in which data is written to an area temporarily prepared in the NAND flash memory separately from the area to be originally written (for example, , see Patent Document 1.).

Patent Document 1: Japanese Patent Laid-Open No. 2017-174387

In the prior art described above, latency is reduced by recording data in a temporarily prepared area. However, in this prior art, after completion of copying, effective data is mixed in the copied area and the temporary area, so a process for merging the data thereafter is also required.

The present technology was developed in view of such a situation, and it is an object of the present invention to minimize waiting for access when an access to the memory is issued in a case where a copy operation of the memory is being executed.

The present technology has been made to solve the above-described problem, and the first aspect thereof is a copy operation from a second storage area in which a plurality of first storage areas that are a copy unit of a memory are integrated to another storage area of the memory. In this case, when an access to the second storage area is issued, the memory control device, the memory module, and the information processing system control the access in the first storage area as a unit. This brings about the effect of controlling access by using the first storage area as a unit in the case where the copy operation is being performed with the second storage area as a unit.

Further, in the first aspect, there is provided an address conflict determination unit that determines an address conflict between the copy operation and the access in the copy unit, and the area of the copy unit to be accessed is stored in the other storage area. When the determination that the copy has been completed is made in the address collision determination, an address replacement unit for continuing the access by replacing the address of the area to be accessed with the address of the copy destination may be provided. Thereby, when the area to be accessed has been copied, the effect of continuing access to the address of the copy destination is brought about.

Further, in the first aspect, in the case where a determination is made in the address collision determination that the access is a read access and the target copy unit area is being copied to the other storage area, The access may be continued without performing the substitution. This brings about the effect of continuing access to the copy source address when the read access target area is being copied.

Further, in the first aspect, when the address replacement unit determines that the access is a write access and the target copy unit area is being copied to the other storage area is made in the address collision determination, The write access may be made to wait until the copy unit area is copied. Thereby, when the area to be written access is being copied, the effect of waiting for the write access is brought about until the area to be copied is completed.

Further, in the first aspect, a write request buffer for holding the write access request while the write access is waiting may be further provided. This brings about the effect of waiting for the write access in the write request buffer until the copy of the area to be written access is being copied.

Further, in the first aspect, the address replacement unit performs the replacement when a determination is made in the address conflict determination that the area of the copy unit to be accessed is before copying to the other storage area. You may make it continue the said access without performing. Thereby, if the area to be accessed is before copying, an effect of continuing access to the address of the copy source is brought about.

Further, in the first aspect, the address replacement unit is configured to replace the address when it is determined in the address collision determination that the copy unit area to be accessed does not collide with the other storage area. The access may be continued without performing . This brings about the effect of continuing the access when the areas to be accessed do not collide.

Further, in the first aspect, there is provided an address converting unit that converts the target address to be accessed from a logical address to a physical address of the memory, using the second storage area as a unit, wherein the address converting unit comprises: After the copy operation is performed, it may be updated to indicate the physical address after copying. This brings about an effect of accessing the second area of the copy destination after copy completion.

Further, in the first aspect, the other storage area is an area of a logical address space that is inaccessible before the copy operation is performed, and is an area of a logical address space accessible by the address conversion unit after the copy operation is performed. updated in the area. This brings about an effect that access is controlled by the first storage area as a unit, without accessing the entire second storage area until the completion of copying.

Further, in the first aspect, in the case where the access to the second storage area relates to an area larger than the copy unit, the address conflict determination unit divides each area into areas not exceeding the copy unit. You may make it further provide the access division part which supplies to. Thereby, even when the area to be accessed exceeds the copy unit, the effect of controlling the access by dividing the first storage area as a unit is brought about.

In addition, in this 1st aspect, it may be assumed that the said memory is a non-volatile memory. For example, in a nonvolatile memory in which data can be rewritten without erasing, a copy operation is required for wear leveling or the like. It brings about the effect of controlling access by using the storage area as a unit.

BRIEF DESCRIPTION OF THE DRAWINGS It is a figure which shows one structural example of the information processing system in embodiment of this technology.
Fig. 2 is a diagram showing a configuration example of a memory controller 200 according to the first embodiment of the present technology.
Fig. 3 is a diagram showing a corresponding example of the address space of the memory 300 in the embodiment of the present technology.
Fig. 4 is a diagram showing an example of the state of the table of the address conversion unit 260 in the embodiment of the present technology.
Fig. 5 is a diagram showing an example of a data copy state in the embodiment of the present technology;
Fig. 6 is a diagram showing an example of the state of the table of the address conversion unit 260 after data copy in the embodiment of the present technology;
Fig. 7 is a diagram showing an example of the state of each page in a block when data is copied in the embodiment of the present technology;
Fig. 8 is a flowchart showing an example of a data copy processing procedure of the memory controller 200 in the embodiment of the present technology;
Fig. 9 is a diagram showing an example of the relationship between the state of the address conflict and the operation in the embodiment of the present technology;
Fig. 10 is a diagram showing an operation example in the case of cases #1 and #4 in the embodiment of the present technology;
Fig. 11 is a diagram showing an operation example in the case of Case #2 in the embodiment of the present technology;
Fig. 12 is a diagram showing an operation example in the case of cases #3 and #6 in the embodiment of the present technology;
Fig. 13 is a diagram showing an operation example in case #5 in the embodiment of the present technology;
Fig. 14 is a diagram showing an operation example in the case of Case #7 in the embodiment of the present technology;
Fig. 15 is a flowchart showing an example of a processing procedure related to address collision determination of the memory controller 200 in the embodiment of the present technology;
Fig. 16 is a diagram showing one configuration example of a memory controller 200 according to the second embodiment of the present technology.

Hereinafter, a form for implementing the present technology (hereinafter, referred to as an embodiment) will be described. The explanation is given in the following order.

1. First embodiment (example of processing page unit access from host)

2. Second embodiment (Example in which access from the host is divided into page units and processed)

<1. First embodiment>

[Configuration of information processing system]

1 is a diagram showing an example of a configuration of an information processing system according to an embodiment of the present technology.

This information processing system includes a host computer 100 , a memory controller 200 , and a memory 300 . The memory controller 200 and the memory 300 constitute the memory module 400 .

The host computer 100 issues commands for instructing the memory 300 to read data, write data, and the like. The host computer 100 includes a processor that executes processing as the host computer 100 and a controller interface for communicating with the memory controller 200 .

The memory controller 200 performs request control for the memory 300 according to a command from the host computer 100 . Also, the memory controller 200 is an example of the memory control device described in the claims.

The memory 300 includes a control unit and a memory cell array. The control unit of the memory 300 performs access to the memory cell according to a request from the memory controller 200 . The memory cell array of the memory 300 is a memory cell array composed of a plurality of memory cells, and a memory cell that stores any one of two values for each bit, or a memory that stores a multivalent value for each bit. A large number of cells are arranged in a two-dimensional shape (matrix shape). This memory cell array uses a non-volatile memory (NVM) in which data can be rewritten without erasing as an access unit for reading or writing pages having a multi-byte size (eg, 512B). assume

[Configuration of memory controller]

2 is a diagram showing an example of a configuration of the memory controller 200 according to the first embodiment of the present technology. The memory controller 200 includes a copy control unit 210 , a logical address collision determination unit 230 , a logical address replacement unit 240 , a write request buffer 250 , an address conversion unit 260 , RAM 270 is provided. In addition, the memory controller 200 includes a host interface 201 for communicating with the host computer 100 and a memory interface 203 for communicating with the memory 300 . be prepared

The copy control unit 210 controls copying and deletion between regions for wear leveling and the like. This copy control unit 210 controls read and write access in the background independently of processing by commands from the host computer 100 . The access from the copy control unit 210 is indicated by a logical address, similarly to the access from the host computer 100 .

The copy operation by the copy control unit 210 is instructed for each block of the memory 300 as a unit. A block is composed of a plurality of pages. In the copy operation, one page at a time is processed as a copy unit. Accordingly, in a block to be copied, three types of states can exist: a copy-completed page, a copy-in-progress page, and a copy-previous page. Note that a page is an example of the first storage area described in the claims. Note that a block is an example of the second storage area described in the claims.

The logical address collision determination unit 230 determines a collision between the logical address space of the area targeted for the copy operation by the copy control unit 210 and the logical address specified by the command issued from the host computer 100 . will do The logical address conflict determination unit 230 determines whether or not a conflict exists, and, if a conflict occurs, the page The state (one of the three types described above) is determined. The result of this determination is supplied to the logical address replacement unit 240 . In addition, the logical address collision determination unit 230 is an example of the address collision determination unit described in the claims.

The logical address replacement unit 240 replaces the logical address specified by the command issued from the host computer 100 with another logical address in response to the determination result by the logical address collision determination unit 230 . The specific content of this address substitution will be described later. Note that the logical address replacement unit 240 is an example of the address replacement unit described in the claims.

The write request buffer 250 is a buffer that holds the contents in order to wait for the write request when a write request is issued from the host computer 100 for a page being copied. If it is determined as a result of the determination by the logical address collision determination unit 230 that it is a write request for the page being copied, the logical address replacement unit 240 outputs the write request to the write request buffer 250 .

The address conversion unit 260 converts the logical address output from the logical address replacement unit 240 into a physical address of the memory 300 . The address conversion unit 260 maintains, for example, a table associating logical addresses and physical addresses, and performs conversion from logical addresses to physical addresses by referring to the table.

The random access memory (RAM) 270 is an internal memory that stores a work area necessary for the operation of the memory controller 200 . The RAM 270 is used as a buffer area for temporarily storing data read from the memory 300 during a copy operation for wear leveling.

[Address space in memory]

FIG. 3 is a diagram showing a corresponding example of the address space of the memory 300 in the embodiment of the present technology.

A command issued from the host computer 100 and control of a copy operation by the copy control unit 210 is indicated by a logical address. The logical address space is mapped to the physical address space of the memory 300 . When the memory 300 is accessed, the address conversion unit 260 converts the logical address into a physical address of the memory 300 in block units.

Here, over-provisioning is assumed. That is, the physical address space has a larger space than the logical address space accessible from the host computer 100 . Therefore, a part of the physical address space is mapped as a logical address space inaccessible from the host computer 100 . In this example, an area of an address lower than page #1000 in the logical address space is mapped as a "logical address space accessible from the host computer 100" (hereinafter referred to as an "accessible space"). On the other hand, the address area after page #1000 in the logical address space is mapped as a "logical address space that cannot be accessed from the host computer 100" (hereinafter referred to as an "inaccessible space").

4 is a diagram showing an example of the state of the table of the address conversion unit 260 in the embodiment of the present technology.

In this example, the logical block addresses #0 to #100 in the logical address space are mapped as accessible spaces. Then, the address area after logical block address #100 is mapped as an inaccessible space.

[Data Copy]

Fig. 5 is a diagram showing an example of a data copy state in the embodiment of the present technology. This data copy is executed for wear leveling or the like.

In this embodiment, in the case of data copying, copying is performed from an accessible space to an inaccessible space in a logical address space. In this example, data of each page of logical block #0 is read into RAM 270, and the read data is copied into logical block #100. That is, the contents of each page of physical block #0 are copied to physical block #200.

After this data copying is completed, the table of the address conversion unit 260 is updated so that blocks copied to the inaccessible space become accessible from the inaccessible space. The following figure shows an example of the state.

6 is a diagram showing an example of the state of the table of the address conversion unit 260 after data copy in the embodiment of the present technology.

In this example, the physical block addresses corresponding to logical block addresses #0 of the accessible space are updated from #0 to #200. On the other hand, physical block addresses corresponding to logical block addresses #100 in the inaccessible space are updated from #200 to #0. That is, the physical block addresses #0 and #200 are swapped between the accessible space and the inaccessible space.

As described above, in the case of data copying in this embodiment, the copy source block is once recorded in the inaccessible space, and is updated to the accessible space after copying is completed so that it is visible from the host computer 100 . Thereby, in an intermediate state from the start of the copy to the completion of the copy, it is not directly visible from the host computer 100 , and the control therebetween can be managed by the memory controller 200 .

Fig. 7 is a diagram showing an example of the state of each page in a block when data is copied in the embodiment of the present technology.

As described above, the copy operation by the copy control unit 210 is instructed for each block of the memory 300 as a unit. In this block copying, page-by-page copying (page copying) is performed a plurality of times. In the copy source block and the copy destination block, each page is copied sequentially from the beginning according to the copy offset indicating the copy position. Each time one page is copied, the copy offset is incremented.

The page indicated by the copy offset is being copied, the copy is completed before the page indicated by the copy offset, and the page after the page indicated by the copy offset is before the copy.

8 is a flowchart showing an example of a data copy processing procedure of the memory controller 200 in the embodiment of the present technology.

First, the copy offset is cleared to "0" (step S911). Then, data is read into the RAM 270 from the page indicated by the copy offset of the copy source (step S912). The data read into this RAM 270 is written to the page indicated by the copy offset of the copy destination (step S913).

If copying is not completed for all the pages in the block (step S914: No), the copy offset is incremented by one (step S915), and the processing after step S912 is repeated.

When copying is completed for all pages in the block (step S914: Yes), the table of the address conversion unit 260 is updated (step S916), and the copy destination area is set as an accessible space.

[Address Conflict]

Fig. 9 is a diagram showing an example of the relationship between the state of the address conflict and the operation in the embodiment of the present technology.

In this embodiment, the logical address conflict determination unit 230 determines a state in which access of a command from the host computer 100 collides with a logical address space being copied. Hereinafter, according to the same drawing, cases are classified into seven cases and described.

Cases #1 to 3 are cases in which the logical address specified by the read command from the host computer 100 and the logical address space of the area targeted for the copy operation collide. Cases #4 to 6 are cases in which the logical address specified by the write command from the host computer 100 and the logical address space of the area subject to the copy operation collide. Case #7 is a case where the logical address specified by the command from the host computer 100 does not collide with the logical address space of the area to be copied.

Fig. 10 is a diagram showing an operation example in the case of cases #1 and #4 in the embodiment of the present technology.

Case #1 is a case where the logical address designated as the read address from the host computer 100 is a copy-completed page. Incidentally, case #4 is a case in which the logical address designated as the write address from the host computer 100 is a copied page. That is, in these cases #1 and #4, the page to be accessed from the host computer 100 has already been copied. Accordingly, when the copy destination page is accessed, the command from the host computer 100 can be processed.

Therefore, the logical address replacement unit 240 replaces the logical address specified by the command issued from the host computer 100 with the logical address of the copy destination. The substituted logical address is converted into a physical address by the address conversion unit 260 .

11 is a diagram showing an operation example in the case of Case #2 in the embodiment of the present technology.

Case #2 is a case where the logical address designated as the read address from the host computer 100 is a page being copied. In this case, when data is read from the copy source page, the read command from the host computer 100 can be processed.

Therefore, the logical address replacement unit 240 outputs the logical address specified by the command issued from the host computer 100 to the address conversion unit 260 as it is without replacement. This unsubstituted logical address is converted into a physical address by the address conversion unit 260 .

12 is a diagram showing an operation example in the case of cases #3 and #6 in the embodiment of the present technology.

Case #3 is a case where the logical address designated as the read address from the host computer 100 is a page before copying. Incidentally, case #6 is a case where the logical address designated as the write address from the host computer 100 is a page before copying. That is, in these cases #3 and #6, the page to be accessed from the host computer 100 is still before copying. Accordingly, when the page of the copy origin is accessed, the command from the host computer 100 can be processed.

Therefore, the logical address replacement unit 240 outputs the logical address specified by the command issued from the host computer 100 to the address conversion unit 260 as it is without replacement. This unsubstituted logical address is converted into a physical address by the address conversion unit 260 .

13 is a diagram showing an operation example in the case of Case #5 in the embodiment of the present technology.

Case #5 is a case where the logical address designated as the write address from the host computer 100 is a page being copied. In this case, writing to the page being copied cannot be performed because the data is destroyed.

Therefore, in order to wait for the write request, the logical address replacement unit 240 holds the contents in the write request buffer 250 . Therefore, the write request is temporarily suspended until the page is in the copy completion state. When the copy of the page is completed, the state of case #4 is entered, and the logical address replacement unit 240 replaces the logical address specified by the command issued from the host computer 100 with the logical address of the copy destination, output to the converter 260 .

14 is a diagram showing an operation example in the case of Case #7 in the embodiment of the present technology.

Case #7 is a case where the logical address specified by the command from the host computer 100 does not collide with the logical address space of the area to be copied. Therefore, it is not necessary to perform substitution of the command from the host computer 100 for either read or write.

Therefore, the logical address replacement unit 240 outputs the logical address specified by the command issued from the host computer 100 to the address conversion unit 260 as it is without replacement. This unsubstituted logical address is converted into a physical address by the address conversion unit 260 .

15 is a flowchart showing an example of a processing procedure related to address collision determination of the memory controller 200 according to the embodiment of the present technology.

When a command to access the memory 300 is issued from the host computer 100 , the logical address collision determination unit 230 generates a collision between the logical address space of the copy operation area and the logical address specified by the host computer 100 . is determined (step S921). And in response to the determination result, each process is performed as follows.

Case #7 corresponds to the case where the logical address specified by the command from the host computer 100 does not collide with the logical address space of the area to be copied (step S931: No). Accordingly, the logical address replacement unit 240 outputs the logical address specified by the command issued from the host computer 100 to the address conversion unit 260 as it is without replacement (step S935). This unsubstituted logical address is converted into a physical address by the address conversion unit 260 (step S939).

Cases #1 and #4 correspond to the case where the page to be accessed from the host computer 100 has been copied (step S932: Yes). Accordingly, the logical address replacement unit 240 replaces the logical address specified by the command issued from the host computer 100 with the logical address of the copy destination (step S936). This substituted logical address is converted into a physical address by the address conversion unit 260 (step S939).

Cases #3 and #6 correspond to the case where the page to be accessed from the host computer 100 has been copied (step S933: Yes). Accordingly, the logical address replacement unit 240 outputs the logical address specified by the command issued from the host computer 100 to the address conversion unit 260 as it is without replacement (step S935). This unsubstituted logical address is converted into a physical address by the address conversion unit 260 (step S939).

If the host computer 100 determines that the page to be accessed is not before copying (step S933: No), the page is being copied. At this time, if the access from the host computer 100 is read access (step S934: Yes), case #2 is applicable. Accordingly, the logical address replacement unit 240 outputs the logical address specified by the command issued from the host computer 100 to the address conversion unit 260 as it is without replacement (step S935). This unsubstituted logical address is converted into a physical address by the address conversion unit 260 (step S939).

If the page to be accessed from the host computer 100 is being copied (step S933: No) and the access is not read access (step S934: No), case #5 is applicable. Accordingly, the logical address replacement unit 240 holds the contents in the write request buffer 250, and waits for the write request until the page is in the copy completion state (step S938). That is, the flow returns to step S932 for determining copy completion.

As described above, according to the first embodiment of the present technology, even when the logical address specified by the command from the host computer 100 and the logical address space of the area to be copied operation collide with each other, page unit You can control access with . That is, accesses other than writing during copying can be continued in units of pages, and the latency required for memory access can be reduced. In addition, there is no need to separately provide another memory area as in the prior art, and a data merging operation can be made unnecessary.

<2. Second embodiment>

In the first embodiment described above, it is assumed that access by a command from the host computer 100 is stored in the page. In contrast, in the second embodiment, a case where access by a command from the host computer 100 is not accommodated in the page is allowed. In addition, about the whole structure as an information processing system, since it is the same as that of 1st Embodiment mentioned above, detailed description is abbreviate|omitted.

[Configuration of memory controller]

16 is a diagram showing an example of a configuration of the memory controller 200 according to the second embodiment of the present technology. The memory controller 200 in the second embodiment is different from the first embodiment described above in that it further includes an access division unit 220, and the rest is the same.

The access division unit 220 divides each area into areas that do not exceed one page when access by a command from the host computer 100 relates to an area larger than one page. For example, if the size of one page is 512B and access by a command from the host computer 100 relates to a data capacity of 128 KB, the access is divided for every 512B and supplied to the logical address collision determination unit 230 do. Accordingly, the processing after the logical address collision determination unit 230 is the same as in the first embodiment described above.

As described above, according to the second embodiment of the present technology, access by a command from the host computer 100 is divided for each page by the access division unit 220, so that even large-sized accesses are page-by-page. You can control access.

In addition, the above-mentioned embodiment showed an example for realizing this technology, and the matter in embodiment and the invention-specific matter in a claim have a corresponding relationship, respectively. Similarly, the invention-specifying matter in the claims and the matter in the embodiment of the present technology to which the same name is attached have a corresponding relationship, respectively. However, the present technology is not limited to the embodiment, and can be implemented by making various modifications to the embodiment without departing from the gist thereof.

In addition, the processing procedure described in the above-mentioned embodiment may be grasped as a method having these series of procedures, and may be grasped as a program for causing a computer to execute these series of procedures or a recording medium storing the program. good. As this recording medium, for example, CD (Compact Disc), MD (MiniDisc), DVD (Digital Versatile Disc), memory card, Blu-ray Disc (Blu-ray (registered trademark) Disc), etc. can be used.

In addition, the effect described in this specification is an illustration to the last, It is not limited, Moreover, another effect may exist.

In addition, this technique can also take the following structures.

(1) When a copy operation is performed from a second storage area in which a plurality of first storage areas that are a copy unit of the memory are integrated to another storage area of the memory, access to the second storage area is A memory control device for controlling the access by using the first storage area as a unit at the time of issuance.

(2) an address conflict determination unit that determines an address conflict between the copy operation and the access in units of the copy;

When it is determined by the address collision determination that the copy unit area to be accessed has been copied to the other storage area, the address of the area to be accessed is replaced with the copy destination address, and The memory control device according to (1) above, comprising an address replacement unit for continuing access.

(3) The address replacement unit performs the access without performing the replacement when a determination is made in the address conflict determination that the access is a read access and the target copy unit area is being copied to the other storage area The memory control device according to (2) above, in which

(4) The address replacement unit is configured to copy the copy unit area when it is determined in the address conflict determination that the access is a write access and the target copy unit area is being copied to the other storage area. The memory control device according to (2) or (3) above, wherein the write access waits until completion.

(5) The memory control device according to (4), further comprising a write request buffer for holding the write access request while the write access is waiting.

(6) The address replacement unit continues the access without performing the replacement when it is determined in the address conflict determination that the copy unit area to be accessed is before copying to the other storage area. The memory control device according to any one of (2) to (5) above.

(7) The address replacement unit continues the access without performing the replacement when it is determined in the address collision determination that the copy unit area to be accessed does not collide with the other storage area. The memory control device according to any one of (2) to (6) above.

(8) an address conversion unit for converting the target address to be accessed from a logical address to a physical address of the memory using the second storage area as a unit;

The memory control device according to any one of (2) to (7), wherein the address converting unit is updated to indicate the physical address after copying after the copy operation is performed.

(9) The other storage area is an area in the logical address space that is not accessible before the copy operation is performed, and is updated to an area in the logical address space accessible by the address conversion unit after the copy operation is performed (8) ) as described in the memory control device.

(10) In the case where the access to the second storage area relates to an area larger than the copy unit, an access division unit that divides each area into areas not exceeding the copy unit and supplies the area to the address conflict determination unit. The memory control device according to any one of (2) to (9), further comprising.

(11) a memory;

When a copy operation is performed from a second storage area in which a plurality of first storage areas that are copy units of the memory are integrated to another storage area of the memory, access to the second storage area is issued and a memory control device configured to control the access by using the first storage area as a unit at a time.

(12) The memory module according to (11), wherein the memory is a nonvolatile memory.

(13) a host computer;

memory and

When a copy operation is performed from a second storage area in which a plurality of first storage areas that are a copy unit of the memory are integrated to another storage area of the memory, the host computer and a memory control device configured to control the access in units of the first storage area when an access is issued.

100: host computer
200: memory controller
201: host interface
203: memory interface
210: copy control unit
220: access partition
230: logical address collision determination unit
240: logical address replacement unit
250: light request buffer
260: address conversion unit
300: memory
400: memory module

Claims (13)

In the case where a copy operation is performed from the second storage area in which a plurality of first storage areas as a copy unit of the memory are integrated to another storage area of the memory, when an access to the second storage area is issued The memory control device according to claim 1, wherein the access is controlled by using the first storage area as a unit. According to claim 1,
an address conflict determination unit that determines an address conflict between the copy operation and the access in units of the copy;
When it is determined by the address collision determination that the copy unit area to be accessed has been copied to the other storage area, the address of the area to be accessed is replaced with the copy destination address, and A memory control device comprising an address replacement unit for continuing access. 3. The method of claim 2,
The address replacement unit continues the access without performing the replacement when it is determined by the address conflict determination that the access is a read access and a determination that the target copy unit area is being copied to the other storage area Memory control device, characterized in that. 3. The method of claim 2,
The address replacement unit is configured to enable the copy unit area to be copied when it is determined in the address conflict determination that the access is a write access and the target area of the copy unit is being copied to the other storage area. and waiting the write access until the memory control device. 5. The method of claim 4,
and a write request buffer for holding the write access request while the write access is waiting. 3. The method of claim 2,
wherein the address replacement unit continues the access without performing the replacement, when it is determined in the address collision determination that the copy unit area to be accessed is before copying to the other storage area memory control unit. 3. The method of claim 2,
wherein the address replacement unit continues the access without performing the replacement when it is determined in the address collision determination that the copy unit area to be accessed does not collide with the other storage area memory control device. 3. The method of claim 2,
an address conversion unit for converting the target address to be accessed from a logical address to a physical address of the memory using the second storage area as a unit;
and the address conversion unit is updated to indicate a physical address after copying after the copy operation is performed. 9. The method of claim 8,
and the other storage area is an area in a logical address space that is inaccessible before the copy operation is performed, and is updated to an area in a logical address space accessible by the address conversion unit after the copy operation is performed. Device. 3. The method of claim 2,
and an access dividing unit that divides each of the regions into regions not exceeding the copy unit and supplies them to the address conflict determination unit when the access to the second storage region is an access to an area larger than the copy unit; Memory control device, characterized in that. memory and
When a copy operation is performed from a second storage area in which a plurality of first storage areas that are copy units of the memory are integrated to another storage area of the memory, access to the second storage area is issued and a memory control device configured to control the access by using the first storage area as a unit at a time. 12. The method of claim 11,
The memory is a memory module, characterized in that the non-volatile memory. host computer;
memory and
When a copy operation is performed from a second storage area in which a plurality of first storage areas that are a copy unit of the memory are integrated to another storage area of the memory, the host computer and a memory control device for controlling the access in units of the first storage area when an access is issued.

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