KR20210113537A - Display apparatus and manufacturing the same - Google Patents

Abstract

The present invention provides a display device including: a first display area provided with a first pixel; a semi-permeable area; and a second display area provided with a second pixel, in order to save process costs by reducing the number of masks needed in a patterning process among processes for the display device. The display device comprises: a first semiconductor layer disposed on a substrate corresponding to the second pixel; a gate insulating layer disposed on the first semiconductor layer; a first gate electrode disposed on the gate insulating layer and partially overlapping the first semiconductor layer; an auxiliary pixel electrode disposed on the same layer as the first semiconductor layer corresponding to the semi-permeable area and including the same material as the first semiconductor layer; an auxiliary intermediate layer disposed on the auxiliary pixel electrode; and a counter electrode disposed on the auxiliary intermediate layer.

Description

Display apparatus and manufacturing method thereof

The present invention relates to a display device and a manufacturing method thereof, and more particularly, to a display device driven by a thin film transistor including an oxide semiconductor and a manufacturing method thereof.

A display device is a device that visually displays data. The display device may be used as a display unit for small products such as mobile phones, or as a display unit for large products such as televisions.

Such a display device includes a substrate divided into a display area and a non-display area, and the gate line and the data line are insulated from each other in the display area. A plurality of pixel areas are defined in the display area by crossing the gate line and the data line, and the plurality of pixel areas receive an electrical signal to display an image to the outside and emit light. A thin film transistor and a pixel electrode electrically connected to the thin film transistor are provided corresponding to each pixel region, and a counter electrode is provided in common in the pixel regions. Various wirings, a gate driver, a data driver, a controller, and the like that transmit electrical signals to the display area may be provided in the non-display area.

Recently, as the use of the display device is diversified, various designs for improving the quality of the display device are being attempted.

In the embodiments of the present invention, the auxiliary pixel electrode of the auxiliary light emitting unit disposed corresponding to the transflective region is disposed on the same layer as the oxide semiconductor layer and patterned together with the oxide semiconductor layer. The number of masks required for the patterning process of the display device is An object of the present invention is to provide a display device having a reduced process cost and a method for manufacturing the same.

However, these problems are exemplary, and the scope of the present invention is not limited thereto.

According to an embodiment of the present invention, in a display device including a first display area including a first pixel, and a second display area including a transflective area and a second pixel, the display device corresponds to the second pixel. a first semiconductor layer disposed on the substrate; a gate insulating layer disposed on the first semiconductor layer; a first gate electrode disposed on the gate insulating layer and partially overlapping the first semiconductor layer; an auxiliary pixel electrode disposed on the same layer as the first semiconductor layer corresponding to the transflective region and including the same material as the first semiconductor layer; an auxiliary intermediate layer disposed on the auxiliary pixel electrode; and a counter electrode disposed on the auxiliary intermediate layer.

In one embodiment, the first insulating layer disposed on the first gate electrode; and an electrode layer disposed on the first insulating layer, wherein the electrode layer may connect the first semiconductor layer and the auxiliary pixel electrode.

In one embodiment, disposed on the electrode layer, a second insulating layer; a pixel electrode disposed on the second insulating layer; and an intermediate layer disposed on the pixel electrode, wherein the counter electrode is disposed on the intermediate layer, wherein the pixel electrode is connected to the electrode layer and is simultaneously driven with the auxiliary pixel electrode.

In an embodiment, the pixel electrode may be farther away from the substrate than the auxiliary pixel electrode.

In an embodiment, the intermediate layer and the auxiliary intermediate layer may emit light of the same wavelength.

In an embodiment, the first semiconductor layer may include an oxide semiconductor material.

In an embodiment, the first semiconductor layer may include IGZO (InGaZnO).

In one embodiment, the insulating layer disposed on the first gate electrode; a pixel electrode disposed on the insulating layer and connected to the first semiconductor layer for driving; and an intermediate layer disposed on the pixel electrode, wherein the counter electrode is disposed on the intermediate layer, and the intermediate layer and the auxiliary intermediate layer may be integrally formed.

In one embodiment, the second semiconductor layer is disposed on the substrate corresponding to the second pixel, comprising a silicon semiconductor material; and a second gate electrode disposed on the second semiconductor layer and partially overlapping the second semiconductor layer.

In an embodiment, the gate insulating layer may be patterned according to a shape of the first gate electrode.

In an embodiment, an insulating layer disposed on the first gate electrode and having a hole corresponding to the transflective region to partially expose the auxiliary pixel electrode may be further included.

In an embodiment, the display device may further include a component disposed under the substrate to correspond to the transflective region.

In an embodiment, a lower gate electrode disposed under the first semiconductor layer and partially overlapping the first semiconductor layer may be further included.

In an embodiment, the first semiconductor layer may include a channel region, a source region, and a drain region, and the lower gate electrode may overlap at least the channel region.

According to another embodiment of the present invention, in a display device including a first display area having a first pixel, and a second display area having a transflective area and a second pixel, the display device corresponds to the second pixel. forming a semiconductor layer on a substrate; forming a gate insulating layer to cover the semiconductor layer; forming a gate electrode on the gate insulating layer at least partially overlapping the semiconductor layer; forming an auxiliary pixel electrode on the same layer as the semiconductor layer and including the same material as the semiconductor layer corresponding to the transflective region; forming an auxiliary intermediate layer on the auxiliary pixel electrode; and forming a counter electrode on the auxiliary intermediate layer.

In one embodiment, the method comprising: forming an insulating layer on the gate electrode; and forming an electrode layer including a first contact hole penetrating the insulating layer and exposing a portion of the semiconductor layer and a second contact hole penetrating the insulating layer and exposing a part of the auxiliary pixel electrode; and the electrode layer may connect the semiconductor layer and the auxiliary pixel electrode.

In an embodiment, the semiconductor layer and the sub-pixel electrode may be patterned together.

In one embodiment, the method comprising: disposing an insulating layer on the gate electrode; and etching the insulating layer corresponding to the transflective region.

In an embodiment, the semiconductor layer may include an oxide semiconductor material.

In one embodiment, the method comprising: disposing an insulating layer on the gate electrode; disposing a pixel electrode connected to the semiconductor layer and driven on the insulating layer; and disposing an intermediate layer on the pixel electrode, wherein the counter electrode is disposed on the intermediate layer, and the intermediate layer and the auxiliary intermediate layer may emit light of the same wavelength.

Other aspects, features and advantages other than those described above will become apparent from the following detailed description, claims and drawings for carrying out the invention.

According to the exemplary embodiment of the present invention made as described above, the number of masks required for the patterning process during the process of the display device is reduced, so that the display device and the method for manufacturing the same can be realized in which the process cost is reduced. Of course, the scope of the present invention is not limited by these effects.

1 is a perspective view schematically illustrating a display device according to an exemplary embodiment.
FIG. 2 is a cross-sectional view schematically illustrating a cross-section taken along line I-I' of FIG. 1 .
3 is an equivalent circuit diagram illustrating one pixel in a display device according to an exemplary embodiment of the present invention.
4 is an equivalent circuit diagram illustrating one pixel in a display device according to an exemplary embodiment of the present invention.
5 is a plan view schematically illustrating a part of a display device according to an exemplary embodiment.
6A and 6B are cross-sectional views schematically illustrating a cross-section taken along line II-II' of FIG. 5 .
7A to 7F are cross-sectional views illustrating a method of manufacturing a display device according to an exemplary embodiment in stages.

Since the present invention can apply various transformations and can have various embodiments, specific embodiments are illustrated in the drawings and described in detail in the detailed description. Effects and features of the present invention, and a method of achieving them, will become apparent with reference to the embodiments described below in detail in conjunction with the drawings. However, the present invention is not limited to the embodiments disclosed below and may be implemented in various forms.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings, and when described with reference to the drawings, the same or corresponding components are given the same reference numerals, and the overlapping description thereof will be omitted. .

In the following embodiments, terms such as first, second, etc. are used for the purpose of distinguishing one component from another, not in a limiting sense.

In the following examples, the singular expression includes the plural expression unless the context clearly dictates otherwise.

In the following embodiments, terms such as include or have means that the features or components described in the specification are present, and the possibility of adding one or more other features or components is not excluded in advance.

In the following embodiments, when it is said that a part such as a film, region, or component is on or on another part, it is not only when it is directly on the other part, but also another film, region, component, etc. is interposed therebetween. Including cases where there is

In the drawings, the size of the components may be exaggerated or reduced for convenience of description. For example, since the size and thickness of each component shown in the drawings are arbitrarily indicated for convenience of description, the present invention is not necessarily limited to the illustrated bar.

Where certain embodiments are otherwise feasible, a specific process sequence may be performed different from the described sequence. For example, two processes described in succession may be performed substantially simultaneously, or may be performed in an order opposite to the order described.

As used herein, "A and/or B" refers to A, B, or A and B. And, "at least one of A and B" represents the case of A, B, or A and B.

In the following embodiments, when a film, region, or component is connected, when the film, region, or component is directly connected, or/and in the middle of another film, region, or component Including cases where they are interposed and indirectly connected. For example, in the present specification, when it is said that a film, region, component, etc. are electrically connected, when the film, region, component, etc. are directly electrically connected, and/or another film, region, component, etc. is interposed therebetween. to indicate an indirect electrical connection.

The x-axis, y-axis, and z-axis are not limited to three axes on a Cartesian coordinate system, and may be interpreted in a broad sense including them. For example, the x-axis, y-axis, and z-axis may be orthogonal to each other, but may refer to different directions that are not orthogonal to each other.

1 is a perspective view schematically illustrating a display device according to an exemplary embodiment.

Referring to FIG. 1 , the display device 1 includes a first display area DA1 , a second display area DA2 surrounded by the first display area DA1 , and a peripheral area outside the first display area DA1 . (SA).

As an embodiment, FIG. 1 illustrates that one second display area DA2 is disposed inside the first display area DA1 . In another embodiment, the number of the second display areas DA2 may be two or more, and the shapes and sizes of the plurality of second display areas DA2 may be different from each other. The peripheral area SA may be a kind of non-display area in which pixels are not disposed. The first display area DA1 may be entirely or partially surrounded by the peripheral area SA.

Although FIG. 1 illustrates that the second display area DA2 has a substantially circular shape, the present invention is not limited thereto. The shape of each of the second display areas DA2 on a plane (or when viewed from a direction perpendicular to one surface of the substrate) may be variously changed, such as a polygonal shape such as a circle, an oval, or a square, a star shape, or a diamond shape.

Also, although FIG. 1 illustrates that the second display area DA2 is disposed on one side (upper right side) of the quadrangular first display area DA1, the present invention is not limited thereto. In another exemplary embodiment, the second display area DA2 may be disposed on one side (eg, upper left or upper center) of the quadrangular first display area DA1 .

Hereinafter, the display device 1 including the organic light emitting display panel will be described as an example as the display device 1 according to the exemplary embodiment, but the display device 1 of the present invention is not limited thereto. As another embodiment, the display device 1 of the present invention may include a display panel such as an inorganic light emitting display panel or a quantum dot light emitting display panel. For example, the light emitting layer of the display element provided in the display panel 10 (refer to FIG. 2 ) may include an organic material, an inorganic material, a quantum dot, an organic material and a quantum dot, or an inorganic material and a quantum dot.

The display device 1 may provide a predetermined image using light emitted from a light emitting element included in each of the plurality of pixels PX disposed in the first display area DA1 and the second display area DA2. can The pixel PX includes a first pixel PX1 and a second pixel PX2 . The first pixels PX1 may be two-dimensionally arranged in the first display area DA1 , and the second pixels PX2 may be two-dimensionally arranged in the second display area DA2 .

The display device 1 may provide a first image (or a main image) by using light emitted from a light emitting element included in each of the plurality of first pixels PX1 disposed in the first display area DA1 . In addition, a second image (or an auxiliary image) may be provided using light emitted from a light emitting element included in each of the plurality of second pixels PX2 disposed in the second display area DA2 . The first image and the second image may each correspond to parts of one image or may be independent images. The second image provided in the second display area DA2 may have a lower resolution than the first image provided in the first display area DA1 .

The display device 1 may include a component 20 to be described later (refer to FIG. 2 ) positioned in the second display area DA2 , and the second display area DA2 is transflective for driving the component 20 . It may include an area (STA).

FIG. 2 is a cross-sectional view schematically illustrating a display device according to an exemplary embodiment, and may correspond to a cross-section taken along line II′ of FIG. 1 .

Referring to FIG. 2 , the display device 1 may include a display panel 10 including a light emitting element and a component 20 positioned below the display panel 10 and corresponding to the second display area DA2 . have.

The component 20 may be located in the second display area DA2 . The component 20 may be an electronic element using light. For example, the component 20 may be an imaging device such as a camera, a sensor that receives and uses light such as an infrared sensor, a sensor that outputs and senses light to measure a distance or recognize a fingerprint, or a small lamp that outputs light. . In the case of the component 20 using light, light of various wavelength bands such as visible light, infrared light, and ultraviolet light may be used.

Light output from the component 20 and/or directed to the component 20 may pass through the semi-transmissive area STA.

The component 20 disposed in the second display area DA2 may include one or a plurality of components. For example, the component 20 may include a light-emitting element and a light-receiving element arranged adjacent to each other. Alternatively, one component 20 itself may have the functions of a light emitting unit and a light receiving unit at the same time.

The display panel 10 includes a substrate 100 , a buffer layer 111 disposed on the substrate 100 , a light emitting element layer 400 disposed on the buffer layer 111 , and a sealing member sealing the light emitting element layer 400 . As such, the thin film encapsulation layer 300 may be included. In addition, the display panel 10 may further include a lower protective film 175 disposed under the substrate 100 .

The substrate 100 may include glass or a polymer resin. In an embodiment, the substrate 100 may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, and polyphenyl. It may include a polymer resin such as polyphenylene sulfide, polyarylate, polyimide, polycarbonate, or cellulose acetate propionate. The substrate 100 including the polymer resin may have flexible, rollable, or bendable properties. The substrate 100 may have a multilayer structure including a layer including the above-described polymer resin and an inorganic layer.

The light emitting element layer 400 may include a circuit layer including a thin film transistor (TFT), an organic light-emitting diode (OLED) as a light emitting element, and an inorganic insulating structure IL′ therebetween.

The first pixel PX1 disposed in the first display area DA1 may include a pixel circuit PC (refer to FIG. 3 ) including a thin film transistor TFT and a first light emitting element LE1 related thereto. . Also, wirings WL electrically connected to the first light emitting elements LE1 may be disposed in the first display area DA1 .

The second pixel PX2 disposed in the second display area DA2 includes a pixel circuit PC including a thin film transistor TFT and a second light emitting element LE2 related thereto. Also, wirings WL electrically connected to the second light emitting elements LE2 may be disposed in the second display area DA2 .

A transflective area STA may be disposed in the second display area DA2 . The semi-transmissive area STA is an area in which the configuration of the pixel circuit PC is not disposed, and may transmit light or a signal. The semi-transmissive area STA corresponds to an area through which light or a signal emitted from the component 20 is transmitted and/or a light or signal incident to the component 20 is transmitted.

In addition, an auxiliary light emitting element OLED' including a transparent electrode may be disposed to correspond to the semi-transmissive area STA, and the semi-transmissive area STA is an area through which light emitted from the auxiliary light-emitting element OLED' is emitted. can also be understood as

The thin film encapsulation layer 300 may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. In this regard, FIG. 2 shows the first and second inorganic encapsulation layers 310 and 330 and the organic encapsulation layer 320 therebetween.

The first and second inorganic encapsulation layers 310 and 330 may include one or more inorganic insulating materials such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. . The organic encapsulation layer 320 may include a polymer-based material. Polymer-based materials include polyethylene terephthalate, polyethylene naphthalate, polycarbonate, polyimide, polyethylene sulfonate, polyoxymethylene, polyarylate, hexamethyldisiloxane, acrylic resin (e.g., polymethyl methacrylate, polyacrylic acid, etc.) or any combination thereof.

The lower protective film 175 may be attached to the lower portion of the substrate 100 to support and protect the substrate 100 . The lower protective film 175 may have an opening 175OP corresponding to the second display area DA2 . By providing the opening 175OP in the lower protective film 175 , the light transmittance of the second display area DA2 may be improved. The lower protective film 175 may include polyethylene terephthalate (PET) or polyimide (PI).

An area of the second display area DA2 may be larger than an area in which the component 20 is disposed. In FIG. 2 , the second display area DA2 and the opening 175OP of the lower protective film 175 have the same area, but the area of the opening 175OP of the lower protective film 175 is equal to the area of the second display area ( It may not match the area of DA2). For example, the area of the opening 175OP of the lower protective film 175 may be smaller than the area of the second display area DA2.

Although not shown, components such as an input sensing member for sensing a touch input, an antireflection member including a polarizer and a retarder or a color filter and a black matrix, and a transparent window are provided on the display panel 10 . more can be placed.

Meanwhile, although the thin film encapsulation layer 300 is used as an encapsulation member for sealing the light emitting element layer 400 in this embodiment, the present invention is not limited thereto. For example, as a member for sealing the light emitting element layer 400 , a sealing substrate (eg, a glass substrate, etc.) that is bonded to the substrate 100 by a sealant or a frit may be used.

3 is an equivalent circuit diagram illustrating one pixel in a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 3 , each pixel PX includes a pixel circuit PC connected to a scan line SL and a data line DL and an organic light emitting diode OLED connected to the pixel circuit PC.

The pixel circuit PC includes a driving TFT (T1), a switching TFT (T2), and a storage capacitor (Cst). The switching thin film transistor T2 is connected to the scan line SL and the data line DL, and the data signal ( Dm) to the driving thin film transistor T1.

The storage capacitor Cst is connected to the switching thin film transistor T2 and the driving voltage line PL, and corresponds to the difference between the voltage received from the switching thin film transistor T2 and the driving voltage ELVDD supplied to the driving voltage line PL. store the voltage

The driving thin film transistor T1 is connected to the driving voltage line PL and the storage capacitor Cst, and a driving current flowing from the driving voltage line PL to the organic light emitting diode OLED in response to the voltage value stored in the storage capacitor Cst. can control The organic light emitting diode (OLED) may emit light having a predetermined luminance by a driving current.

In FIG. 3 , a case in which the pixel circuit PC includes two thin film transistors and one storage capacitor has been described, but the present invention is not limited thereto. For example, the pixel circuit PC may include three or more thin film transistors and/or two or more storage capacitors. In an embodiment, the pixel circuit PC may include seven thin film transistors and one storage capacitor. This will be explained in FIG. 4 .

4 is an equivalent circuit diagram illustrating one pixel in a display device according to an exemplary embodiment of the present invention.

Referring to FIG. 4 , one pixel PX may include a pixel circuit PC and an organic light emitting diode OLED electrically connected to the pixel circuit PC.

For example, as shown in FIG. 4 , the pixel circuit PC may include a plurality of thin film transistors T1 to T7 and a storage capacitor (Cst). The thin film transistors T1 to T7 and the storage capacitor Cst may be connected to the signal lines SL1, SL2, SLp, SLn, EL, DL, the initialization voltage line VIL, and the driving voltage line PL. In some embodiments, at least one of the signal lines SL1 , SL2 , SLp, SLn, EL, and DL, for example, the initialization voltage line VIL and/or the driving voltage line PL is shared by neighboring pixels PXs. can be

The thin film transistor is a driving thin film transistor (T1), a switching thin film transistor (T2), a compensation thin film transistor (T3), a first initialization thin film transistor (T4), an operation control thin film transistor (T5), a light emission control thin film transistor (T6) and a second 2 may include an initialization thin film transistor (T7).

Some of the plurality of thin film transistors T1 to T7 may be provided as n-channel MOSFETs (NMOS), and others may be provided as p-channel MOSFETs (PMOS).

For example, as shown in FIG. 4 , the compensation thin film transistor T3 and the first initialization thin film transistor T4 among the plurality of thin film transistors T1 to T7 are provided as NMOS (n-channel MOSFET), and the rest are PMOS. (p-channel MOSFET) may be provided.

In another embodiment, the compensation thin film transistor T3, the first initialization thin film transistor T4, and the second initialization thin film transistor T7 among the plurality of thin film transistors T1 to T7 are NMOS (n-channel MOSFET). , and the rest may be provided as a p-channel MOSFET (PMOS). Alternatively, only one of the plurality of thin film transistors T1 to T7 may be provided as an NMOS, and the rest may be provided as a PMOS. Alternatively, all of the plurality of thin film transistors T1 to T7 may be formed of NMOS.

The signal line is the first scan line SL1 transmitting the first scan signal Sn, the second scan line SL2 transmitting the second scan signal Sn′, and the first initialized thin film transistor T4. The previous scan line SLp transmitting the signal Sn-1, the emission control line EL transmitting the emission control signal En to the operation control thin film transistor T5 and the emission control thin film transistor T6, the second A next scan line SLn that transmits a subsequent scan signal Sn+1 to the initialization thin film transistor T7, and a data line that crosses the first scan line SL1 and transmits the data signal Dm (DL).

The driving voltage line PL transfers the driving voltage ELVDD to the driving thin film transistor T1 , and the initialization voltage line VIL transfers the driving thin film transistor T1 and an initialization voltage Vint for initializing the pixel electrode.

The driving gate electrode of the driving thin film transistor T1 is connected to the storage capacitor Cst, and the driving source region of the driving thin film transistor T1 is connected to the driving voltage line PL via the operation control thin film transistor T5. The driving drain region of the driving thin film transistor T1 is electrically connected to the pixel electrode of the organic light emitting diode OLED via the emission control thin film transistor T6. The driving thin film transistor T1 receives the data signal Dm according to the switching operation of the switching thin film transistor T2 and supplies the _{driving current I OLED to the organic light emitting diode OLED.}

The switching gate electrode of the switching thin film transistor T2 is connected to the first scan line SL1, the switching source region of the switching thin film transistor T2 is connected to the data line DL, and the switching thin film transistor T2 is connected to the data line DL. The switching drain region of is connected to the driving source region of the driving thin film transistor T1 and connected to the driving voltage line PL via the operation control thin film transistor T5. The switching thin film transistor T2 is turned on according to the first scan signal Sn received through the first scan line SL1 and drives the data signal Dm transmitted through the data line DL to the driving thin film transistor T1 ) to the driving source region and perform a switching operation.

The compensation gate electrode of the compensation thin film transistor T3 is connected to the second scan line SL2. The compensation drain region of the compensation thin film transistor T3 is connected to the driving drain region of the driving thin film transistor T1 and is connected to the pixel electrode of the organic light emitting diode OLED via the emission control thin film transistor T6. The compensation source region of the compensation thin film transistor T3 is connected to the first electrode CE1 of the storage capacitor Cst and the driving gate electrode of the driving thin film transistor T1. In addition, the compensation source region is connected to the first initialization drain region of the first initialization thin film transistor T4.

The compensation thin film transistor T3 is turned on according to the second scan signal Sn' received through the second scan line SL2 to electrically connect the driving gate electrode and the driving drain region of the driving thin film transistor T1. Thus, the driving thin film transistor (T1) is diode-connected.

The first initialization gate electrode of the first initialization thin film transistor T4 is connected to the previous scan line SLp. The first initialization source region of the first initialization thin film transistor T4 is connected to the second initialization source region of the second initialization thin film transistor T7 and the initialization voltage line VIL. The first initialization drain region of the first initialization thin film transistor T4 is connected to the first electrode CE1 of the storage capacitor Cst, the compensation source region of the compensation thin film transistor T3, and the driving gate electrode of the driving thin film transistor T1. connected. The first initialization thin film transistor T4 is turned on according to the previous scan signal Sn-1 received through the previous scan line SLp to apply the initialization voltage Vint to the driving gate electrode of the driving thin film transistor T1. An initialization operation is performed to initialize the voltage of the driving gate electrode of the driving thin film transistor T1 by transferring it.

The operation control gate electrode of the operation control thin film transistor T5 is connected to the light emission control line EL, the operation control source region of the operation control thin film transistor T5 is connected to the driving voltage line PL, and the operation control thin film The operation control drain region of the transistor T5 is connected to the driving source region of the driving thin film transistor T1 and the switching drain region of the switching thin film transistor T2 .

The emission control gate electrode of the emission control thin film transistor T6 is connected to the emission control line EL, and the emission control source region of the emission control thin film transistor T6 is the driving drain region and the compensation thin film of the driving thin film transistor T1. It is connected to the compensation drain region of the transistor T3, and the emission control drain region of the emission control thin film transistor T6 is the second initialization drain region of the second initialization thin film transistor T7 and the pixel electrode of the organic light emitting diode (OLED). is electrically connected to

The operation control thin film transistor T5 and the light emission control thin film transistor T6 are simultaneously turned on according to the light emission control signal En received through the light emission control line EL, and the driving voltage ELVDD is applied to the organic light emitting diode ( OLED) to allow the driving current I _OLED to flow through the organic light emitting diode (OLED).

The second initialization gate electrode of the second initialization thin film transistor T7 is then connected to the scan line SLn, and the second initialization drain region of the second initialization thin film transistor T7 emits light of the emission control thin film transistor T6. It is connected to the control drain region and the pixel electrode of the organic light emitting diode (OLED), and the second initialization source region of the second initialization thin film transistor T7 includes the first initialization source region and the initialization voltage line of the first initialization thin film transistor T4. (VIL) is connected. After being transmitted through the scan line SLn, the second initialization thin film transistor T7 is turned on according to the scan signal Sn+1 to initialize the pixel electrode of the organic light emitting diode OLED.

The second initialization thin film transistor T7 may be connected to the subsequent scan line SLn as shown in FIG. 4 . As another embodiment, the second initialization thin film transistor T7 may be connected to the emission control line EL and driven according to the emission control signal En. Meanwhile, the positions of the source regions and the drain regions may be changed according to the type of transistor (p-type or n-type).

The storage capacitor Cst includes a first electrode CE1 and a second electrode CE2 . The first electrode CE1 of the storage capacitor Cst is connected to the driving gate electrode of the driving thin film transistor T1 , and the second electrode CE2 of the storage capacitor Cst is connected to the driving voltage line PL. The storage capacitor Cst may store a charge corresponding to a difference between the driving gate electrode voltage of the driving thin film transistor T1 and the driving voltage ELVDD.

A detailed operation of each pixel PX according to an exemplary embodiment is as follows.

During the initialization period, when the previous scan signal Sn-1 is supplied through the previous scan line SLp, the first initialization thin film transistor T4 is turned on in response to the previous scan signal Sn-1. ), and the driving thin film transistor T1 is initialized by the initialization voltage Vint supplied from the initialization voltage line VIL.

During the data programming period, when the first scan signal Sn and the second scan signal Sn' are supplied through the first scan line SL1 and the second scan line SL2, the first scan signal Sn and The switching thin film transistor T2 and the compensation thin film transistor T3 are turned on in response to the second scan signal Sn'. At this time, the driving thin film transistor T1 is diode-connected by the turned-on compensation thin film transistor T3 and is forward biased.

Then, in the data signal Dm supplied from the data line DL, the compensation voltage (Dm+Vth, Vth is a (-) value) reduced by the threshold voltage Vth of the driving thin film transistor T1 is driven. It is applied to the driving gate electrode G1 of the thin film transistor T1.

A driving voltage ELVDD and a compensation voltage Dm+Vth are applied to both ends of the storage capacitor Cst, and a charge corresponding to the voltage difference between both ends is stored in the storage capacitor Cst.

During the light emission period, the operation control thin film transistor T5 and the light emission control thin film transistor T6 are turned on by the light emission control signal En supplied from the light emission control line EL. The driving current (I _OLED) in accordance with the voltage difference between the driving thin film transistor (T1) driving gate electrode (G1) voltage and the drive voltage (ELVDD) of a generated, and the drive current through the light emission control thin film transistor (T6) (I _OLED ) is supplied to the organic light emitting diode (OLED).

In the present embodiment, at least one of the plurality of thin film transistors T1 to T7 includes a semiconductor layer including oxide, and the rest includes a semiconductor layer including silicon.

Specifically, the driving thin film transistor T1, which directly affects the brightness of the display device, is configured to include a semiconductor layer made of polycrystalline silicon having high reliability, thereby realizing a high-resolution display device.

On the other hand, since the oxide semiconductor has high carrier mobility and low leakage current, the voltage drop is not large even if the driving time is long. That is, since the color change of the image according to the voltage drop is not large even during low-frequency driving, low-frequency driving is possible.

As described above, since the oxide semiconductor has an advantage of a small leakage current, the compensation thin film transistor T3 connected to the driving gate electrode G1 of the driving thin film transistor T1, the first initialization thin film transistor T4, and the second By employing at least one of the initialization thin film transistors T7 as an oxide semiconductor, it is possible to prevent leakage current flowing to the driving gate electrode G1 and reduce power consumption.

5 is a plan view schematically illustrating a part of a display device according to an exemplary embodiment, and schematically illustrates an enlarged partial area of the second display area DA2.

Referring to FIG. 5 , second pixels PX2 and auxiliary pixels Pr, Pg, and Pb may be disposed in the second display area DA2. Each of the second pixels PX2 may emit light through a second light emitting element LE2 (refer to FIG. 2 ), for example, an organic light emitting diode (OLED). An area where the second light emitting element LE2 emits light may be a light emitting area. Also, the sub-pixels Pr, Pg, and Pb may be disposed together with the second pixels PX2 to increase the luminance of light emitted from the second display area DA2, and the sub-pixels Pr, Pg , Pb) may emit light through the auxiliary light emitting unit 200 ′ (refer to FIG. 6A ), for example, an organic light emitting diode (OLED).

Although FIG. 5 illustrates that the second pixels PX2 are disposed to be spaced apart from each other, the second pixels PX2 may be disposed to form one group, and the second pixels PX2 included in one group may be disposed. The number of may be designed to be modified according to the resolution of the second display area DA2. For example, eight second pixels PX2 may be gathered to form one group. The second pixels PX2 may implement red (R), green (G), and blue (B) colors.

A plurality of wirings WL electrically connecting the second pixels PX2 may be disposed in the second display area DA2 . The plurality of wirings WL includes a first wiring WL1 and a second wiring WL2 extending in a direction crossing each other, respectively. The first wiring WL1 may include a data line DL (refer to FIG. 4 ) or a driving voltage line PL (refer to FIG. 4 ), and the second wiring WL2 may include the scan lines SL1 , SL2 , SLp, SLn, 4) may be included.

The first wiring WL1 may be disposed to extend in the first direction (eg, the y-direction) in order to connect the plurality of second pixels PX2 arranged in the same column. The second wiring WL2 may be disposed to extend in the second direction (eg, the x direction) to connect the plurality of second pixels PX2 arranged in the same row. The first direction and the second direction may be orthogonal to each other, or may be different directions that are not orthogonal to each other.

Although the first wiring WL1 and the second wiring WL2 are shown as straight lines in FIG. 5 , depending on the arrangement of the second pixels PX2 , the first wiring WL1 and the second wiring WL2 are partially bent or It can be bent and arranged.

In the second display area DA2 , the second pixels PX2 may be spaced apart from each other to define the transflective area STA. The semi-transmissive area STA may be defined as an area in the second display area DA2 excluding the area in which the second pixels PX2 and the wirings WL are located. Although the semi-transmissive area STA is formed in a quadrangle in FIG. 5 , it may be formed in various ways such as polygonal, circular, oval, diamond-shaped, cross-shaped, etc. depending on the arrangement and shape of the second pixels PX2 and wirings WL. may be

In the semi-transmissive area STA as described above with reference to FIG. 2 , an auxiliary light emitting element OLED' including a transparent electrode may be disposed to correspond to the semi-transmissive area STA.

In an embodiment, as shown in FIG. 5 , the second pixel PX2 and the semi-transmissive area STA adjacent to each other may implement the same color. 'Adjacent to each other' may mean that the distance between the center of the second pixel PX2 and the center of the semi-transmissive area STA is the minimum.

For example, the second pixel PX2 may implement blue B, and a blue sub-pixel Pb may be disposed in the semi-transmissive area STA adjacent to the second pixel PX2.

As shown in the drawing, the plurality of second pixels PX2 arranged in the first direction (eg, the x direction) are sequentially blue (B), green (G), red (R), and green (G). may be implemented, respectively, and a blue sub-pixel Pb, a green sub-pixel Pg, a red sub-pixel Pr, and a green sub-pixel in the plurality of transflective areas STA adjacent to the plurality of second pixels PX2, respectively. A pixel Pg may be disposed.

In an embodiment, the plurality of second pixels PX2 arranged in the second direction (eg, the y-direction) may implement the same color or different colors. For example, based on the drawing, the second pixel PX2 disposed above may implement blue (B), and the second pixel PX2 disposed below may implement red (R). Alternatively, all of the plurality of second pixels PX2 arranged in the second direction may implement green G.

Sub-pixels Pr, Pg, and Pb may be disposed in the plurality of transflective areas STA adjacent to the plurality of second pixels PX2 according to colors implemented by the plurality of second pixels PX2 . . For example, a blue sub-pixel Pb may be disposed in the upper transflective area STA with reference to the drawing, and a red sub-pixel Pr may be disposed in the lower semi-transmissive area STA. . Also, the green sub-pixel Pg may be disposed in all of the plurality of transflective areas STAs disposed in the second direction.

6A is a cross-sectional view schematically illustrating a cross-section taken along line II-II' of FIG. 5 .

Referring to FIG. 6A , the display device 1 (refer to FIG. 1 ) according to an embodiment of the present invention may include a second display area DA2 including a transflective area STA and a second pixel PX2. and may include an auxiliary light emitting unit 200 ′ disposed to correspond to the semi-transmissive area STA. In addition, the display device 1 includes a first thin film transistor TFT1 disposed on a substrate 100 and including a first semiconductor layer A1 and a first gate electrode G1, a second semiconductor layer A2, and A second thin film transistor TFT2 including a second gate electrode G2 and a storage capacitor Cst may be included.

In this embodiment, the auxiliary light emitting unit 200' includes an auxiliary pixel electrode 210', an auxiliary intermediate layer 220', and a counter electrode 230, and the auxiliary pixel electrode 210' is a first semiconductor layer. It may be disposed on the same floor as (A1). Also, the auxiliary pixel electrode 210 ′ may include the same material as the first semiconductor layer A1 .

Hereinafter, a configuration included in the display device 1 will be described in more detail according to a stacking order with reference to FIG. 6A .

The substrate 100 may include a glass material, a ceramic material, a metal material, or a material having flexible or bendable properties. When the substrate 100 has a flexible or bendable characteristic, the substrate 100 may include polyethersulfone, polyacrylate, polyetherimide, polyethylene naphthalate, or polyethylene. Polymer resins such as polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate or cellulose acetate propionate may include

The substrate 100 may have a single-layer or multi-layer structure of the above material, and may further include an inorganic layer in the case of a multi-layer structure. In some embodiments, the substrate 100 may have an organic/inorganic/organic structure.

A barrier layer 110 may be further included between the substrate 100 and the buffer layer 111 . The barrier layer 110 may serve to prevent or minimize the penetration of impurities from the substrate 100 into the first and second semiconductor layers A1 and A2 . The barrier layer 110 may include an inorganic material such as an oxide or a nitride, an organic material, or an organic/inorganic composite, and may have a single-layer or multi-layer structure of an inorganic material and an organic material.

The first and second semiconductor layers A1 and A2 may be disposed on the buffer layer 111 , and the auxiliary light emitting unit 200 ′ may be disposed to correspond to the transflective area STA. The auxiliary light emitting unit 200 ′ includes an auxiliary pixel electrode 210 ′, an auxiliary intermediate layer 220 ′, and a counter electrode 230 . The auxiliary intermediate layer 220 ′ and the counter electrode 230 of the auxiliary light emitting unit 200 ′ will be described later.

The first and second semiconductor layers A1 and A2 and the auxiliary pixel electrode 210 ′ may include an oxide semiconductor material. The first and second semiconductor layers A1 and A2 and the auxiliary pixel electrode 210 ′ are, for example, indium (In), gallium (Ga), stanium (Sn), zirconium (Zr), vanadium (V), and hafnium. At least selected from the group comprising (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce) and zinc (Zn) oxides of one or more substances.

For example, the first and second semiconductor layers A1 and A2 may be an ITZO (InSnZnO) semiconductor layer, an IGZO (InGaZnO) semiconductor layer, or the like. Oxide semiconductor has a wide band gap (about 3.1 eV), high carrier mobility, and low leakage current, so the voltage drop is not large even if the driving time is long. The advantage is that there is not much change.

The auxiliary pixel electrode 210 ′ may be a transparent electrode. For example, the auxiliary pixel electrode 210 ′ may include InSnZnO (ITZO), InGaZnO (IGZO), or the like. The auxiliary pixel electrode 210' undergoes a process of making it conductive by plasma treatment, etc. In this case, since the auxiliary pixel electrode 210' is disposed to correspond to the semi-transmissive area STA, it is exposed to plasma treatment to perform a function as a conductor. can In addition, the sub-pixel electrode 210 ′, which is a transparent electrode, may have high transmittance.

The first and second semiconductor layers A1 and A2 are first and second channel regions C1 and C2 and first and second semiconductor layers C1 and C2 respectively disposed on one side and the other side of the first and second channel regions C1 and C2. and second source regions S1 and S2 and first and second drain regions D1 and D2. The first and second semiconductor layers A1 and A2 may be configured as a single layer or a multilayer.

A lower metal layer BML may be disposed between the barrier layer 110 and the buffer layer 111 . The lower metal layer BML may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), and the like, and may be formed as a multi-layer or a single layer including the above material. have. For example, the lower metal layer BML may have a multilayer structure of Ti/Al/Ti.

The lower metal layer BML may be disposed to overlap the first semiconductor layer A1 including an oxide semiconductor material. Since the first semiconductor layer A1 including the oxide semiconductor material is vulnerable to light, the lower metal layer BML is photocurrent to the first semiconductor layer A1 by external light incident from the substrate 100 side. It is possible to prevent a change in device characteristics of the first thin film transistor TFT1 including the oxide semiconductor material due to the induced ?

In FIG. 6A , the lower metal layer BML is illustrated to overlap at least the first channel region C1 of the first thin film transistor TFT1, but the lower metal layer BML is extended to form the first layer of the first thin film transistor TFT1. The entirety of the semiconductor layer A1 may overlap. A third gate insulating layer 118 may be disposed on the first and second semiconductor layers A1 and A2 . The third gate insulating layer 118 is silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), titanium oxide (TiO ₂ ), tantalum oxide (Ta) ₂ O ₅ ), hafnium oxide (HfO ₂ ), or zinc oxide (ZnO ₂ ) and the like.

In one embodiment, as shown in FIG. 6A , the third gate insulating layer 118 may be patterned to overlap a portion of the first and second semiconductor layers A1 and A2 . That is, the third gate insulating layer 118 may be patterned to expose the first and second source regions S1 and S2 and the first and second drain regions D1 and D2, and the third gate insulating layer The side surface of 118 and the side surfaces of the first and second gate electrodes G1 and G2 may be the same etched surface.

Regions in which the third gate insulating layer 118 and the first and second semiconductor layers A1 and A2 overlap may be understood as first and second channel regions C1 and C2. The first and second source regions S1 and S2 and the first and second drain regions D1 and D2 are subjected to a conductive process such as plasma treatment, in which case the first and second semiconductor layers A1 and A2 are formed. The portion overlapping the third gate insulating layer 118 (ie, the first and second channel regions C1 and C2) is not exposed to the plasma treatment, so that the first and second source regions S1 and S2 and the first and second source regions S1 and S2 It has properties different from those of the first and second drain regions D1 and D2. That is, when plasma treatment is performed on the first and second semiconductor layers A1 and A2, the first and second gate electrodes G1 and G2 positioned on the third gate insulating layer 118 are self-aligned. By using as a mask, first and second channel regions C1 and C2 that are not subjected to plasma treatment are formed at positions overlapping the third gate insulating layer 118 , and the first and second channel regions C1 and C2 are formed. Plasma-treated first and second source regions S1 and S2 and first and second drain regions D1 and D2 may be respectively formed on both sides of the .

In another embodiment, the third gate insulating layer 118 is not patterned to overlap a portion of the first and second semiconductor layers A1 and A2, but to cover the first and second semiconductor layers A1 and A2. It may be disposed on the entire surface of the substrate 100 .

The first and second gate electrodes G1 and G2 may be disposed on the third gate insulating layer 118 to at least partially overlap the first and second semiconductor layers A1 and A2. The first and second gate electrodes G1 and G2 are aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium ( Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), copper (Cu) at least one metal selected from a single layer or It may be formed in multiple layers.

In one embodiment, the first thin film transistor TFT1 and the second thin film transistor TFT2 may be any one of the plurality of thin film transistors T1 to T7 described above with reference to FIG. 4 .

An interlayer insulating layer IL may be provided to cover the first and second semiconductor layers A1 and A2 and the first and second gate electrodes G1 and G2. The interlayer insulating layer (IL) is silicon oxide (SiO ₂ ), silicon nitride (SiN _X ), silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), titanium oxide (TiO ₂ ), tantalum oxide (Ta ₂ O) ₅ ), hafnium oxide (HfO ₂ ) or zinc oxide (ZnO ₂ ) and the like.

The first electrode layer E1 may be disposed on the interlayer insulating layer IL, and the planarization layer 120 may be disposed on the first electrode layer E1.

In one embodiment, the first electrode layer E1 is a bridge connecting the first semiconductor layer A1 of the first thin film transistor TFT1 and the auxiliary pixel electrode 210 ′ of the auxiliary light emitting unit 200 ′. ) can play a role.

The first electrode layer E1 includes aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), and iridium (Ir). ), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu) may be formed in a single layer or in multiple layers. . In an embodiment, the first electrode layer E1 may be a single layer of Mo or a multilayer of Mo/Al/Mo.

The planarization layer 120 may be formed as a single layer or a multilayer film made of an organic material, and provides a flat top surface. The planarization layer 120 is a general purpose polymer such as Benzocyclobutene (BCB), polyimide, HMDSO (Hexamethyldisiloxane), Polymethylmethacrylate (PMMA), or Polystyrene (PS), a polymer derivative having a phenolic group, an acrylic polymer , imide-based polymers, arylether-based polymers, amide-based polymers, fluorine-based polymers, p-xylene-based polymers, vinyl alcohol-based polymers, and blends thereof.

In an embodiment, as shown in FIG. 6A , the planarization layer 120 may be provided in multiple layers to include the first planarization layer 121 and the second planarization layer 123 . In this case, the second electrode layer E2 may be disposed on the first planarization layer 121 , and the second electrode layer E2 may include the same material as the first electrode layer E1 .

In one embodiment, the second electrode layer E2 may serve to connect the first electrode layer E1 and the pixel electrode 210 of the main light emitting unit 200 to be described later. Both the pixel electrode 210 of the main light emitting unit 200 and the auxiliary pixel electrode 210 ′ of the auxiliary light emitting unit 200 ′ may be connected to the first thin film transistor TFT1 , and as a result, the pixel electrode 210 and the auxiliary pixel electrode 210 ′ The pixel electrodes 210 ′ may be driven simultaneously.

Although the figure shows that the pixel electrode 210 of the main light emitting unit 200 is connected to the first electrode layer E1 through the second electrode layer E2, the second electrode layer E2 may be omitted and the main light emitting unit 200 ) of the pixel electrode 210 may be directly connected to the first electrode layer E1 .

Wirings WL may be respectively disposed on the barrier layer 110 , the interlayer insulating layer IL, and the planarization layer 120 . The wirings WL may be any one of a data line DL (refer to FIG. 4 ), a driving voltage line PL (refer to FIG. 4 ), and scan lines SL1 , SL2 , SLp, SLn (refer to FIG. 4 ).

A main light emitting unit 200 is disposed on the planarization layer 120 , and the main light emitting unit 200 includes a pixel electrode 210 , an intermediate layer 220 , and a counter electrode 230 .

The pixel electrode 210 may be a (semi)transmissive electrode or a reflective electrode. In some embodiments, the pixel electrode 210 includes a reflective layer formed of Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, and a compound thereof, and a transparent or translucent electrode layer formed on the reflective layer. can do. The transparent or translucent electrode layer includes indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In ₂ O ₃ ; indium oxide), and indium gallium. At least one selected from the group consisting of indium gallium oxide (IGO) and aluminum zinc oxide (AZO) may be included. In some embodiments, the pixel electrode 210 may be formed of ITO/Ag/ITO.

In an embodiment, the distance d1 between the pixel electrode 210 of the main light emitting unit 200 and the substrate 100 is the distance d1 between the auxiliary pixel electrode 210 ′ of the auxiliary light emitting unit 200 ′ from the substrate 100 . It may be farther than the distance d2.

A pixel defining layer 125 may be disposed on the planarization layer 120 . In addition, the pixel defining layer 125 increases the distance between the edge of the pixel electrode 210 and the counter electrode 230 on the pixel electrode 210 to prevent arcs from occurring at the edge of the pixel electrode 210 . may play a role in preventing

The pixel defining layer 125 is made of one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin, and may be formed by spin coating or the like.

The intermediate layer 220 of the main light emitting unit 200 and the auxiliary intermediate layer 220 ′ of the auxiliary light emitting unit 200 ′ may include an organic light emitting layer. The organic light emitting layer may include an organic material including a fluorescent or phosphorescent material emitting red, green, blue, or white light. The organic light emitting layer may be a low molecular weight organic material or a high molecular weight organic material, and below and above the organic light emitting layer, a hole transport layer (HTL), a hole injection layer (HIL), an electron transport layer (ETL; electron transport layer) and A functional layer such as an electron injection layer (EIL) may be optionally further disposed.

The intermediate layer 220 and the auxiliary intermediate layer 220 ′ may be disposed to correspond to each of the plurality of pixel electrodes 210 and the plurality of auxiliary pixel electrodes 210 ′. However, the present invention is not limited thereto. Various modifications are possible for the intermediate layer 220 and the auxiliary intermediate layer 220 ′, such as being able to include an integral layer over the plurality of pixel electrodes 210 and the plurality of auxiliary pixel electrodes 210 ′.

In an embodiment, the intermediate layer 220 of the main light emitting unit 200 and the auxiliary intermediate layer 220 ′ of the auxiliary light emitting unit 200 ′ may emit light of the same wavelength. For example, the intermediate layer 220 of the main light emitting unit 200 disposed to correspond to the second pixel PX2 may emit light of a blue (B) wavelength, and an auxiliary layer disposed to correspond to the semi-transmissive area STA. The auxiliary intermediate layer 220' of the light emitting unit 200' may also emit light of a blue (B) wavelength. That is, the blue sub-pixel Pb may be disposed to correspond to the transflective area STA.

The counter electrode 230 may be a light-transmitting electrode or a reflective electrode. In some embodiments, the counter electrode 230 may be a transparent or translucent electrode, and is formed of a metal thin film having a small work function including Li, Ca, LiF/Ca, LiF/Al, Al, Ag, Mg, and compounds thereof. can be formed. In addition, a transparent conductive oxide (TCO) layer such as ITO, IZO, ZnO, or In ₂ O _{3 may be further disposed on the metal thin film.} The counter electrode 230 is disposed over the first and second display areas DA1 and DA2 , and may be disposed on the intermediate layer 220 , the auxiliary intermediate layer 220 ′, and the pixel defining layer 125 . The counter electrode 230 is integrally formed in the plurality of main light emitting units 200 and the plurality of auxiliary light emitting units 200 ′ to include a plurality of pixel electrodes 210 and a plurality of auxiliary pixel electrodes 210 . ') can be dealt with.

A capping layer (not shown) may be disposed on the counter electrode 230 . The capping layer may be configured to protect the counter electrode 230 and may be configured to increase light extraction efficiency. For example, the capping layer may be made of a material having a refractive index of 1.2 to 3.1. In addition, the capping layer may be made of an organic material. However, it is also possible that the capping layer is removed.

Referring to FIG. 6A , the component 20 may be positioned under the second display area DA2 . The component 20 may be an electronic element using light or sound. For example, the component 20 is a sensor that receives and uses light, such as an infrared sensor, a sensor that outputs and senses light or sound to measure a distance or recognizes a fingerprint, etc., a small lamp that outputs light, or a speaker that outputs sound , a camera, and the like. Of course, in the case of an electronic element using light, light of various wavelength bands such as visible light, infrared light, and ultraviolet light may be used. The number of components 20 disposed in the second display area DA2 may be plural. For example, as the component 20 , a light emitting device and a light receiving device may be provided together in one second display area DA2 . Alternatively, the light emitting unit and the light receiving unit may be simultaneously provided in one component 20 .

A plurality of second pixels PX2 and a plurality of transflective areas STA may be disposed in the second display area DA2 . The plurality of semi-transmissive areas STA are the light/signal emitted by the plurality of auxiliary light-emitting units 200 ′ or light/signal emitted from the component 20 or light/signal incident to the component 20 are transmitted (tansmission). area can be understood.

The semi-transmissive area STA may include first to fourth holes H1 , H2 , H3 and H4 to correspond to the semi-transmissive area STA.

The fact that the first to fourth holes H1 , H2 , H3 , and H4 are formed to correspond to the semi-transmissive area STA means that the interlayer insulating layer IL, the planarization layer 120 and the pixel are formed in the semi-transmissive area STA. As this means that the member such as the defining layer 125 is removed, the light transmittance in the semi-transmissive area STA may be significantly increased.

The display device 1 according to an embodiment of the present invention has a first display area DA1 including a first pixel PX1 and a second display area including a transflective area STA and a second pixel PX2 . The area DA2 may be included. A first semiconductor layer A1 may be disposed on the substrate 100 to correspond to the second pixel PX2 , and auxiliary light emission is provided on the same layer as the first semiconductor layer A1 to correspond to the transflective area STA. The sub-pixel electrode 210' of the part 200' may be disposed. In this case, the first semiconductor layer A1 and the auxiliary pixel electrode 210 ′ may include the same material.

In addition, in one embodiment, the auxiliary pixel electrode 210 ′ is connected to the first semiconductor layer A1 of the first thin film transistor TFT1 through the first electrode layer E1 disposed on the interlayer insulating layer IL. It can be connected and driven.

As a comparative example, in order to form the auxiliary light emitting part in the area through which light is transmitted, the pixel electrode of the main light emitting unit may be extended to correspond to the area through which light is transmitted. In this case, since the auxiliary pixel electrode of the auxiliary light emitting unit disposed to correspond to the semi-transmissive region for light transmission must be made of a transparent electrode, the pixel electrode of the main light emitting unit is a dual pixel electrode including a main pixel electrode and a transparent auxiliary pixel electrode. is provided with In order to form the pixel electrode of the main light emitting part, the main pixel electrode is disposed on the substrate and then primary patterning is performed, and after the auxiliary pixel electrode is disposed on the main pixel electrode, secondary patterning is performed.

That is, since the materials constituting the main pixel electrode and the auxiliary pixel electrode are different, a total of two patterning processes are performed to form the main light emitting part including the double pixel electrode, and a mask process is added.

However, when the auxiliary pixel electrode 210 ′ of the auxiliary light emitting unit 200 ′ is disposed on the same layer as the first semiconductor layer A1 corresponding to the transflective area STA as in an embodiment of the present invention, Since a basic patterning process is performed when the first semiconductor layer A1 is formed, a separate patterning process for forming the auxiliary pixel electrode 210 ′ of the auxiliary light emitting unit 200 ′ may not be required. That is, since a separate mask process is not required, cost and time may be saved when manufacturing the display device 1 .

In addition, by disposing the auxiliary light emitting part 200 ′ in the area through which light is transmitted, luminance may be increased compared to when only the second pixel PX2 is provided in the second display area DA2 .

FIG. 6B is a cross-sectional view schematically illustrating a cross-section taken along line II-II' of FIG. 5 . In FIG. 6B , the same reference numerals as those of FIG. 6A refer to the same members, and thus redundant descriptions thereof will be omitted.

Referring to FIG. 6B , a first thin film transistor TFT1 , a second thin film transistor TFT2 , a main light emitting unit 200 , and an auxiliary light emitting unit 200 ′ may be included on the substrate 100 .

In FIG. 6A , the first and second semiconductor layers A1 and A2 are illustrated to include an oxide semiconductor material, but as in FIG. 6B , the first and second semiconductor layers A1 and A2 are disposed on different layers. Materials constituting the first and second semiconductor layers A1 and A2 may be different from each other.

For example, the first semiconductor layer A1 may include a silicon semiconductor material such as amorphous silicon or polysilicon, and the second semiconductor layer A2 may include an oxide semiconductor material.

In an embodiment, the auxiliary pixel electrode 210 ′ of the auxiliary light emitting unit 200 ′ may be disposed on the same layer as the second semiconductor layer A2 including an oxide semiconductor material. Since the first and second semiconductor layers A1 and A2 must be disposed on different layers, the interlayer insulating layer IL may include the first interlayer insulating layer 117 and the second interlayer insulating layer 119, The second semiconductor layer A2 and the auxiliary pixel electrode 210 ′ of the auxiliary light emitting unit 200 ′ may be disposed on the first interlayer insulating layer 117 .

Hereinafter, a configuration included in the display device 1 will be described in more detail according to a stacking order with reference to FIG. 6B .

The substrate 100 may include a glass material, a ceramic material, a metal material, or a material having flexible or bendable properties. The substrate 100 may have a single-layer or multi-layer structure of the above material, and may further include an inorganic layer in the case of a multi-layer structure. In some embodiments, the substrate 100 may have an organic/inorganic/organic structure.

A first semiconductor layer A1 may be disposed on the buffer layer 111 . The first semiconductor layer A1 may include amorphous silicon or polysilicon.

The first semiconductor layer A1 may include a first channel region C1 and a first source region S1 and a first drain region D1 disposed on both sides of the first channel region C1. . The first semiconductor layer A1 may be formed of a single layer or a multilayer.

A first gate insulating layer 113 and a second gate insulating layer 115 may be stacked on the substrate 100 to cover the first semiconductor layer A1 . The first gate insulating layer 113 and the second gate insulating layer 115 are silicon oxide (SiO ₂ ), silicon nitride (SiN _x ), silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), and titanium oxide. (TiO ₂ ), tantalum oxide (Ta ₂ O ₅ ), hafnium oxide (HfO ₂ ), or zinc oxide (ZnO ₂ ) and the like.

The first gate electrode G1 may be disposed on the first gate insulating layer 113 to at least partially overlap the first semiconductor layer A1 .

In an embodiment, the storage capacitor Cst is provided with the first electrode CE1 and the second electrode CE2 , and may overlap the first thin film transistor TFT1 as shown in FIG. 6B . For example, the first gate electrode G1 of the first thin film transistor TFT1 may function as the first electrode CE1 of the storage capacitor Cst. Unlike this, the storage capacitor Cst does not overlap the first thin film transistor TFT1 and may exist separately.

The second electrode CE2 of the storage capacitor Cst overlaps the first electrode CE1 with the second gate insulating layer 115 interposed therebetween to form a capacitance. In this case, the second gate insulating layer 115 may function as a dielectric layer of the storage capacitor Cst.

A first interlayer insulating layer 117 and a second interlayer insulating layer 119 may be provided on the second gate insulating layer 115 to cover the second electrode CE2 of the storage capacitor Cst.

A second semiconductor layer A2 may be disposed on the first interlayer insulating layer 117 , and an auxiliary light emitting unit 200 ′ may be disposed to correspond to the transflective area STA.

The second semiconductor layer A2 includes a second channel region C2 and a second source region S2 and a second drain region D2 respectively disposed on one side and the other side of the second channel region C2. can do.

The auxiliary light emitting unit 200 ′ includes an auxiliary pixel electrode 210 ′, an auxiliary intermediate layer 220 ′, and a counter electrode 230 .

The second semiconductor layer A2 and the sub-pixel electrode 210 ′ may include an oxide semiconductor material. The second semiconductor layer A2 and the auxiliary pixel electrode 210 ′ are, for example, indium (In), gallium (Ga), stanium (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), and cadmium. Oxide of at least one material selected from the group comprising (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce) and zinc (Zn) may include. For example, the second semiconductor layer A2 may be an InSnZnO (ITZO) semiconductor layer, an InGaZnO (IGZO) semiconductor layer, or the like.

The auxiliary pixel electrode 210 ′ may be a transparent electrode. For example, the auxiliary pixel electrode 210 ′ may include InSnZnO (ITZO), InGaZnO (IGZO), or the like. The auxiliary pixel electrode 210' undergoes a process of making it conductive by plasma treatment, etc. In this case, since the auxiliary pixel electrode 210' is disposed to correspond to the semi-transmissive area STA, it is exposed to plasma treatment to perform a function as a conductor. can In addition, the sub-pixel electrode 210 ′, which is a transparent electrode, may have high transmittance.

A lower gate electrode G2a may be disposed under the second semiconductor layer A2. The lower gate electrode G2a includes aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), and iridium (Ir). ), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu) may be formed in a single layer or in multiple layers. .

A third gate insulating layer 118 may be disposed on the second semiconductor layer A2 . In an embodiment, as shown in FIG. 6B , the third gate insulating layer 118 may be patterned to overlap a portion of the second semiconductor layer A2 .

In another embodiment, the third gate insulating layer 118 is not patterned to overlap a portion of the second semiconductor layer A2 , but is disposed on the entire surface of the substrate 100 to cover the second semiconductor layer A2 . could be

An upper gate electrode G2b may be disposed on the third gate insulating layer 118 to at least partially overlap the second semiconductor layer A2. The upper gate electrode G2b includes aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), and iridium (Ir). ), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu) may be formed in a single layer or in multiple layers. .

In one embodiment, the first thin film transistor TFT1 and the second thin film transistor TFT2 may be any one of the plurality of thin film transistors T1 to T7 described above with reference to FIG. 4 .

A second interlayer insulating layer 119 may be provided to cover the second gate electrode G2 and the auxiliary pixel electrode 210 ′. A first electrode layer E1 may be disposed on the second interlayer insulating layer 119 , and a planarization layer 120 may be disposed on the first electrode layer E1 .

In one embodiment, the first electrode layer E1 is a bridge connecting the first semiconductor layer A1 of the first thin film transistor TFT1 and the auxiliary pixel electrode 210 ′ of the auxiliary light emitting unit 200 ′. ) can play a role. The first electrode layer E1 may be a single layer of Mo or a multilayer of Mo/Al/Mo.

In one embodiment, as shown in FIG. 6B , the planarization layer 120 may be provided in multiple layers to include the first planarization layer 121 and the second planarization layer 123 . In this case, the second electrode layer E2 may be disposed on the first planarization layer 121 , and the second electrode layer E2 may include the same material as the first electrode layer E1 .

In an embodiment, the second electrode layer E2 may serve to connect the first electrode layer E1 and the pixel electrode 210 of the main light emitting unit 200 . Both the pixel electrode 210 of the main light emitting unit 200 and the auxiliary pixel electrode 210 ′ of the auxiliary light emitting unit 200 ′ may be connected to the first thin film transistor TFT1 , and as a result, the pixel electrode 210 and the auxiliary pixel electrode 210 ′ The pixel electrodes 210 ′ may be driven simultaneously.

Although the figure shows that the pixel electrode 210 of the main light emitting unit 200 is connected to the first electrode layer E1 through the second electrode layer E2, the second electrode layer E2 may be omitted and the main light emitting unit 200 ) of the pixel electrode 210 may be directly connected to the first electrode layer E1 .

Wirings WL may be respectively disposed on the second gate insulating layer 115 , the second interlayer insulating layer 119 , and the first planarization layer 121 . The wirings WL may be any one of a data line DL (refer to FIG. 4 ), a driving voltage line PL (refer to FIG. 4 ), and scan lines SL1 , SL2 , SLp, SLn (refer to FIG. 4 ).

A main light emitting unit 200 is disposed on the planarization layer 120 , and the main light emitting unit 200 includes a pixel electrode 210 , an intermediate layer 220 , and a counter electrode 230 .

The pixel electrode 210 may be a (semi)transmissive electrode or a reflective electrode. In some embodiments, the pixel electrode 210 may be formed of ITO/Ag/ITO.

A pixel defining layer 125 may be disposed on the planarization layer 120 . The pixel defining layer 125 is made of one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin, and may be formed by spin coating or the like.

The intermediate layer 220 of the main light emitting unit 200 and the auxiliary intermediate layer 220 ′ of the auxiliary light emitting unit 200 ′ may include an organic light emitting layer. The organic light emitting layer may include an organic material including a fluorescent or phosphorescent material emitting red, green, blue, or white light.

The intermediate layer 220 and the auxiliary intermediate layer 220 ′ may be disposed to correspond to each of the plurality of pixel electrodes 210 and the plurality of auxiliary pixel electrodes 210 ′. However, the present invention is not limited thereto. Various modifications are possible for the intermediate layer 220 and the auxiliary intermediate layer 220 ′, such as being able to include an integral layer over the plurality of pixel electrodes 210 and the plurality of auxiliary pixel electrodes 210 ′.

In an embodiment, the intermediate layer 220 of the main light emitting unit 200 and the auxiliary intermediate layer 220 ′ of the auxiliary light emitting unit 200 ′ may emit light of the same wavelength. For example, the intermediate layer 220 of the main light emitting unit 200 disposed to correspond to the second pixel PX2 may emit light of a blue (B) wavelength, and an auxiliary layer disposed to correspond to the semi-transmissive area STA. The auxiliary intermediate layer 220' of the light emitting unit 200' may also emit light of a blue (B) wavelength. That is, the blue sub-pixel Pb may be disposed to correspond to the transflective area STA.

The counter electrode 230 may be a light-transmitting electrode or a reflective electrode. The counter electrode 230 is disposed over the first and second display areas DA1 and DA2 , and may be disposed on the intermediate layer 220 , the auxiliary intermediate layer 220 ′, and the pixel defining layer 125 . The counter electrode 230 is integrally formed in the plurality of main light emitting units 200 and the plurality of auxiliary light emitting units 200 ′ to include a plurality of pixel electrodes 210 and a plurality of auxiliary pixel electrodes 210 . ') can be dealt with.

Referring to FIG. 6B , the component 20 may be positioned under the second display area DA2 . The component 20 may be an electronic element using light or sound.

A plurality of second pixels PX2 and a plurality of transflective areas STA may be disposed in the second display area DA2 . The semi-transmissive area STA may include first to fourth holes H1 , H2 , H3 and H4 to correspond to the semi-transmissive area STA. The fact that the first to fourth holes H1 , H2 , H3 , and H4 are formed to correspond to the semi-transmissive area STA means that the interlayer insulating layer IL, the planarization layer 120 and the pixel are formed in the semi-transmissive area STA. As this means that the member such as the defining layer 125 is removed, the light transmittance in the semi-transmissive area STA may be significantly increased.

The display device 1 according to an embodiment of the present invention may include a first thin film transistor TFT1 and a second thin film transistor TFT2, and a first thin film transistor TFT1 and a second thin film transistor TFT2 At least one of them may include a semiconductor layer including an oxide semiconductor material. For example, the second semiconductor layer A2 of the second thin film transistor TFT2 may include an oxide semiconductor material.

In an embodiment, the auxiliary pixel electrode 210 ′ of the auxiliary light emitting unit 200 ′ may be disposed on the same layer as the second semiconductor layer A2 corresponding to the transflective area STA. Also, the second semiconductor layer A2 and the auxiliary pixel electrode 210 ′ may include the same material. For example, the second semiconductor layer A2 may be an ITZO (InSnZnO) semiconductor layer, an IGZO (InGaZnO) semiconductor layer, etc., and the auxiliary pixel electrode 210 ′ may include ITZO (InSnZnO), IGZO (InGaZnO), or the like. have.

In this case, since a basic patterning process is performed when the second semiconductor layer A2 is formed, a separate patterning process for forming the auxiliary pixel electrode 210 ′ of the auxiliary light emitting unit 200 ′ may not be required. That is, since a separate mask process is not required, cost and time may be saved when manufacturing the display device 1 .

In addition, by disposing the auxiliary light emitting part 200 ′ in the area through which light is transmitted, luminance may be increased compared to when only the second pixel PX2 is provided in the second display area DA2 .

So far, only the display device has been mainly described, but the present invention is not limited thereto. For example, it will be said that a display device manufacturing method for manufacturing such a display device also falls within the scope of the present invention.

7A to 7F are cross-sectional views illustrating a method of manufacturing a display device according to an exemplary embodiment in stages. In FIGS. 7A to 7F , the same reference numerals as those of FIG. 6B refer to the same members, and thus redundant descriptions thereof will be omitted.

Referring to FIG. 7A , first, the buffer layer 111 on the substrate 100, the first semiconductor layer A1 of the first thin film transistor TFT1, the first and second gate insulating layers 113 and 115, the first The first gate electrode G1 of the thin film transistor TFT1, the first electrode CE1 and the second electrode CE2 of the storage capacitor Cst, the lower gate electrode G2a of the second thin film transistor TFT2, and the interlayer The insulating layer IL is sequentially formed.

The substrate 100 may include a glass material, a ceramic material, a metal material, or a material having flexible or bendable properties. The substrate 100 may have a single-layer or multi-layer structure, and may further include an inorganic layer in the case of a multi-layer structure. In some embodiments, the substrate 100 may have an organic/inorganic/organic structure.

The buffer layer 111 may be made of silicon oxide (SiO ₂ ) or silicon nitride (SiN _X ), and may be formed by a deposition method such as Chemical Vapor Deposition (CVD) or sputtering.

The first semiconductor layer A1 of the first thin film transistor TFT1 may be disposed on the buffer layer 111 . The first semiconductor layer A1 may be formed by patterning a pre-semiconductor layer (not shown). The pre-semiconductor layer may be formed of an amorphous silicon semiconductor, and may be deposited by chemical vapor deposition. In addition, when the pre-semiconductor layer is an amorphous silicon layer, after forming it, a rapid thermal annealing (RTA) method, a solid phase crystallzation (SPC) method, an excimer laser annealing (ELA) method, a metal induced crystallzation (MIC) method, or MILC The polycrystalline silicon layer may be formed by crystallization by various methods such as a (metal induced lateral crystallzation) method and a sequential lateral solidification (SLS) method.

The first semiconductor layer A1 may include a first channel region C1 and a first source region S1 and a first drain region D1 disposed on both sides of the first channel region C1. . The first semiconductor layer A1 may be formed of a single layer or a multilayer.

A first gate insulating layer 113 and a second gate insulating layer 115 may be stacked on the substrate 100 to cover the first semiconductor layer A1 . The first and second gate insulating layers 113 and 115 are silicon oxide (SiO ₂ ), silicon nitride (SiN _X ), silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), titanium oxide (TiO ₂ ) , tantalum oxide (Ta ₂ O ₅ ), hafnium oxide (HfO ₂ ), or zinc oxide (ZnO ₂ ) may be provided, and may be formed by a deposition method such as chemical vapor deposition (CVD) or sputtering, It does not limit this.

The first gate electrode G1 may be disposed on the first gate insulating layer 113 to at least partially overlap the first semiconductor layer A1 . The first gate electrode G1 includes molybdenum (Mo), aluminum (Al), copper (Cu), titanium (Ti), and the like, and may be formed of a single layer or multiple layers. For example, the first gate electrode G1 may be a single layer of Mo.

The first electrode CE1 of the storage capacitor Cst may be formed of the same material as the first gate electrode G1 on the first gate insulating layer 113 . The second electrode CE2 of the storage capacitor Cst overlaps the first electrode CE1 with the second gate insulating layer 115 interposed therebetween to form a capacitance. In this case, the second gate insulating layer 115 may function as a dielectric layer of the storage capacitor Cst.

Also, a lower gate electrode G2a of the second thin film transistor may be disposed on the second gate insulating layer 115 .

7A , the first electrode CE1 of the storage capacitor Cst may overlap the first thin film transistor TFT1. For example, the first gate electrode G1 of the first thin film transistor TFT1 may function as the first electrode CE1 of the storage capacitor Cst.

In order to form the first gate electrode G1 and the first electrode CE1 of the storage capacitor Cst, a metal layer (not shown) may be formed on the entire surface of the substrate 100 and then patterned. The metal layer can be formed by chemical vapor deposition (CVD), plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), physical vapor deposition (PVD), sputtering, or atomic layer deposition. , ALD) may be formed by a deposition method, but is not limited thereto. In the method of forming the second electrode CE2 of the storage capacitor Cst and the lower gate electrode G2a of the second thin film transistor, the first gate electrode G1 and the first electrode CE1 of the storage capacitor Cst are formed. It may be the same as the method of forming.

A first interlayer insulating layer 117 is formed on the entire surface of the substrate 100 to cover the second electrode CE2 of the storage capacitor Cst and the lower gate electrode G2a of the second thin film transistor. The first interlayer insulating layer 117 is silicon oxide (SiO ₂ ), silicon nitride (SiN _X ), silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), titanium oxide (TiO ₂ ), tantalum oxide (Ta) ₂ O ₅ ), hafnium oxide (HfO ₂ ), or zinc oxide (ZnO ₂ ), etc. may be provided, and may be formed by a deposition method such as chemical vapor deposition (CVD) or sputtering, but is not limited thereto.

Referring to FIG. 7B , the second semiconductor layer A2 of the second thin film transistor TFT2 on the first interlayer insulating layer 117, the auxiliary pixel electrode 210' of the auxiliary light emitting unit 200', the pre- A gate insulating layer 118' and a pre-metal layer G' are sequentially formed.

The second semiconductor layer A2 and the auxiliary pixel electrode 210 ′ may be formed by patterning a pre-semiconductor layer (not shown). The pre-semiconductor layer may be formed of an oxide semiconductor, and may be deposited by chemical vapor deposition. The second semiconductor layer A2 and the auxiliary pixel electrode 210 ′ are indium (In), gallium (Ga), stanium (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), and cadmium (Cd). ), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce) and contains an oxide of at least one material selected from the group including zinc (Zn) can do. For example, the second semiconductor layer A2 may be an ITZO (InSnZnO) semiconductor layer, an IGZO (InGaZnO) semiconductor layer, etc., and the auxiliary pixel electrode 210 ′ may include ITZO (InSnZnO), IGZO (InGaZnO), or the like. have.

Pre-gate insulating layer 118' is silicon oxide (SiO ₂ ), silicon nitride (SiN _X ), silicon oxynitride (SiON), aluminum oxide (Al ₂ O ₃ ), titanium oxide (TiO ₂ ), tantalum oxide ( Ta ₂ O ₅ ), hafnium oxide (HfO ₂ ), or zinc oxide (ZnO ₂ ), etc. may be provided, and may be formed by a deposition method such as Chemical Vapor Deposition (CVD) or sputtering. may, but is not limited thereto.

The pre-metal layer (G') is aluminum (Al), platinum (Pt), palladium (Pd), silver (Ag), magnesium (Mg), gold (Au), nickel (Ni), neodymium (Nd), iridium ( One or more metals selected from among Ir), chromium (Cr), lithium (Li), calcium (Ca), molybdenum (Mo), titanium (Ti), tungsten (W), and copper (Cu) may be provided in a single layer or in multiple layers. chemical vapor deposition, plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), physical vapor deposition (PVD), sputtering, atomic layer deposition , ALD) may be formed by a deposition method, but is not limited thereto.

Referring to FIG. 7C , the upper gate electrode G2b of the second gate electrode G2 is formed by patterning the pre-metal layer G′.

The third gate insulating layer 118 is formed by patterning the pre-gate insulating layer 118' by using the upper gate electrode G2b of the second gate electrode G2 as a self-aligning mask. . That is, the third gate insulating layer 118 may be patterned to overlap a portion of the second semiconductor layer A2 .

A portion of the second semiconductor layer A2 exposed without overlapping with the upper gate electrode G2b of the second gate electrode G2 and the auxiliary light emitting part ( 200'), the sub-pixel electrode 210' is subjected to a conductive process by plasma treatment.

As a result, the second source region S2 , the second drain region D2 , and the auxiliary pixel electrode 210 ′ exposed during the plasma treatment become conductors, and the upper gate electrode G2b of the second gate electrode G2 and The overlapping second channel region C2 has different properties from the second source region S2 and the second drain region D2.

A second interlayer insulating layer 119 is formed on the second gate electrode G2 and the auxiliary pixel electrode 210 ′ of the auxiliary light emitting unit 200 ′. A method and a material for forming the second interlayer insulating layer 119 may be the same as those of the first interlayer insulating layer 117 .

After the second interlayer insulating layer 119 is formed, the first interlayer insulating layer IL, the first and second gate insulating layers 113 and 115, and exposing a part of the first semiconductor layer A1 A second contact hole CNT2 passing through the contact hole CNT1 and the second interlayer insulating layer 119 and exposing a portion of the auxiliary pixel electrode 210 ′ is formed.

Referring to FIG. 7D , the first electrode layer E1 , the first planarization layer 121 , the second electrode layer E2 , the second planarization layer 123 , and the main light emitting part 200 are formed on the interlayer insulating layer IL. A pixel electrode 210 and a pixel defining layer 125 are formed.

The first electrode layer (E1), the second electrode layer (E2), and the pixel electrode 210 of the main light emitting unit 200 are formed by depositing a pre-conductive layer (not shown) on the entire upper surface of each layer, and performing a mask process and an etching process. can be formed through

In one embodiment, the auxiliary pixel electrode 210 ′ of the auxiliary light emitting unit 200 ′ is connected to the first contact hole CNT1 and the second contact hole CNT2 through the first electrode layer E1 embedded in the first contact hole CNT2 . It may be connected to the semiconductor layer A1.

Also, the pixel electrode 210 of the main light emitting unit 200 is connected to the second electrode layer E2, the second electrode layer E2 is connected to the first electrode layer E1, and the pixel electrode 210 is connected to the first semiconductor layer. (A1) can be connected.

In one embodiment, the pixel electrode 210 of the main light-emitting unit 200 and the auxiliary pixel electrode 210' of the auxiliary light-emitting unit 200' are connected to the first semiconductor layer A1 of the first thin film transistor TFT1. may be connected and simultaneously driven by the first thin film transistor TFT1.

A pixel defining layer 125 having an opening OP that covers the edge of the pixel electrode 210 and exposes a central portion is formed on the entire top surface of the planarization layer 120 . The pixel defining layer 125 is made of one or more organic insulating materials selected from the group consisting of polyimide, polyamide, acrylic resin, benzocyclobutene, and phenol resin, and may be formed by spin coating or the like.

Referring to FIG. 7E , the first hole H1 of the second interlayer insulating layer 119 , the second hole H2 of the first planarization layer 121 , and the second planarization layer correspond to the semi-transmissive area STA. A third hole H3 of 123 and a fourth hole H4 of the pixel defining layer 125 are formed. The auxiliary pixel electrode 210 ′ of the auxiliary light emitting unit 200 ′ may be partially exposed through the first to fourth holes H1 , H2 , H3 and H4 .

Referring to FIG. 7F , the intermediate layer 220 is formed inside the opening OP of the pixel defining layer 125 and the auxiliary pixel electrode partially exposed by the first to fourth holes H1 , H2 , H3 and H4 . An auxiliary intermediate layer 220' is formed on the 210'.

The intermediate layer 220 and the auxiliary intermediate layer 220 ′ may include a low-molecular or high-molecular material. The intermediate layer 220 and the auxiliary intermediate layer 220 ′ may be formed by a vacuum deposition method, a screen printing method or an inkjet printing method, a laser induced thermal imaging (LITI) method, or the like.

Next, the counter electrode 230 is formed to correspond to the plurality of main light emitting units 200 and the plurality of auxiliary light emitting units 200 ′. The counter electrode 230 may be formed to cover the first display area DA1 (refer to FIG. 1 ) and the second display area DA2 (refer to FIG. 1 ) of the substrate 100 through the open mask. The counter electrode 230 may be formed by chemical vapor deposition, plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), physical vapor deposition (PVD), sputtering, or atomic layer deposition. It may be formed by a deposition method such as (atomic layer deposition, ALD).

The counter electrode 230 may be a light-transmitting electrode or a reflective electrode. In some embodiments, the counter electrode 230 may be a transparent or translucent electrode, and is formed of a metal thin film having a small work function including Li, Ca, LiF/Ca, LiF/Al, Al, Ag, Mg, and compounds thereof. can be formed. In addition, a transparent conductive oxide (TCO) layer such as ITO, IZO, ZnO, or In ₂ O _{3 may be further disposed on the metal thin film.}

According to an embodiment of the present invention, the auxiliary pixel electrode 210' of the auxiliary light emitting unit 200' disposed to correspond to the transflective area STA is some semiconductor disposed in the pixel circuit (PC, see FIG. 3). It may be formed by patterning together with the layers A1 and A2.

In this case, since a basic patterning process is performed when the semiconductor layers A1 and A2 are formed, a separate patterning process for forming the auxiliary pixel electrode 210' of the auxiliary light emitting unit 200' is not required, and a separate mask process is not required. Since this is not required, cost and time can be saved when manufacturing the display device 1 .

Although the present invention has been described with reference to the embodiment shown in the drawings, which is merely exemplary, those skilled in the art will understand that various modifications and equivalent other embodiments are possible therefrom. Therefore, the true technical protection scope of the present invention should be determined by the technical spirit of the appended claims.

100: substrate
110: barrier layer
111: buffer layer
120: planarization layer
200: main light emitting unit
210: pixel electrode
220: middle layer
230: counter electrode
200': auxiliary light emitting part
210': auxiliary pixel electrode
220': secondary middle layer
IL: interlayer insulating layer
PX1, PX2: 1st pixel, 2nd pixel
STA: semi-transmissive area
WL: wiring
E1, E2: first electrode layer, second electrode layer
H1, H2, H3, H4: Halls 1 to 4

Claims (20)

A display device comprising: a first display area including a first pixel; and a second display area including a transflective area and a second pixel;
a first semiconductor layer disposed on the substrate corresponding to the second pixel;
a gate insulating layer disposed on the first semiconductor layer;
a first gate electrode disposed on the gate insulating layer and partially overlapping the first semiconductor layer;
an auxiliary pixel electrode disposed on the same layer as the first semiconductor layer corresponding to the transflective region and including the same material as that of the first semiconductor layer;
an auxiliary intermediate layer disposed on the auxiliary pixel electrode; and
and a counter electrode disposed on the auxiliary intermediate layer. According to claim 1,
a first insulating layer disposed on the first gate electrode; and
It further comprises; an electrode layer disposed on the first insulating layer,
The electrode layer connects the first semiconductor layer and the auxiliary pixel electrode. 3. The method of claim 2,
a second insulating layer disposed on the electrode layer;
a pixel electrode disposed on the second insulating layer;
It further comprises; an intermediate layer disposed on the pixel electrode;
The counter electrode is disposed on the intermediate layer,
The pixel electrode is connected to the electrode layer and is driven simultaneously with the auxiliary pixel electrode. 4. The method of claim 3,
and the pixel electrode has a greater distance from the substrate than the auxiliary pixel electrode. 4. The method of claim 3,
and the intermediate layer and the auxiliary intermediate layer emit light of the same wavelength. According to claim 1,
and the first semiconductor layer includes an oxide semiconductor material. 7. The method of claim 6,
The first semiconductor layer includes IGZO (InGaZnO). According to claim 1,
an insulating layer disposed on the first gate electrode;
a pixel electrode disposed on the insulating layer and connected to the first semiconductor layer for driving; and
It further comprises; an intermediate layer disposed on the pixel electrode;
The counter electrode is disposed on the intermediate layer, and the intermediate layer and the auxiliary intermediate layer are integrally formed. According to claim 1,
a second semiconductor layer disposed on the substrate corresponding to the second pixel and including a silicon semiconductor material; and
and a second gate electrode disposed on the second semiconductor layer and partially overlapping the second semiconductor layer. According to claim 1,
and the gate insulating layer is patterned according to a shape of the first gate electrode. According to claim 1,
and an insulating layer disposed on the first gate electrode and having a hole corresponding to the transflective region to partially expose the auxiliary pixel electrode. According to claim 1,
and a component disposed under the substrate corresponding to the transflective region. According to claim 1,
and a lower gate electrode disposed under the first semiconductor layer and partially overlapping the first semiconductor layer. 14. The method of claim 13,
The first semiconductor layer includes a channel region, a source region, and a drain region,
and the lower gate electrode overlaps at least the channel region. A display device comprising: a first display area including a first pixel; and a second display area including a transflective area and a second pixel;
forming a semiconductor layer on a substrate corresponding to the second pixel;
forming a gate insulating layer to cover the semiconductor layer;
forming a gate electrode on the gate insulating layer at least partially overlapping the semiconductor layer;
forming an auxiliary pixel electrode including the same material as that of the semiconductor layer in the semi-transmissive region and on the same layer as the semiconductor layer;
forming an auxiliary intermediate layer on the auxiliary pixel electrode; and
and forming a counter electrode on the auxiliary intermediate layer. 16. The method of claim 15,
forming an insulating layer on the gate electrode; and
Forming an electrode layer including a first contact hole penetrating the insulating layer and exposing a part of the semiconductor layer and a second contact hole penetrating the insulating layer and exposing a part of the auxiliary pixel electrode; do,
and the electrode layer connects the semiconductor layer and the auxiliary pixel electrode. 16. The method of claim 15,
and the semiconductor layer and the auxiliary pixel electrode are patterned together. 16. The method of claim 15,
disposing an insulating layer on the gate electrode; and
and etching the insulating layer corresponding to the transflective region. 16. The method of claim 15,
wherein the semiconductor layer includes an oxide semiconductor material. 16. The method of claim 15,
disposing an insulating layer on the gate electrode;
disposing a pixel electrode connected to the semiconductor layer and driven on the insulating layer; and
disposing an intermediate layer on the pixel electrode; further comprising
The counter electrode is disposed on the intermediate layer,
and the intermediate layer and the auxiliary intermediate layer emit light of the same wavelength.

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