KR20210106392A - Adapative gain control neural signal detection circuit - Google Patents

Abstract

According to this embodiment of the present invention, a neural signal detection circuit includes: an amplifier unit for outputting a differential signal by adaptively adjusting a gain according to a size of a signal input by overlapping a neural signal and artifacts; a first ADC receiving an output signal of the amplifier unit and outputting a level code corresponding to a level of the output signal; a second ADC which compares and outputs the voltage difference formed by accumulating the difference of the differential signal; and an analog-to-digital converter including a logic circuit for outputting a digital code corresponding to the input signal by increasing or decreasing the level code according to an output of the second ADC. The amplifier unit adjusts the gain of the amplifier unit from the level code. Therefore, the present invention has a wide dynamic range, so that even when a signal with a large amplitude difference is input, the signal can be detected without being saturated.

Description

Adaptive Gain Control Brain Neural Signal Detection Circuit {ADAPATIVE GAIN CONTROL NEURAL SIGNAL DETECTION CIRCUIT}

The present technology relates to an adaptive gain control brain neural signal detection circuit.

A variety of neurological and psychiatric disorders have been demonstrated to be clinically detectable and treatable using neurological devices. Several previous studies have shown that symptoms of abnormal brain activity can be alleviated through electrical stimulation, and the effectiveness of these treatments is markedly improved when performed in a closed-loop manner. Accordingly, closed-loop neuro-modulation ICs are being actively studied. The low-power implantable bidirectional neural interface system can be applied to patients who need closed-loop control of brain function for a long time. However, the existing bidirectional neural interface system has a problem in that it is difficult to simultaneously perform high-fidelity recording of neural signals and electrical stimulation.

The voltage provided for stimulation may be several to hundreds of times greater than that of a brain nerve signal to be measured in general. A portion of the stimulation signal with this large amplitude appears at the input of the recording circuit and is referred to as a stimulation artifact (SA). Stimulation artifact SA causes significant distortion of recorded neural signals and even complete saturation of the circuitry, making it difficult to perform targeted closed-loop neuromodulation tasks as a result.

Artifacts are unwanted noise in a neural recording system, and when amplifying a brain neural signal with a large gain, the artifact is amplified. Accordingly, since saturation occurs due to the amplified artifacts, there is a problem in that a target brain nerve signal cannot be detected.

The present technology is one of the problems to be solved to solve the difficulties of the prior art. That is, one of the tasks to be solved by the present technology is to provide a technology capable of detecting a target brain neural signal by extending a dynamic range by adaptively adjusting a gain.

The neural signal detection circuit according to this embodiment includes: an amplifier unit that adaptively adjusts a gain according to the size of an input signal by overlapping a neural signal and an artifact and outputs a differential signal; and a first ADC that receives an output signal from the amplifier unit and outputs a level code corresponding to the level of the output signal, and a second ADC and a second ADC that compares and outputs a voltage difference formed by accumulating the difference of the differential signal and an analog-to-digital converter including a logic circuit unit for outputting a digital code corresponding to an input signal by increasing/decreasing a level code according to , and the amplifier unit adjusts a gain of the amplifier unit from the level code.

In the signal detection circuit according to the present embodiment, a first signal and a second signal having a larger amplitude than that of the first signal are superimposed, and the gain is adaptively adjusted according to the size of the input signal and output as a differential signal. an amplifier unit; and a first ADC (coarse ADC) that converts a level code corresponding to the output signal level of the amplifier unit, and a second ADC that compares and outputs a voltage difference formed by accumulating the difference of the differential signal and a reference according to the output of the second ADC and an analog-to-digital converter including a logic circuit unit for outputting a digital code corresponding to an input signal by increasing or decreasing the code, and the amplifier unit adjusts a gain of the amplifier unit from the reference code.

According to the present embodiment, it has a wide dynamic range, so even when a signal having a large amplitude difference is input, the signal can be detected without being saturated.

Fig. 1 is a block diagram showing the outline of a brain neural signal detection circuit according to the present embodiment.
2 is a circuit diagram showing in more detail the brain neural signal measuring circuit according to the present embodiment.
3 is a diagram showing an outline of the capacitor banks Cp and Cn.
4(a) to 4(c) are diagrams illustrating the shape of a signal output by the amplifier unit 200. Referring to FIG.
5 is a timing diagram for explaining the operations of the second ADC 120 and the logic circuit unit 130 .
6 is a photomicrograph of the die of the brain neural signal detection circuit according to the present embodiment.
7 is a diagram illustrating a change in signal to noise distortion ratio (SNDR) according to an input of a brain neural signal detection circuit according to the present embodiment.

Hereinafter, this embodiment will be described with reference to the accompanying drawings. However, in the accompanying drawings for describing the present embodiment, a line may mean a bus including a plurality of lines or a single line. In addition, each element of the present embodiment may operate in a single ended signaling scheme or in a differential signaling scheme.

Fig. 1 is a block diagram showing the outline of a brain neural signal detection circuit according to the present embodiment. Referring to FIG. 1 , the cranial nerve signal detection circuit according to the present embodiment adaptively adjusts a gain according to the size of an input cranial nerve signal and outputs an amplifier unit 200 and an amplifier to output a differential signal. A first ADC (coarse ADC, 110) that receives the output signal of the unit 200 and outputs a level code corresponding to the level of the output signal, and a second that compares and outputs a voltage difference formed by accumulating the difference between the differential signal 2 ADC (fine ADC, 120) and analog-to-digital converter 100 including a logic circuit unit 130 for outputting a digital code corresponding to the input cranial nerve signal by increasing or decreasing the level code according to the output of the second ADC (120) Including, the amplifier unit 200 adaptively adjusts the gain of the amplifier unit 200 from the reference code.

In an embodiment, the measured brain neural signal may be provided in the form of differential signals (Vinp, Vinn). The differential brain neural signal is amplified by a low noise amplifier (LNA) and output to the amplifier unit 200 .

2 is a circuit diagram showing in more detail the brain neural signal measuring circuit according to the present embodiment. Referring to FIG. 2 , the differential output signals LNAoutp and LNAoutn of the low noise amplifier (LNA, see FIG. 1 ) are provided to the amplifier unit 200 . The amplifier unit 200 is located in the differential amplifier 210 and a feedback path connecting the differential input and the differential output of the differential amplifier 210, respectively, and has a controllable equivalent capacitance of capacitor banks (Cp, Cn). includes

3 is a diagram showing an outline of the capacitor banks Cp and Cn. 2 and 3 , the capacitor banks Cp and Cn include switches whose conduction and/or disconnection are controlled by the gain control code GC provided by the gain control unit 220 . The switches included in the capacitor banks Cp and Cn are controlled by the gain control code GC to conduct and/or cut off, so the equivalent capacitances of the capacitor banks Cp and Cn are controlled by the gain control code GC. . In addition, since the capacitor banks Cp and Cn are located in the feedback path of the differential amplifier 210, the gain of the amplifier unit 200 can be controlled by controlling the equivalent capacitors of the capacitor banks Cp and Cn. have. In an embodiment, the equivalent capacitance of the capacitor banks Cp and Cn may vary from 10 fF to 30 pF by the gain control code GC.

The brain nerve signal output by the amplifier unit 200 is input to the first ADC 110 . _{The first ADC forms a level code (D LEV} ) corresponding to the level of the input brain neural signal and outputs it to the gain control unit 220 and the logic circuit unit 130 . The gain adjusting unit 220 receiving the level code D _LEV adjusts the gain of the amplifier unit 400 to correspond to the level of the brain neural signal. Also, the gain control unit 220 outputs the gain control code GC to the adaptive clock generator 129 .

In an embodiment, the first ADC 110 may be a successive-approximation ADC (SAR ADC) that performs analog-to-digital conversion by performing a binary search, and may reduce power consumption.

4(a) to 4(c) are diagrams illustrating the shape of a signal output by the amplifier unit 200. Referring to FIG. 4(a) is a diagram illustrating a case in which saturation occurs. Referring to FIG. 4A , a signal shown by a black solid line is a signal in which a brain nerve signal and artifacts such as a stimulation artifact or a motion artifact are superimposed. When this is amplified by a fixed-gain amplifier, the output signal of the amplifier shown in blue is saturated (saturation), so that the cranial nerve signal cannot be measured and recorded.

FIG. 4( b ) is a diagram illustrating a relationship between an output signal of the amplifier unit 200 according to the present embodiment when a brain neural signal overlaps an artifact and is provided as an input of the amplifier unit 200 . For reference, the input signal shown in blue and the output signal shown in red in FIG. 4(b) are shown in different proportions. _{Referring to FIG. 4B , the first ADC 110 forms a level code D LEV} corresponding to the level of the input signal overlapping the artifact and provides it to the gain adjuster 220 . When the input level code D _LEV is greater than the threshold value Vth,k, the gain control unit 220 forms the gain control code GC to correspond to the threshold value and outputs it to the capacitor banks Cp and Cn. .

Since the gain of the amplifier unit 200 is controlled by the capacitor banks Cp and Cn in which the equivalent capacitance corresponding to the gain control code GC is formed, the brain neural signal is saturated as shown by the red line in FIG. 4(b). It can be amplified and output without

FIG. 4( c ) is a diagram illustrating a relationship between an output signal of the amplifier unit 200 according to the present embodiment when a cranial nerve signal whose amplitude is gradually increased is provided as an input of the amplifier unit 200 . Similarly, as shown in FIG. 4(b), the input signal shown in blue and the output signal shown in red are shown in different proportions. Referring to FIG. 4( c ), when a cranial nerve signal (blue) of increasing amplitude is input, the first ADC 110 _{forms a level code (D LEV} ) corresponding to the level of the cranial nerve input signal to form a gain control unit ( 220) is provided. When the input level code D _LEV is greater than the threshold value Vth,k, the gain control unit 220 forms the gain control code GC to correspond to the threshold value and outputs it to the capacitor banks Cp and Cn.

Since the gain of the amplifier unit 200 is controlled by the capacitor banks Cp and Cn in which the equivalent capacitance corresponding to the gain control code GC is formed, the brain neural signal is saturated as shown by the red line in FIG. 4(c). It can be amplified and output without

In the illustrated embodiment, the gain control unit 220 may store codes corresponding to a plurality of thresholds, and the amplifier unit 220 by identifying the magnitude relationship with _{the level code D LEV provided by the first ADC 110 .} ) forms and outputs the gain control code (GC) to amplify the input signal with an appropriate gain.

Referring back to FIGS. 1 and 2 , the signal amplified and output by the amplifier unit 200 is provided to the second ADC 120 . The second ADC 120 includes a first integrator INT1 for accumulating the signal amplified and output by the amplifier unit 200, a second integrator INT2 for accumulating and outputting the output of the first integrator INT1, and the first The analog multiplier k 126 feed-forward the output of the integrator INT1 and the comparator 128 comparing the output of the second integrator INT2 with the output of the feed-forwarded first integrator INT1 ) may be included. That is, the comparator 128 differentially compares the sum of the feed-forwarded output of the first integrator and the output of the second integrator. Accordingly, the result of comparing the sum of the voltages at the non-inverting output node of the first integrator and the non-inverting output node of the second integrator and the sum of the voltages at the inverting output node of the first integrator and the inverting output node of the second integrator is output as a comparison result signal (D _{ΔΣ ).}

The signal amplified and output by the amplifier unit 200 is provided to the input of the integrator INT1 through the blocking capacitor Cs. The blocking capacitor removes the DC component from the signal amplified and output by the amplifier unit 200 and provides the AC signal component as an input of the first integrator INT1 . In an embodiment, the second ADC 120 may further include a second integrator INT2 , and the second integrator INT2 may be cascaded to the first integrator.

The cascaded first integrator INT1 and the second integrator INT2 can function as a low-pass filter having two poles, and feed-forward using an analog multiplier 126 (see FIG. 1). Stability can be obtained by inserting a zero point into the configuration.

The first integrator INT1 includes a first transconductance amplifier Gm1 that outputs a current corresponding to a voltage difference formed between a non-inverting input and an inverting input, and a first transconductance amplifier ( A capacitor may be included to form a voltage signal by accumulating the + current provided by the non-inverting output of Gm1) and the - current provided by the inverting output of the Gm1).

Accordingly, the first integrator INT1 is a first signal differentially formed by the amplifier unit 200 and provided as a non-inverting input of the first transconductance amplifier Gm1, and the inversion of the first transconductance amplifier Gm1 The difference between the second signal provided as an input is accumulated.

The second integrator INT2 receives the signal formed by the first integrator INT1 , accumulates it again, and outputs it to the comparator 128 . The comparator 128 applies the first signal output by the amplifier unit 200 in the form of a differential signal and provided to the non-inverting input of the first transconductance amplifier Gm1 to the first integrator INT1 and the second integrator INT2 . The magnitude of the signal formed by accumulating and the magnitude of the signal formed by accumulating the second signal provided to the inverting input of the first transconductance amplifier Gm1 by the second integrator INT1 and the second integrator INT2; The magnitudes of the accumulated results of the feed-forwarded first integrator are compared.

_{The comparator 128 outputs a comparison result code D ΔΣ in a} logic high state when the accumulated value of the first signal is greater than the accumulated value of the second signal, and on the contrary, the accumulated value of the second signal is the first signal is greater than the accumulated value, the comparison result code D _{ΔΣ in the} logic low state is output.

The comparison result code D _ΔΣ is provided to the logic circuit unit 130 . The logic circuit unit 130 receives the level code D _LEV output by the first ADC 110 and the comparison result code D _ΔΣ output by the second ADC 120 , and amplified by the amplifier unit 200 It includes a combination circuit (132, combiner) for forming a _{digital code (D OUT} ) corresponding to the output brain neural signal.

As an embodiment of the logic circuit unit 130 , the logic circuit unit 130 may further include a bit truncation unit 134 for discarding some bits of the digital code formed by the combination circuit 132 . For example, when the number of output bits of the combination circuit 132 is high and a data bottleneck occurs in data processing, the lower two bits of _{the digital code D OUT output by the combination circuit 132 may be discarded.}

In an embodiment, the logic circuit unit 130 may further include an amplitude difference control code generator (ADCC gen., amplitude difference control code generator, 136). The magnitude difference control code generator 136 is configured to apply a ground voltage V _GND and a boost voltage _{to one electrode of capacitors included in the capacitor banks C p} . C _n included in the differential signal magnitude difference control circuits 121p and 121n . A control code generating circuit (not shown) that forms a code for controlling switches connecting any one of (V _BST ) and capacitors included in the capacitor house to mitigate the capacitance difference caused by the PVT variation in the capacitor formation process It may further include a dynamic element matching circuit (not shown) that drives the logic circuit unit 130 to turn on/off evenly.

_{The digital code D OUT} corresponding to the brain neural signal amplified and output by the amplifier unit 200 is provided to the size difference control code generation unit 136 . The control code generated and output by the magnitude difference control code generator 136 is provided to the differential signal magnitude difference control circuits 121p and 121n, and a non-inverting input of the second ADC 120 and the first transconductance amplifier Gm1 and reduces the voltage difference formed between the inverting input.

In one embodiment, when the magnitude of the first signal provided to the non-inverting input among the differential signals output by the amplifier unit 200 is greater than the magnitude of the second signal provided to the inverting input, the second ADC 120 is Outputs the comparison result code (D _{ΔΣ) of the logic high state.}

The combination circuit 132 combines the comparison result code (D _ΔΣ ) and the level code (D _LEV ) to form _{a digital code (D OUT} ) corresponding to the brain neural signal amplified and output by the amplifier unit 200, and control The code forming unit forms a code for controlling the switch of the capacitor DAC (capacitor DAC, C _DACp . C _{DACn ) to correspond to the digital code (D OUT ).}

The codes formed by the control code generating circuit (not shown) are provided to the differential signal magnitude difference control circuits 121p and 121n that operate complementary to each other to control the difference in magnitude of signals formed at the input of the integrator. The differential signal magnitude difference adjusting circuits 121p and 121n are provided in switches that operate complementary to each other.

That is, the control code generating circuit is a boost voltage from the first is larger than the voltage at the inverting node of the transconductance amplifier (Gm1) a first transconductance amplifier (Gm2) voltage of the non-inverting node of the capacitor bank (C _p) ( A control code is formed and output to reduce the number of capacitors connected to _{V BST} , and a control code is formed and output to reduce the number of capacitors connected to the boost voltage V _{BST in the capacitor bank C n .} Accordingly, the difference in magnitude of the input signal formed at the input terminal of the second ADC may be kept constant.

5 is a timing diagram for explaining the operations of the second ADC 120 and the logic circuit unit 130 . Referring to Figure 5. The brain nerve signal amplified and output by the amplifier unit 200 is shown as a blue INPUT signal. In section ①, the first ADC (coarse ADC) samples the brain neural signal (INPUT), and outputs the _{sampled result as a level code (D LEV ).} In FIG. 5 , _{the solid line indicated by the level code D LEV} indicates a voltage corresponding to the digital code.

The combination circuit unit 130 receives the level code D _LEV and the comparison result code D _{ΔΣ , and increases the level code D LEV} by two when the comparison result code D _ΔΣ is in a logic high state. This is, for example, in section ①, since the DAC level is N or more and is quantized to N when it is less than N+1, when it is in a logic high state, the level code (D _LEV ) is increased by two steps to form a corresponding digital code. .

Conversely, when the comparison result code D _ΔΣ is in a logic low state, the level code D _LEV is decreased by one step to generate _{a code DOUT} corresponding to the brain neural signal amplified and output by the amplifier unit 200. .

There may be cases in which the brain nerve signal output and provided by the amplifier abruptly increases or decreases rapidly (see FIG. 2(b) ). That is, when an input signal having a large instantaneous change amount is provided, the gain of the amplifier unit 200 may be rapidly reduced, and thus the resolution of the second ADC 120 may be reduced. In this case, the clock of the comparator 180 is boosted in order to maintain the resolution of the second ADC 120 as illustrated in section ③.

As an example, the adaptive clock generator 128 receives the gain control code GC provided by the gain control unit 220 , and when the gain of the amplifier unit 200 rapidly decreases, the resolution of the second ADC 120 . It is provided by boosting the clock provided to the comparator to improve . For example, the boosting clock provided to the comparator may have a frequency of twice or more, preferably three times or more, compared to a clock frequency provided in a general section indicated by sections ① and ②.

The above has described the embodiment of the circuit for detecting and recording the cranial nerve signal overlapped with the artifact. However, it goes without saying that it can be implemented as a circuit for detecting and recording two signals having a large amplitude difference provided superimposed from the above disclosure.

Implementation and Experimental Examples

6 is a photomicrograph of the die of the brain neural signal detection circuit according to the present embodiment. Referring to FIG. 6 , the brain neural signal detection circuit according to the present embodiment is implemented in a 180 nm process. The total consumed area of the die was 0.72 mm ² .

The power consumption of the brain neural signal detection circuit according to the present embodiment was analyzed. When the first ADC operated at 320 kHz, the first ADC consumed 2.74 μW of power, and the first ADC and the second ADC consumed a total of 7.1 μW of power.

In case the input signal suddenly changes significantly, the frequency of the clock provided to the comparator is boosted and provided. In this embodiment, the clock provided to the comparator is provided three times higher than in the general case. In this case, the first ADC consumed 2.74 μW of power in the same way as above, and the first ADC and the second ADC consumed a total of 10.9 μW of power.

7 is a diagram illustrating a signal to noise distortion ratio (SNDR) of the brain neural signal detection circuit according to the present embodiment. Referring to FIG. 7 , it can be seen that the SNDR of the brain nerve signal detection circuit according to this embodiment reaches a maximum of 70.1 dB when the gain of the amplifier part is 16, and a wide dynamic range (DR) characteristic of 97 dB is obtained. You can check what you have.

Although it has been described with reference to the embodiment shown in the drawings in order to help the understanding of the present invention, this is an embodiment for implementation, it is merely an example, and various modifications and equivalents from those of ordinary skill in the art It will be appreciated that other embodiments are possible. Accordingly, the true technical protection scope of the present invention should be defined by the appended claims.

100: delta sigma ADC 110: first ADC
120: second ADC 122, 124: first and second integrators
121p, 121n: differential signal magnitude difference adjustment circuit
126: analog multiplier 128: comparator
129: adaptive clock generator 130: logic circuitry
132: combination circuit section 134: bit discard section
136: size difference control code generation unit 200: amplifier unit

Claims (16)

an amplifier unit (amplifier unit) for outputting a differential signal by adaptively adjusting a gain (gain) according to the size of the input signal by overlapping the neural signal and artifacts; and
a first ADC receiving the output signal of the amplifier unit and outputting a level code corresponding to the level of the output signal;
a second ADC that compares and outputs the voltage difference formed by accumulating the difference of the differential signal; and
and an analog-to-digital converter including a logic circuit unit for outputting a digital code corresponding to the input signal by increasing or decreasing the level code according to the output of the second ADC,
The amplifier unit is a neural signal detection circuit for adjusting the gain of the amplifier unit from the level code. According to claim 1,
The amplifier unit,
a differential amplifier receiving the differentially amplified input signal, amplifying the input and outputting the differential signal;
a capacitor bank having a controllable equivalent capacitance and positioned in a feedback path connecting the differential input and the differential output of the differential amplifier, respectively;
and a gain control unit configured to receive the level code and to form a gain control code for controlling the equivalent capacitance to correspond to the level code. According to claim 1,
The second ADC,
a first integrator for accumulating a difference between a first signal and a second signal constituting a differential signal;
a second integrator that is cascaded to the first integrator to accumulate an output of the first integrator;
an analog multiplier for feed-forwarding the cumulative result of the first integrator; and
A neural signal detection circuit for outputting a result of comparing the magnitudes of the accumulation result of the first integrator, the accumulation result of the second integrator, and the size of the feed-forward accumulation result of the first integrator. According to claim 1,
The second ADC is
being provided with a digital code corresponding to the signal,
and a differential signal magnitude difference control circuit for controlling the magnitude of the differential signal difference. 5. The method of claim 4,
The differential signal magnitude difference control circuit is
Comprising a first capacitor bank and a second capacitor bank operating complementary to each other,
The first capacitor bank and the second capacitor bank are
a plurality of capacitors,
a first node connected to the first electrode of the plurality of capacitors and provided with each signal constituting the differential signal;
and a switch respectively connected to the second electrode of the plurality of capacitors and connecting the second node to a ground voltage or a boost voltage in response to the digital code. According to claim 1,
The logic circuit unit,
A combination circuit (combiner) that receives the level code and the comparison result code, and outputs a digital code corresponding to the input cranial nerve signal by increasing the level code by two steps or decreasing the level code by one step according to the comparison result code Neural signal detection circuit comprising. 7. The method of claim 6,
The logic circuit unit,
The neural signal detection circuit further comprising a bit truncation unit for truncating the output of the combination circuit according to a desired resolution. 4. The method of claim 3,
The brain nerve signal recording device,
and an adaptive clock generator for increasing a frequency of a clock signal provided to the comparator when an amount of increase of the input signal per time from the level code is greater than a reference value. an amplifier unit for outputting a differential signal by adaptively adjusting a gain according to a magnitude of an input signal by superimposing the first signal and a second signal having an amplitude greater than that of the first signal; and
a first coarse ADC (ADC) for converting a level code corresponding to the level of the output signal of the amplifier unit;
a second ADC that compares and outputs the voltage difference formed by accumulating the difference of the differential signal; and
and an analog-to-digital converter including a logic circuit unit for outputting a digital code corresponding to the input signal by increasing or decreasing the reference code according to the output of the second ADC,
The amplifier unit is a signal detection circuit for adjusting a gain of the amplifier unit from the reference code. 10. The method of claim 9,
The amplifier unit,
a differential amplifier receiving the differentially amplified input signal, amplifying the input and outputting it as a differential signal;
a capacitor bank having a controllable equivalent capacitance and positioned in a feedback path connecting the differential input and the differential output of the differential amplifier, respectively;
and a gain adjusting unit receiving the first code and forming a gain adjusting code for controlling the equivalent capacitance to correspond to the first code. 10. The method of claim 9,
The second ADC,
a first integrator for accumulating a difference between a first signal and a second signal constituting the differential signal in an inversion relationship;
a second integrator that is cascaded to the first integrator to accumulate an output of the first integrator;
an analog multiplier for feed-forwarding the cumulative result of the first integrator; and
A signal detection circuit for outputting a result of comparing the magnitudes of the accumulation result of the first integrator, the accumulation result of the second integrator, and the size of the feed-forward accumulation result of the first integrator. 10. The method of claim 9,
The second ADC is
being provided with a digital code corresponding to the signal,
and a differential signal magnitude difference adjusting circuit for controlling the magnitude of the differential signal difference. 13. The method of claim 12,
The differential signal magnitude difference control circuit is
Comprising a first capacitor bank and a second capacitor bank operating complementary to each other,
The first capacitor bank and the second capacitor bank are
a plurality of capacitors,
a first node connected to the first electrode of the plurality of capacitors and provided with each signal constituting the differential signal;
and a switch respectively connected to the second electrode of the plurality of capacitors and connecting the second node to a ground voltage or a boost voltage according to the digital code. 10. The method of claim 9,
The logic circuit unit,
and a combination circuit (combiner) that receives the level code and the comparison result code and outputs a digital code corresponding to the input signal by increasing the level code by two steps or decreasing the level code by one step according to the comparison result code signal detection circuit. 15. The method of claim 14,
The logic circuit unit,
The signal detection circuit further comprising a bit truncation unit for truncating the output of the combination circuit according to a desired resolution. 12. The method of claim 11,
The signal detection circuit,
and an adaptive clock generator for increasing the frequency of the clock signal provided to the comparator when the amount of increase of the input signal per time from the level code is greater than a reference value.

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