KR20210098088A - Synchronous Rectification Flyback Converter - Google Patents

Abstract

The present invention relates to a synchronous rectification flyback converter and, more specifically, to a synchronous rectification flyback converter with reduced EMI noise and switching loss. To this end, the present invention comprises: an input unit; and an output unit insulated from the input unit. The input unit includes an input power source, a first coil, and a first transistor. The input power source, the first coil, and the first transistor constitute a circuit. The output unit includes an output capacitor, a second coil, second and third transistors, and a second snubber circuit. The output capacitor, the second coil, and the second transistor constitute the circuit and the third transistor and the second snubber circuit are connected in series with each other and connected in parallel with the second transistor. A synchronous rectification flyback converter is provided.

Description

Synchronous Rectification Flyback Converter

The present invention relates to a synchronous rectification flyback converter, and more particularly, to a synchronous rectification flyback converter with reduced EMI noise and switching loss.

The flyback converter has a structure in which the circuit of the input power and the circuit of the output power are separated, and it converts between alternating current (AC) and direct current (DC) or converts the voltage of direct current (DC). can

The flyback converter requires a small number of parts and has a simple structure, so it is easy to design. In addition, the input and output can be separated and have characteristics that can be insulated.

1A and 1B are circuit diagrams illustrating a conventional flyback converter.

The flyback converter 1 may include an input unit 10 and an output unit 20 as shown in FIGS. 1A and 1B . The input unit 10 may include an input power source 11 , a first coil 12 , and a switch 13 , and the output unit 20 includes a diode 21 , a second coil 22 , and an output capacitor 23 . ), and an output load 24 .

The first coil 12 and the second coil 22 may each consist of a core made of an electromagnet and a winding surrounding the core, and the first coil 12 and the second coil 22 may form a single transformer. . And the transformation ratio may correspond to the ratio of the number of turns of the first coil 12 and the second coil 22 .

When the switch 13 of the input unit 10 is turned on as shown in FIG. 1A , the current flowing through the first coil 12 and the magnetic flux are increased. At this time, the voltage applied to the second coil 22 of the output unit 20 reversely biases the diode 21 . Accordingly, no current flows through the diode 21 , and energy is supplied from the output capacitor 23 to the output load 24 .

When the switch 13 of the input unit 10 is turned off as shown in FIG. 1B , the current flowing through the first coil 12 and the magnetic flux are reduced. At this time, the voltage applied to the second coil 22 of the output unit 20 biases the diode 21 in the forward direction. Accordingly, a current flows through the diode 21 , and some of the energy supplied from the first coil 12 to the second coil 22 is stored in the output capacitor 23 , and the rest is supplied to the output load 24 . do.

The flyback converter 1, like other converters, can be driven in a current continuous mode (Continuous Conduction Mode; CCM) and a current discontinuous mode (Discontinuous Conduction Mode; DCM).

In the continuous current mode (CCM), a current greater than or equal to a predetermined current value may continuously flow through the second coil 22 .

In addition, in the current discontinuous mode (DCM), the current flowing through the second coil 22 may be controlled to be zero.

Meanwhile, in the flyback converter 1 , the diode 21 of the output unit 20 is replaced with a metal oxide semiconductor field effect transistor (MOSFET, hereinafter 'MOSFET'), which is a synchronous rectification flyback. It is called a Synchronous Rectification Flyback Converter.

Since the synchronous rectification flyback converter includes a MOSFET instead of the diode 21, it is difficult to control the current flowing in the second coil 22 to be zero, so instead of the current discontinuous mode (DCM), the forced current continuous mode (Forced Continuous Mode) It operates in Conduction Mode (FCCM).

When the synchronous rectification flyback converter is driven in the forced current continuous mode (FCCM), since the effective value (RMS) of the current is large, the stress of the elements constituting the synchronous rectification flyback converter is increased. Therefore, there is a disadvantage that a high-rated device must be used to solve this problem.

In addition, when controlling the switch 13 of the input unit 10 and the MOSFET of the output unit 20, if the gate signal applied to the switch 13 and the MOSFET overlaps, a current spike may occur, so EMI noise and switching The problem of increasing losses arises.

It is an object of the present invention to prevent an increase in EMI noise and switching loss by overlapping a gate signal applied to a transistor of an input unit and an output unit in a synchronous rectification flyback converter.

In order to achieve the above object, the present invention includes an input unit, an output unit insulated from the input unit, and the input unit includes an input power supply, a first coil, and a first transistor, the input power supply and the first The coil and the first transistor constitute a circuit, and the output unit includes an output capacitor, a second coil, second, third transistors, and a second snubber circuit, the output capacitor, the second coil, and the second transistor comprising a circuit and the third transistor and the second snubber circuit are connected in series with each other, and provide a synchronous rectification flyback converter connected in parallel with the second transistor.

And, the input unit further comprises a mutual inductor, the mutual inductor is connected in parallel with the first coil, the input power supply, the mutual inductor, the first transistor provides a synchronous rectification flyback converter forming a circuit.

And, the input unit further comprises a first snubber circuit, the input power source, the first snubber circuit, the first transistor provides a synchronous rectification flyback converter forming a circuit.

The first snubber circuit includes a first resistor, a first capacitor, and a first diode, the first resistor and the first capacitor are connected in parallel to each other, and a synchronous rectifying fly connected in series with the first diode. A back converter is provided.

And, the second snubber circuit provides a synchronous rectification flyback converter comprising a second resistor, a second capacitor, and a second diode.

And, the second resistor and the second capacitor are connected in parallel to each other, and provides a synchronous rectification flyback converter connected in series with the second diode.

And, the second resistor and the second capacitor are connected in series with each other, and provides a synchronous rectification flyback converter connected in parallel with the second diode.

And, the second resistor and the second capacitor provide a synchronous rectification flyback converter connected in parallel or in series with each other.

and a controller, wherein the controller transmits a signal for turning off the second transistor when the drain-source voltage of the second transistor is greater than a second threshold voltage, and turns on the third transistor when the drain-source voltage of the second transistor is clamped to the voltage of the second snubber circuit, the voltage of the second snubber circuit is greater than the second threshold voltage to provide a synchronous rectification flyback converter .

As described above, the present invention includes a third transistor and a second snubber circuit in the output unit in the synchronous rectification flyback converter, and turns the third transistor on or off to turn the second transistor of the output unit into a second snubber. It can be clamped by the voltage of the circuit.

Accordingly, the second transistor of the output unit can be turned off before the first transistor of the input unit is turned on, so that the magnitude of the current spike generated when the gate signals applied to the first and second transistors overlap can be reduced, and EMI Reduce noise and switching losses.

1A and 1B are circuit diagrams illustrating a conventional flyback converter.
2 is a circuit diagram illustrating a synchronous rectification flyback converter according to an embodiment of the present invention.
3A to 3D are circuit diagrams each showing a second snubber circuit according to an embodiment of the present invention.
4A and 4B are diagrams illustrating waveforms illustrating voltages and currents between drains and sources of first and second transistors in a comparative example and an embodiment of the present invention.
5A and 5B are enlarged views showing waveforms of gate signals applied to the first to third transistors in a comparative example and an embodiment of the present invention.

Hereinafter, the present invention will be described in detail with reference to the drawings.

The following examples are examples for describing the present invention in detail, and do not limit or limit the scope of the present invention.

Accordingly, from the detailed description and examples of the present invention, what can be easily inferred by an expert in the technical field to which the present invention belongs is construed as belonging to the scope of the present invention.

2 is a circuit diagram illustrating a synchronous rectification flyback converter according to an embodiment of the present invention. 3A to 3D are each a circuit diagram illustrating a second snubber circuit according to an embodiment of the present invention.

Synchronous rectification flyback converter 100 according to an embodiment of the present invention may include an input unit 110 , an output unit 120 , and a control unit 130 . In addition, in order not to complicate the drawing, the conducting wire connecting the input unit 110 and the output unit 120 and the control unit 130 is omitted.

The input unit 110 includes an input power source Vin, a first snubber capacitor Cs1, a first snubber resistor Rs1, a first snubber diode Ds1, a mutual inductor Lm, and a first coil W1. , a first transistor Q1 and first to fifth nodes N1 to N5 may be included.

The input power Vin may be connected between the first node N1 and the second node N2 . The input power Vin may be a DC power source, but is not limited thereto and may be an AC power source. And the second node N2 may be connected to the ground terminal.

The first snubber capacitor Cs1 and the first snubber resistor Rs1 may be connected between the first node N1 and the third node N3 .

The anode electrode of the first snubber diode Ds1 may be connected to the fourth node N4 , and the cathode electrode may be connected to the third node N3 .

The first snubber capacitor Cs1, the first snubber resistor Rs1, and the first snubber diode Ds1 may constitute the first snubber circuit S1.

The mutual inductor Lm and the first coil W1 may be connected between the fourth node N4 and the fifth node N5 .

The mutual inductor Lm may receive and store energy from the input power Vin when the first transistor Q1 is turned on, and store the energy stored when the first transistor Q1 is turned off to the first coil ( W1) can be forwarded.

The first coil W1 may be formed of a core made of an electromagnet and a winding that surrounds the core a plurality of times. In this case, in order to increase energy stored in the first coil W1 , a plurality of gaps may be formed in the core.

The first coil W1 may transfer energy to the second coil W2 of the output unit 120 when the first transistor Q1 is turned off.

The drain electrode of the first transistor Q1 may be connected to the fourth node N4 , the source electrode may be connected to the second node N2 , and the gate electrode may be connected to the first transistor control terminal 131 of the controller 130 . ) can be associated with

The first transistor Q1 may be a MOSFET including a body diode. However, the present invention is not limited thereto, and other types of transistors may be used.

When the first transistor Q1 is turned on, energy is accumulated from the input power source Vin to the mutual inductor Lm, and when the first transistor Q1 is turned off, the energy stored in the mutual inductor Lm is the first It is transmitted to the second coil W2 through the first coil W1. That is, the first transistor Q1 may control the accumulation and transfer of energy.

The air gap formed in the core of the first coil W1 causes the leakage inductance to increase, and for example, as shown in FIG. 2 , between the first node N1 and the fifth node N5, the first A leakage inductance Lk1 may occur.

The energy accumulated in the first leakage inductance Lk1 is not transferred to the output unit 120 through the first coil W1, but causes a surge voltage to be generated.

The surge voltage may be applied between the drain and the source of the first transistor Q1 , and when the surge voltage exceeds the withstand voltage of the first transistor Q1 , the first transistor Q1 may be damaged.

The first snubber circuit S1 constituted by the first snubber capacitor Cs1, the first snubber resistor Rs1, and the first snubber diode Ds1 is the energy stored in the first leakage inductance Lk1. is consumed by the first snubber resistor Rs1 to prevent damage to the first transistor Q1 by the surge voltage.

In Figure 2, the first snubber circuit (S1), the first snubber capacitor (Cs1) and the first snubber resistor (Rs1) are connected in parallel, the first snubber diode (Ds1) is connected in series thereto Although the structure is shown, it is not limited to this.

For example, the first snubber circuit S1 has a structure in which a first snubber resistor Rs1 and a first snubber diode Ds1 are connected in parallel, and a first snubber capacitor Cs1 is connected in series thereto. can be Also, the first snubber resistor Rs1 and the first snubber capacitor Cs1 may be connected in series. The first snubber circuit S1 having such a structure may be connected in series between the first node N1 and the fourth node N4, but is not limited thereto, and the first node N1 and the fifth node ( N5) may be connected in parallel.

The output unit 120 includes a second coil W2, an output capacitor Cout, an output load Rout, a second transistor Q2, a third transistor Q3, a second snubber circuit S2, and a sixth to 10 nodes N6 to N10 may be included.

The second coil W2 may be connected between the sixth node N6 and the seventh node N7 .

Like the first coil W1 , the second coil W2 may be formed of a core made of an electromagnet and a winding that surrounds the core a plurality of times. And in order to increase the energy stored in the second coil W2, a plurality of voids may be formed in the core.

Accordingly, a second leakage inductance Lk2 may be generated between the sixth node N6 and the eighth node N8 .

The second coil W2 may receive energy stored in the mutual inductor Lm through the first coil W1 when the first transistor Q1 is turned off. In addition, the received energy may be transferred to the output capacitor Cout or the output load Rout.

The output capacitor Cout and the output load Rout may be connected between the eighth node N8 and the ninth node N9 . Between the eighth node N8 and the ninth node N9 may be an output terminal. In addition, the ninth node N9 may be connected to a ground terminal, and in this case, the ground terminal may be a chassis ground terminal.

The output capacitor Cout may store the energy received from the second coil W2 , and may transfer the stored energy to the output load Rout when the first transistor Q1 is turned on. The output capacitor Cout may be a polarity capacitor, but is not limited thereto and may be another type of capacitor.

Although the output load Rout is shown only as a resistor, the output load Rout is not limited thereto, and may be another type of device capable of consuming energy by receiving energy from the output unit 120 . And

The drain electrode of the second transistor Q2 may be connected to the ninth node N9 , the source electrode may be connected to the seventh node N7 , and the gate electrode may be connected to the second transistor control terminal 132 of the controller 130 . ) can be associated with

The drain electrode of the third transistor Q3 may be connected to the tenth node N10 , the source electrode may be connected to the ninth node N9 , and the gate electrode may be connected to the third transistor control terminal 133 of the controller 130 . ) can be associated with

Each of the second transistor Q2 and the third transistor Q3 may be a MOSFET including a body diode. However, the present invention is not limited thereto, and may be different types of transistors.

The seventh node N7 and the ninth node N9 may be respectively connected to the source voltage input terminal 134 and the drain voltage input terminal 135 of the controller 130 .

The controller 130 senses the voltage between the drain and the source of the second transistor Q2 and sends a signal to turn on the second transistor Q2 when it is less than the first threshold voltage Vth1 to the second transistor Q2. and a signal for turning off the second transistor Q2 when it is greater than the second threshold voltage Vth2 is transmitted to the gate electrode of the second transistor Q2 to control the second transistor Q2 can do.

After the second transistor Q2 is turned off, the first transistor Q1 is turned on to charge energy to be transferred to the output unit 120 in the mutual inductor Lm.

In the current continuous mode, in order to turn off the second transistor Q2, the voltage between the drain and the source of the second transistor Q2 must be formed to be greater than the second threshold voltage Vth2. For this purpose, the first transistor Q1 ) must be turned on first.

In this case, a period in which the first transistor Q1 and the second transistor Q2 are turned on may overlap, and thus EMI noise and switching loss may increase.

In one embodiment of the present invention, by connecting the third transistor Q3 and the second snubber circuit S2 connected in series to the second transistor Q2 in parallel, the third transistor Q3 is turned on or According to the turn-off, the voltage between the drain and the source of the second transistor Q2 may be controlled.

By turning on the third transistor Q3 , the drain-source voltage of the second transistor Q2 may be greater than the second threshold voltage Vth2 .

In addition, the drain-source voltage of the second transistor Q2 is clamped to the voltage of the second snubber circuit S2, so that the drain-source voltage of the second transistor Q2 becomes higher than the withstand voltage. Since the second transistor Q2 can be blocked, damage to the second transistor Q2 can be prevented.

The second snubber circuit S2 may be connected between the seventh node N7 and the tenth node N10 .

The connection structure of the elements included in the second snubber circuit S2 may be any one illustrated in FIGS. 3A to 3D , but is not limited thereto.

The second snubber circuit S2 may include a second snubber resistor Rs2 , a second snubber capacitor Cs2 , and a second snubber diode Ds2 .

In each of the drawings shown in FIGS. 3A to 3D , the eleventh node N11 may be connected to the seventh node N7 , and the twelfth node N12 may be connected to the tenth node N10 .

As shown in FIG. 3A , in the second snubber circuit S2 , the second snubber resistor Rs2 and the second snubber capacitor Cs2 are between the eleventh node N11 and the thirteenth node N13, respectively. can be connected to form a parallel structure.

And the second snubber diode (Ds2) is connected between the twelfth node (N12) and the thirteenth node (N13) to form a series structure with the second snubber resistor (Rs2) and the second snubber capacitor (Cs2) can

Alternatively, as shown in FIG. 3B , in the second snubber circuit S2, a second snubber resistor Rs2 is connected between the eleventh node N11 and the thirteenth node N13, and the second snubber capacitor Cs2 may be connected between the twelfth node N12 and the thirteenth node N13 to form a series structure.

And a second snubber diode (Ds2) is connected between the eleventh node (N11) and the twelfth node (N12) to form a parallel structure with the second snubber resistor (Rs2) and the second snubber capacitor (Cs2) can

Alternatively, as shown in FIG. 3C , in the second snubber circuit S2 , the second snubber resistor Rs2 and the second snubber capacitor Cs2 have the eleventh node N11 and the twelfth node N12, respectively. They can be connected to form a parallel structure.

Alternatively, as shown in FIG. 3D , in the second snubber circuit S2, a second snubber resistor Rs2 is connected between the eleventh node N11 and the thirteenth node N13, and a second snubber capacitor Cs2 may be connected between the twelfth node N12 and the thirteenth node N13 to form a series structure.

Referring back to FIG. 2 , the controller 130 may include first to third transistor control terminals 131 to 133 , a source voltage input terminal 134 , and a drain voltage input terminal 135 .

In order to charge energy in the mutual inductor Lm of the input unit 110 , the controller 130 may transmit a gate signal for turning on the first transistor Q1 through the first transistor control terminal 131 .

In addition, the controller 130 transmits a gate signal for turning on the third transistor Q3 through the third transistor control terminal 133 to convert the drain-source voltage of the second transistor Q2 to the second snubber. It can be clamped by the voltage of the circuit S2.

At this time, when the voltage of the second snubber circuit S2 is set higher than the second threshold voltage Vth2 , the controller 130 turns off the second transistor Q2 through the second transistor control terminal 132 . A gate signal can be transmitted.

To this end, the controller 130 may set and store the first and second threshold voltages Vth1 and Vth2.

4A and 4B are diagrams illustrating waveforms showing voltages and currents between drains and sources of the first and second transistors Q1 and Q2 in a comparative example and an embodiment of the present invention.

The comparative example is an example in which the third transistor Q3 and the second snubber circuit S2 are removed from the output unit ( 120 in FIG. 2 ).

In the comparative example and an embodiment of the present invention, the voltage of the input power supply (Vin in FIG. 2) is 375 V, the switching frequency is 95 KHz, the voltage of the output load Rout is 12 V, and the first leakage inductance Lk1 is 15.8 μH, the second leakage inductance Lk2 is 0.4 μH, the inductance of the mutual inductor Lm is 70 μH, the capacitance of the output capacitor Cout is 200 μF, the first snubber capacitor Cs1 is 1 nF, the first The snubber resistor Rs1 has 100 KΩ.

And in the waveform showing the gate signal, a high value indicates a signal that turns on the transistor, and a low value indicates a signal that turns off the transistor.

In the first and second sections t1 and t2 of the comparative example illustrated in FIG. 4A , the second transistor Q2 is turned off and the first transistor Q1 is turned on. In this case, a period in which the first transistor Q1 and the second transistor Q2 are turned on may overlap.

Due to this, spikes occur in the current flowing between the drain-source of the first transistor Q1 and the current flowing between the drain-source of the second transistor Q2, respectively, which increases EMI noise and switching loss. do.

The third and fourth sections t3 and t4 of the exemplary embodiment illustrated in FIG. 4B are sections in which the second transistor Q2 is turned off and the first transistor Q1 is turned on.

In one embodiment of the present invention, the third transistor Q3 is turned on, so that the voltage between the drain and the source of the second transistor Q2 is higher than the second threshold voltage Vth2 in the second snubber circuit S2 By clamping to a voltage of , the second transistor Q2 may be turned off before the first transistor Q1 is turned on.

Accordingly, the magnitude of the spikes respectively occurring in the current flowing between the drain-source of the first transistor Q1 and the current flowing between the drain-source of the second transistor Q2 is reduced, thereby reducing EMI noise and switching loss. can

5A and 5B are enlarged views showing waveforms of gate signals applied to the first to third transistors Q1 to Q3 in a comparative example and an embodiment of the present invention.

In FIG. 5A , the first section t1 of the comparative example shown in FIG. 4A is enlarged.

In the comparative example, it can be seen that the first transistor Q1 is turned on before the second transistor Q2 is turned off, and thus the current flowing between the drain and the source of the first transistor Q1 and the second transistor Q1 are turned on. Each spike may occur in the current flowing between the drain and source of (Q2).

In FIG. 5B , the third section t3 of the embodiment of the present invention shown in FIG. 4B is enlarged.

In one embodiment of the present invention, it can be seen that the third transistor Q3 is turned on before the second transistor Q2 is turned off. And after the turn-off of the second transistor Q2 is completed, it can be seen that the first transistor Q1 is turned on.

Accordingly, the gate signals applied to the first transistor Q1 and the second transistor Q2 do not overlap, and the current flowing between the drain and source of the first transistor Q1 and the drain-source of the second transistor Q2 do not overlap. The spikes that each occurred in the current flowing between them can be reduced, and EMI noise and switching loss can be reduced.

As described above, the present invention has been described with reference to the above embodiments, but various modifications can be made without departing from the spirit of the present invention.

100: synchronous rectification flyback converter 110: input unit
120: output unit 130: control unit
Vin: input power Rs1, Rs2: first and second snubber resistors
Cs1, Cs2: first and second snubber capacitors
Ds1, Ds2: 1st, 2nd snubber diode
Lm: mutual inductors W1, W2: 1st, 2nd coil
Q1 to Q3: first to third transistors S1, S2: first and second snubber circuits
Cout : output capacitor Rout : output load
131 to 133: first to third transistor control terminals
134: source voltage input terminal 135: drain voltage input terminal

Claims (9)

an input unit and an output unit insulated from the input unit;
The input unit includes an input power supply, a first coil, and a first transistor,
The input power source, the first coil, and the first transistor constitute a circuit,
The output unit includes an output capacitor, a second coil, second and third transistors, and a second snubber circuit,
The output capacitor, the second coil, and the second transistor constitute a circuit,
The third transistor and the second snubber circuit are connected in series with each other, and a synchronous rectification flyback converter connected in parallel with the second transistor.
The method of claim 1,
The input unit further comprises a mutual inductor,
the mutual inductor is connected in parallel with the first coil,
A synchronous rectification flyback converter in which the input power supply, the mutual inductor, and the first transistor form a circuit.
3. The method of claim 2,
The input unit further comprises a first snubber circuit,
The input power source, the first snubber circuit, and the first transistor form a circuit synchronous rectification flyback converter.
4. The method of claim 3,
The first snubber circuit includes a first resistor, a first capacitor, and a first diode;
The first resistor and the first capacitor are connected in parallel with each other, and the synchronous rectification flyback converter is connected in series with the first diode.
5. The method according to any one of claims 1 to 4,
The second snubber circuit is a synchronous rectification flyback converter comprising a second resistor, a second capacitor, and a second diode.
6. The method of claim 5,
The second resistor and the second capacitor are connected in parallel with each other, and the synchronous rectification flyback converter is connected in series with the second diode.
6. The method of claim 5,
The second resistor and the second capacitor are connected in series with each other, and the synchronous rectification flyback converter is connected in parallel with the second diode.
6. The method of claim 5,
The second resistor and the second capacitor are connected in parallel or series to each other in a synchronous rectification flyback converter.
The method of claim 1,
further comprising a control unit,
When the drain-source voltage of the second transistor is greater than a second threshold voltage, the controller transmits a signal to turn off the second transistor,
When the third transistor is turned on, the drain-source voltage of the second transistor is clamped to the voltage of the second snubber circuit, and the voltage of the second snubber circuit is greater than the second threshold voltage. Rectification flyback converter.

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