KR20210092751A - 내적 계산기 및 그 연산 방법 - Google Patents

내적 계산기 및 그 연산 방법 Download PDF

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KR20210092751A
KR20210092751A KR1020217015961A KR20217015961A KR20210092751A KR 20210092751 A KR20210092751 A KR 20210092751A KR 1020217015961 A KR1020217015961 A KR 1020217015961A KR 20217015961 A KR20217015961 A KR 20217015961A KR 20210092751 A KR20210092751 A KR 20210092751A
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페르갈 코노르
데이비드 베르나르드
니알 한라한
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모비디어스 리미티드
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/544—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices for evaluating functions by calculation
    • G06F7/5443—Sum of products
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F17/00—Digital computing or data processing equipment or methods, specially adapted for specific functions
    • G06F17/10—Complex mathematical operations
    • G06F17/16—Matrix or vector computation, e.g. matrix-matrix or matrix-vector multiplication, matrix factorization
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/38—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation
    • G06F7/48—Methods or arrangements for performing computations using exclusively denominational number representation, e.g. using binary, ternary, decimal representation using non-contact-making devices, e.g. tube, solid state device; using unspecified devices
    • G06F7/52—Multiplying; Dividing
    • G06F7/523—Multiplying only
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/3001—Arithmetic instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30018—Bit or string instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30007—Arrangements for executing specific machine instructions to perform operations on data operands
    • G06F9/30036—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
    • G06F9/30038—Instructions to perform operations on packed data, e.g. vector, tile or matrix operations using a mask
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/0464—Convolutional networks [CNN, ConvNet]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/0495—Quantised networks; Sparse networks; Compressed networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/06—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons
    • G06N3/063—Physical realisation, i.e. hardware implementation of neural networks, neurons or parts of neurons using electronic means
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/38—Indexing scheme relating to groups G06F7/38 - G06F7/575
    • G06F2207/48—Indexing scheme relating to groups G06F7/48 - G06F7/575
    • G06F2207/4802—Special implementations
    • G06F2207/4818—Threshold devices
    • G06F2207/4824—Neural networks
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06N—COMPUTING ARRANGEMENTS BASED ON SPECIFIC COMPUTATIONAL MODELS
    • G06N3/00—Computing arrangements based on biological models
    • G06N3/02—Neural networks
    • G06N3/04—Architecture, e.g. interconnection topology
    • G06N3/045—Combinations of networks

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Analysis (AREA)
  • Mathematical Optimization (AREA)
  • Pure & Applied Mathematics (AREA)
  • Computational Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Computing Systems (AREA)
  • Data Mining & Analysis (AREA)
  • Biophysics (AREA)
  • Biomedical Technology (AREA)
  • Life Sciences & Earth Sciences (AREA)
  • Health & Medical Sciences (AREA)
  • Molecular Biology (AREA)
  • General Health & Medical Sciences (AREA)
  • Evolutionary Computation (AREA)
  • Computational Linguistics (AREA)
  • Artificial Intelligence (AREA)
  • Algebra (AREA)
  • Databases & Information Systems (AREA)
  • Neurology (AREA)
  • Complex Calculations (AREA)
KR1020217015961A 2018-11-08 2019-11-04 내적 계산기 및 그 연산 방법 Withdrawn KR20210092751A (ko)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US16/184,985 2018-11-08
US16/184,985 US10768895B2 (en) 2018-11-08 2018-11-08 Dot product calculators and methods of operating the same
PCT/EP2019/080136 WO2020094586A1 (en) 2018-11-08 2019-11-04 Dot product calculators and methods of operating the same

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KR20210092751A true KR20210092751A (ko) 2021-07-26

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US (3) US10768895B2 (https=)
EP (1) EP3877839A1 (https=)
JP (1) JP2022506345A (https=)
KR (1) KR20210092751A (https=)
CN (1) CN113330421B (https=)
DE (1) DE112019005586T5 (https=)
WO (1) WO2020094586A1 (https=)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11169809B2 (en) * 2017-03-31 2021-11-09 Intel Corporation Method and apparatus for converting scatter control elements to gather control elements used to sort vector data elements
US10409614B2 (en) 2017-04-24 2019-09-10 Intel Corporation Instructions having support for floating point and integer data types in the same register
US10474458B2 (en) 2017-04-28 2019-11-12 Intel Corporation Instructions and logic to perform floating-point and integer operations for machine learning
CN110770722B (zh) * 2017-06-29 2023-08-18 北京清影机器视觉技术有限公司 二维数据匹配方法、装置和逻辑电路
US10768895B2 (en) 2018-11-08 2020-09-08 Movidius Limited Dot product calculators and methods of operating the same
US12182035B2 (en) 2019-03-15 2024-12-31 Intel Corporation Systems and methods for cache optimization
US11934342B2 (en) 2019-03-15 2024-03-19 Intel Corporation Assistance for hardware prefetch in cache access
WO2020190807A1 (en) * 2019-03-15 2020-09-24 Intel Corporation Systolic disaggregation within a matrix accelerator architecture
PL3938914T3 (pl) 2019-03-15 2025-03-31 Intel Corporation Dynamiczna rekonfiguracja pamięci
US12131251B2 (en) * 2019-03-19 2024-10-29 Cirrus Logic Inc. Neurons for artificial neural networks
WO2020218157A1 (ja) * 2019-04-25 2020-10-29 国立大学法人静岡大学 予測システム、予測方法、および予測プログラム
US11741349B2 (en) * 2019-10-31 2023-08-29 Arm Limited Performing matrix-vector multiply operations for neural networks on electronic devices
US11861761B2 (en) 2019-11-15 2024-01-02 Intel Corporation Graphics processing unit processing and caching improvements
US11663746B2 (en) 2019-11-15 2023-05-30 Intel Corporation Systolic arithmetic on sparse data
US11500680B2 (en) * 2020-04-24 2022-11-15 Alibaba Group Holding Limited Systolic array-friendly data placement and control based on masked write
US20220405571A1 (en) * 2021-06-16 2022-12-22 Microsoft Technology Licensing, Llc Sparsifying narrow data formats for neural networks
US12321857B2 (en) 2021-06-24 2025-06-03 Intel Corporation Methods and apparatus to perform machine-learning model operations on sparse accelerators
US20230035474A1 (en) * 2021-07-20 2023-02-02 Gsi Technology Inc. Compiler for a parallel processor
US20230083270A1 (en) * 2021-09-14 2023-03-16 International Business Machines Corporation Mixed signal circuitry for bitwise multiplication with different accuracies
US11789646B2 (en) 2021-09-24 2023-10-17 Intel Corporation Methods, apparatus, and articles of manufacture to increase data reuse for multiply and accumulate (MAC) operations
US11669489B2 (en) * 2021-09-30 2023-06-06 International Business Machines Corporation Sparse systolic array design

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0731669B2 (ja) * 1986-04-04 1995-04-10 株式会社日立製作所 ベクトル・プロセツサ
US20080071851A1 (en) * 2006-09-20 2008-03-20 Ronen Zohar Instruction and logic for performing a dot-product operation
GB2457303A (en) * 2008-02-11 2009-08-12 Linear Algebra Technologies Randomly accessing elements of compressed matrix data by calculating offsets from non-zero values of a bitmap
US20160358069A1 (en) * 2015-06-03 2016-12-08 Samsung Electronics Co., Ltd. Neural network suppression
US10223359B2 (en) * 2016-10-10 2019-03-05 The Directv Group, Inc. Determining recommended media programming from sparse consumption data
US10360163B2 (en) * 2016-10-27 2019-07-23 Google Llc Exploiting input data sparsity in neural network compute units
US10146738B2 (en) * 2016-12-31 2018-12-04 Intel Corporation Hardware accelerator architecture for processing very-sparse and hyper-sparse matrix data
US20180189675A1 (en) * 2016-12-31 2018-07-05 Intel Corporation Hardware accelerator architecture and template for web-scale k-means clustering
US10096134B2 (en) * 2017-02-01 2018-10-09 Nvidia Corporation Data compaction and memory bandwidth reduction for sparse neural networks
US10171084B2 (en) * 2017-04-24 2019-01-01 The Regents Of The University Of Michigan Sparse coding with Memristor networks
US20180330235A1 (en) * 2017-05-15 2018-11-15 National Taiwan University Apparatus and Method of Using Dual Indexing in Input Neurons and Corresponding Weights of Sparse Neural Network
TWI684141B (zh) 2017-10-12 2020-02-01 英屬開曼群島商意騰科技股份有限公司 人工神經元中以非零封包加速乘法運算的裝置及方法
KR102697300B1 (ko) * 2018-03-07 2024-08-23 삼성전자주식회사 전자 장치 및 머신 러닝 수행 방법
US10768895B2 (en) 2018-11-08 2020-09-08 Movidius Limited Dot product calculators and methods of operating the same

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Publication number Publication date
JP2022506345A (ja) 2022-01-17
US20200387350A1 (en) 2020-12-10
US11023206B2 (en) 2021-06-01
US20210247961A1 (en) 2021-08-12
US11656845B2 (en) 2023-05-23
CN113330421A (zh) 2021-08-31
EP3877839A1 (en) 2021-09-15
US10768895B2 (en) 2020-09-08
CN113330421B (zh) 2024-01-16
WO2020094586A1 (en) 2020-05-14
US20200150926A1 (en) 2020-05-14
DE112019005586T5 (de) 2021-12-16

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