KR20210090676A - Signal processing method, apparatus, equipment and computer storage medium - Google Patents

Abstract

The present application discloses a signal processing method, apparatus, equipment and computer storage medium, the method comprising: acquiring clock recovery input data; perform frequency domain clock recovery on the clock recovery input data to obtain clock recovery output data; and performing frequency domain blind equalization processing according to the clock recovery output data to obtain frequency domain equalization data.

Description

Signal processing method, apparatus, equipment and computer storage medium

Embodiments of the present application relate to a signal processing technology of a coherent optical communication system, for example, a signal processing method, apparatus, equipment, and a computer storage medium.

For reference, this application claims priority to the Chinese Patent Application No. 201811549215.3, filed with the Chinese Intellectual Property Office on December 18, 2018, the entire contents of which are incorporated herein by reference.

In coherent optical communication systems, clock recovery and blind equalization are both essential links in signal processing. In the related art, blind equalization is generally implemented in the time domain, and when blind equalization is implemented in the time domain, the amount of computation is relatively large, and power consumption according to computing increases. For example, the blind equalization processing process in the time domain includes two processes: equalizer filtering and equalizer coefficient update.

When these two processes are implemented in the time domain, a large number of complex multiplications are required, resulting in an increase in computing power consumption, which brings certain limitations to the application of the blind equalization technique. Also, in a coherent optical communication system, clock recovery and blind equalization are two links closely connected to each other, and if they are designed independently, repetitive operation may occur. For this reason, when considering the practical application, the overall architecture for these two links should be jointly designed in order to reduce the repetitive operation and reduce the chip power consumption.

An embodiment of the present application provides a signal processing method, the method comprising:

acquire clock recovery input data;

perform frequency domain clock recovery on the clock recovery input data to obtain clock recovery output data;

and performing frequency domain blind equalization processing according to the clock recovery output data to obtain frequency domain equalization data.

An embodiment of the present application also provides a signal processing apparatus, the apparatus comprising:

an acquiring unit, configured to acquire clock recovery input data;

a first processing unit, configured to perform frequency domain clock recovery on the clock recovery input data to obtain clock recovery output data;

and a second processing unit, configured to perform, according to the clock recovery output data, frequency domain blind equalization processing, to obtain frequency domain equalization data.

An embodiment of the present application also provides a signal processing facility, which includes a processor and a memory configured to store a computer program executing in the processor; The processor is configured to execute the arbitrary signal processing method when executing the computer program.

Embodiments of the present application also provide a computer storage medium, which stores a computer program and executes any of the signal processing methods when the computer program is executed by a processor.

Embodiments of the present application provide a signal processing method, apparatus, equipment and computer storage medium for performing an overall architectural design for clock recovery and blind equalization, which can implement clock recovery and blind equalization processing in the frequency domain. Compared with each method of implementing clock recovery and blind equalization processing in the time domain, the amount of computation and computing power consumption are reduced.

1 is a flowchart of a blind equalization algorithm in the related art.
2 is a flowchart of a signal processing method provided by an embodiment of the present application.
3 is a flowchart of a signal processing method provided by an embodiment of the present application.
4 is a flowchart of frequency domain clock recovery provided by an embodiment of the present application.
5 is a flowchart of a Constant Modulus Algorithm (CMA) filtering provided by an embodiment of the present application.
6 is a flowchart of a coefficient update provided by an embodiment of the present application.
7 is a flowchart of another frequency domain clock recovery provided by an embodiment of the present application.
8 is a flowchart of another CMA filtering provided by an embodiment of the present application.
9 is a flowchart of another frequency domain clock recovery provided by an embodiment of the present application.
10 is a flowchart of another CMA filtering provided by an embodiment of the present application.
11 is a schematic diagram of a configuration structure of a signal processing apparatus provided by an embodiment of the application.
12 is a schematic diagram of a hardware structure of a signal processing facility provided by an embodiment of the application;

The present application is described below in conjunction with the drawings and examples. The examples described herein are used only to illustrate the present application and not to limit the present application.

In a coherent optical communication system, two polarization modes orthogonal to each other have different transmission speeds due to optical fiber ellipticity and pressure during optical fiber transmission, which exhibits a birefringence effect and induces Polarization Mode Dispersion (PMD). , it causes an increase in the bit error rate of the receiving end and deterioration of the communication system performance.

In order to compensate for the polarization mode dispersion and match the characteristics of the time-varying or unknown channel, an adaptive equalization method is usually used to timely update the equalizer coefficients to improve the signal tracking function and improve the compensation effect. The blind equalization algorithm, which is one of the adaptive equalization methods, is widely used due to its advantages of not requiring additional training sequences and improving channel utilization. 1 is a flowchart of a blind equalization algorithm in the related art. 1 , it shows that blind equalization filtering can be implemented based on an adaptive algorithm in the related art.

A common blind equalization algorithm is CMA, and after CMA was proposed, many scholars improved or applied this algorithm. In the related art, CMA mainly includes two processes: equalizer filtering and equalizer coefficient update. Both of these processes are performed in the time domain and require a lot of complex multiplication. In practical applications, when CMA is implemented through a chip, there are certain limitations because it increases the computing power consumption of the chip.

Also in coherent optical communication systems, clock recovery is an essential link. A mismatch between the transmitter clock and the local clock can result in a constant phase error. The presence of phase error cannot guarantee that each individual signal is sampled at the optimal sampling position, and if the phase error is too large, it will affect the filtering effect of blind equalization and degrade system performance. Clock recovery and blind equalization are two closely coupled modules. When performing blind equalization processing, it is necessary to acquire input data based on a clock recovery process, and perform frequency domain filtering and frequency domain coefficient update through Fast Fourier Transformation (FFT). When performing clock recovery, blind equalized frequency domain filtered data should be used for error extraction. If two modules for clock recovery and blind equalization are designed independently, there may be an iterative processing process for both modules. Therefore, considering the practical application, the overall architecture for the two modules should be jointly designed in order to reduce the power consumption of the computing chip by reducing the iterative processing process that exists when the two modules are designed independently.

Based on the above content, the following embodiments are proposed.

first embodiment

The first embodiment of the present application proposes a signal processing method applicable to a coherent optical communication system.

2 is a flowchart of a signal processing method provided by an embodiment of the present application, and as shown in FIG. 2 , it may include the following.

Step 2010: Acquire clock recovery input data.

Step 2020: Perform frequency domain clock recovery on the clock recovery input data to obtain clock recovery output data.

In this embodiment, the purpose of performing frequency domain clock recovery is to restore data to the best sampling position. In practical applications, in classical coherent optical communication systems, the clock recovery input data usually comes from dispersion compensation.

In the case of the implementation manner of this step, exemplarily, acquiring data of a phase determination target; extracting a phase error value by performing phase determination on the data of the phase determination target; Interpolation processing may be performed on the clock recovery input data using the phase error value to obtain the clock recovery output data.

In the case of an implementation method of acquiring data to be determined for phase, in one example, FFT transformation is performed on the clock recovery input data to obtain clock recovery input data in the frequency domain, and the clock recovery input data in the frequency domain is converted to a frequency By multiplying it with a frequency domain coefficient used in the domain blind equalization process, it is possible to obtain the data of the phase discrimination target.

In the case of an implementation method of acquiring the data of the phase discrimination target, in another example, the frequency domain equalization data obtained immediately before may be used as the data of the phase discrimination target.

As one implementation method, after obtaining the data of the phase discrimination target, the phase error value may be extracted by performing the phase discrimination on the data of the phase discrimination target using the Godard phase discriminator.

In the case of an implementation method of interpolation processing, it may be implemented in a time domain or a frequency domain.

The interpolation process implemented in the time domain is as follows: Finite Impulse Response (FIR) filtering (which can be implemented using a FIR filter) is performed on the clock recovery input data according to the phase error value, so that the clock recovery output data is acquire

The interpolation processing process implemented in the frequency domain is as follows: performing FFT transformation on the clock recovery input data to obtain clock recovery input data in the frequency domain; In the frequency domain, phase adjustment is performed on the clock recovery input data in the frequency domain to obtain clock recovery output data.

Step 2030: According to the clock recovery output data, a frequency domain blind equalization process is performed to obtain frequency domain equalization data.

For the implementation manner of this step, in one example, obtain frequency domain blind equalization input data according to the clock recovery output data; obtain frequency domain coefficients; Frequency domain equalization data may be obtained by multiplying the frequency domain blind equalization input data by a frequency domain coefficient.

In the embodiment of the present application, when the clock recovery output data is data obtained in the time domain, FFT transformation may be performed on the clock recovery output data to obtain the frequency domain blind equalized input data.

When the clock recovery output data is data acquired in the frequency domain, the frequency domain blind equalization input data may be acquired according to the clock recovery output data of the frequency domain.

In practical applications, the blind equalization algorithm used for the frequency domain blind equalization is not limited. For example, frequency domain blind equalization processing may be performed using CMA, and if frequency domain blind equalization processing is performed using CMA, frequency domain blind equalization input data is recorded as frequency domain CMA input data.

In one embodiment, the frequency domain coefficients represent coefficients required for the frequency domain blind equalization process. In the case of the implementation method of obtaining the frequency domain coefficients, exemplarily, the time domain coefficients may be obtained, and an FFT transform may be performed on the time domain coefficients to obtain the frequency domain coefficients. The time-domain coefficient may be obtained according to an initial value of the time-domain coefficient and an update flow of the time-domain coefficient, and the initial value of the time-domain coefficient may be a set value.

In one embodiment, after obtaining the frequency-domain equalized data, the time-domain equalized data may be obtained by performing Inverse Fast Fourier Transformation (IFFT) on the frequency-domain equalized data.

In an embodiment of the present application, time domain coefficients may also be updated, and when updating time domain coefficients, time domain equalization data must be obtained. In practical applications, in classical coherent optical communication systems, time domain equalization data can be used as a basis for carrier synchronization in addition to being used to update coefficients.

In one implementation manner, the process of updating the time-domain coefficients may include: according to the frequency-domain blind equalized input data and the time-domain equalized data, updating the time-domain coefficients to obtain updated time-domain coefficients. .

In one embodiment, an error calculation is performed on the time-domain equalized data to obtain time-domain error data; performing FFT transformation on the time domain error data to obtain frequency domain error data; performing conjugate multiplication of the frequency domain error data with the frequency domain blind equalization input data to obtain cross-spectral data; An updated time-domain coefficient may be obtained by updating the time-domain coefficient according to the cross-spectral data.

For the implementation manner of updating the time-domain coefficients according to the cross-spectral data, for example, performing IFFT transformation on the cross-spectral data to obtain a coefficient adjustment amount; The time-domain coefficient may be updated using the coefficient adjustment amount to obtain an updated time-domain coefficient. In practical application, after obtaining the coefficient adjustment amount, the time-domain coefficient may be updated according to the frequency-domain coefficient update algorithm.

In this embodiment, the time domain coefficient may be updated once every bit, or the time domain coefficient may be updated once every few bits. In this embodiment, one bit means a time for performing one frequency domain clock recovery and frequency domain blind equalization processing. That is, each bit implements one frequency domain clock recovery and frequency domain blind equalization processing.

In practical application, after the time-domain coefficients are updated each time, the time-domain coefficients that should be obtained for the frequency-domain blind equalization process are the updated time-domain coefficients.

In actual application, the aforementioned steps 2010 to 2030 may be implemented by a processor, wherein the processor is an Application Specific Integrated Circuit (ASIC), a Digital Signal Processor (DSP), or a digital signal processing unit. Device (Digital Signal Processing Device, DSPD), Programmable Logic Device (PLD), Field Programmable Gate Array (FPGA), Central Processing Unit (CPU), Controller, Microcontroller and It may be one or more of a microprocessor.

Compared with the related art, by using the signal processing method of the embodiment of the present application, clock recovery and blind equalization processing can be implemented in the frequency domain, thereby reducing the computational complexity implemented in the time domain, and frequency in a processor such as DSP. When implementing the domain clock recovery and blind equalization processing, compared with the frequency domain clock recovery and blind equalization processing implemented in the time domain, the number of multipliers used in the processor can be saved, thereby reducing computing power consumption, and clock recovery And through the integrated architecture design of the blind equalization processing, it is possible to reduce the repetitive work part existing in each design of the clock recovery and the blind equalization processing.

Based on the foregoing, an implementation flow of an embodiment of the present application will be intuitively described with reference to FIG. 3: FIG. 3 is a flowchart of a signal processing method provided by an embodiment of the present application, as shown in FIG. , by performing frequency domain clock recovery first, clock recovery output data may be obtained. The implementation method of the frequency domain clock recovery has already been described in the above description, so it will not be repeated here.

After acquiring the clock recovery output data, frequency domain CMA equalization may be performed using the clock recovery output data, and the frequency domain CMA equalization process may include CMA filtering and coefficient updating. Since the process of updating coefficients is the process of updating the time domain coefficients of the above description, it is not repeated here. Time-domain equalized data may be obtained through CMA filtering, the time-domain equalized data may be used as a basis for coefficient update, and updated time-domain coefficients obtained through coefficient update may be used as a basis for CMA filtering.

The process of CMA filtering may include: acquiring frequency domain CMA input data; performing FFT transformation on the updated time-domain coefficients to obtain frequency-domain coefficients; multiplying the frequency domain CMA input data with frequency domain coefficients to obtain frequency domain equalization data; IFFT transformation is performed on the frequency-domain equalized data to convert the frequency-domain equalized data into a time domain to obtain time-domain equalized data.

second embodiment

In order to implement the object of the present application, based on the first embodiment of the present application, for example, the description will proceed.

The signal processing process of the second embodiment of the present application includes two processes of frequency domain clock recovery and frequency domain CMA equalization, among which the process of frequency domain CMA equalization includes CMA filtering and coefficient updating.

The frequency domain clock recovery process is implemented by the frequency domain clock recovery module, the frequency domain CMA equalization process is implemented by the frequency domain CMA equalization module, the CMA filtering process is implemented by the CMA filter submodule, and the coefficient update process is the coefficient Implemented by the update submodule.

In the second embodiment of the present application, input data to be obtained when performing frequency domain clock recovery (clock recovery input data) is time domain data at a sampling rate of 1.5 times.

4 is a frequency domain clock recovery flow chart provided by an embodiment of the present invention, and as shown in FIG. 4 , the frequency domain clock recovery flow may include:

Step 410: Frequency domain phase determination.

The implementation method of this step is as follows: Phase discrimination is performed on the multi-segment frequency domain equalization data output from the CMA filter submodule through Equation (1) using Godard phase discriminator, and the phase according to Equation (2) Extract the error value.

및

는 각각 X 편광 상태와 Y 편광 상태에서의 m 번째 세그먼트와 K+1 번째 다중 세그먼트 주파수 영역 등화 데이터이며, M은 세그먼트 수, C는 추출된 클럭 신호, u는 위상 오차 값, N은 4의 정수 배수, 위 첨자 *는 켤레를 의미한다.among these,

and

are the m-th segment and K+1-th multi-segment frequency domain equalization data in X and Y polarization states, respectively, M is the number of segments, C is the extracted clock signal, u is the phase error value, and N is an integer of 4 Multiples, the superscript * means conjugate.

Step 420: Data segmentation, data FFT, and data interpolation are sequentially performed.

The implementation manner of this step is as follows: through formula (3), interpolation processing is performed on the multi-segment frequency-domain input data to obtain multi-segment frequency-domain interpolated data (that is, the above-described clock recovery output data) . Multi-segment frequency-domain input data is obtained in the following way: by dividing the clock recovery input data of 1.5 times the sampling rate, to obtain multi-segment time-domain input data of length 0.75N each; the time domain input data of two adjacent segments overlap, and the number of midpoints is not less than the number of taps of the frequency domain CMA equalization coefficient minus one; A 0.75N-point FFT transform is performed on the multi-segment time-domain input data to obtain multi-segment frequency-domain input data.

및

은 각각 X 편광 상태와 Y 편광 상태에서의 m 번째 세그먼트와 k+1 번째 다중 세그먼트 주파수 영역 입력 데이터이며,

및

는 각각 보간 처리된 X 편광 상태와 Y 편광 상태에서의 m 번째 세그먼트와 k+1 번째 다중 세그먼트 주파수 영역 보간 데이터이다. among these,

and

are the m-th segment and k+1-th multi-segment frequency domain input data in the X polarization state and the Y polarization state, respectively,

and

are interpolated m-th segment and k+1-th multi-segment frequency domain data in X polarization state and Y polarization state, respectively.

5 is a CMA filtering flowchart provided by an embodiment of the present application, and as shown in FIG. 5 , the flow of CMA filtering may include:

Step 510: Acquire input data of a frequency domain CMA.

In one embodiment, the function of inserting N/4 zeros at the middle position of multi-segment frequency domain interpolation data, multiplying each data by 4/3, and converting the 1.5 times sampling rate into 2 times the sampling rate , to obtain multi-segment frequency domain CMA input data. Here, the multi-segment frequency domain CMA input data is the aforementioned frequency domain CMA input data.

Step 520: Coefficients FFT.

In one embodiment, an N-point FFT transform is performed on the updated time-domain coefficients output from the coefficient update submodule to obtain frequency-domain coefficients.

Step 530: Equalization filtering.

Through Equation (4), the input data of the multi-segment frequency domain CMA is multiplied by the frequency domain coefficients to obtain multi-segment frequency domain equalization data to implement the equalization filtering function.

및

는 각각 X 편광 상태와 Y 편광 상태에서 m 번째 세그먼트와 k+1 번째 다중 세그먼트 주파수 영역 CMA의 입력 데이터이며;

,

,

및

는 4 세트의 주파수 영역 계수의 k+1 번째 탭 값이다. among these,

and

are the input data of the m-th segment and the k+1-th multi-segment frequency domain CMA in the X polarization state and the Y polarization state, respectively;

,

,

and

is the k+1th tap value of 4 sets of frequency domain coefficients.

By adding multi-segment frequency-domain equalization data of the front half segment and the rear half segment for aliasing processing, a function of converting the double sampling rate to 1 is implemented to obtain multi-segment frequency-domain equalized data after aliasing.

Step 540: Data IFFT.

In one embodiment, an N/2-point IFFT transform is performed on the multi-segment frequency-domain equalized data after aliasing to obtain multi-segment time-domain equalized data, and then overlapping data in the multi-segment time-domain equalized data is removed, Combined, output to the coefficient update sub-module and the subsequent module of the coherent optical communication system (eg, a module implementing carrier synchronization).

In the embodiment of the present application, the coefficient update submodule takes the input and output of the CMA filtering submodule as its own input, and the coefficient update submodule outputs the updated equalization coefficient.

6 is a coefficient update flow chart provided by an embodiment of the present application, and as shown in FIG. 6 , the coefficient update flow may include:

Step 610: Calculate the error.

In one embodiment, the overlap data value of the multi-segment time-domain equalization data is set to 0, and then multiplied by a constant and the difference of the square of the modulus of the data to obtain multi-segment error data, and to reduce the amount of computation, update the coefficients The number of segments used for can be about half that of M.

Step 620: Error FFT.

In one embodiment, an N/2-point FFT transform is performed on multi-segment error data, and then the FFT transform result is copied and spliced to implement a function of converting a 1x sampling rate to 2x, so that the frequency domain error data to acquire

Step 630: Calculate the cross spectrum.

In one embodiment, using formula (5), the input data of the multi-segment frequency domain CMA is conjugated with the multi-segment frequency domain error data to obtain multi-segment cross-spectral data.

및

는 각각 X 편광 상태와 Y 편광 상태에서의 m 번째 세그먼트와 k+1 번째 다중 세그먼트 주파수 영역 오차 데이터이며,

,

,

및

는 다중 세그먼트 교차 스펙트럼 데이터이다. among these,

and

are the m-th segment and k+1-th multi-segment frequency domain error data in the X polarization state and the Y polarization state, respectively,

,

,

and

is multi-segment cross-spectral data.

Multi-segment accumulation is sequentially performed on multi-segment cross-spectral data to obtain full cross-spectral data.

Step 640: Cross-spectrum IFFT.

In one embodiment, the number of taps of the time-domain coefficient is set to T, N-point IFFT transformation is performed on the entire cross-spectral data, and the first T data are taken to obtain a coefficient adjustment amount.

Step 650: Update coefficients.

In one embodiment, an updated time-domain coefficient is obtained by selecting iteration coefficients, multiplying each by a coefficient adjustment amount, and adding correspondingly to the current time-domain coefficients.

Data of 1.5 times the sampling rate is only an exemplary implementation method of clock recovery input data, and the embodiment of the present application provides clock recovery input data as long as the clock recovery input data satisfies the condition that the data sampling rate is 1 times or more. does not limit the sampling rate of recovery input data; In the frequency domain CMA equalization process, the data sampling rate is doubled.

third embodiment

In order to implement the object of the present application, based on the first embodiment of the present application, for example, the description will proceed.

The signal processing process of the third embodiment of the present application includes two processes of frequency domain clock recovery and frequency domain CMA equalization, among which the frequency domain CMA equalization process includes CMA filtering and coefficient updating. The frequency domain clock recovery process is implemented by the frequency domain clock recovery module, the frequency domain CMA equalization process is implemented by the frequency domain CMA equalization module, the CMA filtering process is implemented by the CMA filter submodule, and the coefficient update process is Implemented by the update submodule.

In the third embodiment of the present application, input data to be obtained when performing frequency domain clock recovery (clock recovery input data) is time domain data at a double sampling rate.

7 is another frequency domain clock recovery flowchart provided by an embodiment of the present invention, and as shown in FIG. 7 , the frequency domain clock recovery process may include the following.

Step 710: Frequency domain phase determination.

In one embodiment, using Equation (1), phase discrimination is performed on multi-segment frequency domain equalization data output from the CMA filtering submodule, and a phase error value is extracted according to Equation (2).

Step 720: data interpolation and data addition and deletion processing.

의 소수 부분이다.In one embodiment, compute the fractional interpolation pointer u1 according to the phase error value u, and the value is

is the fractional part of

According to formula (6), calculate the interpolation filter coefficients of 6 taps by decimal interpolation pointers.

splicing at least one bit previous clock recovery input data with first eight data bits of clock recovery input data one bit later to obtain spliced data; The spliced data is convolved in the time domain with an interpolation filter h to obtain interpolated data (ie, the above-described clock recovery output data).

로 기록되면, 다음과 같은 세 가지 조건이 있다:The interpolation data obtained from the current bit is merged with the end of the interpolation data obtained from the previous bit, the combined data is added or deleted according to the phase error value, and the phase error value of the previous bit is

When written as , there are three conditions:

일 때, 결합된 데이터를 주파수 영역 CMA 등화 모듈로 직접 출력한다.One)

When , the combined data is directly output to the frequency domain CMA equalization module.

일 때, 결합된 데이터의 처음 2 개 데이터를 삭제하고 주파수 영역 CMA 등화 모듈로 출력한다.2)

When , the first two data of the combined data are deleted and output to the frequency domain CMA equalization module.

3) When the above conditions 1) and 2) are not satisfied (except for the circumstances except for condition 1) and 2), the first 1 data of the combined data is deleted and provided to the frequency domain CMA equalization module .

8 is another CMA filtering flowchart provided by an embodiment of the present application, and as shown in FIG. 8 , the process of CMA filtering may include the following.

Step 810: Data Segmentation and Data FFT.

In one embodiment, the input data of the frequency domain CMA equalization module is divided into a total of M segments, each segment has a data length of 2N, adjacent two segment data are overlapped, and the number of overlapping points is the frequency domain CMA not less than the number of taps in the equalization coefficient minus one; Then, the division result is divided into multi-segment time-domain odd sequence input data and multi-segment time-domain even sequence input data according to the parity index, and N-point FFT transformation is performed to obtain multi-segment frequency domain odd sequence input data and multi-segment Acquire frequency domain even sequence input data.

Step 820: Coefficients FFT.

In one embodiment, the time-domain coefficients output by the coefficient update submodule are divided into time-domain odd sequence coefficients and time-domain even sequence coefficients according to the parity index, and N-point FFT transform is performed to obtain frequency-domain odd sequence coefficients and Obtain frequency domain even sequence coefficients.

Step 830: Equalization filtering.

In one embodiment, through formula (7), the multi-segment frequency domain odd sequence input data and the multi-segment frequency domain even sequence input data are multiplied by the frequency domain odd sequence coefficient and the frequency domain even sequence coefficient, respectively, so that the multi-segment frequency domain By acquiring equalization data, an equalization filtering function is implemented.

,

,

및

는 각각 k+1 번째 주파수 영역 홀수 시퀀스 계수이고,

,

,

및

는 각각 k+1 번째 주파수 영역 짝수 시퀀스 계수이며;

및

는 각각 X 편광 상태와 Y 편광 상태에서의 m 번째 섹션 k+1 번째 다중 세그먼트 주파수 영역 홀수 시퀀스 입력 데이터이고,

및

는 각각 X 편광 상태 및 Y 편광 상태에서의 m 번째 섹션 k+1번째 다중 세그먼트 주파수 영역 짝수 시퀀스 입력 데이터이다. Among these, k = 0,1,..,N-1,

,

,

and

are the k+1th frequency domain odd sequence coefficients, respectively,

,

,

and

are the k+1th frequency domain even sequence coefficients, respectively;

and

is the m-th section k+1-th multi-segment frequency domain odd sequence input data in the X polarization state and the Y polarization state, respectively,

and

is the k+1th multi-segment frequency domain even sequence input data of the m-th section in the X polarization state and the Y polarization state, respectively.

Step 840: Data IFFT.

performing N-point IFFT transformation on the multi-segment frequency-domain equalized data to obtain multi-segment time-domain equalized data; Remove overlapping data from time-domain equalization data of multiple segments and combine according to the natural sequence of indices, and output a coefficient update submodule and a coherent optical communication system subsequent module (for example, a module implementing carrier synchronization) .

In the embodiment of the present application, the coefficient update submodule takes the input and output of the CMA filtering submodule as its own input, and the coefficient update submodule outputs the updated equalization coefficient.

In the third embodiment of the present application, referring to FIG. 6 , the coefficient update flow may include:

Step A10: Calculate the error.

Since the implementation method of this step is the same as the implementation method of step 610, it is not repeated here.

Step A20: Error FFT.

In one embodiment, N-point FFT transform is performed on multi-segment error data to obtain multi-segment frequency domain error data.

Step A30: Calculate the cross spectrum.

In one embodiment, using formula (8), multi-segment frequency domain odd sequence input data and multi-segment frequency domain even sequence input data are conjugated with multi-segment frequency domain error data to obtain multi-segment spectral data.

및

는 각각 X 편광 상태와 Y 편광 상태에서의 k+1번째 다중 세그먼트 주파수 영역 홀수 시퀀스 입력 데이터이고,

및

는 각각 X 편광 상태의 및 Y 편광 상태에서의 k+1번째 다중 세그먼트 주파수 영역 홀수 시퀀스 입력 데이터이고,

,

,

,

,

,

,

및

는 제1 세그먼트의 k+1번째 다중 세그먼트 교차 스펙트럼 데이터이며,

은 계수 업데이트에 사용된 세그먼트의 수이다. among these,

and

are k+1th multi-segment frequency domain odd sequence input data in X polarization state and Y polarization state, respectively,

and

is the k+1th multi-segment frequency domain odd sequence input data in the X polarization state and in the Y polarization state, respectively,

,

,

,

,

,

,

and

is the k+1th multi-segment cross-spectral data of the first segment,

is the number of segments used for coefficient update.

Multi-segment accumulation is sequentially performed on multi-segment cross-spectral data to obtain full cross-spectral data.

Step A40: Cross-Spectral IFFT.

Since the implementation method of this step is the same as the implementation method of step 640, it is not repeated here.

Step A50: Update coefficients.

In one embodiment, iteration coefficients are selected, each multiplied by a coefficient adjustment amount; adding the result to each current time-domain odd sequence coefficient and time-domain even sequence coefficient to obtain updated time-domain odd sequence coefficient and time-domain even sequence coefficient; Sort and combine the updated time-domain odd sequence coefficients and the time-domain even sequence coefficients according to the natural sequence of indices to obtain updated time-domain coefficients.

4th embodiment

In order to implement the object of the present application, based on the first embodiment of the present application, for example, description will proceed.

The signal processing process of the fourth embodiment of the present application includes two processes of frequency domain clock recovery and frequency domain CMA equalization, among which the process of frequency domain CMA equalization includes CMA filtering and coefficient updating. The frequency domain clock recovery process is implemented by the frequency domain clock recovery module, the frequency domain CMA equalization process is implemented by the frequency domain CMA equalization module, the CMA filtering process is implemented by the CMA filter submodule, and the coefficient update process is Implemented by the update submodule.

9 is another frequency domain clock recovery flowchart provided in an embodiment of the present invention, and as shown in FIG. 9 , the process of frequency domain clock recovery may include:

Step 910: data segmentation, data FFT, pre-filtering and frequency domain phase determination.

In one embodiment, using a Godard phase discriminator, the phase discrimination is performed on the data of the phase discrimination target through the formula (1), and a phase error value is obtained according to the formula (2).

The method of acquiring the data of the phase discrimination target is as follows:

First, the clock recovery input data is divided into segments of length N, and FFT transformation is performed on the divided data to obtain multi-segment frequency domain input data, and then, the multi-segment frequency domain input data is added to the multi-segment frequency domain input data in the frequency domain CMA equalization module. By multiplying the obtained frequency domain coefficients to implement a pre-filtering operation, data to be identified as a phase is obtained.

Step 920: Data Interpolation.

In one embodiment, through formula (9), interpolation processing is performed on the multi-segment frequency-domain input data to obtain multi-segment frequency-domain interpolated data (ie, the aforementioned clock recovery output data), and the multi-segment frequency Output the domain interpolated data to the frequency domain CMA equalization module.

10 is another CMA filtering flowchart provided by an embodiment of the present application, and as shown in FIG. 10 , the CMA filtering process may include:

Step 10010: Coefficients FFT.

In one embodiment, input data of the frequency domain CMA is obtained. That is, multi-segment frequency domain interpolation data is obtained. An N-point FFT transform is performed on the updated time-domain coefficients output from the coefficient update submodule to obtain frequency-domain coefficients.

Step 10020: Equalization filtering.

In one embodiment, through formula (4), input data of the multi-segment frequency domain CMA is multiplied by frequency domain coefficients, respectively, to obtain multi-frequency domain equalization data, to implement an equalization filtering function.

Step 10030: Data IFFT.

In one embodiment, performing N-point IFFT transformation on the multi-segment frequency-domain equalized data to obtain multi-segment time-domain equalized data; The overlapping data in the multi-segment time-domain equalization data is removed and combined, and output to a coefficient update sub-module and a subsequent module of the coherent optical communication system (eg, a module implementing carrier synchronization).

In the embodiment of the present application, the coefficient update submodule takes the input and output of the CMA filtering submodule as its own input, and the coefficient update submodule outputs the updated equalization coefficient.

In the fourth embodiment of the present application, referring to FIG. 6 , the flow of coefficient update may include:

Step B10: Calculate the error.

Since the implementation method of this step is the same as the implementation method of step 610, it is not repeated here.

Step B20: Error FFT.

In one embodiment, N-point FFT transform is performed on multi-segment error data to obtain multi-segment frequency domain error data.

Step B30: Cross Spectrum Calculation.

In one embodiment, using formula (5), the multi-segment frequency domain CMA input data is conjugated with the multi-segment frequency domain error data to obtain multi-segment cross-spectral data. Multi-segment accumulation is sequentially performed on multi-segment cross-spectral data to obtain full cross-spectral data.

Step B40: Cross-Spectral IFFT.

In one embodiment, the number of taps of the time-domain coefficient is set to T, an N-point IFFT transformation is performed on the entire cross-spectral data, and the preceding T data is taken to obtain a coefficient adjustment amount.

Step B50: Update coefficients.

In one embodiment, an updated time-domain coefficient is obtained by selecting iteration coefficients, multiplying each by a coefficient adjustment amount, and adding correspondingly to the current time-domain coefficients.

The frequency domain CMA equalization method of the embodiment of the present application is different from the CMA algorithm of the related art. In the embodiment of the present application, the CMA filtering process and the coefficient updating process may be implemented by using an FFT transform to transform data into a frequency domain, and may also be implemented by direct multiplication in the frequency domain. Implementing CMA equalization in the frequency domain reduces the computational complexity of implementing in the time domain.

Table 1 is a comparison table of complex multiplication numbers of the CMA time-frequency domain equalization method in multiple mode. Referring to Table 1, since the number of complex multiplications required for the frequency domain CMA method is actually less than that of the time domain CMA method, which saves about 50% of computing resources, computing power consumption can be reduced by applying the chip of the embodiment of the present application.

5th embodiment

Based on the signal processing method proposed in the above-described embodiment of the present application, the fifth embodiment of the present application proposes a signal processing apparatus applicable to a coherent optical communication system.

11 is a schematic diagram of a configuration structure of a signal processing apparatus provided by an embodiment of the present application. 11 , the apparatus includes an acquiring unit 1101 , a first processing unit 1102 , and a second processing unit 1103 . Among them, the acquiring unit 1101 is configured to acquire the clock recovery input data; the first processing unit 1102 is configured to perform frequency domain clock recovery on the clock recovery input data to obtain clock recovery output data; The second processing unit 1103 is configured to perform, according to the clock recovery output data, frequency domain blind equalization processing, to obtain frequency domain equalization data.

In one implementation manner, the first processing unit 1102 acquires the data of the phase determination object; performing phase determination on the data of the phase determination target to extract a phase error value; and perform interpolation processing on the clock recovery input data using the phase error value to obtain the clock recovery output data.

In one implementation manner, the first processing unit 1102 is configured to obtain the data of the phase determination object through the following manner: converts the clock recovery input data into a frequency domain, so as to convert the clock recovery input data in the frequency domain obtaining, and multiplying the frequency domain clock recovery input data by a frequency domain coefficient used in the frequency domain blind equalization process to obtain the phase discrimination target data; Alternatively, the frequency domain equalization data obtained immediately before is used as the phase determination target data.

In one implementation manner, the first processing unit 1102 is configured to perform interpolation processing on the clock recovery input data using the phase error value through the following manner to obtain the clock recovery output data: time domain , performing finite-length unit impulse response FIR filtering on the clock recovery input data according to the phase error value to obtain clock recovery output data; or converting the clock recovery input data into a frequency domain to obtain clock recovery input data in the frequency domain; In the frequency domain, phase adjustment is performed through the clock recovery input data in the frequency domain to obtain clock recovery output data.

In one embodiment, the second processing unit 1103 obtains the frequency domain blind equalization input data according to the clock recovery output data; obtain frequency domain coefficients; and multiplying the frequency-domain blind equalized input data with a frequency-domain coefficient to obtain frequency-domain equalized data.

In one embodiment, the second processing unit 1103 is configured to obtain the frequency domain blind equalized input data according to the clock recovery output data in the following manner: the clock recovery output data is data obtained in the time domain case, converting the clock recovery output data into a frequency domain to obtain frequency domain blind equalization input data; When the clock recovery output data is data acquired in the frequency domain, the clock recovery output data in the frequency domain is the frequency domain blind equalization input data.

In one implementation manner, the second processing unit 1103 is configured to obtain the frequency domain coefficients in the following manner: obtain the time domain coefficients, transform the time domain coefficients into the frequency domain, to obtain the frequency domain coefficients do.

In one implementation manner, the second processing unit 1103 is further configured to, after obtaining the frequency domain equalized data, transform the frequency domain equalized data into the time domain to obtain the time domain equalized data.

In one implementation manner, the second processing unit 1103 is further configured to update the time-domain coefficients according to the frequency-domain blind equalized input data and the time-domain equalized data, to obtain updated time-domain coefficients.

In one implementation manner, the second processing unit 1103 is configured to update the time-domain coefficients according to the frequency-domain blind equalized input data and the time-domain equalized data through the following manner, to obtain updated time-domain coefficients. be: perform error calculation on the time-domain equalization data to obtain time-domain error data; converting the time domain error data into a frequency domain to obtain frequency domain error data; conjugate the frequency-domain error data with the frequency-domain blind equalized input data to obtain cross-spectral data; The time-domain coefficients are updated according to the cross-spectral data to obtain updated time-domain coefficients.

In one implementation manner, the second processing unit 1103 is configured to update the time-domain coefficient according to the cross-spectral data through the following manner, to obtain an updated time-domain coefficient: convert the cross-spectral data into the time-domain transform to obtain a coefficient adjustment amount; The time-domain coefficient is updated using the coefficient adjustment amount to obtain an updated time-domain coefficient.

In practical applications, the above-described acquisition unit 1101, first processing unit 1102, and second processing unit 1103 are all located in a coherent optical communication system, including CPU, Micro Processor Unit (MPU), DSP , FPGA, or the like.

In addition, a plurality of functional modules in the present embodiment may be integrated into one processing unit, each unit may exist alone physically, or two or more units may be integrated into one unit. The above-described integrated unit may be implemented in the form of a hardware function module or may be implemented in the form of a software function module.

When the integrated unit is implemented in the form of a software function module and is not sold or used as an independent product, it may be stored in a computer-readable storage medium. Based on this understanding, all or part of the technical solution of this embodiment may be implemented in the form of a software product. The computer software product is stored in a storage medium and includes a plurality of instructions that cause a computer device (such as a personal computer, server or network device) or processor to execute all or some steps of the method of the present embodiment. The aforementioned storage medium may include a Universal Serial Bus disk (U disk), a mobile hard disk, a read only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk. It includes various media that can store program code, such as.

The computer program instructions corresponding to the signal processing method of the present embodiment may be stored in a storage medium such as an optical disk, a hard disk, a U disk, or the like. When the computer program instruction corresponding to the signal processing method of the storage medium is read or executed by the electronic equipment, the steps of any signal processing method of the above-described embodiments are implemented.

Based on the same technical concept as the above-described embodiment, referring to FIG. 12 , a signal processing facility 120 provided by an embodiment of the present application is illustrated. The device may include a memory 121 and a processor 122; Among them, the memory 121 is set to store computer programs and data; The processor 122 is configured to execute a computer program stored in the memory to implement any signal processing method of the above-described embodiment.

In practical applications, the above-described memory 121 is a volatile memory such as RAM or ROM, flash memory or a hard disk (HDD)) or a solid-state drive (Solid-State Drive, non-volatile memory such as SSD); Alternatively, a combination of the types of memory described above may provide instructions and data to the processor 122 .

The aforementioned processor 122 may be at least one of ASIC, DSP, DSPD, PLD, FPGA, CPU, controller, microcontroller, and microprocessor. In the case of other facilities, the electronic device configured to implement the above-described processor function may be different, which is not limited to the embodiment of the present application.

Embodiments of the present application may be provided as methods, systems, or computer program products. Accordingly, the present application may adopt the form of a hardware embodiment, a software embodiment, or an embodiment combining software and hardware. In addition, the present application may adopt the form of one or more computer program products embodied in a computer usable storage medium (including but not limited to disk storage devices, optical storage devices, etc.) comprising program code for a computer. have.

The present application is described with reference to flowcharts and/or block diagrams of methods, equipment (systems) and computer program products according to embodiments of the present application. It should be understood that each flow and/or block in the flowcharts and/or block diagrams, and combinations of flows and/or blocks in the flowcharts and/or block diagrams, may be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor or other programmable data processing facility to create a device, via instructions executed by the processor of the computer or other programmable data processing facility. Create a device that implements one or more flows in the flowchart and/or the functionality specified in one or more blocks in the block diagram.

These computer program instructions may also be stored in a computer readable memory capable of instructing a computer or other programmable data processing facility to operate in a particular manner, such that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device. can This instruction device implements functions specified in one or more flows in the flowchart and/or in one or more blocks in the block diagram.

Such computer program instructions may also be loaded into a computer or other programmable data processing facility such that a series of steps of work are executed on the computer or other programmable facility to produce computer implemented processing, such that the computer or other programmable facility executes the computer program instructions. The instructions may provide for implementing one or more flows in the flowcharts and/or implementing functions specified in one or more blocks in the block diagrams. The above description is only an embodiment of the present application, and is not used to limit the protection scope of the present application.

1101: acquiring unit, 1102: first processing unit, 1103: second processing unit, 121: memory, 122: processor

Claims (14)

acquire clock recovery input data;
perform frequency domain clock recovery on the clock recovery input data to obtain clock recovery output data;
and performing frequency domain blind equalization processing according to the clock recovery output data to obtain frequency domain equalization data. The method according to claim 1, wherein performing frequency domain clock recovery on the clock recovery input data to obtain clock recovery output data comprises:
acquiring data of a phase discrimination target;
performing phase determination on the data of the phase determination target to extract a phase error value from the data of the phase determination target;
and performing interpolation processing on the clock recovery input data using the phase error value to obtain clock recovery output data. The method according to claim 2, wherein acquiring the data of the phase determination target comprises:
The clock recovery input data is converted into a frequency domain to obtain clock recovery input data in the frequency domain, and the clock recovery input data in the frequency domain is multiplied by a frequency domain coefficient used for frequency domain blind equalization processing, and the phase determination target obtain data of;
and using the frequency domain equalization data obtained immediately before as the phase determination target data. 4. The method of claim 2 or 3, wherein performing interpolation processing on the clock recovery input data using the phase error value to obtain clock recovery output data comprises:
in the time domain, perform finite-length unit impulse response FIR filtering on the clock recovery input data according to the phase error value to obtain clock recovery output data;
or, converting the clock recovery input data into a frequency domain to obtain clock recovery input data in the frequency domain; and performing phase adjustment on the clock recovery input data in the frequency domain through the phase error value in the frequency domain to obtain clock recovery output data. The method according to any one of claims 1 to 4, wherein, according to the clock recovery output data, performing frequency domain blind equalization processing to obtain frequency domain equalization data comprises:
acquire frequency domain blind equalization input data according to the clock recovery output data;
obtain frequency domain coefficients;
multiplying the frequency domain blind equalized input data by the frequency domain coefficients to obtain the frequency domain equalized data. 6. The method of claim 5, wherein obtaining frequency domain blind equalized input data according to the clock recovery output data comprises:
when the clock recovery output data is data obtained in the time domain, converting the clock recovery output data into a frequency domain to obtain the frequency domain blind equalization input data;
and when the clock recovery output data is data acquired in the frequency domain, acquiring the frequency domain blind equalized input data according to the clock recovery output data of the frequency domain. 7. The method of claim 5 or 6, wherein obtaining the frequency domain coefficients comprises:
obtaining time domain coefficients, and converting the time domain coefficients into frequency domain to obtain the frequency domain coefficients. The signal processing method according to claim 7, further comprising, after acquiring the frequency domain equalized data, converting the frequency domain equalized data into a time domain to obtain time domain equalized data. The method according to claim 8, further comprising: after obtaining the time-domain equalized data, updating the time-domain coefficients according to the frequency-domain blind equalized input data and the time-domain equalized data to obtain updated time-domain coefficients which is a signal processing method. The method according to claim 9, wherein updating the time-domain coefficients according to the frequency-domain blind equalized input data and the time-domain equalized data to obtain updated time-domain coefficients comprises:
performing error calculation on the time-domain equalization data to obtain time-domain error data;
converting the time domain error data into a frequency domain to obtain frequency domain error data;
conjugately multiplying the frequency domain error data with the frequency domain blind equalized input data to obtain cross-spectral data;
updating the time-domain coefficients according to the cross-spectral data to obtain updated time-domain coefficients. The method of claim 10 , wherein updating the time-domain coefficients according to the cross-spectral data to obtain the updated time-domain coefficients comprises:
transform the cross-spectral data into a time domain to obtain a coefficient adjustment amount;
and updating the time-domain coefficients using the coefficient adjustment amount to obtain updated time-domain coefficients. an acquiring unit, configured to acquire clock recovery input data;
a first processing unit, configured to perform frequency domain clock recovery on the clock recovery input data to obtain clock recovery output data;
and a second processing unit, configured to perform frequency domain blind equalization processing according to the clock recovery output data to obtain frequency domain equalization data. a processor and a memory configured to store a computer program executing on the processor; 12. A signal processing facility, wherein the processor is configured to execute the signal processing method according to any one of claims 1 to 11 when executing the computer program. A computer storage medium storing a computer program and executing the signal processing method of any one of claims 1 to 11 when the computer program is executed by a processor.

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