KR20210089341A - Method and circuit for detecting metastability of comparator - Google Patents

Abstract

The present invention relates to a method for detecting metastability of a comparator and a detection circuit thereof. According to an embodiment of the present invention, a circuit for detecting metastability of a comparator comprises: a driving voltage generator receiving differential output signals from a differential output comparator and generating a driving voltage for each of the differential output signals when each of the differential output signals falls less than or equal to a detection voltage; and a metastability detection unit generating a metastability detection signal on the basis of the driving voltage. Accordingly, the circuit for detecting metastability of a comparator is implemented as a simple circuit, thereby efficiently detecting metastability of a comparator. In addition, the circuit can occupy a small space, reduce power consumption, and quickly determine whether a comparator is metastable.

Description

METHOD AND CIRCUIT FOR DETECTING METASTABILITY OF COMPARATOR

The present invention relates to a semiconductor circuit, and more particularly, to a metastability detection circuit and a detection method of a comparator.

The comparator compares the voltage levels of the received input signals to determine which is greater, and represents this as an output signal. Accordingly, when the comparator cannot determine which of the input signals is greater, it may be in an unstable state, which may persist for a longer period as the voltage level difference between the input signals is smaller. In this case, it can be said that the comparator has metastability.

SUMMARY OF THE INVENTION An object of the present invention for solving the above problems is to provide a method and a semiconductor circuit capable of efficiently detecting metastability of a comparator.

In order to achieve the above object, a metastability detection circuit of a comparator according to an embodiment of the present invention receives differential output signals from the differential output comparator, and when each differential output signal goes below a detection voltage, the differential and a driving voltage generator configured to generate a driving voltage for each of the output signals, and a metastability detector configured to generate a metastability detection signal based on the driving voltage.

The driving voltage generator may include first and second PMOS transistors, first and second NMOS transistors, and a capacitor, wherein the first PMOS transistor is connected between a power supply voltage and a first node wherein the first NMOS transistor is connected between the first node and a ground node, the capacitor is connected between the first node and the ground node, and the second PMOS transistor is connected between the power supply voltage and a second node. may be connected to, the second NMOS transistor may be connected between the second node and the ground node, and the capacitor may be connected between the second node and the ground node.

According to an embodiment, each of the first and second PMOS transistors may use any one of the differential output signals as a gate voltage.

In some embodiments, the metastability detector may include a NAND-gate, and an input signal of the NAND-gate may be voltage levels of the first node and the second node.

In some embodiments, the driving voltage generator may be reset while the comparator is deactivated.

In some embodiments, a magnitude of a current flowing from the power supply voltage to each of the first node and the second node may be determined based on a channel width and a channel length of the first PMOS transistor and the second PMOS transistor.

In order to achieve the above object, a method for detecting metastability of a comparator according to another embodiment of the present invention includes: receiving differential output signals from a differential output comparator; when each differential output signal goes below a detection voltage, the generating a driving voltage for each of the differential output signals, and generating a metastability detection signal based on the driving voltage.

The driving voltage generator may include first and second PMOS transistors, first and second NMOS transistors, and a capacitor, wherein the first PMOS transistor is connected between a power supply voltage and a first node wherein the first NMOS transistor is connected between the first node and a ground node, the capacitor is connected between the first node and the ground node, and the second PMOS transistor is connected between the power supply voltage and a second node. may be connected to, the second NMOS transistor may be connected between the second node and the ground node, and the capacitor may be connected between the second node and the ground node.

In some embodiments, the metastability detector may include a NAND-gate, and an input signal of the NAND-gate may be voltage levels of the first node and the second node.

In some embodiments, a magnitude of a current flowing from the power supply voltage to each of the first node and the second node may be determined based on a channel width and a channel length of the first PMOS transistor and the second PMOS transistor.

The metastability detection method and detection circuit of a comparator according to an embodiment of the present invention is implemented as a simple circuit, so that the metastability of the comparator can be efficiently detected. Accordingly, the metastability detection circuit of the comparator according to the embodiments of the present invention occupies a small space and can reduce power consumption. Furthermore, the method and detection circuit for metastability of a comparator according to embodiments of the present invention can quickly determine whether the comparator is metastability.

1 is a flowchart illustrating a method for detecting metastability of a comparator according to an embodiment of the present invention.
2 is a block diagram illustrating a metastability detection circuit of a comparator according to an embodiment of the present invention.
3 is a diagram for explaining metastability of a comparator.
4A is a block diagram illustrating a metastability detection circuit of a comparator according to an embodiment of the present invention.
Fig. 4B is a circuit diagram of the metastability detection circuit of the comparator shown in Fig. 4A.
5A is a block diagram illustrating a metastability detection circuit of a comparator according to another embodiment of the present invention.
Fig. 5B is a circuit diagram of the metastability detection circuit of the comparator shown in Fig. 5A.
6A is a block diagram illustrating a metastability detection circuit of a comparator according to another embodiment of the present invention.
6B is a circuit diagram of a metastability detection circuit of the comparator shown in FIG. 6A.
7 is a diagram illustrating an image sensor having an analog-to-digital converter including a comparator according to embodiments of the present invention.

Hereinafter, preferred embodiments of the present invention will be described in more detail with reference to the accompanying drawings. The same reference numerals are used for the same components in the drawings, and repeated descriptions of the same components are omitted.

1 is a flowchart illustrating a method for detecting metastability of a comparator according to an embodiment of the present invention. 2 is a block diagram illustrating a metastability detection circuit according to an embodiment of the present invention.

1 and 2 , the metastability detection circuit 10 receives differential output signals vo1 and vo2 from the differential output comparator 20 ( S10 ).

Here, the comparator 20 receives the input signals vip and vin, compares the voltage levels of the input signals vip and vin, determines which one is greater, and converts it to the differential output signals vo1 , vo2).

Here, the input signals vip and vin may be analog input signals, and according to an embodiment, the input signals vip and vin may be a signal converted from an analog signal and a reference signal corresponding thereto. According to an embodiment, when the comparator 20 is used in a Successive Approximation Register Analog-to-digital converter (SAR ADC), the input signal vip samples and holds the analog input signal. It may be a single signal, and the input signal vin may be a signal obtained by converting a digital signal provided from a successive approximation logic circuit into an analog signal.

Here, when the difference between the voltage levels of the input signals vip and vin is small, the comparator 20 may not be able to determine which is greater within a preset time. In this case, the comparator 20 has metastability, and as the difference between the voltage levels of the input signals vip and vin is smaller, the time with metastability may be longer. Hereinafter, the metastability of the comparator will be described in more detail.

3 is a diagram for explaining metastability of a comparator.

Referring to FIG. 3 , the comparator 20 may compare voltage levels of the received input signals vip and vin, and may represent them as differential output signals vo1 and vo2.

Here, when the comparator 20 determines that either one of the input signals vip and vin is greater, the comparator 20 applies any one of the differential output signals vo1 and vo2 (eg, vo1) to the first voltage level. It can be controlled to reach the second voltage level, and the other (eg, vo2 ) can be controlled to reach the second voltage level. Here, the first voltage level and the second voltage level may be preset voltage levels, and the first voltage level or the second voltage level may include a margin. In some embodiments, the first voltage level may be 1V, and the second voltage level may be 0V. According to an embodiment, the margin may be the detection voltage VREF, and may be 0.25V.

Here, the comparator 20 may have to control each of the differential output signals vo1 and vo2 to reach either the first voltage level or the second voltage level within a preset time. According to an embodiment, the preset time may be a set time to satisfy functional conditions required by the semiconductor circuit in which the comparator 20 is used. According to an embodiment, the semiconductor circuit may be a Successive Approximation Register Analog-to-Digital Converter (SAR ADC), and according to another embodiment, it may be an image sensor. , the scope of the present invention is not limited thereto. According to an embodiment, when the semiconductor circuit is a SAR ADC, the preset time may be a half cycle of the driving clock input to the comparator 20 . In this case, the driving clock may be an asynchronous clock that is not synchronized with an external clock driving the SAR ADC.

That is, each of the differential output signals vo1 and vo2 should reach the first voltage level and the second voltage level within the preset time. According to an embodiment, when each of the differential output signals vo1 and vo2 does not reach the first voltage level and the second voltage level having the margin, it may be determined that the comparator 20 has metastability. have. According to another embodiment, when any one of the differential output signals vo1 and vo2 does not reach the first voltage level having the margin, it may be determined that the comparator 20 has metastability. According to another embodiment, when any one of the differential output signals vo1 and vo2 does not reach the second voltage level having the margin, it may be determined that the comparator 20 has meta-stability.

Referring back to FIGS. 1 and 2 , the metastability detection circuit 10 generates a driving voltage for each of the differential output signals when the differential output signals fall below the detection voltage ( S20 ). Then, the metastability detection circuit 10 generates a metastability detection signal based on the driving voltage (S30).

Here, when each of the differential output signals vo1 and vo2 falls below the detection voltage VREF, any one of the differential output signals vo1 and vo2 does not reach the first voltage level having the margin. It can be seen as a case in which the comparator 20 cannot be regarded as having metastability. According to the exemplary embodiment, when each of the differential output signals vo1 and vo2 goes down below the detection voltage VREF, it can be regarded as the time when the comparator 20 has metastability, and the differential output signals vo1 and vo2 ), when any one of them rises above the detection voltage VREF, it may be viewed as a time when the comparator 20 no longer has metastability.

Here, the metastability detection signal MD may be a signal that is continuously activated from a point in time when the comparator 20 has metastability until a point in time when the comparator 20 no longer has metastability. According to an embodiment, the metastability detection signal MD may be a digital signal, and in this case, the metastability detection signal MD may be generated as an inverted signal.

Hereinafter, a process of generating a metastability detection signal will be described in more detail with reference to specific embodiments of the metastability detection circuit 10 .

4A is a block diagram illustrating a metastability detection circuit of a comparator according to an embodiment of the present invention, and FIG. 4B is a circuit diagram of the metastability detection circuit of the comparator shown in FIG. 4A .

2, 4A, and 4B , the metastability detection circuit 10 may include a driving voltage generator 100 and a metastability detector 200 . In addition, the driving voltage generator 100 may include a resistor R1 and a capacitor Cx as the PMOS transistors P11 and P12 and other elements, and the metastability detector 200 may include a NAND gate. have.

Here, the PMOS transistor P11 may be connected between the first node N1 and the first power voltage VDD. The first resistor R1 and the first capacitor Cx may be connected between the first node N1 and the ground node, and the PMOS transistor P11 is turned on so that the first node N1 and the power supply voltage VDD are connected. When connected, it may contribute to the determination of the voltage level of the first node N1 based on a preset time constant .

Here, the PMOS transistor P12 is driven using the differential output signal vo2 as a gate voltage, and may be connected between the second node N2 and the first power voltage VDD. The second resistor R1 and the second capacitor Cx may be connected between the second node N2 and the ground node, and the PMOS P12 is turned on to connect the second node N2 and the power supply voltage VDD. In this case, it may contribute to the determination of the voltage level of the second node N2 based on the preset time constant .

Here, the PMOS transistor P11 may be driven by using the differential output signal vo1 as a gate voltage, and the PMOS transistor P12 may be driven by using the differential output signal vo2 as a gate voltage. According to an embodiment, in each of the PMOS transistors P11 and P12 , the voltage level of each of the differential output signals vo1 and vo2 is a power supply voltage VDD and a threshold voltage of each of the PMOS transistors P11 and P12 . voltage), it can be turned on when it goes below the difference. In this case, the timing at which each of the PMOS transistors P11 and P12 is turned on may be when the voltage level of each of the differential output signals vo1 and vo2 falls below the detection voltage VREF.

Here, when all of the PMOS transistors P11 and P12 are turned on, the first current I1 and the second current flowing from the power supply voltage VDD to the first node N1 and the second node N2, respectively I2), the voltage levels vsft1 and vsft2 of the first node N1 and the second node N2 may each represent a logic high. In this case, the magnitudes of the first current I1 and the second current I2 may be determined based on the channel width W and the channel length L of each of the PMOS transistors P11 and P12 .

In this case, the metastability detection unit 200 uses the voltage levels vsft1 and vsft2 of the first node N1 and the second node N2 as input signals, and converts the metastability detection signal MD to the inverted signal ( /MD). According to an embodiment, the metastability detection unit 200 may include a NAND-gate, in which case the voltage levels vsft1 and vsft2 of the first node N1 and the second node N2 are respectively the NAND-gates. It can be the input signal of the gate.

5A is a block diagram illustrating a metastability detection circuit of a comparator according to another embodiment of the present invention, and FIG. 5B is a circuit diagram of the metastability detection circuit of the comparator shown in FIG. 5A.

4A, 4B, 5A, and 5B , the metastability detection circuit 10a illustrated in FIG. 5A may include a driving voltage generator 100a and a metastability detector 200 . Here, the driving voltage unit 100a illustrated in FIG. 5A may further include a reset signal /ckc, unlike the driving voltage unit 100 illustrated in FIG. 4A . Components having the same reference numerals in FIGS. 4A, 4B, 5A, and 5B perform the same functions, and thus, redundant descriptions will be omitted below.

According to an embodiment, the reset signal /ckc may be an inverted signal /ckc of the driving clock ckc supplied to the comparator 20 . That is, the driving voltage generator 100a operates the first node of the driving voltage generator 100a during a time when the comparator 20 is deactivated (ie, when the voltage level of the driving clock ckc is at a logic low level). The voltage levels of the (N1) and the second node (N2) may be reset to the ground voltage. In this case, unlike the driving voltage generator 100 , the driving voltage generator 100a may include NMOS transistors N11 and N12 instead of the resistor R1 . Here, the NMOS transistors N11 and N12 may be driven using the reset signal /ckc as a gate voltage.

According to an embodiment, the capacitor Cp included in the driving voltage generator 100a may perform the same function as the capacitor Cx included in the driving voltage generator 100 , but this may include the PMOS transistors P11, P12) can also be implemented as a parasitic capacitor.

6A is a block diagram illustrating a metastability detection circuit of a comparator according to another embodiment of the present invention, and FIG. 6B is a circuit diagram of the metastability detection circuit of the comparator shown in FIG. 6A .

5A, 5B, 6A, and 6B , the metastability detection circuit 10b illustrated in FIG. 6A may include a driving voltage generator 100b and a metastability detector 200 . Here, the driving voltage unit 100b illustrated in FIG. 6A may include a reset signal /ckmd instead of the reset signal /ckc, unlike the driving voltage unit 100a illustrated in FIG. 5A . Components having the same reference numerals in FIGS. 5A, 5B, 6A, and 6B perform the same functions, and thus, redundant descriptions are omitted below.

According to an embodiment, the reset signal /ckmd is an inverted signal (ckmd) obtained by AND-gating the metastability detection signal MD generated by the metastability detection unit 200 and the driving clock ckc of the comparator. /ckmd). In this case, the driving voltage generator 100b is a time during which the comparator 20 is deactivated, and during a time during which the metastability detection signal MD is output, the first node N1 and the second node N1 of the driving voltage generator 100b The voltage level of the node N2 may be reset to the ground voltage. In this case, the driving voltage generator 100b may further include an OR gate, unlike the driving voltage generator 100a . In this case, the OR gate may be driven using the metastability detection signal MD and the driving clock ckc of the comparator as a gate voltage.

As described above, the metastability detection circuit of the comparator according to the embodiments of the present invention is implemented as a simple circuit to efficiently detect the metastability of the comparator. Accordingly, the metastability detection circuit of the comparator according to the embodiments of the present invention occupies a small space and can reduce power consumption. Furthermore, the method and detection circuit for metastability of a comparator according to embodiments of the present invention can quickly determine whether the comparator is metastability.

7 is a diagram illustrating an image sensor having an analog-to-digital converter including a metastability detection circuit of a comparator according to embodiments of the present invention.

Referring to FIG. 7 , the image sensor 1000 includes an active pixel array 1010 , an analog-to-digital converting circuit 1020 , a voltage generation circuit 1030 , a vertical scan circuit 1040 , a horizontal scan circuit 1050 , and a timing It may include a control circuit 1060 , an amplification circuit 1070 , and a digital signal processing circuit 1080 . In this case, the image sensor 1000 includes analog-to-digital converters 1022 as many as the number of column lines connected to the active pixel array 1010 in the analog-to-digital converting circuit 1020 , and to the active pixel array 1010 . The connected column lines may be respectively connected to the analog-to-digital converters 1022 . That is, the image sensor 1000 may employ a column analog-to-digital conversion method.

The active pixel array 1010 may include a plurality of unit pixels (not shown). These unit pixels may be arranged in a matrix form in the active pixel array 1010 , and may each include a photodiode and a signal generating circuit. In this case, the unit pixels may be classified into a 3-transistor structure, a 4-transistor structure, a 5-transistor structure, etc. according to the number of transistors included in the signal generating circuit. In the active pixel array 1010 , row lines may be wired for each row, and column lines may be wired for each column. For example, when the active pixel array 1010 includes m*n unit pixels, n row lines and m column lines may be wired to the active pixel array 1010 . A row address and a row scan of the active pixel array 1010 may be controlled through row lines by the vertical scan circuit 1040 , and a column address of the active pixel array 1010 may be controlled by the vertical scan circuit 1040 . ) and column scan may be controlled through row lines by the horizontal scan circuit 1050 . According to an exemplary embodiment, when the image sensor 1000 employs a Bayer pattern technology, unit pixels in the active pixel array 1010 may include red light (RED), green light (GREEN), and blue light (BLUE), respectively. It may be arranged to receive magenta light (MAGENTA), yellow light (YELLOW), and cyan light (CYAN). According to an exemplary embodiment, when the image sensor 1000 employs an Auto Dark Level Compensation (ADLC) technology, an optical block is formed around the active pixel array 1010 to prevent light from entering the unit pixels. A black pixel array (not shown) may be disposed.

The analog-to-digital converting circuit 1020 includes a plurality of analog-to-digital converters 1022 , and each analog-to-digital converter 1022 has a pixel output voltage (POS) output from a unit pixel of the active pixel array 1010 . can be converted into a digital signal (DS). In one embodiment, the analog-to-digital converter 1022 is a ramp voltage generator that generates a ramp voltage RV, the structure is changed according to the auto zero mode and the comparison mode, and performs an offset removal operation in the auto zero mode, and compares A dual-mode comparator that compares the pixel output voltage POS and the ramp voltage RAMP in the mode to generate a comparison result signal, and a digital signal corresponding to the pixel output voltage POS in a clock signal counting method based on the comparison result signal (DS) may include a digital signal generator for generating. According to an embodiment, the analog-to-digital converter 1022 may further include a correlated double sampler that performs a correlated double sampling operation on the pixel output voltage POS. In this case, the dual-mode comparator includes a target voltage input unit that generates a first current flowing through the first path and a second current flowing through the second path based on the pixel output voltage POS and the ramp voltage RAMP; A current mirror unit that performs a current mirror operation on two paths and outputs a second comparison voltage through an output terminal, a bias unit that generates a bias voltage corresponding to the sum of the first current and the second current, and an auto-zero mode and a mode switching unit that determines whether the current mirror unit has a first structure and determines that the current mirror unit has a second structure in the comparison mode. Accordingly, the dual-mode comparator may have a structure capable of performing an auto-zero operation in the auto-zero mode, and have a structure in which the current consumed before and after the determination time, ie, the bias current, can be kept constant in the comparison mode. However, since this has been described above, the overlapping description will be omitted. Meanwhile, the analog-to-digital converting circuit 1020 may perform a signal conversion operation based on the control signals CTL2 output from the timing control circuit 1060 , and this signal conversion operation is performed by the vertical scanning circuit 1040 The row lines of the active pixel array 1010 may be selected every period, that is, every horizontal scan period.

The voltage generating circuit 1030 may generate a plurality of voltages (eg, a ramp voltage, etc.) used in the analog-to-digital converting circuit 1022 and respectively supply the generated voltages to the analog-to-digital converter 1022 . The vertical scan circuit 1040 may receive the control signals CTL1 from the timing control circuit 1060 to control row addresses and row scans of the active pixel array 1010 . That is, the vertical scan circuit 1040 may supply a signal for activating a corresponding row line in order to select a corresponding row line from among the row lines of the active pixel array 1010 . In an embodiment, the vertical scan circuit 1040 may include a vertical decoder for selecting a row line in the active pixel array 1010 and a vertical driver for supplying a signal for activating the selected row line. The horizontal scan circuit 1050 may receive the control signals CTL4 from the timing control circuit 1060 to control the column address and column scan of the active pixel array 1010 . That is, the horizontal scanning circuit 1050 outputs the digital signal DS output from the analog-to-digital converting circuit 1020 to the digital signal processing circuit 1080 through the horizontal transmission line HTL and the amplifier circuit 1070 . can For example, the horizontal scan circuit 1050 outputs the horizontal scan control signal HSC to the analog-to-digital converting circuit 1020 , thereby sequentially converting the analog-to-digital converters 1022 in the analog-to-digital converting circuit 1020 . You can choose. In one embodiment, the horizontal scan circuit 1050 transmits the output of the selected analog-to-digital converter 1022 and a horizontal decoder that selects the analog-to-digital converter 1022 in the analog-to-digital converting circuit 1020 to a horizontal transmission line (HTL). It may include a horizontal driver leading to Meanwhile, the horizontal transmission line HTL may have a bit width for outputting the digital signal DS.

The timing control circuit 1060 controls the vertical scanning circuit 1040, the analog-to-digital converting circuit 1020, the ramp voltage generating circuit 1030, the horizontal scanning circuit 1050, and the like based on the master clock signal (not shown). can do. That is, the timing control circuit 1060 includes a clock signal required for the operation of the vertical scanning circuit 1040 , the analog-to-digital converting circuit 1020 , the ramp voltage generating circuit 1030 , and the horizontal scanning circuit 1050 , and timing control. Control signals CTL1 , CTL2 , CTL3 , CTL4 such as signals may be supplied. In one embodiment, the timing control circuit 1060 may include a logic control circuit, a phase locked loop circuit, a timing control circuit, a communication interface circuit, and the like. The amplifying circuit 1070 may amplify the digital signal DS output from the analog-to-digital converters 1022 in the analog-to-digital converting circuit 1020 and output it to the digital signal processing circuit 1080 . Although one amplifying circuit 1070 is illustrated in FIG. 14 , a plurality of amplifying circuits 1070 may be provided. The digital signal processing circuit 1080 is output from the analog-to-digital converters 1022 in the digital converting circuit 1020 and passed through the horizontal transmission line (HTL) and the amplification circuit 1070. Based on the digital signal DS, the image signal ( IMG) can be created. According to an embodiment, the digital signal processing circuit 1080 may include a sense circuit, a subtraction circuit, an output circuit, and the like. Thereafter, the image signal IMG may be implemented on a display such as a liquid crystal display (LCD) device, an organic light emitting diode (OLED) display device, or the like.

As described above, the metastability detection circuit of the comparator according to the embodiments of the present invention may be implemented as a simple circuit to efficiently detect the metastability of the comparator. Accordingly, the metastability detection circuit of the comparator according to the embodiments of the present invention occupies a small space and can reduce power consumption. Furthermore, the method and detection circuit for metastability of a comparator according to embodiments of the present invention can quickly determine whether the comparator is metastability.

Those skilled in the art will understand that the embodiments of the present invention may be implemented in the form of a system, a method, a product including a computer readable program code stored in a computer readable medium, and the like. The computer readable program code may be provided to the processors of various computers or other data processing devices. The computer-readable medium may be a computer-readable signal medium or a computer-readable recording medium. The computer-readable recording medium may be any tangible medium that can store or include a program in or connected to an instruction execution system, equipment, or device.

Embodiments of the present invention may be usefully used in a semiconductor manufacturing process. In particular, embodiments of the present invention include a memory card, a solid state drive (SSD), an embedded multimedia card (eMMC), a universal flash storage (UFS), a computer, a notebook computer ( laptop), cellular phone, smart phone, MP3 player, Personal Digital Assistants (PDA), Portable Multimedia Player (PMP), digital TV, digital camera, portable game console ), navigation (navigation) devices, wearable (wearable) devices, IoT (internet of things;) devices, IoE (internet of everything:) devices, e-books (e-books), VR (virtual reality) devices, AR ( It can be more usefully applied to the semiconductor manufacturing process required for electronic devices such as augmented reality) devices.

Although the present invention has been described with reference to preferred embodiments, those skilled in the art can variously modify and change the present invention without departing from the spirit and scope of the present invention as set forth in the following claims. you will understand that you can

Claims (10)

A metastability detection circuit for a differential output comparator, comprising:
a driving voltage generator for receiving differential output signals from the differential output comparator and generating a driving voltage for each of the differential output signals when the respective differential output signals fall below a detection voltage;
and a metastability detection unit configured to generate a metastability detection signal based on the driving voltage. According to claim 1,
The driving voltage generator includes first and second PMOS transistors, first and second NMOS transistors, and first and second capacitors,
The first PMOS transistor is connected between a power supply voltage and a first node, the first NMOS transistor is connected between the first node and a ground node, and the first capacitor is connected between the first node and the ground node. connected,
The second PMOS transistor is connected between the power supply voltage and a second node, the second NMOS transistor is connected between the second node and the ground node, and the second capacitor is connected between the second node and the ground node. A metastability detection circuit of a comparator, characterized in that connected between. 3. The method of claim 2,
The metastability detection circuit of a comparator, wherein each of the first and second PMOS transistors uses any one of the differential output signals as a gate voltage. 3. The method of claim 2,
The metastability detection unit includes a NAND-gate,
and the input signal of the NAND-gate is voltage levels of the first node and the second node. According to claim 1,
The driving voltage generator is reset while the comparator is deactivated. 3. The method of claim 2,
The magnitude of the current flowing from the power supply voltage to each of the first node and the second node is determined based on channel widths and channel lengths of the first PMOS transistor and the second PMOS transistor. Stability detection circuit. A method for detecting metastability of a differential output comparator, comprising:
receiving differential output signals from the differential output comparator;
generating a driving voltage for each of the differential output signals when the respective differential output signals fall below a detection voltage;
and generating a metastability detection signal based on the driving voltage. 8. The method of claim 7,
The driving voltage generator includes first and second PMOS transistors, first and second NMOS transistors, and first and second capacitors,
The first PMOS transistor is connected between a power supply voltage and a first node, the first NMOS transistor is connected between the first node and a ground node, and the first capacitor is connected between the first node and the ground node. connected,
The second PMOS transistor is connected between the power supply voltage and a second node, the second NMOS transistor is connected between the second node and the ground node, and the second capacitor is connected between the second node and the ground node. Method for detecting metastability of a comparator, characterized in that it is connected between. 9. The method of claim 8,
The metastability detection unit includes a NAND-gate,
and the input signal of the NAND-gate is voltage levels of the first node and the second node. 9. The method of claim 8,
The magnitude of the current flowing from the power supply voltage to each of the first node and the second node is determined based on channel widths and channel lengths of the first PMOS transistor and the second PMOS transistor. Stability detection method.

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