KR20210088272A - Apparatus of expandable high density for performance acceleration devices and control method thereof - Google Patents

Abstract

Disclosed are a high-integrated expansion device for a performance acceleration device and a control method thereof. The high-integrated expansion device for the performance acceleration device according to one embodiment of the present invention comprises: one or more slots to mount the performance acceleration device; an external connector that connects to a server or another high-integrated expansion device; a switch device that controls the slot and the external connector; a control panel that controls the performance acceleration device; and a power supply device block that supplies a power supply to the performance acceleration device. Therefore, the present invention is capable of increasing the effectiveness of spatial costs.

Description

High-density expansion device for performance accelerator and its control method {APPARATUS OF EXPANDABLE HIGH DENSITY FOR PERFORMANCE ACCELERATION DEVICES AND CONTROL METHOD THEREOF}

The present invention relates to an expansion device for high integration of various performance accelerators such as GPU, GPGPU, FPGA and TPU, and a control method thereof, and extends a server system bus used for a computer peripheral device to the outside, and the outside of the server It is about a technology that can extend the system bus in

Unless otherwise indicated herein, the material described in this section is not prior art to the claims of this application, and inclusion in this section is not an admission that it is prior art.

Current computer systems require high-speed data analysis and processing according to the development of intelligent information processing.

Such intelligent information processing requires performing calculations more times than the processing performance of the CPU, which is a central processing unit, and therefore, a performance accelerator for processing high-speed calculations is used as a peripheral device.

Performance accelerators include GPGPU (General-Purpose Computing on Graphics Proseccing Unit), which is a graphic device-based (GPU, Graphics Processing Unit) vector arithmetic processing unit, and a dedicated co-processor (FPGA) device. Field Programmable Gate Array) is widely used.

Although the above-described performance accelerator provides high computational performance, the number of performance accelerators that can be accommodated at one time is limited due to limitations in the physical size and power capacity of the server.

In order to solve this problem, various types of performance accelerator systems have been developed. However, the existing performance accelerator systems still have limitations such as power consumption and the number of performance accelerators that can be accommodated according to physical specifications.

Korean Patent No. 10-0262677, registered on May 03, 2000 (Name: Expansion board with enable/disable expansion ROM for PCI bus computer)

SUMMARY OF THE INVENTION It is an object of the present invention to provide a highly integrated expansion device in which a plurality of performance accelerators are built on a unit basis.

Another object of the present invention is to provide scalability based on unit units through interconnection of one or more highly integrated expansion devices.

Another object of the present invention is to increase the independence and space cost efficiency of a highly integrated expansion device by embedding a separate power supply device.

In addition, it is not limited to the above-described objects, and it is obvious that other objects may be derived from the following description.

In order to achieve the above object, a high-density expansion device for a performance accelerator according to an embodiment of the present invention includes one or more slots for mounting the performance accelerator, an external connector for connecting to a server or other high-density expansion device, the slot and and a switch device for controlling an external connector, a control panel for controlling the performance accelerator, and a power supply block for supplying power to the performance accelerator.

In this case, the external connector is formed of two or more, and is connected to a server or other high-density expansion device to provide two or more uplinks capable of transmitting the PCI Express protocol.

At this time, the uplink includes an uplink A and an uplink B, and when one or more high-density expansion devices are extended and connected, the server using the uplink A and, by extending and connecting the uplink B and uplink A of another high-density expansion device, they may be connected in a daisy chain manner.

In this case, the switch device may provide one or more upstream connections for a host server or one or more high-density expansion devices, and may provide one or more downstream connections for a performance accelerator.

At this time, further comprising a system control block for controlling the operation of the high-integration expansion device, wherein the system control block, FPGA (Field Programmable Gate Array) for control, a communication port for external communication, and the setting of the switch device It may include memory for

In this case, the FPGA may control selection and connection of the memory for setting the shape of the switch device according to an input of the control panel.

In this case, the control panel includes a mechanical switch and an optical display device, and controls a shape, an operation mode setting, and a system reset of the highly integrated expansion device according to an input of the mechanical switch, and controls the switch through the optical display device Device connection status, power information, shape information, reset information, etc. can be displayed.

In this case, the power supply block may be configured to receive external AC power, convert it into DC power, and have redundancy of 1+1.

In addition, in order to achieve the above object, a control method of a high-integration expansion device for a performance accelerator according to an embodiment of the present invention includes the steps of checking a connection state of an external connector included in the high-integration expansion device, the high-integration expansion device setting the operation of the performance accelerator included in the method; setting a single connection mode or an extended connection mode based on the connection state; and controlling the highly integrated expansion device according to the set mode.

In this case, the single connection mode is a first single connection mode in which one server is connected using one external connector of the high-integration expansion device, and one server is connected using two external connectors of the high-integration expansion device. It may include a second single connection mode and a third single connection mode for connecting to two servers using the two external connectors of the high-integration expansion device.

At this time, in the expansion connection mode, a first external connector of the high-integration expansion device is used to connect to one server, and a second external connector is used to connect to another high-integration expansion device, but the other high-integration expansion device is another It can be connected repeatedly in a daisy chain format with a high-density expansion device.

According to the present invention, it is possible to provide a highly integrated expansion device in which a plurality of performance accelerators are built on a unit basis.

Also, according to the present invention, it is possible to provide unit-based scalability through interconnection of one or more highly integrated expansion devices.

In addition, according to the present invention, it is possible to increase the independence and space cost efficiency of the high-integration expansion device by embedding a separate power supply device.

In addition, according to the present invention, one or more high-density expansion devices and one or more servers can be connected, and the CPU of the server and one or more performance accelerators can be selectively connected according to efficiency.

Effects of the present embodiments are not limited to the above-mentioned effects, and other effects not mentioned will be clearly understood by those skilled in the art from the description of the claims.

1 is a state diagram of a high-integration expansion device for a performance accelerator according to an embodiment of the present invention.
2, 3 and 4 are block diagrams of a highly integrated expansion device for a performance accelerator according to an embodiment of the present invention.
5A, 5B and 5C are diagrams illustrating the use of a single connection mode according to an embodiment of the present invention.
6 is a diagram illustrating the use of an extended connection mode according to an embodiment of the present invention.
7 is a flowchart of a control method of a high-integration expansion device for a performance accelerator according to an embodiment of the present invention.
8 is a diagram illustrating a computer system according to an embodiment of the present invention.

The present invention will be described in detail with reference to the accompanying drawings as follows. Here, repeated descriptions, well-known functions that may unnecessarily obscure the gist of the present invention, and detailed descriptions of configurations will be omitted. The embodiments of the present invention are provided in order to more completely explain the present invention to those of ordinary skill in the art. Accordingly, the shapes and sizes of elements in the drawings may be exaggerated for clearer description.

The present invention can solve the following problems that may occur in the expansion of the performance accelerator as described above.

The first problem is that there is a limitation in expansion due to the fixed backplane structure of the rack-mount unit.

The existing performance accelerator system unit integrates 8 to 16 performance accelerators in 3U (Rack unit) or 4U height based on the general standard rack system specification (standard 19" or 21"). .

These unit performance accelerator systems are connected to the server based on the unit unit of the rack-mount type, and do not provide connectivity scalability beyond the unit unit.

In particular, the existing rack-mount unit provides a connection between a plurality of performance accelerators and the host in the form of a shared backplane, but does not provide the connection between the performance accelerators and the built-in rack-mount unit. does not

In general, it is known that there is a decrease in performance efficiency due to data sharing and communication when one server extends more than several performance accelerators. However, in the case of applications where locality of data is guaranteed, such as recent intelligent information processing, many It is possible to expand the performance linearly even by using a numerical performance accelerator.

In such intelligent information processing, it is important to provide the scalability of the performance accelerator more than the rack-mount unit, but the existing performance accelerator system has a problem in that it cannot provide the scalability more than the rack-mount unit.

The second problem is that there are space and cost-effective limitations due to the sharing of the power supply within the rack-mount unit.

The existing performance accelerator system unit can use 8 to 16 level performance accelerators, and for this purpose, a high-capacity power supply is built-in.

All (8 to 16) performance accelerators in the unit are powered from a single high-capacity power supply.

If the user does not need multiple performance accelerators, an idle space is created inside the unit unit, and accordingly, a power supply with a capacity greater than necessary is used. Also, when the performance accelerator system is used, the performance used Regardless of the number of accelerators, rack-mount unit units using the maximum number of performance accelerators must be used, resulting in inefficiency in terms of cost.

The third problem is that the complexity of air conditioning control increases due to the high integration of performance accelerators in the rack-mount unit.

In the existing performance accelerator system rack mount unit, in order to obtain the maximum density within the standard rack system specification (10 to 16 units), the performance accelerator is arranged in two rows before and after.

Individual performance accelerators are high-heat devices that consume up to 250W of power, and the arrangement of the front and rear two rows can maximize the density of the rack-mount unit units, but Additional air inflow and control is required for temperature control.

Hereinafter, a preferred embodiment according to the present invention for solving the above-described problems will be described in detail with reference to the accompanying drawings.

1 is a state diagram of a high-integration expansion device for a performance accelerator according to an embodiment of the present invention.

First, the highly integrated expansion device 110 for the performance accelerator according to an embodiment of the present invention may mean the same as the unit unit of the high integration expansion type performance accelerator system.

Referring to FIG. 1 , a highly integrated expansion device 110 for a performance accelerator according to an embodiment of the present invention may be connected to a server 120 to extend the performance accelerator.

In addition, the highly integrated expansion device 110 may be formed as one unit, so that a plurality of high integration expansion devices 110 may be serially connected to one server 120 . The connection relationship between the server 120 and the plurality of highly integrated expansion devices 110 will be described later.

2, 3 and 4 are block diagrams of a highly integrated expansion device 110 for a performance accelerator according to an embodiment of the present invention.

Referring to FIG. 2 , a high-integration expansion device 110 for a performance accelerator according to an embodiment of the present invention includes one or more external connectors 210 , a PCI Express switch device 220 , and one for mounting the performance accelerator device. The above PCI Express slot 230, the control panel 240 for controlling and operating the high-integration expansion device 110, the system control block 250 for controlling the operation and shape of the high-integration expansion device 110, the high integration expansion device A fan 260 for air conditioning of 110 and a power supply block 270 for supplying total power to the highly integrated expansion device 110 may be included.

In this case, the high-integration expansion device 110 may have one row of performance accelerators disposed in the inner space, thereby increasing the air-conditioning control efficiency.

At this time, it is preferable that at least two external connectors 210 are formed for connection between the server and other high-density expansion devices 110 as will be described later, and the PCI Express slots 230 have at least 4 for securing expandability. It is preferable to form more than one.

3 and 4, two or more external connectors 330 are formed in the high-density expansion unit 110, and serve to transfer the PCI Express protocol for expansion connection with a host server or a plurality of high-density expansion devices. can be done

In addition, the external connector 330 may be formed to be connected to a cable assembly capable of transmitting the above-described PCI Express protocol, and uplink A (Uplink A, 331) and uplink B (Uplink A, 331) using each cable assembly Uplink B, 333) may provide an external connection.

At this time, the PCI Express switch device 310 may provide two or more upstreams for host server connection or expansion connection between a plurality of high-density expansion devices, and one or more performance accelerators 321, 323, 325, 327) can provide 4 or more downstream connections for mounting.

In this case, the performance accelerators 321 , 323 , 325 , and 327 may be connected using a physical slot according to the PCI Express standard.

At this time, the system control block 340 is a block for the operation and control of the high-integration expansion device 110, FPGA (Field Programmable Gate Array, 410) for control, and a communication port (Communication port, 420) for external communication. , one or more memory (ROM, 430) for setting the shape of the PCI Express switch device 310 and various devices inside the high-integration expansion device 110 and one or more temperature sensors 440 for detecting the internal temperature. have.

At this time, the FPGA 410 may operate based on the auxiliary power generated by the power supply block 370 , and according to the switch input of the control panel 350 , the shape of the PCI Express switch device 310 . It may be responsible for selecting and connecting a memory (ROM) 430 for setting, obtaining temperature information from the temperature sensor 440, controlling a fan, and controlling the communication port 420 for communication with an external host server.

In this case, the control panel 350 may include a mechanical switch and an optical display device, and through manipulation of the switch, the shape of the highly integrated expansion device, operation mode setting, and system reset can be performed, and the optical display device is It is possible to display the host connection state of the PCI Express switch device 310 in the high-integration expansion device 110 , the connection state of the performance accelerators 321 , 323 , 325 , 327 , power information, shape information, reset information, and the like.

At this time, the power supply block 370 may receive an external AC power source and generate a DC 12V main and auxiliary voltage, and through the power circuit inside the power supply block 370, a high-integration expansion device Any DC voltage can be generated.

In addition, the internal power supply of the power supply block 370 may be configured to have a redundancy of (1+1), thereby preventing malfunction of the high-integration expansion device 110 due to malfunction and damage of the individual power supply unit. can do.

5A, 5B and 5C are diagrams illustrating the use of a single connection mode according to an embodiment of the present invention.

5A, 5B and 5C , the highly integrated expansion device 520 for a performance accelerator according to an embodiment of the present invention may be connected to one or two servers 510, and the server 510. It is possible to provide a 1:2 or 1:4 connection between the CPU 511 and the internal performance accelerator.

FIG. 5A is a diagram illustrating an example of using a total of four performance accelerators using two uplinks (Uplink A and Uplink B).

A single server 510 and two uplinks (Uplink A, Uplink B) of the high-density expansion device 520 are connected using a shape to connect with the server through the host interface board 513 for connection with the server 510 can connect

FIG. 5B is an example of using four performance accelerators using one uplink (Uplink A or Uplink B). A 1:4 connection is provided between the CPU 511 of the server 510 and the performance accelerator. can do.

FIG. 5C is a shape in which two servers 510 are connected by using two uplinks (Uplink A and Uplink B), and is an exemplary diagram in which each server 510 utilizes two performance accelerators.

In this case, a 1:2 connection may be provided between the CPU 511 of the server 510 and the performance accelerator.

6 is a diagram illustrating the use of an extended connection mode according to an embodiment of the present invention.

Referring to FIG. 6 , as an example of using one or more high-density expansion devices 620 to show an extended connection structure, one high-density expansion device 620 is connected to the server 610 using uplink A (Uplink A). and may be connected to another adjacent high-integration expansion device 620 using uplink B.

In this case, the high-density expansion device 620 may be interconnected with another adjacent high-density expansion device 620 through uplinks (Uplink A, Uplink B), and may be connected in a daisy chain manner.

In this case, the server 610 may be connected to the server through the host interface board 613 for connection to the server 610 , and a plurality of performance accelerators included in the CPU 611 of the server 610 and each high-density expansion device 620 . connection can be provided.

Hereinafter, a highly integrated expansion device for a performance accelerator according to an embodiment of the present invention will be described with reference to FIGS. 1 to 6 .

1 to 6 , a high-integration expansion device for a performance accelerator according to an embodiment of the present invention includes one or more slots for mounting the performance accelerator, an external connector for connecting to a server or other high-density expansion device, the slot and a switch device for controlling an external connector, a control panel for controlling the performance accelerator, and a power supply block for supplying power to the performance accelerator.

In this case, the external connector is formed of two or more, and is connected to a server or other high-density expansion device to provide two or more uplinks capable of transmitting the PCI Express protocol.

At this time, the uplink includes an uplink A and an uplink B, and when one or more high-density expansion devices are extended and connected, the server using the uplink A and, the uplink B and the uplink A of another high-integration expansion device are used for extension connection, but may be connected in a daisy chain manner.

In this case, the switch device may provide one or more upstream connections for a host server or one or more high-density expansion devices, and may provide one or more downstream connections for a performance accelerator.

At this time, further comprising a system control block for controlling the operation of the high-integration expansion device, wherein the system control block, FPGA (Field Programmable Gate Array) for control, a communication port for external communication, and the setting of the switch device It may include memory for

In this case, the FPGA may control selection and connection of the memory for setting the shape of the switch device according to an input of the control panel.

In this case, the control panel includes a mechanical switch and an optical display device, and controls a shape, an operation mode setting, and a system reset of the highly integrated expansion device according to an input of the mechanical switch, and controls the switch through the optical display device Device connection status, power information, shape information, reset information, etc. can be displayed.

In this case, the power supply block may be configured to receive external AC power, convert it into DC power, and have redundancy of 1+1.

7 is a flowchart of a control method of a high-integration expansion device for a performance accelerator according to an embodiment of the present invention.

Referring to FIG. 7 , in the method of controlling the high-integration expansion device for the performance accelerator, first, a connection state of an external connector included in the high-integration expansion device is checked ( S710 ).

In addition, the control method of the high-integration expansion device for the performance accelerator sets the operation of the performance accelerator included in the high-density expansion device (S720).

In addition, the control method of the high-integration expansion device for the performance accelerator sets a single connection mode or an extended connection mode based on the connection state (S730).

In addition, the method of controlling the high-integration expansion device for the performance accelerator controls the high-integration expansion device according to the set mode (S740).

At this time, the server single connection mode is a first single connection mode in which one server is connected using one external connector of the high-density expansion device, and one server and one server using two external connectors of the high-density expansion device. It may include a second single connection mode for connecting and a third single connection mode for connecting to two servers using two external connectors of the high-integration expansion device.

In this case, in the expansion connection mode, a first external connector of the high-integration expansion device is used to connect to one server, and a second external connector is used to connect to another high-integration expansion device, but the other high-integration expansion device is connected to another server. It can be connected repeatedly in a daisy chain format with a high-density expansion device.

8 is a diagram illustrating a computer system according to an embodiment of the present invention.

Referring to FIG. 8 , an embodiment of the present invention may be implemented in a computer system such as a computer-readable recording medium. As shown in FIG. 8 , the computer system 800 includes one or more processors 810 , a memory 830 , a user interface input device 840 , and a user interface output device 850 that communicate with each other via a bus 820 . and storage 860 . In addition, computer system 800 may further include a network interface 870 coupled to network 880 . The processor 810 may be a central processing unit or a semiconductor device that executes processing instructions stored in the memory 830 or the storage 860 . The memory 830 and the storage 860 may be various types of volatile or non-volatile storage media. For example, the memory may include ROM 831 or RAM 832 .

Accordingly, the embodiment of the present invention may be implemented as a computer-implemented method or a non-transitory computer-readable medium in which computer-executable instructions are recorded. When the computer readable instructions are executed by a processor, the computer readable instructions may perform a method according to at least one aspect of the present invention.

As described above, the configuration and method of the embodiments described above are not limitedly applicable to the highly integrated expansion device for the performance accelerator and the control method thereof for the performance accelerator according to the present invention, but various modifications may be made to the embodiments. All or part of each embodiment may be selectively combined and configured.

110: high-density expansion device
120 : server
210: external connector
220: switch device
230 : PCI Express Slot
240: control panel
250: system control block
260: fan
270 : power unit block

Claims (1)

one or more slots for mounting a performance accelerator;
External connectors to connect to servers or other high-density expansion devices;
a switch device for controlling the slot and the external connector;
a control panel for controlling the performance accelerator; and
a power supply block for supplying power to the performance accelerator; A high-density expansion device for a performance accelerator that includes a.

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