KR20210086434A - Tunnel field effect transistor and ternary inverter including the same - Google Patents

Abstract

A tunnel field effect transistor comprises: a constant current forming layer; a source region and a drain region provided onto the constant current forming layer; a channel layer provided between the source region and the drain region; a gate electrode provided onto the channel layer; and a gate insulating film provided between the gate electrode and the channel layer, wherein the source region and the drain region individually have different conductivity types and the constant current forming layer forms a constant current between the drain region and the constant current forming layer.

Description

Tunnel field effect transistor and ternary inverter including same

The present disclosure relates to a tunnel field effect transistor and a ternary inverter.

Conventional binary logic-based digital systems have focused on increasing the bit density of information through miniaturization of CMOS devices in order to quickly process large amounts of data. However, with the recent integration to less than 30-nm, the bit density has been limited due to the increase in leakage current and power consumption due to the quantum tunneling effect. In order to overcome this bit density limitation, interest in ternary logic elements and circuits, which are one of multi-valued logics, is rapidly increasing. In particular, standard ternary inverters ( STI) has been actively developed. However, unlike the conventional binary inverter that uses two CMOS for one voltage source, the conventional techniques related to STI have a problem in that more voltage sources are required or a complex circuit configuration is required.

An object to be solved is to provide a tunnel field effect transistor having a constant current.

A problem to be solved is to provide a ternary inverter having a constant current.

However, the problem to be solved is not limited to the above disclosure.

In one aspect, the constant current forming layer; a source region and a drain region provided on the constant current forming layer; a channel layer provided between the source region and the drain region; a gate electrode provided on the channel layer; and a gate insulating film provided between the gate electrode and the channel layer, wherein the source region and the drain region have different conductivity types, and the constant current forming layer passes a constant current between the drain region and the constant current forming layer. Forming a tunnel field effect transistor may be provided.

The constant current may be independent from a gate voltage applied to the gate electrode.

The constant current forming layer and the source region may have a first conductivity type, and the drain electrode may have a second conductivity type.

A doping concentration of the constant current forming layer may be higher than a doping concentration of the channel layer.

The doping concentration of the constant current forming layer may be ^{3 X 10 18} cm ^{-3 or more.}

An electric field is formed between the drain region and the constant current forming layer, and the strength of the electric field ^{may be 10 6} V/cm or more.

The constant current forming layer may be disposed adjacent to the drain region and electrically connected to the drain region.

The constant current forming layer may extend to a region adjacent to the source region.

In one aspect, the fin structure extending in the first direction; a gate electrode extending in a second direction crossing the first direction; and a gate insulating layer provided between the fin structure and the gate electrode, wherein the fin structure includes a constant current forming layer provided under the fin structure, and a source region and a drain region provided on the constant current forming layer and the source region and the drain region each have different conductivity types, and the constant current forming layer may be provided with a tunnel field effect transistor that forms a constant current between the drain region and the constant current forming layer.

The fin structure may overlap the gate electrode along the second direction.

The constant current may be independent from a gate voltage applied to the gate electrode.

The constant current forming layer and the source region may have a first conductivity type, and the drain electrode may have a second conductivity type.

The fin structure may further include a channel layer provided between the source region and the drain region, wherein a doping concentration of the constant current forming layer may be higher than a doping concentration of the channel layer.

The doping concentration of the constant current forming layer may be ^{3 X 10 18} cm ^{-3 or more.}

An electric field is formed between the drain region and the constant current forming layer, and the strength of the electric field ^{may be 10 6} V/cm or more.

The constant current forming layer may be disposed adjacent to the drain region and electrically connected to the drain region.

The constant current forming layer may extend in the first direction and overlap the source region and the drain region in a third direction crossing the first direction and the second direction.

In one aspect, a first constant current forming layer and a second constant current forming layer respectively provided on the first well region and the second well region, the first well region and the second well region, and on the first constant current forming layer A first source region, a first channel layer, and a first drain region, a second source region provided on the second constant current forming layer, a second channel layer, and the second drain region, the first channel layer and the second a first gate electrode and a second gate electrode respectively provided on the second channel layer, wherein the first source region and the first drain region have different conductivity types, respectively, the second source region and the second gate electrode The two drain regions each have different conductivity types, the first constant current forming layer forms a first constant current between the first drain region and the first constant current forming layer, and the second constant current forming layer is formed with the second drain region and A ternary inverter for generating a second constant current may be provided between the second constant current forming layers.

The first constant current and the second constant current may be independent from gate voltages applied to the first gate electrode and the second gate electrode, respectively.

The first constant current forming layer and the first source region have a first conductivity type, the first drain electrode has a second conductivity type different from the first conductivity type, and the second constant current forming layer and the second source region may have the second conductivity type, and the second drain electrode may have the first conductivity type.

The present disclosure may provide a tunnel field effect transistor having a constant current.

The present disclosure may provide a ternary inverter having a constant current.

However, the effect of the invention is not limited to the above disclosure.

1 is a cross-sectional view of a tunnel field effect transistor according to exemplary embodiments.
2 illustrates gate voltage-drain current graphs of NMOS transistors according to the present disclosure and conventional NMOS transistors.
3 shows gate voltage-drain current graphs of the PMOS transistors of the present disclosure and the conventional PMOS transistors.
4 is a circuit diagram of a ternary inverter according to exemplary embodiments.
5 is a cross-sectional view of a ternary inverter according to an exemplary embodiment.
6 shows a gate voltage-drain current graph of ternary inverters and binary inverters of the present disclosure.
7 is a graph illustrating an input voltage (Vin)-output voltage (Vout) of the ternary inverter and the binary inverter of the present disclosure.
8 is a perspective view of a tunnel field effect transistor according to an exemplary embodiment.
9 is a cross-sectional view taken along lines I-I' and II-II' of FIG. 11 .
Fig. 10 is a perspective view of a ternary inverter according to an exemplary embodiment.
11 is a cross-sectional view of a tunnel field effect transistor according to exemplary embodiments.
12 is a perspective view of a transistor according to an exemplary embodiment.
13 is a cross-sectional view taken along lines II' and II-II' of FIG. 12 .

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. In the following drawings, the same reference numerals refer to the same components, and the size of each component in the drawings may be exaggerated for clarity and convenience of description. Meanwhile, the embodiments described below are merely exemplary, and various modifications are possible from these embodiments.

Hereinafter, what is described as "upper" or "upper" may include not only those directly above in contact, but also those above in non-contact.

The singular expression includes the plural expression unless the context clearly dictates otherwise. In addition, when a part "includes" a certain component, this means that other components may be further included, rather than excluding other components, unless otherwise stated.

In addition, terms such as “.. unit” described in the specification may mean a unit for processing at least one function or operation.

1 is a cross-sectional view of a tunnel field effect transistor according to exemplary embodiments.

Referring to FIG. 1 , a tunnel field effect transistor 10 may be provided. The tunnel field effect transistor 10 includes a substrate 100 , a constant current forming layer 210 , a pair of isolation regions ST, a source region 310 , a drain region 320 , a channel layer 220 , and a gate. It may include a structure 400 .

The substrate 100 may be a semiconductor substrate. For example, the substrate 100 may include silicon (Si). The substrate 100 may have a first conductivity type. For example, the first conductivity type may be n-type or p-type. When the conductivity type of the substrate 100 is n-type, the substrate 100 may include a group V element (eg, P or As) as an impurity. When the conductivity type of the substrate 100 is p-type, the substrate 100 may include a group III element (eg, B or In) as an impurity. Hereinafter, a region having an n-type conductivity may include a group V element (eg, P, As) as an impurity, and a region having a p-type conductivity may include a group III element (eg, B, In). It may contain impurities.

A constant current forming layer 210 may be provided on the substrate 100 . For example, the constant current forming layer 210 may include silicon (Si). The constant current forming layer 210 may have a first conductivity type. The doping concentration of the constant current forming layer 210 may be higher than that of the substrate 100 . For example, the doping concentration of the constant current forming layer 210 may be ^{3 X 10 18} cm ^{-3 or more.}

A source region 310 and a drain region 320 may be provided on the constant current forming layer 210 . The source region 310 and the drain region 320 may be spaced apart from each other in a first direction DR1 parallel to the top surface 100u of the substrate 100 . The source region 310 may have a first conductivity type. The doping concentration of the source region 310 may be higher than that of the constant current forming layer 210 . The drain region 320 may have a second conductivity type different from the first conductivity type. For example, when the first conductivity type is n-type, the second conductivity type may be p-type. Conversely, when the first conductivity type is p-type, the second conductivity type may be n-type.

The source region 310 and the drain region 320 may be electrically connected to the constant current forming layer 210 . For example, the source region 310 and the drain region 320 may directly contact the constant current forming layer 210 . An electric field may be formed between the constant current forming layer 210 and the drain region 320 . For example, the strength of the electric field ^{may be 10 6} V/cm or more.

A channel layer 220 may be provided on the constant current forming layer 210 . The channel layer 220 may be provided between the source region 310 and the drain region 320 . The channel layer 220 may include substantially the same material as the substrate 100 . For example, the channel layer 220 may include silicon (Si). The channel layer 220 may have a first conductivity type. The doping concentration of the channel layer 220 may be substantially the same as that of the substrate 100 .

A pair of device isolation regions ST may be provided on the constant current forming layer 210 . The pair of isolation regions ST may be spaced apart from each other in the first direction DR1 . The pair of isolation regions ST may extend in a second direction DR2 perpendicular to the top surface 100u of the substrate 100 . For example, a thickness of the pair of device isolation regions ST in the second direction DR2 may be greater than a thickness of the channel layer 220 in the second direction DR2 . The pair of isolation regions ST may include an electrically insulating material. For example, the pair of isolation regions ST may include SiO ₂ or a high-k material (eg, SiON, HfO ₂ , ZrO ₂ ).

A gate structure 400 may be provided on the channel layer 220 . When viewed along the second direction DR2 , the gate structure 400 may be provided between the source region 310 and the drain region 320 . In one example, the gate structure 400 may partially overlap the source region 310 and the drain region 320 in the second direction DR2 . The gate structure 400 may include a gate insulating layer 410 , a gate electrode 420 , and a pair of spacers 430 .

The gate electrode 420 may include an electrically conductive material. For example, the gate electrode 420 may include a doped semiconductor material, a metal, an alloy, or a combination thereof. For example, the gate electrode 420 may include doped polysilicon, tungsten (W), titanium nitride (TiN), or a combination thereof.

A gate insulating layer 410 may be provided between the gate electrode 420 and the channel layer 220 . The gate insulating layer 410 may electrically insulate the gate electrode 420 and the channel layer 220 from each other. For example, the gate insulating layer 410 may directly contact the upper surface of the channel layer 220 .

The gate insulating layer 410 may be provided between the gate electrode 420 and the channel layer 220 . For example, the gate insulating layer 410 may directly contact the channel layer 220 and the gate electrode 420 . The gate insulating layer 410 may have a material capable of realizing a desired capacitance. The gate insulating layer 410 may include a material having a high dielectric constant. The high dielectric constant may mean a dielectric constant higher than that of silicon oxide. In one embodiment, the gate insulating layer 410 is selected from Ca, Sr, Ba, Sc, Y, La, Ti, Hf, Zr, Nb, Ta, Ce, Pr, Nd, Gd, Dy, Yb, and Lu. A metal oxide comprising at least one metal may be used. For example, the gate insulating layer 410 may include HfO ₂ , ZrO ₂ , CeO ₂ , La ₂ O ₃ , Ta ₂ O ₃ , or TiO ₂ . The gate insulating layer 410 may have a single-layer structure or a multi-layer structure.

In one example, the threshold voltage of the tunnel field effect transistor 10 may be adjusted by a doping concentration of the substrate 100 and/or a work function of the gate electrode 420 . For example, the work function of the gate electrode 420 may be controlled by the material of the gate electrode 420 or by an additional work function control layer (not shown). For example, an additional work function control layer may be interposed between the gate insulating layer 410 and the substrate 100 .

In the tunnel field effect transistor 10 , a channel may be formed by inter-band tunneling that occurs between the source region 310 and the channel layer 220 . The occurrence of the inter-band tunneling may be controlled by a gate voltage. A case in which inter-band tunneling occurs may be defined as a case in which the tunnel field effect transistor 10 has an on state. A case in which inter-band tunneling does not occur may be defined as a case in which the tunnel field effect transistor 10 has an off state. When the tunnel field effect transistor 10 is an NMOS transistor, the conductivity type of the drain region 320 may be n-type. When the tunnel field effect transistor 10 is a PMOS transistor, the conductivity type of the drain region 320 may be p-type.

The constant current forming layer 210 may form a constant current between the drain region 320 and the constant current forming layer 210 . The constant current may be a band-to-band tunneling (BTBT) current flowing between the drain region 320 and the constant current forming layer 210 . The constant current may be independent from the gate voltage applied to the gate electrode 420 . That is, the constant current may flow regardless of the gate voltage. When the tunnel field effect transistor 10 is an NMOS transistor, a constant current may flow from the drain region 320 to the substrate 100 through the constant current forming layer 210 . When the tunnel field effect transistor 10 is a PMOS transistor, a constant current may flow from the substrate 100 to the drain region 320 through the constant current forming layer 210 .

The present disclosure may provide a tunnel field effect transistor 10 in which a constant current is formed between the drain region 320 and the constant current forming layer 210 .

2 illustrates gate voltage-drain current graphs of NMOS transistors according to the present disclosure and conventional NMOS transistors.

2 , gate voltage-drain current graphs NGR1 and NGR2 of conventional NMOS transistors and gate voltage-drain current graphs NGR3, NGR4, and NGR5 of NMOS transistors according to the present disclosure are shown. .

The drain currents of the conventional NMOS transistors do not have a constant current component that flows regardless of the gate voltage.

The drain currents of the NMOS transistors of the present disclosure have a constant current component flowing regardless of the gate voltage. For example, even when the NMOS transistors of the present disclosure have an off state, a constant current flows through the NMOS transistors of the present disclosure.

3 shows gate voltage-drain current graphs of the PMOS transistors of the present disclosure and the conventional PMOS transistors.

Referring to FIG. 3 , gate voltage-drain current graphs PGR1 and PGR2 of conventional PMOS transistors and gate voltage-drain current graphs PGR3, PGR4, and PGR5 of PMOS transistors of the present disclosure are shown.

The drain currents of the conventional PMOS transistors do not have a constant current component that flows regardless of the gate voltage.

The drain currents of the PMOS transistors of the present disclosure have a constant current component that flows regardless of the gate voltage. For example, even when the PMOS transistors of the present disclosure have an off state, a constant current flows through the PMOS transistors of the present disclosure.

4 is a circuit diagram of a ternary inverter according to exemplary embodiments. For brevity of description, contents substantially the same as those described with reference to FIG. 1 may not be described.

Referring to FIG. 4 , a ternary inverter 20 including an NMOS transistor and a PMOS transistor may be provided. Each of the NMOS transistor and the PMOS transistor may be substantially the same as the tunnel field effect transistor 10 described with reference to FIG. 1 . The conductivity type of the substrate 100 , the constant current forming layer 210 , the channel layer 220 , and the source region 310 of the NMOS transistor may be p-type. The conductivity type of the drain region 320 of the NMOS transistor may be n-type. The conductivity type of the substrate 100 , the constant current forming layer 210 , the channel layer 220 , and the source region 310 of the PMOS transistor may be n-type. The conductivity type of the drain region 320 of the PMOS transistor may be p-type.

A ground voltage may be applied to the source and the substrate of the NMOS transistor. For brevity of explanation, it is assumed that the ground voltage is 0 volts (V) hereinafter. _{A driving voltage V DD} may be applied to the source and the substrate of the PMOS transistor. An input voltage Vin may be applied to each of the gate electrode of the NMOS transistor and the gate electrode of the PMOS transistor.

The drain of the NMOS transistor may be electrically connected to the drain of the PMOS transistor, and may have the same voltages, respectively. The voltage of the drain of the NMOS transistor and the drain of the PMOS transistor may be the output voltage Vout of the ternary inverter 20 .

A constant current may flow from the drain of the NMOS transistor to the substrate. A constant current may flow from the substrate of the PMOS transistor to the drain. The constant currents may be independent from the input voltage Vin.

In one example, the first input voltage may be applied to the gate electrode of the PMOS transistor and the gate electrode of the NMOS transistor such that the PMOS transistor has a constant current dominant over the channel current and the NMOS transistor has a channel current dominant over the constant current . In this case, the output voltage Vout of the ternary inverter 20 may be the first voltage.

In another example, the second input voltage may be applied to the gate electrode of the PMOS transistor and the gate electrode of the NMOS transistor such that the NMOS transistor has a constant current dominant over the channel current and the PMOS transistor has a channel current dominant over the constant current. . In this case, the output voltage of the ternary inverter 20 may be a second voltage greater than the first voltage.

In another example, the third input voltage may be applied to the gate electrode of the PMOS transistor and the gate electrode of the NMOS transistor so that each of the NMOS transistor and the PMOS transistor has a constant current dominant over the channel current. In this case, the output voltage of the ternary inverter 20 may be a third voltage between the first voltage and the second voltage.

The constant current flowing from the drain of the NMOS transistor to the substrate and the constant current flowing from the substrate to the drain of the PMOS transistor may flow regardless of gate voltages applied to the PMOS transistor and the gate electrodes of the NMOS transistor. The current in the ternary inverter 20 may flow from the substrate of the PMOS transistor to the substrate of the NMOS transistor through the drain of the PMOS transistor and the drain of the NMOS transistor. The driving voltage V _DD applied to the substrate of the PMOS transistor may be distributed between a resistance between the substrate of the PMOS transistor and a drain of the PMOS transistor and a resistance between the substrate of the NMOS transistor and a drain of the NMOS transistor. The output voltage Vout may be a voltage applied to a resistor between the substrate of the NMOS transistor and the drain of the NMOS transistor. The output voltage Vout may have a value between the _{driving voltage V DD and 0 V.}

The output voltage Vout is 0 V ('0' state), a voltage _{between the driving voltage V DD} and 0 V ('1' state), or a driving voltage V _DD ) (' depending on the input voltage Vin) 2' state). The present disclosure may provide the ternary inverter 20 having three states according to the input voltage Vin.

5 is a cross-sectional view of a ternary inverter according to an exemplary embodiment. For brevity of description, contents substantially the same as those described with reference to FIG. 1 may not be described.

Referring to FIG. 5 , a ternary inverter 30 may be provided. The ternary inverter 30 includes a substrate 1100 , a first well region 1102 , a second well region 1104 , a device isolation layer SL, a first constant current forming layer 1212 , a second constant current forming layer 1214 , and a second 1 channel layer 1222 , second channel layer 1224 , first source region 1312 , first drain region 1314 , second source region 1322 , second drain region 1324 , first gate structure 1402 , and a second gate structure 1404 .

The substrate 1100 may be a semiconductor substrate. For example, the substrate 1100 may include silicon (Si). The substrate 1100 may be an intrinsic semiconductor substrate or a semiconductor substrate having a conductivity type.

The first well region 1102 and the second well region 1104 may be provided on the substrate 1100 . The first well region 1102 and the second well region 1104 may be spaced apart from each other in a first direction DR1 parallel to the top surface 1100u of the substrate 1100 . The first well region 1102 may be a p-type region. The second well region 1104 may be an n-type region.

A device isolation layer SL exposing the first well region 1102 and the second well region 1104 may be provided on the substrate 1100 . The device isolation layer SL may include substantially the same material as the pair of device isolation regions ST described with reference to FIG. 1 .

A first constant current forming layer 1212 may be provided on the first well region 1102 . For example, the first constant current forming layer 1212 may be an epitaxial layer. For example, the first constant current forming layer 1212 may include silicon (Si). A conductivity type of the first constant current forming layer 1212 may be substantially the same as a conductivity type of the first well region 1102 . The conductivity type of the first constant current forming layer 1212 may be p-type. A doping concentration of the first constant current forming layer 1212 may be higher than a doping concentration of the first well region 1102 . For example, the doping concentration of the first constant current forming layer 1212 may be ^{3 X 10 18} cm ^{-3 or more.}

A second constant current forming layer 1214 may be provided on the second well region 1104 . For example, the second constant current forming layer 1214 may be an epitaxial layer. For example, the second constant current forming layer 1214 may include silicon (Si). A conductivity type of the second constant current forming layer 1214 may be substantially the same as a conductivity type of the second well region 1104 . The second constant current forming layer 1214 may have an n-type conductivity. A doping concentration of the second constant current forming layer 1214 may be higher than a doping concentration of the second well region 1104 . For example, the doping concentration of the second constant current forming layer 1214 may be ^{3 X 10 18} cm ^{-3 or more.}

A first channel layer 1222 may be provided on the first constant current forming layer 1212 . For example, the first channel layer 1222 may be an epitaxial layer. For example, the first channel layer 1222 may include silicon (Si). A conductivity type of the first channel layer 1222 may be substantially the same as a conductivity type of the first constant current forming layer 1212 . The conductivity type of the first channel layer 1222 may be p-type. A doping concentration of the first channel layer 1222 may be lower than a doping concentration of the first constant current forming layer 1212 . For example, the doping concentration of the first channel layer 1222 may be substantially the same as the doping concentration of the first well region 1102 .

A second channel layer 1224 may be provided on the second constant current forming layer 1214 . For example, the second channel layer 1224 may be an epitaxial layer. For example, the second channel layer 1224 may include silicon (Si). A conductivity type of the second channel layer 1224 may be substantially the same as a conductivity type of the second constant current forming layer 1214 . The second channel layer 1224 may have an n-type conductivity. A doping concentration of the second channel layer 1224 may be lower than a doping concentration of the second constant current forming layer 1214 . For example, the doping concentration of the second channel layer 1224 may be substantially the same as the doping concentration of the second well region 1104 .

A first source region 1312 and a first drain region 1314 may be provided on the first constant current forming layer 1212 . The first source region 1312 and the first drain region 1314 may be spaced apart from each other in the first direction DR1 with the first channel layer 1222 interposed therebetween. The first source region 1312 may have the same conductivity type as the first constant current forming layer 1212 . The conductivity type of the first source region 1312 may be p-type. A doping concentration of the first source region 1312 may be higher than a doping concentration of the first constant current forming layer 1212 . The first drain region 1314 may have a conductivity type different from that of the first constant current forming layer 1212 . The conductivity type of the first drain region 1314 may be n-type.

A second source region 1322 and a second drain region 1324 may be provided on the second constant current forming layer 1214 . The second source region 1322 and the second drain region 1324 may be spaced apart from each other in the first direction DR1 with the second channel layer 1224 interposed therebetween. The second source region 1322 may have the same conductivity type as the second constant current forming layer 1214 . The conductivity type of the second source region 1322 may be n-type. The doping concentration of the second source region 1322 may be higher than that of the second constant current forming layer 1214 . The second drain region 1324 may have a conductivity type different from that of the second constant current forming layer 1214 . The second drain region 1324 may have a p-type conductivity.

A first gate structure 1402 may be provided on the first channel layer 1222 . The first gate structure 1402 may include a first gate insulating layer 1412 , a first gate electrode 1422 , and a first pair of spacers 1432 . The first gate insulating film 1412 , the first gate electrode 1422 , and the first pair of spacers 1432 are the gate insulating film 410 , the gate electrode 420 , and the one described with reference to FIG. 1 , respectively. The pair of spacers 430 may be substantially the same.

A second gate structure 1404 may be provided on the second channel layer 1224 . The second gate structure 1404 may include a second gate insulating layer 1414 , a second gate electrode 1424 , and a second pair of spacers 1434 . The second gate insulating film 1414 , the second gate electrode 1424 , and the second pair of spacers 1434 are the gate insulating film 410 , the gate electrode 420 , and the one described with reference to FIG. 1 , respectively. The pair of spacers 430 may be substantially the same.

The present disclosure may provide a ternary inverter 30 . The first well region 1102 , the first constant current forming layer 1212 , the first channel layer 1222 , the first source region 1312 , the first drain region 1314 , and the first gate structure 1402 are N A MOS (NMOS) transistor can be configured. The second well region 1104 , the second constant current forming layer 1214 , the second channel layer 1224 , the second source region 1322 , the second drain region 1324 , and the second gate structure 1404 are A MOS (PMOS) transistor can be configured. A ground voltage may be applied to the first well region 1102 and the source of the NMOS transistor. A driving voltage may be applied to the second well region 1104 and the source of the PMOS transistor. The input voltage Vin may be applied to each of the first gate electrode 1432 of the NMOS transistor and the second gate electrode 1434 of the PMOS transistor.

The drain of the NMOS transistor (ie, the first drain region 1314 and the drain of the PMOS transistor (ie, the second drain region 1324 )) may be electrically connected to each other. The voltage of the drain may be the output voltage Vout of the ternary inverter 30. The description of the ternary inverter may be substantially the same as that described with reference to FIG.

6 shows a gate voltage-drain current graph of ternary inverters and binary inverters of the present disclosure.

Referring to FIG. 6 , gate voltage-drain current graphs IGR1 and IGR2 of binary inverters and gate voltage-drain current graphs IGR3 , IGR4 and IGR5 of ternary inverters of the present disclosure are shown.

The drain currents of the binary inverters did not have a constant current component that flows regardless of the gate voltage.

The drain currents of the ternary inverters of the present disclosure have a constant current component flowing regardless of the gate voltage. For example, even when the ternary inverters of the present disclosure have an off state, a constant current flows through the ternary inverters of the present disclosure.

7 is a graph illustrating an input voltage (Vin)-output voltage (Vout) of the ternary inverter and the binary inverter of the present disclosure.

Referring to FIG. 7 , the driving voltage (V _DD ) of the ternary inverter and the binary inverter of the present disclosure was 1.0 V and the ground voltage (GND) was 0 V. The input voltage (Vin) of the ternary inverter and the binary inverter was 0 V to 1.0 V.

In the case of the binary inverter, when the input voltage was changed from 0 V to 1 V, the output voltage Vout rapidly decreased from 1 V to 0 V in the vicinity of the input voltage of 0.5 V. That is, the binary inverter had two states (eg, a '0' state and a '1' state).

In the case of the ternary inverter of the present disclosure, when the input voltage is changed from 0 V to 1 V, the output voltage Vout rapidly decreases from 1 V to 0.5 V to maintain 0.5 V, and then from 0.5 V to 0 V once more decreased sharply. That is, the ternary inverter of the present disclosure had three states (eg, a '0' state, a '1' state, and a '2' state).

8 is a perspective view of a tunnel field effect transistor according to an exemplary embodiment. 9 is a cross-sectional view taken along lines II' and II-II' of FIG. 8 . For brevity of description, contents substantially the same as those described with reference to FIG. 1 may not be described.

8 and 9 , a tunnel field effect transistor 40 may be provided. The tunnel field effect transistor 40 may include a substrate 2100 , a fin structure FS, a pair of lower insulating layers 2110 , and a gate structure 2400 .

The substrate 2100 may be a semiconductor substrate. For example, the substrate 2100 may include silicon (Si). The substrate 2100 may have a first conductivity type. For example, the first conductivity type may be n-type or p-type.

A fin structure FS may be provided on the substrate 2100 . The fin structure FS may extend in a first direction DR1 parallel to the upper surface 2100u of the substrate 2100 . The fin structure FS may protrude from the upper surface 2100u of the substrate 2100 . The fin structure FS may include a source region 2310 , a drain region 2320 , a channel layer 2220 , and a constant current forming layer 2210 .

A source region 2310 and a drain region 2320 spaced apart from each other in the first direction DR1 may be provided on the fin structure FS. The source region 2310 may have a first conductivity type. The drain region 2320 may have a second conductivity type different from the first conductivity type. When the first conductivity type is n-type, the second conductivity type may be p-type. When the first conductivity type is p-type, the second conductivity type may be n-type.

A channel layer 2220 may be provided on the fin structure FS. The channel layer 2220 may be provided between the source region 2310 and the drain region 2320 . The channel layer 2220 may include substantially the same material as the substrate 2100 . For example, the channel layer 2220 may include silicon (Si). The channel layer 2220 may have a first conductivity type. The doping concentration of the channel layer 2220 may be substantially the same as that of the substrate 2100 .

The constant current forming layer 2210 may be provided under the fin structure FS. The constant current forming layer 2210 may extend in the first direction DR1 . The constant current forming layer 2210 may overlap the source region 2310 , the channel layer 2220 , and the drain region 2320 in the third direction DR3 . The constant current forming layer 2210 may be electrically connected to the source region 2310 and the drain region 2320 . For example, the constant current forming layer 2210 may directly contact the bottom surfaces of the source region 2310 and the drain region 2320 . The constant current forming layer 2210 may have a first conductivity type. The doping concentration of the constant current forming layer 2210 may be higher than that of the substrate 2100 and the channel layer 2220 . For example, the doping concentration of the constant current forming layer 2210 may be ^{3 X 10 18} cm ^{-3 or more.} A doping concentration of the constant current forming layer 2210 may be lower than a doping concentration of the source region 2310 . An electric field may be formed between the constant current forming layer 2210 and the drain region 2320 . For example, the strength of the electric field ^{may be 10 6} V/cm or more.

The constant current forming layer 2210 may form a constant current between the drain region 2320 and the constant current forming layer 2210 . The constant current may be a band-to-band tunneling (BTBT) current between the drain region 2320 and the constant current forming layer 2210 . The constant current may be independent from a gate voltage applied to the gate electrode 2420 . That is, the constant current may flow regardless of the gate voltage. When the tunnel field effect transistor 40 is an NMOS transistor device, a constant current may flow from the drain region 2320 to the substrate 2100 through the constant current forming layer 2210 . When the tunnel field effect transistor 40 is a PMOS transistor device, a constant current may flow from the substrate 2100 to the drain region 2320 through the constant current forming layer 2210 .

The pair of lower insulating layers 2110 may be spaced apart from each other with the fin structure FS interposed therebetween. The pair of lower insulating layers 2110 may be parallel to the upper surface 2100u of the substrate 2100 and may be arranged in a second direction DR2 crossing the first direction DR1 . The pair of lower insulating layers 2110 may overlap a lower portion of the fin structure FS along the second direction DR2 . A pair of lower insulating layers 2110 may cover both side surfaces of the constant current forming layer 2210 . The pair of lower insulating layers 2110 may expose the source region 2310 and the drain region 2320 . In other words, the source region 2310 and the drain region 2320 may protrude from the pair of lower insulating layers 2110 . The pair of lower insulating layers 2110 may include an electrically insulating material. For example, the pair of lower insulating _{layers 2110 may include SiO 2} or a high-k material (eg, SiON, HfO ₂ , ZrO ₂ ).

A gate electrode 2420 may be provided on the fin structure FS and the pair of lower insulating layers 2110 . The gate electrode 2420 may extend in the second direction DR2 . The gate electrode 2420 may cross the fin structure FS from a viewpoint along the third direction DR3 crossing the first direction DR1 and the second direction DR2 . The gate electrode 2420 may be provided on the channel layer 2220 . The gate electrode 2420 may include an electrically conductive material. For example, the gate electrode 420 may include a doped semiconductor material, a metal, an alloy, or a combination thereof. For example, the gate electrode 420 may include doped polysilicon, tungsten (W), titanium nitride (TiN), or a combination thereof.

A gate insulating layer 2410 may be provided between the gate electrode 2420 and the fin structure FS. For example, the gate insulating layer 2410 may conformally cover an upper portion of the fin structure FS. The gate insulating layer 2410 may electrically insulate the gate electrode 2420 and the fin structure FS from each other. The gate insulating layer 2410 may separate the gate electrode 2420 and the fin structure FS from each other. The gate insulating layer 2410 may include an electrically insulating material. For example, the gate insulating layer 2410 may be formed of at least one material selected from among silicon oxide, silicon nitride, silicon oxynitride, oxide/nitride/oxide (ONO), and a high-k dielectric material. . For example, the gate insulating layer 2410 may include a material having a dielectric constant of about 10 to about 25 . For example, the gate insulating layer 2410 may include hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide ( LaAlO), zirconium oxide (ZrO), zirconium silicon oxide (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide ( and at least one material selected from among BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO).

The present disclosure may provide a tunnel field effect transistor 40 through which a constant current flows between the drain region 2320 and the substrate 2100 .

Fig. 10 is a perspective view of a ternary inverter according to an exemplary embodiment. For brevity of description, contents substantially the same as those described with reference to FIGS. 8 and 9 may not be described.

Referring to FIG. 10 , a ternary inverter 50 may be provided. The ternary inverter 50 includes a substrate 3100 , a first well region 3102 , a second well region 3104 , a first fin structure 3202 , a second fin structure 3204 , a lower insulating film 3110 , and A gate structure 3400 may be included. The substrate 3100 may be a semiconductor substrate. For example, the substrate 3100 may include silicon (Si). The substrate 3100 may be substantially the same as the substrate 3100 described with reference to FIGS. 8 and 9 .

The first well region 3102 and the second well region 3104 may extend along a first direction DR1 parallel to the top surface of the substrate 3100 . The first well region 3102 and the second well region 3104 may be arranged in a second direction DR2 parallel to the top surface of the substrate 3100 . The first direction DR1 and the second direction DR2 may cross each other. The conductivity type of the first well region 3102 may be p-type. The conductivity type of the second well region 3104 may be n-type. For example, the first well region 3102 and the second well region 3104 may be formed by an ion implantation process.

A first fin structure 3202 and a second fin structure 3204 may be provided on the first well region 3102 and the second well region 3104 , respectively. Each of the first and second fin structures 3202 and 3204 may be substantially the same as the fin structure FS described with reference to FIGS. 8 and 9 except for the conductivity type. The first channel layer may be provided between the first source region 3312 and the first drain region 3314 . The conductivity type of the first source region 3312 , the first channel layer, and the first constant current forming layer 3212 may be p-type. The conductivity type of the first drain region 3314 may be n-type. The second channel layer may be provided between the second source region 3322 and the second drain region 3324 . The conductivity type of the second source region 3322 , the second channel layer, and the second constant current forming layer 3214 may be n-type. The second drain region 3324 may have a p-type conductivity.

Lower insulating layers 3110 may be provided on both sides of the first constant current forming fin 3212 and on both sides of the second constant current forming fin 3214 . Both side surfaces of the first constant current forming fin 3212 and both side surfaces of the second constant current forming fin 3214 may extend in the first direction DR1 . The lower insulating layers 3110 may include an electrically insulating material. For example, the lower insulating _{layers 3110 may include SiO 2} or a high-k material (eg, SiON, HfO ₂ , ZrO ₂ ).

A gate structure 3400 may be provided on the first and second fin structures 3202 and 3204 . The gate structure 3400 may include a gate insulating layer 3410 and a gate electrode 3420 that are sequentially stacked. The gate insulating layer 3410 and the gate electrode 3420 may be substantially the same as the gate insulating layer 2410 and the gate electrode 2420 described with reference to FIGS. 8 and 9 , respectively. The gate structure 3400 may intersect the first and second fin structures 3202 and 3204 . For example, the gate structure 400 may extend in the second direction DR2 . The gate structure 400 may extend along the lower insulating layer 3110 and the surfaces of the first and second fin structures 3202 and 3204 exposed on the lower insulating layers 3110 .

The present disclosure may provide a ternary inverter 50 including tunnel field effect transistors. The ternary inverter 50 may be substantially the same as the ternary inverter 20 described with reference to FIG. 4 . The first well region 3102 , the first fin structure 3202 , and the gate structure 3400 on the first fin structure 3202 may be NMOS tunnel field effect transistors. The second well region 3104 , the second fin structure 3204 , and the gate structure 3400 on the second fin structure 3204 may be a PMOS tunnel field effect transistor.

_{A driving voltage V DD} may be applied to the second well region 3104 and the second source region 3322 . A ground voltage may be applied to the first well region 3102 and the first source region 3312 . An input voltage Vin may be applied to the gate electrode 3420 . The second drain region 3324 and the first drain region 3314 may be electrically connected to each other. The voltage of the second drain region 3324 and the first drain region 3314 may be the output voltage Vout of the ternary inverter 50 .

A constant current (ie, a constant current of the PMOS tunnel field effect transistor) may flow from the second well region 3104 to the second drain region 3324 . A constant current (ie, a constant current of the NMOS tunnel field effect transistor) may flow from the first drain region 3314 to the first well region 3102 . The constant currents may be independent of the input voltage Vin (ie, the gate voltage).

The driving mode of the ternary inverter 50 may be substantially the same as the driving mode of the ternary inverter 20 described with reference to FIG. 7 .

As described with reference to FIG. 7 , the output voltage Vout of the ternary inverter 50 is 0 V ('0' state) depending on the input voltage Vin, and a voltage between the _{driving voltage V DD and 0 V (} '1' state), or a driving voltage V _DD ('2' state). The present disclosure may provide the ternary inverter 50 having three states according to the input voltage Vin.

11 is a cross-sectional view of a tunnel field effect transistor according to exemplary embodiments.

Referring to FIG. 11 , a tunnel field effect transistor 60 may be provided. The tunnel field effect transistor 60 includes a substrate 4100 , a pair of isolation regions ST, a source region 4410 , a drain region 4420 , a pair of constant current forming regions 4200 , and a gate structure. (4300) may be included.

The substrate 4100 may be a semiconductor substrate. For example, the substrate 4100 may include silicon (Si). The substrate 4100 may have a first conductivity type. For example, the first conductivity type may be n-type or p-type.

A pair of device isolation regions ST may be provided on the substrate 4100 . The pair of isolation regions ST may be spaced apart from each other in a first direction DR1 parallel to the upper surface 4100u of the substrate 4100 . The pair of device isolation regions ST may extend in a second direction DR2 perpendicular to the top surface 4100u of the substrate 4100 . The pair of isolation regions ST may include an electrically insulating material. For example, the pair of isolation regions ST may include SiO ₂ or a high-k material (eg, SiON, HfO ₂ , ZrO ₂ ).

A source region 4410 and a drain region 4420 may be provided on the substrate 4100 . The source region 4410 and the drain region 4420 may be spaced apart from each other in the first direction DR1 . The source region 4410 may have a first conductivity type. The drain region 4420 may have a second conductivity type different from the first conductivity type. For example, when the conductivity type of the source region 4410 is n-type, the conductivity type of the drain region 4420 may be p-type. For example, when the conductivity type of the source region 4410 is p-type, the conductivity type of the drain region 4420 may be n-type.

A pair of constant current forming regions 4200 may be provided on the bottom surface of the source region 4410 and on the bottom surface of the drain region 4420 , respectively. The pair of constant current forming regions 4200 may respectively overlap the source region 4410 and the drain region 4420 in the second direction DR2 . The pair of constant current forming regions 4200 may be electrically connected to the source region 4410 and the drain region 4420 . For example, the pair of constant current forming regions 4200 may directly contact the source region 4410 and the drain region 4420 . The pair of constant current forming regions 4200 may be spaced apart from each other in the first direction DR1 . The pair of constant current forming regions 4200 may have a first conductivity type. The doping concentration of the pair of constant current forming regions 4200 may be higher than that of the substrate 4100 . For example, the doping concentration of the pair of constant current forming regions 4200 may be ^{3 X 10 18} cm ^{-3 or more.} An electric field may be formed between the pair of constant current forming regions 4200 and the drain region 4420 . For example, the strength of the electric field ^{may be 10 6} V/cm or more.

A gate structure 4300 may be provided on the substrate 4100 . The gate structure 4300 may include a gate insulating layer 4310 , a gate electrode 4320 , and a pair of spacers 4330 . The gate electrode 4320 may include an electrically conductive material. For example, the gate electrode 4320 may include a doped semiconductor material, a metal, an alloy, or a combination thereof. For example, the gate electrode 4320 may include doped-polysilicon, tungsten (W), titanium nitride (TiN), or a combination thereof.

A gate insulating layer 4310 may be provided between the gate electrode 4320 and the substrate 4100 . The gate insulating layer 4310 may electrically insulate the gate electrode 4320 and the substrate 4100 from each other. The gate insulating layer 4310 may include an electrically insulating material. For example, the gate insulating layer 4310 may be formed of at least one material selected from among silicon oxide, silicon nitride, silicon oxynitride, oxide/nitride/oxide (ONO), and a high-k dielectric material. . For example, the gate insulating layer 4310 may include a material having a dielectric constant of about 10 to 25. For example, the gate insulating layer 4310 may include hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide ( LaAlO), zirconium oxide (ZrO), zirconium silicon oxide (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide ( and at least one material selected from among BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO).

A pair of spacers 4330 may be provided on both sidewalls of the gate electrode 4320 , respectively. A pair of spacers 4330 may extend on both sidewalls of the gate insulating layer 4310 , respectively. The pair of spacers 4330 may include an electrically insulating material. For example, the pair of spacers 4330 may include SiO ₂ or a high-k material (eg, SiON, HfO ₂ , ZrO ₂ ).

In an example, the threshold voltage of the tunnel field effect transistor 60 may be adjusted by a doping concentration of the substrate 4100 and/or a work function of the gate electrode 4320 . For example, the work function of the gate electrode 4320 may be controlled by the material of the gate electrode 4320 or by an additional work function control layer (not shown). For example, an additional work function control layer may be interposed between the gate insulating layer 4310 and the substrate 4100 .

The constant current formation region 4200 immediately adjacent to the drain region 4420 may form a constant current between the drain region 4420 and the constant current formation region 4200 immediately adjacent thereto. The constant current may be a band-to-band tunneling (BTBT) current between the drain region 4420 and the constant current forming region 4200 immediately adjacent thereto. The constant current may be independent from the gate voltage applied to the gate electrode 4320 . That is, the constant current may flow regardless of the gate voltage. When the tunnel field effect transistor 60 is an NMOS transistor, a constant current may flow from the drain region 4420 to the substrate 4100 through the constant current forming region 4200 immediately adjacent thereto. When the tunnel field effect transistor 60 is a PMOS transistor, a constant current may flow from the substrate 4100 to the drain region 4420 through the constant current forming region 4200 immediately adjacent to the drain region 4420 .

The present disclosure may provide a tunnel field effect transistor 60 in which a constant current is formed between the drain region 4320 and the constant current formation region 4200 immediately adjacent thereto.

12 is a perspective view of a transistor according to an exemplary embodiment. 13 is a cross-sectional view taken along lines II' and II-II' of FIG. 12 . For brevity of description, contents substantially the same as those described with reference to FIGS. 8 and 9 may not be described.

12 and 13 , a tunnel field effect transistor 70 may be provided. The tunnel field effect transistor 70 may include a substrate 5100 , a fin structure FS, a pair of lower insulating layers 5110 , and a gate structure 5300 .

The substrate 5100 may be a semiconductor substrate. For example, the substrate 5100 may include silicon (Si). The substrate 5100 may have a first conductivity type. For example, the first conductivity type may be n-type or p-type.

A fin structure FS may be provided on the substrate 5100 . The fin structure FS may include a lower semiconductor region LSR, a pair of constant current forming regions 5200 , a source region 5410 , a drain region 5420 , and a channel region CR. The lower semiconductor region LSR may be provided under the fin structure FS. The lower semiconductor region LSR may extend in a second direction DR2 parallel to the top surface 5100u of the substrate 5100 . The lower semiconductor region LSR may protrude from the upper surface 5100u of the substrate 5100 . The lower semiconductor region LSR may include silicon (Si). The lower semiconductor region LSR may have a first conductivity type.

A pair of constant current forming regions 5200 may be provided on the lower semiconductor region LSR. The pair of constant current forming regions 5200 may be spaced apart from each other with the gate structure 5300 interposed therebetween. For example, the pair of constant current forming regions 5200 may be spaced apart from each other in the second direction DR2 . For example, the pair of constant current forming regions 5200 may include silicon (Si). The pair of constant current forming regions 5200 may have a first conductivity type. A doping concentration of the pair of constant current forming regions 5200 may be higher than that of the substrate 5100 and the lower semiconductor region LSR. For example, the doping concentration of the pair of constant current forming regions 5200 may be ^{3×10 18} cm ^{−3 or more.}

A source region 5410 and a drain region 5420 may be respectively provided on a pair of constant current forming regions 5200 . The source region 5410 and the drain region 5420 may be spaced apart from each other in the second direction DR2 . The source region 5410 may have a first conductivity type. The doping concentration of the source region 5420 may be higher than that of the pair of constant current forming regions 5200 . The drain region 5420 may have a second conductivity type different from the first conductivity type. For example, when the conductivity type of the source region 5410 is n-type, the conductivity type of the drain region 5420 may be p-type. For example, when the conductivity type of the source region 5410 is p-type, the conductivity type of the drain region 5420 may be n-type.

The source region 5410 and the drain region 5420 may be electrically connected to a pair of constant current forming regions 5200 , respectively. For example, the source region 5410 and the drain region 5420 may directly contact the pair of constant current forming regions 5200 . An electric field may be formed between the pair of constant current forming regions 5200 and the drain region 5420 . For example, the strength of the electric field ^{may be 10 6} V/cm or more.

The channel region CR may be provided on the lower semiconductor region LSR. The channel region CR may extend from the lower semiconductor region LSR to a region between the source region 5410 and the drain region 5420 . The channel region CR may be provided between the pair of constant current forming regions 5200 and between the source region 5410 and the drain region 5420 . The channel region CR may include silicon (Si). The channel region CR may have a first conductivity type. The doping concentration of the channel region CR may be lower than that of the pair of constant current forming regions 5200 . For example, the doping concentration of the channel region CR may be substantially the same as that of the lower semiconductor region LSR. The channel region CR may be a region in which a channel of the tunnel field effect transistor 70 is formed.

The pair of lower insulating layers 5110 may be spaced apart from each other with the fin structure FS interposed therebetween. For example, the pair of lower insulating layers 5110 may be parallel to the upper surface 5100u of the substrate 5100 and spaced apart from each other in the first direction DR1 intersecting the second direction DR2 . The pair of lower insulating layers 5110 may overlap the lower semiconductor region LSR in the first direction DR1 . The pair of lower insulating layers 5110 may include an electrically insulating material. For example, the pair of lower insulating _{layers 5110 may include SiO 2} or a high-k material (eg, SiON, HfO ₂ , ZrO ₂ ).

The gate structure 5300 may be provided on the fin structure FS and the pair of lower insulating layers 5110 . The gate structure 5300 may include a gate insulating layer 5310 and a gate electrode 5320 that are sequentially stacked. The gate structure 5300 may extend in the first direction DR1 . The gate structure 5300 may overlap the channel region CR along the third direction DR3 . The gate structure 5300 may extend along the pair of lower insulating layers 5110 and the surface of the fin structure FS exposed on the pair of lower insulating layers 5110 . The gate insulating layer 5310 may include an electrically insulating material. For example, the gate insulating layer 5310 may include at least one material selected from among silicon oxide, silicon nitride, silicon oxynitride, oxide/nitride/oxide (ONO), and a high-k dielectric material. have. For example, the gate insulating layer 5310 may include a material having a dielectric constant of about 10 to 25 . For example, the gate insulating layer 5310 may include hafnium oxide (HfO), hafnium silicon oxide (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum aluminum oxide ( LaAlO), zirconium oxide (ZrO), zirconium silicon oxide (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide ( and at least one material selected from among BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), and lead scandium tantalum oxide (PbScTaO). The gate electrode 5320 may include an electrically conductive material. For example, the gate electrode 5320 may include a doped semiconductor material, a metal, an alloy, or a combination thereof. For example, the gate electrode 5320 may include doped polysilicon, tungsten (W), titanium nitride (TiN), or a combination thereof.

In one example, the threshold voltage of the tunnel field effect transistor 70 may be adjusted by a doping concentration of the channel region CR and/or a work function of the gate electrode 5320 . For example, the work function of the gate electrode 5320 may be controlled by the material of the gate electrode 5320 or by an additional work function control layer (not shown). For example, an additional work function control layer may be interposed between the gate insulating layer 5310 and the channel region CR.

The constant current forming region 5200 immediately adjacent to the drain region 5420 may form a constant current between the drain region 5420 and the constant current forming region 5200 . The constant current may be a band-to-band tunneling (BTBT) current between the drain region 5420 and the constant current forming region 5200 immediately adjacent thereto. The constant current may be independent from a gate voltage applied to the gate electrode 5320 . That is, the constant current may flow regardless of the gate voltage. When the tunnel field effect transistor 70 is an NMOS transistor, the constant current flows from the drain region 5420 through the constant current forming region 5200 immediately adjacent thereto to the lower semiconductor region LSR and the substrate 5100 . can When the tunnel field effect transistor 70 is a PMOS transistor, the constant current passes from the substrate 5100 to the lower semiconductor region LSR and the constant current formation region 5200 immediately adjacent to the drain region 5420 to the drain region. (5420).

The present disclosure may provide a tunnel field effect transistor 70 through which a constant current flows between the drain region 5420 and the constant current forming region 5200 immediately adjacent thereto.

The above description of embodiments of the technical idea of the present invention provides an example for the description of the technical idea of the present invention. Therefore, the technical spirit of the present invention is not limited to the above embodiments, and within the technical spirit of the present invention, a person skilled in the art may perform various modifications and changes such as combining the above embodiments. It is clear that this is possible.

Claims (20)

constant current forming layer;
a source region and a drain region provided on the constant current forming layer;
a channel layer provided between the source region and the drain region;
a gate electrode provided on the channel layer; and
a gate insulating film provided between the gate electrode and the channel layer;
The source region and the drain region each have different conductivity types,
The constant current forming layer is a tunnel field effect transistor for forming a constant current between the drain region and the constant current forming layer. The method of claim 1,
The constant current is independent of the gate voltage applied to the gate electrode tunnel field effect transistor. The method of claim 1,
The constant current forming layer and the source region have a first conductivity type,
The drain electrode is a tunnel field effect transistor having a second conductivity type. The method of claim 1,
A doping concentration of the constant current forming layer is higher than a doping concentration of the channel layer. 5. The method of claim 4,
The doping concentration of the constant current forming layer is 3 X 10 ¹⁸ cm ^-3 or more tunnel field effect transistor. The method of claim 1,
An electric field is formed between the drain region and the constant current forming layer,
The electric field strength is 10 ⁶ V/cm or more tunnel field effect transistor. The method of claim 1,
The constant current forming layer is disposed adjacent to the drain region and electrically connected to the drain region. 8. The method of claim 7,
wherein the constant current forming layer extends into a region adjacent to the source region. a fin structure extending in a first direction;
a gate electrode extending in a second direction crossing the first direction; and
a gate insulating layer provided between the fin structure and the gate electrode;
The fin structure includes a constant current forming layer provided under the fin structure, and a source region and a drain region provided on the constant current forming layer,
The source region and the drain region each have different conductivity types,
The constant current forming layer is a tunnel field effect transistor for forming a constant current between the drain region and the constant current forming layer. 10. The method of claim 9,
The fin structure is a tunnel field effect transistor overlapping the gate electrode in the second direction. 10. The method of claim 9,
The constant current is independent of the gate voltage applied to the gate electrode tunnel field effect transistor. 10. The method of claim 9,
The constant current forming layer and the source region have a first conductivity type,
The drain electrode is a tunnel field effect transistor having a second conductivity type. 10. The method of claim 9,
The fin structure further includes a channel layer provided between the source region and the drain region,
A doping concentration of the constant current forming layer is higher than a doping concentration of the channel layer. 14. The method of claim 13,
The doping concentration of the constant current forming layer is 3 X 10 ¹⁸ cm ^-3 or more tunnel field effect transistor. 10. The method of claim 9,
An electric field is formed between the drain region and the constant current forming layer,
The electric field strength is 10 ⁶ V/cm or more tunnel field effect transistor. 10. The method of claim 9,
The constant current forming layer is disposed adjacent to the drain region and electrically connected to the drain region. 17. The method of claim 16,
The constant current forming layer extends in the first direction and overlaps the source region and the drain region in a third direction crossing the first direction and the second direction. a first constant current forming layer and a second constant current forming layer respectively provided on the first well region and the second well region, the first well region and the second well region, a first source region provided on the first constant current forming layer; a first channel layer, a first drain region, a second source region provided on the second constant current forming layer, a second channel layer, and on the second drain region, the first channel layer and the second channel layer A first gate electrode and a second gate electrode respectively provided; including,
the first source region and the first drain region each have different conductivity types, and the second source region and the second drain region have different conductivity types, respectively;
The first constant current forming layer forms a first constant current between the first drain region and the first constant current forming layer, and the second constant current forming layer forms a second constant current between the second drain region and the second constant current forming layer a ternary inverter. 19. The method of claim 18,
The first constant current and the second constant current are independent from gate voltages applied to the first gate electrode and the second gate electrode, respectively. 19. The method of claim 18,
the first constant current forming layer and the first source region have a first conductivity type;
The first drain electrode has a second conductivity type different from the first conductivity type,
the second constant current forming layer and the second source region have the second conductivity type;
The second drain electrode is a ternary inverter having the first conductivity type.

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