KR20210086240A - Display device and manufacturing method thereof - Google Patents

Abstract

A display device and a manufacturing method thereof are provided. The display device comprises: a substrate; a light emitting element disposed on the substrate; a protective layer formed on the light emitting element; a color filter formed on the protective layer to correspond to the light emitting element; a bank formed to surround a side surface of the color filter; and a pond formed between the protective layer and the color filter. The color filter comprises: a peripheral portion in contact with the bank; and a central portion surrounded by the peripheral portion and having an upper surface with a different height than an upper surface of the peripheral portion, wherein a thickness of the central portion and a thickness of the peripheral portion are substantially the same.

Description

Display device and manufacturing method thereof

The present invention relates to a display device and a method for manufacturing the same.

As the information society develops, various types of display devices are being developed. Recently, various display devices such as a liquid crystal display (LCD), a plasma display panel (PDP), and an organic light emitting display (OLED) have been used.

The organic light emitting device constituting the organic light emitting display device is a self-emissive type and does not require a separate light source, so that the thickness and weight of the display device can be reduced. In addition, the organic light emitting diode display exhibits high quality characteristics such as low power consumption, high luminance, and high response speed.

The display panel includes pixels including a transistor, a capacitor, and a light emitting device. As the resolution of the display device increases and the size of the display device increases, a denser and larger number of pixels are disposed in the display device. In order to secure the reliability of the display device, a method capable of reducing the complexity of the process and improving the yield is required.

In particular, in a recent method of manufacturing a display device, a method of forming a color filter included in a sub-pixel by applying an organic solvent through an inkjet printing method has been proposed.

SUMMARY The technical problem to be solved by the present invention is to provide a display device including a color filter having a uniform thickness.

Another technical problem to be solved by the present invention is to provide a method of manufacturing a display device including a color filter having a uniform thickness.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems not mentioned will be clearly understood by those skilled in the art from the following description.

A display device according to some embodiments of the present invention provides a substrate, a light emitting device disposed on the substrate, a protective layer formed on the light emitting device, and the light emitting device on the protective layer a color filter formed by doing so, a bank formed to surround a side surface of the color filter, and a pond formed between the protective layer and the color filter, wherein the color filter includes a periphery in contact with the bank and a periphery surrounded by the periphery a central portion, wherein the distance from the top surface of the device protection layer to the top surface of the peripheral portion is different from the distance from the top surface of the device protection layer to the top surface of the central portion, and the thickness of the central portion and the thickness of the peripheral portion are substantially is the same as

In some embodiments of the present invention, the top profile of the color filter may be formed along the top profile of the pond.

In some embodiments of the present invention, the pond includes a convexly formed upper surface such that the height decreases from the central portion of the pond to the periphery of the pond, and the color filter is located at the center of the color filter. The upper surface of the color filter may have a convex shape such that the height of the upper surface of the color filter decreases toward the peripheral portion.

In some embodiments of the present invention, the sidewalls of the bank may include a hydrophobic material.

In some embodiments of the present invention, the pond includes an upper surface concavely formed to increase in height from a central portion of the pond to a periphery of the pond, and the color filter is located at the center of the color filter. The upper surface of the color filter may be formed concavely so that the height of the upper surface of the color filter increases toward the peripheral portion.

In some embodiments of the present invention, the sidewalls of the bank may include a hydrophilic material.

In some embodiments of the present invention, the pond and the bank may include the same material.

In some embodiments of the present invention, the top surface of the protective layer exposed by the bank may be flat.

A method of manufacturing a display device according to some embodiments of the present invention for achieving the above technical problem includes forming a light emitting device on a substrate, forming a passivation layer covering the light emitting device, and on the passivation layer. forming a bank exposing the upper surface of the protective layer corresponding to the light emitting element; forming a pond to cover the upper surface of the protective layer exposed by the bank; and injecting ink on the pond to filter the color filter forming, wherein the color filter includes a periphery in contact with the bank and a central portion surrounded by the periphery, the distance from the top surface of the device protection layer to the top surface of the periphery, the device protection The distance from the upper surface of the layer to the upper surface of the central portion is different, and the thickness of the central portion and the thickness of the peripheral portion are substantially the same.

In some embodiments of the present invention, the forming of the pond may include injecting an organic solution onto the protective layer and curing it.

In some embodiments of the present invention, the forming of the bank and the forming of the pond may include sequentially forming an insulating film and a photoresist on the protective layer, and a transflective portion of the photoresist corresponds to the light emitting device. Forming a photoresist pattern by selectively exposing to light using a halftone mask disposed to do so, and forming the banks and ponds by etching the insulating layer using the photoresist pattern as an etching mask. have.

A display device and a method of manufacturing the same according to embodiments of the present invention include a color filter having a constant thickness throughout. Through this, the amount of light transmitted through the color filter is kept constant, and the turbidity of the image displayed on the panel and the ease of spectroscopic inspection can be improved due to the improvement of color purity of the transmitted light.

1 is a block diagram illustrating a configuration of a display device according to some exemplary embodiments.
FIG. 2 is a circuit diagram illustrating some embodiments of the pixel illustrated in FIG. 1 .
3 is a perspective view of the display device illustrated in FIG. 1 according to some exemplary embodiments;
4 is a cross-sectional view of a display panel according to some exemplary embodiments.
FIG. 5 is an enlarged cross-sectional view of the CV region of FIG. 4 .
6 is a cross-sectional view of a display device according to another exemplary embodiment.
FIG. 7 is an enlarged cross-sectional view of the CV region of FIG. 6 .
8 to 15 are diagrams for explaining a method of manufacturing a display panel according to some exemplary embodiments.
16 to 18 are diagrams for explaining a method of manufacturing a display panel according to another exemplary embodiment of the present invention.

Hereinafter, various embodiments will be described with reference to the drawings. In this specification, when an element (or region, layer, portion, etc.) is referred to as "on," "connected to," or "coupled to," another element, it is on the other element. It means that they can be directly connected/coupled or that a third component can be placed between them.

Like reference numerals refer to like components. In addition, in the drawings, thicknesses, ratios, and dimensions of components are exaggerated for effective description of technical content. “and/or” includes any combination of one or more that the associated configurations may define.

Terms such as first, second, etc. may be used to describe various elements, but the elements are not limited by the terms. The above terms are used only for the purpose of distinguishing one component from another. For example, a first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component without departing from the scope of the various embodiments. The singular expression includes the plural expression unless the context clearly dictates otherwise.

Terms such as "below", "below", "above", "upper" and the like are used to describe the relationship of the components shown in the drawings. The above terms are relative concepts, and are described based on directions indicated in the drawings.

"Comprise." Or "have." The term such as is intended to designate that there is a feature, number, step, action, component, part, or combination thereof described in the specification, but one or more other features or number, step, action, component, part or It should be understood that it does not preclude the possibility of the existence or addition of combinations thereof.

1 is a block diagram illustrating a configuration of a display device according to an exemplary embodiment.

Referring to FIG. 1 , a display device 1 includes a timing controller 10 , a gate driver 20 , a data driver 30 , a power supply unit 40 , and a display panel 50 .

The timing controller 10 may receive an image signal RGB and a control signal CS from the outside. The image signal RGB may include a plurality of grayscale data. The control signal CS may include, for example, a horizontal synchronization signal, a vertical synchronization signal, and a main clock signal.

The timing controller 10 processes the image signal RGB and the control signal CS to be suitable for the operating conditions of the display panel 50 , and thus the image data DATA, the gate driving control signal CONT1, and the data driving control signal. (CONT2) and power supply control signal (CONT3) can be generated and output.

The gate driver 20 may be connected to the pixels PX of the display panel 50 through the plurality of gate lines GL1 to GLn. The gate driver 20 may generate gate signals based on the gate driving control signal CONT1 output from the timing controller 10 . The gate driver 20 may provide the generated gate signals to the pixels PX through the plurality of gate lines GL1 to GLn.

The data driver 30 may be connected to the pixels PX of the display panel 50 through a plurality of data lines DL1 to DLm. The data driver 30 may generate data signals based on the image data DATA and the data driving control signal CONT2 output from the timing controller 10 . The data driver 30 may provide the generated data signals to the pixels PX through the plurality of data lines DL1 to DLm.

The power supply unit 40 may be connected to the pixels PX of the display panel 50 through a plurality of power lines PL1 and PL2 . The power supply unit 40 may generate a driving voltage to be provided to the display panel 50 based on the power supply control signal CONT3 . The driving voltage may include, for example, a high potential driving voltage ELVDD and a low potential driving voltage ELVSS. The power supply unit 40 may provide the generated driving voltages ELVDD and ELVSS to the pixels PX through the corresponding power lines PL1 and PL2 .

A plurality of pixels PX (or referred to as sub-pixels) are disposed on the display panel 50 . The pixels PX may be arranged, for example, in a matrix form on the display panel 50 .

Each pixel PX may be electrically connected to a corresponding gate line and data line. The pixels PX may emit light with luminance corresponding to the gate signal and the data signal supplied through the gate lines GL1 to GLn and the data lines DL1 to DLm.

Each pixel PX may display any one of the first to third colors. In an embodiment, each pixel PX may display any one of red, green, and blue. In another exemplary embodiment, each pixel PX may display any one of cyan, magenta, and yellow. In various embodiments, the pixels PX may be configured to display any one of four or more colors. For example, each pixel PX may display any one of red, green, blue, and white.

The timing controller 10, the gate driver 20, the data driver 30, and the power supply unit 40 are each composed of a separate integrated circuit (IC) or at least a part of an integrated circuit. . For example, at least one of the data driver 30 and the power supply unit 40 may be configured as an integrated circuit integrated with the timing controller 10 .

Also, although the gate driver 20 and the data driver 30 are illustrated as separate components from the display panel 50 in FIG. 1 , at least one of the gate driver 20 and the data driver 30 is formed in the display panel 50 . ) and may be configured in an in-panel method that is integrally formed with

FIG. 2 is a circuit diagram illustrating some embodiments of the pixel illustrated in FIG. 1 . FIG. 2 illustrates the pixel PXij connected to the i-th gate line GLi and the j-th data line DLj as an example.

Referring to FIG. 2 , the pixel PX includes a switching transistor ST, a driving transistor DT, a storage capacitor Cst, and a light emitting device LD.

The first electrode (eg, the source electrode) of the switching transistor ST is electrically connected to the j-th data line DLj, and the second electrode (eg, the drain electrode) is connected to the first node N1 and electrically connected. The gate electrode of the switching transistor ST is electrically connected to the i-th gate line GLi. The switching transistor ST is turned on when the gate signal of the gate-on level is applied to the i-th gate line GLi and transfers the data signal applied to the j-th data line DLj to the first node N1 . .

A first electrode of the storage capacitor Cst may be electrically connected to the first node N1 , and a second electrode may be configured to receive the high potential driving voltage ELVDD. The storage capacitor Cst may be charged with a voltage corresponding to a difference between the voltage applied to the first node N1 and the low potential driving voltage ELVSS.

The first electrode (eg, the source electrode) of the driving transistor DT is configured to receive the high potential driving voltage ELVDD, and the second electrode (eg, the drain electrode) of the light emitting element LD is electrically connected to one electrode (eg, an anode electrode). The gate electrode of the driving transistor DT is electrically connected to the first node N1 . The driving transistor DT is turned on when a gate-on level voltage is applied through the first node N1 , and controls the amount of driving current flowing through the light emitting device LD in response to the voltage applied to the gate electrode. can

The light emitting element LD outputs light corresponding to the driving current. The light emitting device LD may output light corresponding to any one of red, green, and blue. In this specification, an embodiment in which the light emitting device LD is configured of an organic light emitting diode (OLED) will be described.

In various embodiments of the present disclosure, the structure of the pixels PX is not limited to that illustrated in FIG. 2 . According to an embodiment, the pixels PX are configured to compensate for the threshold voltage of the driving transistor DT or initialize the voltage of the gate electrode of the driving transistor DT and/or the voltage of the anode electrode of the light emitting device LD. It may further include one element.

2 illustrates an example in which the switching transistor ST and the driving transistor DT are NMOS transistors, but the present invention is not limited thereto. For example, at least some or all of the transistors constituting each pixel PX may be configured as PMOS transistors. In various embodiments, each of the switching transistor ST and the driving transistor DT is a low temperature poly silicon (LTPS) thin film transistor, an oxide thin film transistor, or a low temperature polycrystalline oxide (LTPO) thin film transistor. can be implemented.

3 is a perspective view of the display device illustrated in FIG. 1 according to some exemplary embodiments; The components of the display device 1 will be described in more detail with reference to FIG. 3 in conjunction with FIGS. 1 and 2 .

The display device 1 may be implemented in various forms. For example, the display device 1 may be implemented in a rectangular plate shape. However, the present invention is not limited thereto, and the display device 1 may have various shapes such as a square, a circle, an ellipse, and a polygon, and may have a shape in which some corners are treated as curved surfaces or a thickness changes in at least one area. . Also, all or part of the display device 1 may have flexibility.

The display panel 50 includes a display area DA and a non-display area NDA. The display area DA is an area in which the pixels PX are disposed and may be referred to as an active area. The non-display area NDA may be disposed around the display area DA. For example, the non-display area NDA may be disposed along the edge of the display area DA. The non-display area NDA may comprehensively mean an area other than the display area DA on the display panel 50 , and may be referred to as a non-active area.

As a driver for driving the pixel PX, for example, the gate driver 20 may be provided in the non-display area NDA. The gate driver 20 may be disposed adjacent to one or both sides of the display area DA in the non-display area NDA. As shown in FIG. 3 , the gate driver 20 may be formed in the non-display area NDA of the display panel 50 in a gate-in-panel manner.

A plurality of pads (not shown) may be provided in the non-display area NDA. The pads may be electrically connected to the data driver 30 and the circuit board 70 to be described later.

The display panel 50 may include wires for supplying electrical signals to the pixels PX. The wirings may include, for example, gate lines GL1 to GLn, data lines DL1 to DLm, and power lines PL1 and PL2.

The power lines PL1 and PL2 are electrically connected to the power supply unit 40 (or the timing control unit 10 ) through the connected pads, and a high potential provided from the power supply unit 40 (or the timing control unit 10 ) The driving power ELVDD and the low potential driving power ELVSS may be provided to the pixels PX.

The flexible film 60 may have one end attached to the pad area PA of the display panel 50 and the other end attached to the circuit board 70 to electrically connect the display panel 50 and the circuit board 70 . . The flexible film 60 may include a plurality of wires for electrically connecting the pads formed in the pad area PA and the wires of the circuit board 70 .

When the data driver 30 is made of a driving chip, the data driver 30 may be mounted on the flexible film 60 using a chip on film (COF) or chip on plastic (COP) method. The data driver 30 generates a data signal based on the image data DATA and the data driving control signal CONT2 received from the timing controller 10 , and outputs the data signal to the data lines DL1 to DLm through the connected pads. can do.

A plurality of circuits implemented with driving chips may be mounted on the circuit board 70 . The circuit board 70 may be a printed circuit board or a flexible printed circuit board, but the type of the circuit board 70 is not limited thereto.

The circuit board 70 may include a timing controller 10 and a power supply unit 40 mounted in the form of an integrated circuit. Although the timing control unit 10 and the power supply unit 40 are illustrated as separate components in FIG. 3 , the present embodiment is not limited thereto. That is, in various embodiments, the power supply unit 40 may be formed integrally with the timing control unit 10 , or the timing control unit 10 may be configured to perform the function of the power supply unit 40 .

4 is a cross-sectional view of a display panel according to some exemplary embodiments. FIG. 5 is an enlarged cross-sectional view of the CV region of FIG. 4 . Hereinafter, various embodiments will be described in conjunction with FIGS. 1 to 3 and FIG. 4 .

Referring to FIG. 4 , the display panel 50 includes a pixel area PXA in which circuit elements and a light emitting device LD constituting the pixel PX are formed, and a non-pixel area disposed around the pixel area PXA. (NPXA). The non-pixel area NPXA may include a boundary between adjacent pixels PX and/or the non-display area NDA.

As illustrated in FIG. 4 , the display panel 50 according to some exemplary embodiments includes a top-emitting light emitting device LD. When the light emitting device LD is a top emission type, light emitted from the organic emission layer may be emitted through a cathode electrode formed on the top surface. The emitted light passes through the color filter CF, and only a specific wavelength is selectively transmitted.

The display panel 50 includes a substrate SUB, a circuit element layer formed on the substrate SUB, a light emitting element layer, and a protective layer.

The substrate SUB is a base substrate of the display panel 50 and may be a light-transmitting substrate. The substrate SUB may be a rigid substrate including glass or tempered glass or a flexible substrate made of plastic. For example, the substrate SUB is formed of a plastic material such as polyimide (PI), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), or polycarbonate (PC). can be However, the material of the substrate SUB is not limited thereto.

The circuit element layer is formed on the substrate SUB, and may include circuit elements (eg, a transistor T and a capacitor, etc.) and wirings constituting the pixel PX.

A second power line PL2 to which the light blocking layer LS and the low potential driving voltage ELVSS are applied is disposed on the substrate SUB. The light blocking layer LS may be disposed to overlap the active pattern ACT of the transistor T, in particular, the channel CH on a plane, to protect the oxide semiconductor device from external light.

In the following embodiments, it will be described that the second power line PL2 is disposed on the substrate SUB, but the present invention is not limited thereto. That is, in various embodiments, the second power line PL2 may be replaced with an arbitrary electrode layer for applying an arbitrary signal or power to the pixel PX.

The buffer layer BUF is disposed on the substrate SUB to cover the light blocking layer LS and the second power line PL2 . The buffer layer BUF may prevent diffusion of ions or impurities from the substrate SUB and may block moisture penetration. In addition, the buffer layer BUF may improve the surface flatness of the substrate SUB. The buffer layer BUF may include an inorganic material such as an oxide and a nitride, an organic material, or an organic/inorganic composite, and may have a single-layer or multi-layer structure. For example, the buffer layer BUF may have a structure of three or more layers made of silicon oxide, silicon nitride, and silicon oxide.

An active pattern ACT may be formed on the buffer layer BUF. The active pattern ACT may be formed of a silicon-based semiconductor material or an oxide-based semiconductor material. Amorphous silicon or polycrystalline silicon may be used as the silicon-based semiconductor material. Examples of oxide-based semiconductor materials include indium tin gallium zinc oxide (InSnGaZnO), which is a quaternary metal oxide, indium gallium zinc oxide (InGaZnO), which is a ternary metal oxide, indium tin zinc oxide (InSnZnO), indium aluminum zinc oxide (InAlZnO), and tin. Gallium Zinc Oxide (SnGaZnO), Aluminum Gallium Zinc Oxide (AlGaZnO), Tin Aluminum Zinc Oxide (SnAlZnO), Binary Metal Oxide Indium Zinc Oxide (InZnO), Tin Zinc Oxide (SnZnO), Aluminum Zinc Oxide (AlZnO), Zinc Magnesium oxide (ZnMgO), tin magnesium oxide (SnMgO), indium magnesium oxide (InMgO), indium gallium oxide (InGaO), indium oxide (InO), tin oxide (SnO), zinc oxide (ZnO), etc. may be used. .

The active pattern ACT may include a source region SR and a drain region DR including p-type or n-type impurities, and a channel CH formed between the source region SR and the drain region DR. can

The gate insulating layer GI may be disposed to correspond to a region in which a gate electrode GE and a first connection electrode CN1 to be described later are to be formed. For example, the gate insulating layer GI may be formed on the channel CH of the active pattern ACT. Also, the gate insulating layer GI may be formed to be adjacent to the second power line PL2 or to overlap at least one region on the buffer layer BUF. The gate insulating layer GI may be a silicon oxide (SiOx), a silicon nitride (SiNx), or a multilayer thereof.

A first conductive layer may be disposed on the gate insulating layer GI. The first conductive layer may be a first gate layer.

The first conductive layer may include a gate electrode GE. The gate electrode GE may be disposed at a position corresponding to the channel CH of the active pattern ACT. The gate electrode GE is selected from the group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It is formed of any one or an alloy thereof. In addition, the gate electrode GE is a group consisting of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). It may be a multi-layer made of any one selected from or alloys thereof. For example, the gate electrode GE may be a double layer of molybdenum/aluminum-neodymium or molybdenum/aluminum.

The first conductive layer may further include a first connection electrode CN1. The first connection electrode CN1 may be disposed to be adjacent to the second power line PL2 or to overlap at least one region. The first connection electrode CN1 may be made of the same material as the gate electrode GE and may be formed through the same process as the gate electrode GE. However, the present invention is not limited thereto.

The first conductive layer may further include electrodes and driving lines of circuit devices such as, for example, the lower electrode of the storage capacitor Cst and the gate lines GL1 to GLn.

An interlayer insulating layer ILD may be formed on the first conductive layer. The interlayer insulating layer ILD covers the gate electrode GE and the first connection electrode CN1 constituting the first conductive layer. The interlayer insulating layer ILD may be a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a multilayer thereof.

In various embodiments, the interlayer insulating layer ILD may be formed of multiple layers, and conductive layers may be further formed between the multilayered interlayer insulating layers ILD. The conductive layers formed between the interlayer insulating layers ILD may further include electrodes and driving lines of circuit devices such as, for example, an auxiliary gate electrode of the transistor T and an upper electrode of the storage capacitor Cst. have.

A second conductive layer may be formed on the interlayer insulating layer ILD. The second conductive layer may be a source-drain layer.

The second conductive layer may include a source electrode SE and a drain electrode DE. The source electrode SE and the drain electrode DE are disposed to be spaced apart from each other by a predetermined distance on the interlayer insulating layer ILD. The source electrode SE and the drain electrode DE may be respectively connected to the source region SR and the drain region DR of the active pattern ACT through a contact hole passing through the interlayer insulating layer ILD.

The source electrode SE and the drain electrode DE include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and copper (Cu). ) may be formed as a single layer or multiple layers made of any one or an alloy thereof. When the source electrode SE and the drain electrode DE are multi-layered, they may be formed of a double layer of molybdenum/aluminum-neodymium, a triple layer of titanium/aluminum/titanium, molybdenum/aluminum/molybdenum or molybdenum/aluminum-neodymium/molybdenum. have.

The source electrode SE, the drain electrode DE, the gate electrode GE, and the active pattern ACT corresponding thereto may constitute the transistor T. The transistor T may be, for example, a driving transistor DT or a switching transistor ST. In FIG. 4 , the driving transistor DT in which the drain electrode DE is connected to the first electrode AE of the light emitting device LD is illustrated as an example.

The second conductive layer may further include a second connection electrode CN2 . The second connection electrode CN2 is connected to the second power line PL2 through a contact hole passing through the interlayer insulating layer ILD and the buffer layer BUF. Although not shown, the second connection electrode CN2 may be further connected to the first connection electrode CN1 through a contact hole penetrating the interlayer insulating layer ILD. The second connection electrode CN2 may be made of the same material as the source electrode SE and the drain electrode DE, and may be formed of a single layer or multiple layers.

In some embodiments of the present invention, the second conductive layer may further include various driving lines, for example, data lines DL1 to DLm, and power lines (eg, the first power line PL1 ). can

A first passivation layer PAS1 may be formed on the second conductive layer. The first passivation layer PAS1 is an insulating layer for protecting lower devices, and may be a silicon oxide layer (SiOx), a silicon nitride layer (SiNx), or a multilayer thereof.

An overcoat layer OC may be formed on the first passivation layer PAS1 . The overcoat layer OC may be a planarization layer for alleviating the step difference of the underlying structure, and may be composed of an organic material such as polyimide, benzocyclobutene series resin, or acrylate.

In various embodiments, any one of the first passivation layer PAS1 and the overcoat layer OC may be omitted.

The light emitting device layer is formed on the overcoat layer OC and includes light emitting devices LDs. The light emitting device LD includes a first electrode AE, an emission layer EML, and a second electrode CE. The first electrode AE may be an anode electrode and the second electrode CE may be a cathode electrode.

At least one of the first electrode AE and the second electrode CE may be a transmissive electrode and at least the other may be a reflective electrode. For example, as illustrated in FIG. 4 , when the light emitting device LD is a top emission type, the first electrode AE may be a reflective electrode, and the second electrode CE may be a transmissive electrode.

In some other embodiments, when the light emitting device LD is a double-sided emission type, both the first electrode AE and the second electrode CE may be a transmissive electrode. Hereinafter, a detailed configuration of the light emitting device LD will be described taking the case where the light emitting device LD is a top emission type as an example.

The first electrode AE is formed on the overcoat layer OC. The first electrode AE is connected to the drain electrode DE of the transistor T through a via hole passing through the overcoat layer OC and the first passivation layer PAS1 . The first electrode AE may be formed of a transparent conductive material such as indium tin oxide (ITO), indium zinc oxide (IZO), or zinc oxide (ZnO). When the first electrode AE is a reflective electrode, the first electrode AE may include a reflective layer. The reflective layer may be made of aluminum (Al), copper (Cu), silver (Ag), nickel (Ni), or an alloy thereof. In one embodiment, the reflective layer may be comprised of APC (silver/palladium/copper alloy).

The first bank BNK1 may be formed on the overcoat layer OC. The first bank BNK1 may be a pixel defining layer defining the emission area EA of the pixel PX. The first bank BNK1 may be formed to expose a portion of the first electrode AE, for example, a central portion, but cover the remaining area, for example, an edge. It may be desirable to design the exposed area of the first electrode AE to the maximum possible value so as to secure a sufficient aperture ratio. The exposed area of the first electrode AE not covered by the first bank BNK1 may be defined as the emission area EA of the pixel PX. In the emission area EA, the first electrode AE, the emission layer EML, and the second electrode CE are stacked to be in direct contact with each other. The first bank (BNK1) may be formed of an organic film such as acryl resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc. can

An emission layer EML is formed between the first electrode AE and the second electrode CE. Specifically, the emission layer EML may be formed to fill the trench formed in the emission area EA by the first bank BNK1 .

The emission layer EML may have a multilayer thin film structure including a light generation layer. For example, the emission layer EML may include a hole transport layer (HTL), an organic emission layer, and an electron transport layer (ETL). The hole transport layer serves to smoothly transfer holes injected from the first electrode AE to the organic emission layer. The organic emission layer may be formed of an organic material including a phosphorescent or fluorescent material. The electron transport layer serves to smoothly transfer electrons injected from the second electrode CE to the organic emission layer. The light emitting layer (EML) includes, in addition to the hole transport layer, the organic light emitting layer, and the electron transport layer, a hole injection layer (HIL), a hole blocking layer (HBL), an electron injection layer (EIL) and an electron blocking layer. It may further include an Electron Blocking Layer (EBL).

The emission layer EML may be formed in a tandem structure of two or more stacks. In this case, each of the stacks may include a hole transport layer, an organic emission layer, and an electron transport layer. When the emission layer EML is formed in a tandem structure of two or more stacks, a charge generation layer may be formed between the stacks. The charge generation layer may include an n-type charge generation layer disposed adjacent to the lower stack and a p-type charge generation layer disposed on the n-type charge generation layer and disposed adjacent to the upper stack. The n-type charge generation layer injects electrons into the lower stack, and the p-type charge generation layer injects holes into the upper stack. The n-type charge generating layer is an organic host material capable of transporting electrons to an alkali metal such as lithium (Li), sodium (Na), potassium (K), or cesium (Cs), or magnesium (Mg), strontium (Sr). The organic layer may be doped with an alkaline earth metal such as , barium (Ba), or radium (Ra). The p-type charge generating layer may be an organic layer in which a dopant is doped into an organic host material having hole transport capability.

The color of light generated in the light generating layer may be white, but the present invention is not limited thereto. For example, the color of light generated in the light generating layer of the emission layer EML may be any one of red, green, magenta, cyan, and yellow.

In some embodiments of the present invention, the light emitting layer EML is not limited to being formed in the light emitting area EA and may extend to cover the top surface of the first bank BNK1 and the top surface of the overcoat layer OC.

The second electrode CE is formed on the emission layer EML. The second electrode CE may be formed to cover the emission layer EML. The second electrode CE is formed of a transparent conductive material (TCO) or molybdenum (Mo), tungsten (W), silver (Ag), magnesium (Mg), aluminum (Al), and platinum that can transmit light. half such as (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) and alloys thereof It may be formed of a semi-transmissive conductive material. When the second electrode CE is formed of a transflective metal material, light output efficiency may be increased due to a micro cavity.

The protective layer is formed on the second electrode CE. The protective layer prevents oxygen or moisture from penetrating into the light emitting element LD. The protective layer may be formed in a multilayer structure including at least one inorganic layer and at least one organic layer. For example, the passivation layer may include a second passivation layer PAS2 , a cover layer PCL, and a third passivation layer PAS3 sequentially stacked.

The second passivation layer PAS2 is an inorganic layer and may be formed of at least one of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, and titanium oxide.

The second passivation layer PAS2 may be widely formed in the display area AA of the substrate SUB.

The cover layer PCL is an organic layer, which serves as a particle cover layer, and has a sufficient thickness to prevent particles from penetrating into the light emitting layer EML and the second electrode CE. can be formed with The cover layer PCL may be formed of a transparent material to allow light emitted from the emission layer EML to pass therethrough. The cover layer (PCL) is an organic material that can pass 99% or more of the light emitted from the light emitting layer (EML), for example, acrylic resin, epoxy resin, phenolic resin, poly It may be formed of an amide resin, a benzocyclobutene resin, or a polyimide resin, but the present invention is not limited thereto.

The third passivation layer PAS3 is an inorganic layer and may be formed of the same material as the second passivation layer PAS2 . For example, the third passivation layer PAS3 may be formed of at least one of silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide, and titanium oxide.

A second bank BNK2 , a pond PD and a color filter CF may be formed on the third passivation layer PAS3 . Specifically, the second bank BNK2 , the pond PD, and the color filter CF may be formed in the light conversion region CV on the third passivation layer PAS3 . The configuration of the second bank BNK2, the pond PD, and the color filter CF will be described in more detail with reference to FIG. 5 .

FIG. 5 is an enlarged cross-sectional view of the CV region of FIG. 4 .

Referring to FIG. 5 , it is illustrated that the pond PD and the color filter CF are stacked in an area partitioned by the second bank BNK2 .

The color conversion region CV is a region in which a color conversion element for selectively transmitting light emitted from the light emitting element LD according to a wavelength is formed. As illustrated, the color conversion area CV may be defined to correspond to the light emitting device LD or the light emitting area EA. In the color conversion region CV, the pond PD, the color filter CF, and the second bank BNK2 surrounding the sides of the pond PD and the color filter CF may be formed.

A second bank BNK2 may be formed in the color conversion region CV on the third passivation layer PAS3 . The second bank BNK2 is, for example, an organic material such as acryl resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc. It can be formed into a film.

In some embodiments of the present invention, a hydrophobic material may be included on the sidewall SW of the second bank BNK2. For example, the body of the second bank BNK2 may include a hydrophilic material, and a hydrophobic-treated layer may be formed on the surface of the second bank BNK2, but the present invention is not limited thereto. Alternatively, since the body of the second bank BNK2 includes a hydrophobic material, the sidewall SW may be hydrophobic.

In some other embodiments, the convex color according to the surface energy of the solution applied when the pond PD or the color filter CF is formed by the inkjet method regardless of the material constituting the sidewall SW of the second bank BNK2 The shape of the top surface TOP1 of the filter or the top surface TOP2 of the pond can be created.

The second bank BNK2 may be formed to partition an area in which the pond PD and the color filter CF are formed. That is, a trench surrounded by the second bank BNK2 may be formed, and the pond PD and the color filter CF may be formed in the trench. The trench formed by the second bank BNK2 may be aligned with the emission area EA and vertically overlapped.

The second bank BNK2 may expose at least a portion of the third passivation layer PAS3 . Specifically, the second bank BNK2 may expose the top surface TOP3 of the third passivation layer PAS3 corresponding to the light emitting device LD. The top surface TOP3 of the third passivation layer PAS3 exposed by the second bank BNK2 may be flat.

4 and 5 , the second bank BNK2 may have a tapered shape. However, the present invention is not limited thereto, and the second bank BNK2 may have a rectangular or reverse tapered shape.

A pond PD is formed on the third passivation layer PAS3 to fill the area partitioned by the second bank BNK2 .

In some embodiments of the present invention, the pond PD may include a transparent material. Since the light emitted from the light emitting device LD is selectively transmitted by the color filter CF through the pond PD, the pond PD may include a material having high transmittance.

For example, the pond PD may include a transparent organic material or a transparent inorganic material capable of transmitting light, and in some embodiments, the pond PD may include the same material as the color filter CF.

In some embodiments of the present invention, the pond PD may include the same material as the second bank BNK2. This is because, as described with reference to FIGS. 16 to 18 , the pond PD and the second bank BNK2 are formed through the same process. A more detailed description of the formation process of the pond PD will be described later with reference to FIG. 16 and the like.

The pond PD may be surrounded by the second bank BNK2 . Specifically, the side of the pond PD may be surrounded by the sidewall SW of the second bank BNK2 .

The pond PD may include a peripheral portion PP2 in contact with the sidewall SW of the second bank BNK2 and a central portion CP2 surrounded by the peripheral portion PP2 .

A distance from the top surface TOP3 of the third passivation layer PAS3 to the top surface of the central portion CP2 of the pond PD may be different from a distance from the top surface of the peripheral portion PP2 of the pond PD. Specifically, as shown in FIGS. 4 and 5 , the height of the upper surface TOP2 of the pond PD decreases from the central portion CP2 to the peripheral portion PP2 so that the central portion CP2 may have a convex shape.

The thickness T3 of the central portion CP2 of the pond PD and the thickness T4 of the peripheral portion PP2 are different from each other. In some embodiments of the present disclosure, the thickness T3 of the central portion CP2 of the pond PD may be greater than the thickness T4 of the peripheral portion PP2 .

As described above, the sidewall of the second bank BNK2 in contact with the peripheral portion PP2 of the pond PD has hydrophobicity. When the pond PD in a solution state is dropped inside the trench formed by the second bank BNK2, the pond PD is caused by a repulsive force between the organic solution constituting the pond PD and the sidewall SW of the second bank BNK2. ), a height difference of the upper surface TOP2 may occur between the central portion CP2 and the peripheral portion PP2 .

Accordingly, the profile of the upper surface TOP2 of the pond PD is not flat and has a convex shape in which the thickness decreases from the central portion CP2 to the peripheral portion PP2.

The pond PD may cover the top surface TOP3 of the third passivation layer PAS3 . As shown in FIG. 3 , the pond PD may cover all of the top surface TOP3 of the third passivation film PAS3 in the light conversion region CV exposed by the second bank BNK2, but the present invention This is not limited thereto.

In some embodiments, the pond PD may be exposed without covering a portion of the upper surface TOP3 of the third passivation layer PAS3 exposed by the second bank BNK2 . In this case, a portion of the upper surface of the third passivation layer PAS3 not covered by the pond PD may be exposed between the peripheral portion PP2 of the pond PD and the sidewall SW of the bank BNK2 .

The profile of the top surface TOP2 of the pond PD may be different from the profile of the top surface TOP3 of the third passivation layer PAS3 covered by the pond PD. That is, as shown, the top surface TOP3 of the third passivation layer PAS3 is flat, but the top surface TOP2 of the pond PD covering it may have a convex shape with a large central portion CP2.

A color filter CF may be formed on the pond PD. The color filter CF may transmit light emitted from the light emitting device LD, and may transmit, for example, any one of red light, green light, and blue light.

The color filter CF fills the trench defined by the sidewall SW of the second bank BNK2 and the top surface TOP2 of the pond PD, for example, with any one of red, green, or blue pigments in an inkjet method, It can be formed by curing it.

The color filter CF may include a peripheral portion PP1 in contact with the sidewall SW of the second bank BNK2 and a central portion CP1 surrounded by the peripheral portion PP1 .

A distance from the top surface TOP3 of the third passivation layer PAS3 to the top surface of the central portion CP1 of the color filter CF and a distance from the top surface of the peripheral portion PP1 of the color filter CF may be different from each other. Specifically, as shown in FIGS. 4 and 5 , the height of the upper surface TOP2 of the pond PD decreases from the central portion CP2 to the peripheral portion PP2 so that the central portion CP2 may have a convex shape. Accordingly, the profile of the upper surface TOP1 of the color filter CF may be the same as the profile of the upper surface TOP2 of the pond PD.

Since the profile of the upper surface TOP1 of the color filter CF is formed along the profile of the upper surface TOP2 of the pond PD, the color filter CF is conformal ( conformal) can be formed. That is, the thickness T1 of the central portion CP1 of the filter CF and the thickness T2 of the peripheral portion PP1 may be substantially the same. In the present specification, 'substantially the same' means not only exactly the same thing, but also includes a minute difference that may occur due to a margin or the like in a process.

As described above, the volume of the color filter CF may be contracted when time passes after formation by the surface tension of the pigment of the color filter CF formed by the inkjet method and the solvent being removed after the inkjet method. Due to this, the top surface profile of the color filter CF may not be maintained flat.

If the pond PD is not formed between the color filter CF and the third passivation layer PAS3 , it is assumed that the color filter CF is formed on the third passivation layer PAS3 . Due to the hydrophobic sidewall SW of the second bank BNK2 , it may have a convex shape in the direction of the top surface TOP3 of the color filter CF like the shape of the pond PD of FIG. 5 .

Due to this, a thickness difference occurs between the central portion and the peripheral portion of the color filter CF, and when the light emitted from the light emitting device LD passes through the color filter CF, the central portion due to the difference in the thickness of the color filter CF There may be a difference in the amount of light transmitted from the periphery and the periphery. Deviation in transmittance of the color filter CF may decrease color purity, increase turbidity of an image displayed from the panel, and increase the difficulty of spectroscopic inspection after panel manufacturing.

In the display device according to the exemplary embodiment illustrated in FIGS. 4 and 5 , the thickness of the color filter CF may be substantially the same due to the pond PD formed thereunder. The color filter CF is formed by injecting a pigment using an inkjet method, and the ink injected onto the pond PD is evenly spread along the profile of the upper surface TOP2 of the pond PD.

The lower surface of the color filter CF is formed along the shape of the upper surface TOP2 of the convexly formed pond PD. Accordingly, the color filter CF may have the same upper and lower profiles.

Accordingly, the thickness of the color filter CF may be substantially maintained at the central portion CP1 and the peripheral portion PP1 . As the thickness of the color filter CF is constant, the amount of light transmitted from the central portion CP1 and the peripheral portion PP1 is also kept constant, and the turbidity of the image displayed on the panel and the ease of spectroscopic inspection due to the improvement of the color purity of the transmitted light can be improved

6 is a cross-sectional view of a display device according to another exemplary embodiment, and FIG. 7 is an enlarged cross-sectional view of a CV region of FIG. 6 . The same points as those of the embodiment described above with reference to FIGS. 4 and 5 will be omitted and differences will be mainly described.

6 and 7 , a hydrophilic material may be included on the sidewall SW of the second bank BNK2. For example, the body of the second bank BNK2 may include a hydrophobic material, and a hydrophilic layer may be formed on the surface of the second bank BNK2, but the present invention is not limited thereto. Alternatively, since the body of the second bank BNK2 includes a hydrophilic material, the sidewall SW may exhibit hydrophilicity.

In some other embodiments, the concave color according to the surface energy of the solution applied when the pond PD or the color filter CF is formed by the inkjet method regardless of the material constituting the sidewall SW of the second bank BNK2 The shape of the top surface TOP1 of the filter or the top surface TOP2 of the convex pond can be created.

When the pond PD in a solution state is dropped inside the trench formed by the second bank BNK2, the pond PD is caused by the tension between the organic solution constituting the pond PD and the sidewall SW of the second bank BNK2. A difference in height of the upper surface TOP2 may occur between the central portion CP2 and the peripheral portion PP2 of the PD.

The thickness T3 of the central portion CP2 of the pond PD may be smaller than the thickness T4 of the peripheral portion PP2. That is, as the height of the upper surface TOP2 increases from the central portion CP2 to the peripheral portion PP2 of the pond PD, the central portion CP2 may have a concave shape.

The profile of the upper surface TOP1 of the color filter CF formed on the pond PD may be the same as the profile of the upper surface TOP2 of the pond PD. Accordingly, the upper surface TOP1 of the color filter CF may have a concave shape in which the height decreases from the central portion CP1 to the peripheral portion PP1 .

The thickness of the color filter CF may be substantially the same due to the pond PD formed thereunder. That is, the color filter CF has a concave shape in the direction of the top surface TOP3 of the third passivation film PAS3, but is concave from the bottom along the shape of the top surface TOP2 of the pond PD. The lower surface of the color filter CF As this is formed, the thickness of the color filter CF may be maintained substantially the same in the central portion CP1 and the peripheral portion PP1 .

8 to 15 are diagrams for explaining a method of manufacturing a display panel according to some exemplary embodiments.

Referring to FIG. 8 , the light blocking layer LS and the second power line PL2 are formed on the substrate SUB, and the buffer layer BUF is formed thereon. An active pattern ACT is formed on the buffer layer BUF. The active pattern ACT is doped with p-type or n-type impurities to form a source region SR and a drain region DR, and a channel CH is formed between the source region SR and the drain region DR. can be

A gate insulating layer GI may be formed on the active pattern ACT. The gate insulating layer GI may be formed at a position connected to the gate electrode GE and the first connection electrode CN1 . A gate electrode GE and a first connection electrode CN1 are formed on the gate insulating layer GI. After that, an interlayer insulating layer ILD is formed. The interlayer insulating layer ILD may cover the gate electrode GE and the first connection electrode CN1 .

A source electrode SE and a drain electrode DE are formed on the interlayer insulating layer ILD. The source electrode SE and the drain electrode DE may be respectively connected to the source region SR and the drain region DR of the active pattern ACT through a contact hole passing through the interlayer insulating layer ILD.

A second connection electrode CN2 is further formed on the interlayer insulating layer ILD. The second connection electrode CN2 is connected to the second power line PL2 through a contact hole passing through the interlayer insulating layer ILD and the buffer layer BUF.

Referring to FIG. 9 , a first passivation layer PAS1 may be formed. The first passivation layer PAS1 may cover the source electrode SE, the drain electrode DE, and the second connection electrode CN2 .

Forming the first passivation layer PAS1 may include, for example, depositing an insulating material such as silicon oxide or silicon nitride, but the present invention is not limited thereto.

Referring to FIG. 10 , an overcoat layer OC is formed on the first passivation layer PAS1 . The overcoat layer OC may be patterned to be formed in the pixel area PXA.

The overcoat layer OC may be formed by, for example, depositing an organic material, but is not limited thereto, and may be formed by depositing an organic material through spin coating and then baking.

A first electrode AE is formed on the overcoat layer OC. The first electrode AE is connected to the drain electrode DE through a via hole passing through the overcoat layer OC and the first passivation layer PAS1 . The first electrode AE may be formed by, for example, physical vapor deposition such as sputtering.

Subsequently, a first bank BNK1 is formed. The first bank BNK1 may be formed to cover the edge of the first electrode AE and the overcoat layer OC. The first bank BNK1 may be patterned to be formed in the pixel area PXA. The patterned first bank BNK1 may expose the first electrode AE in the emission area EA.

Referring to FIG. 11 , an emission layer EML is formed on the first electrode AE. The emission layer EML may be formed to cover the upper surface of the first electrode AE exposed in the emission area EA. In some embodiments of the present invention, the emission layer EML may be formed by an evaporation deposition method.

10 , the emission layer EML may be formed to cover the first bank BNK1 in some embodiments.

In some other embodiments of the present invention, unlike shown in FIG. 10 , the emission layer EML may be formed according to a printing process of applying a liquid material in the trench formed in the first bank BNK1 . As the liquid material is applied and then cured, the upper surface of the light emitting layer EML may not be flat unlike that illustrated in FIG. 10 .

Next, the second electrode CE is formed on the emission layer EML. The second electrode CE may be formed by, for example, sputtering a conductive material. The second electrode CE may contact the emission layer EML in the emission area EA.

A second passivation layer PAS2 may be formed to cover the second electrode CE. The second passivation layer PAS2 may cover all or part of the second electrode CE.

Referring to FIG. 12 , a cover layer PCL and a third passivation layer PAS3 may be sequentially formed. The cover layer PCL and the third passivation layer PAS3 may be formed by depositing an organic material and an inorganic material, respectively.

Referring to FIG. 13 , a second bank BNK2 is formed on the third passivation layer PAS3 . The second bank BNK2 may be formed by forming an insulating material on the third passivation layer PAS3 and patterning the insulating material. The second bank BNK2 may be patterned to expose the top surface TOP3 of the third passivation layer PAS3 vertically overlapping the emission area EA.

Referring to FIG. 14 , an organic solution is injected onto the third passivation layer PAS3 by an inkjet method and cured to form a pond PD. The pond PD may partially fill a trench defined by the top surface TOP3 of the third passivation layer PAS3 and the sidewall SW of the second bank BNK2 .

When the surface of the sidewall SW of the second bank BNK2 is hydrophobic, the upper surface TOP2 of the pond PD may have an upwardly convex shape as shown in FIG. 14 . Conversely, when the surface of the sidewall SW of the second bank BNK2 is hydrophilic, the top surface TOP2 of the pond PD may have a downward concave shape as shown in FIG. 7 .

Referring to FIG. 15 , a color filter CF is formed by injecting a pigment onto the pond PD by an inkjet method and curing it. The injected pigment conformally forms the color filter CF on the pond PD along the profile of the top surface TOP2 of the convexly formed pond PD. The second bank BNK2 may function as a dam that prevents pigments of different colors from being mixed when forming the color filter CF.

16 to 18 are diagrams for explaining a method of manufacturing a display panel according to another exemplary embodiment of the present invention. In the following drawings, a manufacturing process for simultaneously forming the second bank BNK2 and the pond PD on the third passivation layer PAS3 is illustrated.

Referring to FIG. 16 , a bank insulating layer BI and a photoresist 110 are sequentially formed on the third passivation layer PAS3 .

After the halftone mask 210 is disposed to expose the photoresist 110 , exposure is performed. The halftone mask 210 includes a light blocking portion 211 , a semi-transmissive portion 212 , and a light transmitting portion 213 . The halftone mask 210 may be disposed such that the semi-transmissive portion 212 corresponds to the emission area EA.

Light is irradiated through the halftone mask 210 to selectively expose the photoresist 110 .

Referring to FIG. 17 , as a result of selective exposure to the photoresist 110 , the photoresist 110 includes a first portion 111 and a second portion 112 surrounded by the first portion 111 . A pattern 115 may be formed.

Referring to FIG. 18 , the bank insulating layer BI is patterned using the photoresist pattern 115 as an etch mask. As a result of patterning, a second bank BNK2 and a pond PD may be formed. The height of the upper surface of the patterned pond PD using the second portion 112 of the photoresist exposed by the semi-transmissive part 212 as an etching mask may be lower than the height of the upper surface of the second bank BNK2. . Accordingly, a trench defined by the upper surface of the pond PD and the side surface of the second bank BNK2 may be formed. The top surface of the pond PD may be convex as shown in FIG. 18 or concave as shown in FIGS. 6 and 7 according to etching conditions for patterning the bank insulating layer BI.

Since the second bank BNK2 and the pond PD are formed in the same process of patterning the bank insulating layer BI, the second bank BNK2 and the pond PD may be integrally formed.

Then, referring to FIG. 4 , a color filter CF is formed by injecting a pigment onto the pond PD and curing it.

Those of ordinary skill in the art to which the present invention pertains will understand that the present invention may be embodied in other specific forms without changing the technical spirit or essential features thereof. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The scope of the present invention is indicated by the claims described later rather than the detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts are included in the scope of the present invention. should be interpreted

1: display device 10: timing controller
20: gate driver 30: data driver
40: power supply 50: display panel

Claims (19)

Board;
a light emitting device disposed on the substrate;
a protective layer formed on the light emitting device;
a color filter formed on the passivation layer to correspond to the light emitting device;
a bank formed to surround a side surface of the color filter; and
Comprising a pond formed between the protective layer and the color filter,
The color filter includes a peripheral portion in contact with the bank and a central portion surrounded by the peripheral portion,
The distance from the top surface of the device protection layer to the top surface of the peripheral portion and the distance from the top surface of the device protection layer to the top surface of the center are different

display device. According to claim 1,
the thickness of the central portion and the thickness of the periphery are substantially equal;
display device. According to claim 1,
The top profile of the color filter is formed along the top profile of the pond,
display device. 4. The method of claim 3,
The pond is
and an upper surface formed convexly so that the height is lowered from the central part of the pond to the peripheral part of the pond,
wherein the color filter is convexly formed such that a height of an upper surface of the color filter decreases from a central portion of the color filter toward a peripheral portion of the color filter.
display device. 5. The method of claim 4,
wherein the sidewalls of the bank comprise a hydrophobic material;
display device. 4. The method of claim 3,
The pond is
Including an upper surface concavely formed so as to increase in height from the central portion of the pond to the peripheral portion of the pond,
wherein the color filter is concavely formed such that a height of an upper surface of the color filter increases from a central portion of the color filter toward a peripheral portion of the color filter.
display device. 7. The method of claim 6,
wherein the sidewalls of the bank comprise a hydrophilic material;
display device. According to claim 1,
wherein the pond and the bank contain the same material;
display device. According to claim 1,
wherein the pond and the color filter contain the same material,
display device. According to claim 1,
The top surface of the protective layer exposed by the bank is flat,
display device. forming a light emitting device on a substrate;
forming a protective layer covering the light emitting device;
on the protective layer. forming a bank exposing an upper surface of the protective layer corresponding to the light emitting device;
forming a pond to cover an upper surface of the protective layer exposed by the bank; and
Including the step of injecting ink on the pond to form a color filter,
The color filter includes a peripheral portion in contact with the bank and a central portion surrounded by the peripheral portion,
The distance from the top surface of the device protection layer to the top surface of the peripheral portion and the distance from the top surface of the device protection layer to the top surface of the central portion are different from each other,
A method of manufacturing a display device. 12. The method of claim 11,
the thickness of the central portion and the thickness of the periphery are substantially equal;
A method of manufacturing a display device. 13. The method of claim 12,
The step of forming the pond,
Including the step of hardening by injecting an organic solution on the protective layer,
A method of manufacturing a display device. 12. The method of claim 11,
The step of forming the bank and the step of forming the pond,
sequentially forming an insulating film and a photoresist on the protective layer;
forming a photoresist pattern by selectively exposing the photoresist to light using a halftone mask in which a semi-transmissive portion is disposed to correspond to the light emitting device; and
using the photoresist pattern as an etch mask to etch the insulating layer to form the bank and the pond,
A method of manufacturing a display device. 12. The method of claim 11,
The top profile of the color filter is formed along the top profile of the pond,
A method of manufacturing a display device. 15. The method of claim 14,
The pond is
and an upper surface formed convexly so that the height is lowered from the central part of the pond to the peripheral part of the pond,
wherein the color filter is convexly formed such that a height of an upper surface of the color filter decreases from a central portion of the color filter toward a peripheral portion of the color filter.
A method of manufacturing a display device. 17. The method of claim 16,
The side of the bank comprises a hydrophobic material,
A method of manufacturing a display device. 18. The method of claim 17,
The pond is
Including an upper surface concavely formed so as to increase in height from the central portion of the pond to the peripheral portion of the pond,
wherein the color filter is concavely formed such that a height of an upper surface of the color filter increases from a central portion of the color filter toward a peripheral portion of the color filter.
A method of manufacturing a display device. 17. The method of claim 16,
wherein the sidewalls of the bank comprise a hydrophilic material;
A method of manufacturing a display device.

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