KR20210083090A - Semiconductor memory device and method of operating the same - Google Patents

Abstract

The present technology relates to a semiconductor memory device and to an operating method thereof. The semiconductor memory device includes: a memory block connected to a plurality of word lines and a plurality of bit lines; a peripheral circuit for performing a program operation or a read operation on the memory block; and control logic controlling the peripheral circuit so that a word line overdrive section and a bit line overdrive section overlap, during the bit line precharge operation during the program operation or the read operation.

Description

BACKGROUND ART Semiconductor memory device and method of operating the same

The present invention relates to an electronic device, and more particularly, to a semiconductor memory device and a method of operating the same.

Among semiconductor devices, a semiconductor memory device is largely divided into a volatile memory device and a nonvolatile memory device.

Although the nonvolatile memory device has relatively slow write and read speeds, it retains stored data even when power supply is cut off. Accordingly, a nonvolatile memory device is used to store data to be maintained regardless of whether power is supplied or not. Nonvolatile memory devices include ROM (Read Only Memory), MROM (Mask ROM), PROM (Programmable ROM), EPROM (Erasable Programmable ROM), EEPROM (Electrically Erasable Programmable ROM), Flash memory, PRAM (Phase change) Random Access Memory), Magnetic RAM (MRAM), Resistive RAM (RRAM), Ferroelectric RAM (FRAM), and the like. The flash memory is divided into a NOR type and a NAND type.

Flash memory has the advantage of RAM, which allows data to be programmed and erased, and the advantage of ROM, which can preserve stored data even when power supply is cut off. Flash memory is widely used as a storage medium for portable electronic devices such as digital cameras, personal digital assistants (PDAs), and MP3 players.

The flash memory device may be divided into a two-dimensional semiconductor memory device in which a memory string is formed horizontally on a semiconductor substrate and a three-dimensional semiconductor memory device in which the memory string is formed vertically on the semiconductor substrate.

A three-dimensional semiconductor memory device is a memory device designed to overcome the limitations of integration of a two-dimensional semiconductor device, and includes a plurality of memory strings vertically formed on a semiconductor substrate. The memory strings include a drain select transistor, memory cells and a source select transistor coupled in series between a bit line and a source line.

SUMMARY Embodiments of the present invention provide a semiconductor memory device capable of improving a precharge operation time of bit lines during operation of the semiconductor memory device, and a method of operating the same.

A semiconductor memory device according to an embodiment of the present invention includes a memory block connected to a plurality of word lines and a plurality of bit lines; a peripheral circuit for performing a program operation or a read operation on the memory block; and a control logic for controlling the peripheral circuit so that a word line overdrive section and a bit line overdrive section overlap during a bit line precharge operation during the program operation or the read operation.

A semiconductor memory device according to an embodiment of the present invention includes a memory block connected to a plurality of word lines and a plurality of bit lines; a peripheral circuit for applying a set voltage to the plurality of word lines and the plurality of bit lines; and a word line overdrive period in which a first overdrive voltage is applied to a selected one of the plurality of word lines during a bit line precharge operation and a bit line over in which a second overdrive voltage is applied to the plurality of bit lines. and control logic for controlling the peripheral circuit so that the drive section partially overlaps.

A method of operating a semiconductor memory device according to an embodiment of the present invention includes: applying a first overdrive voltage to a selected word line in a word line overdrive period; applying a second overdrive voltage to the bit lines in a bit line overdrive period; applying a first target voltage to the selected word line after the word line overdrive period; and precharging the bit lines to a second target voltage after the bit line overdrive period, wherein the word line overdrive period and the bit line overdrive period partially overlap.

According to the present technology, the operation time of the semiconductor memory device may be improved by partially overlapping the overdrive period of the word line and the overdrive period of the bit lines to quickly perform the precharge operation of the bit lines.

1 is a block diagram illustrating a memory system including a semiconductor memory device according to an embodiment of the present invention.
2 is a diagram for explaining a semiconductor memory device according to an embodiment of the present invention.
3 is a diagram for explaining three-dimensional memory blocks.
FIG. 4 is a circuit diagram specifically explaining any one of the memory blocks shown in FIG. 3 .
FIG. 5 is a circuit diagram for explaining the memory strings shown in FIG. 4 .
6 is a circuit diagram illustrating a bit line precharge circuit included in the page buffers of FIG. 2 .
7 is a flowchart illustrating a method of operating a semiconductor memory device according to an exemplary embodiment of the present invention.
8 is a waveform diagram of operating voltages for explaining a method of operating a semiconductor memory device according to an exemplary embodiment of the present invention.
9 is a diagram for describing another embodiment of a memory system.
10 is a diagram for describing another embodiment of a memory system.
11 is a diagram for describing another embodiment of a memory system.
12 is a diagram for describing another embodiment of a memory system.

Specific structural or functional descriptions of the embodiments according to the concept of the present invention disclosed in this specification or application are only exemplified for the purpose of explaining the embodiments according to the concept of the present invention, and implementation according to the concept of the present invention Examples may be embodied in various forms and should not be construed as being limited to the embodiments described in the present specification or application.

Hereinafter, in order to describe in detail enough that a person of ordinary skill in the art to which the present invention pertains can easily implement the technical idea of the present invention, an embodiment of the present invention will be described with reference to the accompanying drawings. .

1 is a block diagram illustrating a memory system including a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 1 , a memory system 1000 includes a memory device 1100 , a controller 1200 , and a host 1300 . The memory device 1100 includes a plurality of semiconductor memory devices (Semiconductor Memory) 100 . The plurality of semiconductor memory devices 100 may be divided into a plurality of groups GR1 to GRn. In the embodiment of the present invention, the host 1300 is illustrated and described as being included in the memory system 1000 , but the memory system 1000 includes only the controller 1200 and the memory device 1100 , and the host 1300 is It may be configured to be disposed outside the memory system 1000 .

In FIG. 1 , the plurality of groups GR1 to GRn of the memory device 1100 are illustrated to communicate with the controller 1200 through first to nth channels CH1 to CHn, respectively. Each semiconductor memory device 100 will be described later with reference to FIG. 2 .

Each group GR1 to GRn is configured to communicate with the controller 1200 through one common channel. The controller 1200 is configured to control the plurality of semiconductor memories 100 of the memory device 1100 through the plurality of channels CH1 to CHn.

According to an embodiment of the present invention, the plurality of semiconductor memory devices 100 included in the memory device 1100 have an overdrive section of a word line during a bit line precharge operation for precharging bit lines during general operations such as a program operation and a read operation. The operation speed of the semiconductor memory device 100 may be improved by performing the bit line precharge operation faster by overlapping the overdrive period of the bit line and the bit line. For example, after applying the overdrive voltage to the word line during the bit line precharge operation, the bit line overdrive voltage may be applied to the bit line before the word line overdrive period ends. That is, during the bit line precharge operation, the semiconductor memory device 100 may start the overdrive period of the bit line before the overdrive period of the word line ends.

The controller 1200 is connected between the host 1300 and the memory device 1100 . The controller 1200 is configured to access the memory device 1100 in response to a request from the host 1300 . For example, the controller 1200 is configured to control read, write, erase, and background operations of the memory device 1100 in response to a host command Host_CMD received from the host 1300 . During a write operation, the host 1300 may transmit the address ADD and data DATA together with the host command Host_CMD, and during a read operation, the host 1300 may transmit the address ADD together with the host command Host_CMD. During a write operation, the controller 1200 transmits a command corresponding to the write operation and data DATA to be programmed to the memory device 1100 . During a read operation, the controller 1200 transmits a command corresponding to the read operation to the memory device 1100 , receives read data DATA from the memory device 1100 , and transmits the received data DATA to the host 1300 . ) is sent to The controller 1200 is configured to provide an interface between the memory device 1100 and the host 1300 . The controller 1200 is configured to drive firmware for controlling the memory device 1100 .

The host 1300 includes a portable electronic device such as a computer, PDA, PMP, MP3 player, camera, camcorder, mobile phone, and the like. The host 1300 may request a write operation, a read operation, an erase operation, etc. of the memory system 1000 through the host command Host_CMD. The host 1300 transmits a host command (Host_CMD), data (DATA), and an address (ADD) corresponding to a write operation to the controller 1200 for a write operation of the memory device 1100 , and performs a read operation for the read operation. A host command (Host_CMD) and an address (ADD) corresponding to may be transmitted to the controller 1200 . In this case, the address ADD may be a logical address of data.

The controller 1200 and the memory device 1100 may be integrated into one semiconductor memory device. In an exemplary embodiment, the controller 1200 and the memory device 1100 may be integrated into one semiconductor memory device to constitute a memory card. For example, the controller 1200 and the memory device 1100 are integrated into one semiconductor memory device, such as a personal computer memory card international association (PCMCIA), a compact flash card (CF), and a smart media card (SM, SMC). ), memory stick, multimedia card (MMC, RS-MMC, MMCmicro), SD card (SD, miniSD, microSD, SDHC), universal flash memory (UFS), etc.

As another example, the memory system 1000 may be a computer, an Ultra Mobile PC (UMPC), a workstation, a net-book, a Personal Digital Assistants (PDA), a portable computer, a web tablet, a wireless A wireless phone, a mobile phone, a smart phone, an e-book, a portable multimedia player (PMP), a portable game machine, a navigation device, a black box ), digital camera, 3-dimensional television, digital audio recorder, digital audio player, digital picture recorder, digital image player ( digital picture player, digital video recorder, digital video player, device capable of transmitting and receiving information in a wireless environment, one of various electronic devices constituting a home network, composing a computer network It is provided as one of various components of an electronic device, such as one of various electronic devices constituting a telematics network, one of various electronic devices constituting a telematics network, an RFID device, or one of various components constituting a computing system.

As an exemplary embodiment, the memory device 1100 or the memory system 1000 may be mounted in various types of packages. For example, the memory device 1100 or the memory system 1000 may include Package on Package (PoP), Ball grid arrays (BGAs), Chip scale packages (CSPs), Plastic Leaded Chip Carrier (PLCC), and Plastic Dual In Line Package. (PDIP), Die in Waffle Pack, Die in Wafer Form, Chip On Board(COB), Ceramic Dual In Line Package(CERDIP), Plastic Metric Quad Flat Pack(MQFP), Thin Quad Flatpack(TQFP), Small Outline(SOIC) ), Shrink Small Outline Package(SSOP), Thin Small Outline(TSOP), System In Package(SIP), Multi Chip Package(MCP), Wafer-level Fabricated Package(WFP), Wafer-Level Processed Stack Package(WSP), etc. It can be packaged and mounted in the same way.

2 is a diagram for explaining a semiconductor memory device according to an embodiment of the present invention.

Referring to FIG. 2 , the semiconductor memory device 100 includes a memory cell array 110 , an address decoder 120 , a read/write circuit 130 , a control logic 140 , and a voltage generation circuit 150 . . The address decoder 120 , the read/write circuit 130 , and the voltage generation circuit 150 may be defined as a peripheral circuit 160 that performs a read operation on the memory cell array 110 .

The memory cell array 110 includes a plurality of memory blocks BLK1 to BLKz. The plurality of memory blocks BLK1 to BLKz are connected to the address decoder 120 through word lines WL. The plurality of memory blocks BLK1 to BLKz are connected to the read and write circuit 130 through bit lines BL1 to BLm. Each of the plurality of memory blocks BLK1 to BLKz includes a plurality of memory cells. In an embodiment, the plurality of memory cells are nonvolatile memory cells. A plurality of memory cells connected to one word line among the plurality of memory cells may be defined as one page. That is, the memory cell array 110 may be composed of a plurality of pages.

Each of the plurality of memory blocks BLK1 to BLKz of the memory cell array 110 includes a plurality of memory strings. Each of the plurality of memory strings includes a drain select transistor coupled in series between a bit line and a source line, a plurality of memory cells, and a source select transistor. In addition, each of the plurality of memory strings may include a pass transistor between the source select transistor and the memory cells and between the drain select transistor and the memory cells, and may further include a pipe gate transistor between the memory cells. A detailed description of the memory cell array 110 will be provided later.

The address decoder 120 is connected to the memory cell array 110 through word lines WL. The address decoder 120 is configured to operate on the address decoder control signals AD_signals generated by the control logic 140 . The address decoder 120 receives the address ADDR through an input/output buffer (not shown) inside the semiconductor memory device 100 .

The address decoder 120 generates a program voltage Vpgm or a read voltage Vread, a pass voltage Vpass, and a drain select line voltage (Vpgm) generated by the voltage generation circuit 150 during a bit line precharge operation during a program operation or a read operation. V _DSL ), and a plurality of operating voltages including a source select line voltage V _SSL , decode a row address of the received address ADDR and select a plurality of memory cells of the memory cell array 110 according to the decoded row address , may be applied to drain select transistors and source select transistors.

The address decoder 120 is configured to decode a column address among the received addresses ADDR. The address decoder 120 transmits the decoded column address Yi to the read/write circuit 130 .

The address ADDR received during a program operation or a read operation includes a block address, a row address, and a column address. The address decoder 120 selects one memory block and one word line according to the block address and the row address. The column address is decoded by the address decoder 120 and provided to the read and write circuit 130 .

The address decoder 120 may include a block decoder, a row decoder, a column decoder, an address buffer, and the like.

The read and write circuit 130 includes a plurality of page buffers PB1 to PBm. The plurality of page buffers PB1 to PBm are connected to the memory cell array 110 through bit lines BL1 to BLm. Each of the plurality of page buffers PB1 to PBm temporarily stores data to be programmed received from the controller 1200 of FIG. 1 during a program operation, and the bit lines BL1 to PBm according to the temporarily stored data DATA. BLm) to control the potential level. In addition, the read and write circuit 130 performs a read operation by sensing the potential level or current amount of the bit lines BL1 to BLm during the read operation, and transmits the read data DATA to the controller 1200 of FIG. 1 . print out

Each of the plurality of page buffers PB1 to PBm precharges the corresponding bit lines BL1 to BLm to a set level during the bit line precharge operation during the program operation or the read operation, and the bit line during the bit line precharge operation During the overdrive period, an overdrive voltage may be applied to the bit lines to quickly precharge the bit lines.

The read/write circuit 130 operates in response to the page buffer control signals PB_signals output from the control logic 140 .

In an exemplary embodiment, the read and write circuit 130 may include page buffers (or page registers), a column selection circuit, and the like.

The voltage generating circuit 150 may generate a program voltage Vpgm, a pass voltage Vpass, and a drain selection line voltage V _{DSL according to the control of the voltage generating circuit control signals VG_signals output from the control logic 140 during a program operation.} ), and a plurality of operating voltages including the source selection line voltage V _SSL are generated and output to the address decoder 120 . In addition, the voltage generating circuit 150 may have a read voltage Vread, a pass voltage Vpass, and a drain selection line voltage V according to the control of the voltage generating circuit control signals VG_signals output from the control logic 140 during a read operation. _DSL ) and a plurality of operating voltages including the source selection line voltage V _SSL are generated and output to the address decoder 120 .

The voltage generation circuit 150 generates a pass voltage Vpass to be applied to unselected word lines during a bit line precharge operation during a program operation or a read operation, and an operating voltage (program voltage (program voltage) Vpgm) or read voltage (Vread)). The voltage generation circuit 150 generates an overdrive voltage to be applied to the selected word line in the word line overdrive section during the bit line precharge operation, and the overdrive voltage has a potential level higher than the operating voltage Vpgm or Vread. can

Additionally, the voltage generation circuit 150 may generate an erase voltage Vera during an erase operation and provide it to the memory cell array 110 .

The control logic 140 is connected to the address decoder 120 , the read and write circuit 130 , and the voltage generation circuit 150 . The control logic 140 receives the command CMD through an input/output buffer (not shown) of the semiconductor memory device 100 . The control logic 140 is configured to control general operations of the semiconductor memory device 100 in response to the command CMD. For example, the control logic 140 receives a command CMD corresponding to a program operation or a read operation, and receives address decoder control signals AD_signals for controlling the address decoder 120 in response to the received command CMD. ), the page buffer control signals PB_signals for controlling the read and write circuit 130 , and voltage generation circuit control signals VG_signals for controlling the voltage generation circuit 150 are generated and output.

The control logic 140 according to an embodiment of the present invention applies the overdrive voltage to the bit lines and the word line overdrive section for applying the overdrive voltage to the selected word line during the bit line precharge operation during the program operation or the read operation. The address decoder 120 , the read/write circuit 130 , and the voltage generation circuit 150 may be controlled so that the applied bit line overdrive period overlaps.

3 is a diagram for explaining three-dimensional memory blocks.

Referring to FIG. 3 , the three-dimensional memory blocks BLK1 to BLKz may be arranged to be spaced apart from each other along the direction Y in which the bit lines BL1 to BLm extend. For example, the first to z-th memory blocks BLK1 to BLKz may be arranged to be spaced apart from each other in the second direction Y, and include a plurality of memory cells stacked along the third direction Z. can do. The configuration of any one of the first to z-th memory blocks BLK1 to BLKz will be described in detail with reference to FIGS. 4 and 5 to be described later.

FIG. 4 is a circuit diagram specifically explaining any one of the memory blocks shown in FIG. 3 .

FIG. 5 is a circuit diagram for explaining the memory strings shown in FIG. 4 .

4 and 5 , each memory string ST may be connected between bit lines BL1 to BLm and a source line SL. The memory string ST connected between the first bit line BL1 and the source line SL will be described as an example.

The memory string ST includes a source select transistor SST, memory cells F1 to Fn; n is a positive integer, connected in series between the source line SL and the first bit line BL1; It may include a drain select transistor (DST). Gates of the source select transistors SST included in the different memory strings ST connected to the different bit lines BL1 to BLm may be connected to the first source select line SSL0 and the second source select line (SSL1) can be connected. For example, source select transistors adjacent to each other in the second direction Y among the source select transistors SST may be connected to the same source select line. For example, assuming that the source select transistors SST are sequentially arranged along the second direction Y, the other memory strings SST are arranged in the first direction X from the first source select transistor SST. The gates of the source select transistors SST included in ST and the source select transistors SST arranged in the first direction X from the second source select transistor SST and included in other memory strings ST. ) may be connected to the first source select line SSL0. In addition, gates of the source select transistors SST arranged in the first direction X from the third source select transistor SST and included in other memory strings ST and the fourth source select transistor SST Gates of the source select transistors SST arranged in the first direction X and included in the other memory strings ST may be connected to the second source select line SSL1 .

Gates of the memory cells F1 to Fn may be connected to the word lines WL1 to WLn, and gates of the drain select transistors DST may be any one of the first to fourth drain select lines DSL0 to DSL3. can be connected to

Among the drain select transistors DST, gates of transistors arranged in the first direction (X) are commonly connected to the same drain select line (eg, DSL0), but transistors arranged in the second direction (Y) are different from each other. It may be connected to the drain select lines DSL1 to DSL3. For example, assuming that the drain select transistors DST are sequentially arranged along the second direction Y, the other memory strings DST are arranged in the first direction X from the first drain select transistor DST. Gates of the drain select transistors DST included in ST may be connected to the first drain select line DSL0. The drain select transistors DST arranged in the second direction Y from the drain select transistors DST connected to the first drain select line DSL0 are connected to the second to fourth drain select lines DSL1 to DSL3. They can be connected sequentially. Accordingly, in the selected memory block, the memory strings ST connected to the selected drain select line may be selected, and the memory strings ST connected to the remaining unselected drain select lines may be unselected.

Memory cells connected to the same word line may form one page (PG). Here, the page means a physical page. For example, among the memory strings ST connected to the first bit line BL1 to the m th bit line BLm, a group of memory cells connected in the first direction X in the same word line as the page PG ) is called For example, among the first memory cells F1 connected to the first word line WL1 , memory cells arranged along the first direction X may form one page PG. Among the first memory cells F1 commonly connected to the first word line WL1 , cells arranged in the second direction Y may be divided into different pages. Accordingly, when the first drain select line DSL0 is the selected drain select line and the first word line WL1 is the selected word line, the first drain among the plurality of pages PG connected to the first word line WL1 . The page connected to the selection line DSL0 becomes the selected page. Pages commonly connected to the first word line WL1 but connected to the unselected second to fourth drain select lines DSL1 to DSL3 become unselected pages.

Although the figure shows that one source select transistor SST and one drain select transistor DST are included in one memory string ST, a plurality of source select transistors are included in one memory string ST depending on the semiconductor memory device. SST and drain select transistors DST may be included. Also, depending on the semiconductor memory device, dummy cells may be included between the source select transistor SST, the memory cells F1 to Fn, and the drain select transistor DST. The dummy cells do not store user data like the general memory cells F1 to Fn, but may be used to improve electrical characteristics of each memory string ST. However, since the dummy cells are not an important configuration in this embodiment, a detailed description thereof will be omitted.

6 is a circuit diagram illustrating a bit line precharge circuit included in the page buffers of FIG. 2 .

Each of the page buffers PB1 to PBm of FIG. 2 includes a bit line precharge circuit for precharging the corresponding bit lines BL1 to BLm, and in the description of the present invention, the page buffer PB1 includes The bit line precharge circuit 131 will be described as an example.

The bit line precharge circuit 131 is connected to the bit line BL1 and applies the _{power voltage V DD} to the bit line BL1 in response to the control signals V1 and V2 to turn the bit line BL1 on. pre-charge The control signals V1 and V2 may be included in the page buffer control signals PB_signals generated by the control logic 140 of FIG. 2 .

The bit line precharge circuit 131 may include a first switch element M1 and a second switch element M2 connected in series between the _{power supply voltage (V DD ) terminal and the bit line BL1 .} The first switch element M1 is turned on in response to the control signal V2, and the second switch element M2 is turned on in response to the control signal V1 to apply the power supply voltage V _{DD to the bit line BL1.} can be authorized Also, the second switch element M2 may adjust the amount of current applied to the bit line BL1 according to the potential level of the control signal V1 .

For example, during the bit line precharge operation, the bit line precharge circuit 131 responds to the control signal V1 of the overdrive potential level and the control signal V2 of the logic low level in the bit line overdrive section. The power supply voltage V _DD is applied to BL1), but a relatively large amount of current is applied to the bit line BL1 according to the control signal V1 of the overdrive potential level to rapidly increase the potential level of the bit line BL1. can In addition, the bit line precharge circuit 131 responds to the target level control signal V1 and the logic low level control signal V2 after the bit line overdrive period ends during the bit line precharge operation to provide a power supply voltage V _DD ) may be continuously applied to the bit line BL1 to maintain the precharge level. The target level is preferably lower than the overdrive potential level.

As an embodiment, the first switch device M1 may be configured as a PMOS transistor, and the second switch device M2 may be configured as an NMOS transistor.

7 is a flowchart illustrating a method of operating a semiconductor memory device according to an exemplary embodiment of the present invention.

8 is a waveform diagram of operating voltages for explaining a method of operating a semiconductor memory device according to an exemplary embodiment of the present invention.

An operating method of a semiconductor memory device according to an embodiment of the present invention will be described with reference to FIGS. 1 to 8 .

In an embodiment of the present invention, a bit line precharge operation performed during a read operation will be described.

The control logic 140 receives the command CMD corresponding to the read operation from the controller 1200 and controls the peripheral circuit 160 to perform the read operation in response to the received command CMD.

In the t1 period, the voltage generating circuit 150 sets a set voltage (eg, Vpass) to be applied to the unselected word lines Unsel_WLs (eg, WL2 to WLn) according to the control of the voltage generating circuit control signals VG_signals. ) is created. The address decoder 120 converts the set voltage Vpass generated by the voltage generation circuit 150 in response to the address decoder control signals AD_signals to the unselected word lines Unsel_WLs, WL2 to WLn) is applied (S710).

In a t2 period, the voltage generating circuit 150 generates a first overdrive voltage V_WL_od to be applied to the selected word line Sel_WL (eg, WL1) according to the control of the voltage generating circuit control signals VG_signals. . The first overdrive voltage V_WL_od may have a higher potential level than the first target voltage V_WL level of the selected word lines Sel_WL and WL1 during the bit line precharge operation. The level of the first target voltage V_WL may be the level of the read voltage Vread.

The address decoder 120 applies the first overdrive voltage V_WL_od generated by the voltage generation circuit 150 in response to the address decoder control signals AD_signals to the selected word lines Sel_WL and WL1 of the selected memory block BLK1 . to (S720). The first overdrive voltage V_WL_od is applied from a section t2 to a section t4, and a section to which the first overdrive voltage V_WL_od is applied is defined as a word line overdrive section WLoverdrive.

During the t3 period of the word line overdrive period WLoverdrive, the bit line precharge circuits 131 included in each of the page buffers PB1 to PBm respond to the control signals V1 and V2 to the power supply voltage V _DD ) is applied to the bit lines BL1 to BLm; BLs. In this case, the bit line precharge circuits 131 apply the second overdrive voltage to the bit lines BL1 to BLm (BLs) in response to the control signal V1 having the overdrive potential V1_od ( S730 ). The second overdrive voltage is applied from a section t3 to a section t5, and a section to which the second overdrive voltage is applied is defined as a bit line overdrive section (BLoverdrive). The bit line overdrive section BLoverdrive may be a section in which the control signal V1 has the overdrive potential V1_od. The first amount of current applied to the bit lines BL1 to BLm (BLs) in the bit line overdrive period BLoverdrive is applied to the bit lines BL1 after the bit line overdrive period BLoverdrive is finished (eg, period t6). to BLm; BLs) may be relatively larger than the amount of the second current applied to them.

At this time, the first overdrive voltage V_WL_od applied to the word line is higher than the second overdrive voltage applied to the bit lines BL1 to BLm; BLs, and accordingly, the bit lines BL1 to BLm; BLs. The potential level of is precharged to a pre-bit line voltage (V_BL_pre) level lower than the second target voltage (V_BL) level. The word line overdrive section WLoverdrive is a point in time when the cell current in the memory string is large, and when the word line overdrive section WLoverdrive and the bit line overdrive section BLoverdrive overlap, the potential levels of the bit lines BLs are A bit line overshoot phenomenon that is formed to be higher than the level of the second target voltage V_BL may be avoided.

The word line overdrive section WLoverdrive and the bit line overdrive section BLoverdrive may overlap each other in some sections t3 and t4 as shown in FIG. 8 .

In the period t4 , the voltage generating circuit 150 sets the potential level of the first overdrive voltage V_WL_od to be applied to the selected word line Sel_WL (eg, WL1 ) under the control of the voltage generating circuit control signals VG_signals to control the selected word lines Sel WL and WL1 to the level of the first target voltage V_WL ( S740 ). As the potential levels of the selected word lines Sel WL and WL1 fall, the precharge levels of the bit lines BL1 to BLm (BLs) rise.

In the period t5, the potential level of the control signal V1 is lowered to the target level V1_target, and the potential levels of the bit lines BL1 to BLm; BLs are precharged to the second target voltage V_BL (S750). ).

Thereafter, the selected word line Sel_WL maintains the level of the first target voltage V_WL in the period t6, and the bit lines BL1 to BLm (BLs) maintain the level of the second target voltage V_BL.

9 is a diagram for describing another embodiment of a memory system.

Referring to FIG. 9 , a memory system 30000 may be implemented as a cellular phone, a smart phone, a tablet PC, a personal digital assistant (PDA), or a wireless communication device. . The memory system 30000 may include a memory device 1100 and a memory controller 1200 capable of controlling an operation of the memory device 1100 . The memory controller 1200 may control a data access operation, for example, a program operation, an erase operation, or a read operation, of the memory device 1100 according to the control of the processor 3100 . .

Data programmed in the memory device 1100 may be output through a display 3200 under the control of the memory controller 1200 .

The radio transceiver (RADIO TRANSCEIVER) 3300 may transmit and receive radio signals through the antenna ANT. For example, the wireless transceiver 3300 may change a wireless signal received through the antenna ANT into a signal that can be processed by the processor 3100 . Accordingly, the processor 3100 may process the signal output from the wireless transceiver 3300 and transmit the processed signal to the memory controller 1200 or the display 3200 . The memory controller 1200 may program a signal processed by the processor 3100 in the memory device 1100 . Also, the wireless transceiver 3300 may change the signal output from the processor 3100 into a wireless signal and output the changed wireless signal to an external device through the antenna ANT. The input device 3400 is a device capable of inputting a control signal for controlling the operation of the processor 3100 or data to be processed by the processor 3100 , and includes a touch pad and a computer. It may be implemented as a pointing device such as a computer mouse, a keypad, or a keyboard. The processor 3100 controls the display 3200 so that data output from the controller 1200, data output from the wireless transceiver 3300, or data output from the input device 3400 can be output through the display 3200. You can control the action.

According to an embodiment, the memory controller 1200 capable of controlling the operation of the memory device 1100 may be implemented as a part of the processor 3100 or as a chip separate from the processor 3100 . Also, the memory controller 1200 may be implemented through the example of the controller 1200 illustrated in FIG. 1 .

10 is a diagram for describing another embodiment of a memory system.

Referring to FIG. 10 , a memory system (Memory System) 40000 includes a personal computer (PC), a tablet PC, a net-book, an e-reader, and a personal digital assistant (PDA). ), a portable multimedia player (PMP), an MP3 player, or an MP4 player.

The memory system 40000 may include a memory device 1100 and a memory controller 1200 capable of controlling a data processing operation of the memory device 1100 .

The processor 4100 may output data stored in the memory device 1100 through the display 4300 according to data input through the input device 4200 . For example, the input device 4200 may be implemented as a pointing device such as a touch pad or a computer mouse, a keypad, or a keyboard.

The processor 4100 may control the overall operation of the memory system 40000 and may control the operation of the memory controller 1200 . According to an embodiment, the memory controller 1200 capable of controlling the operation of the memory device 1100 may be implemented as a part of the processor 4100 or as a chip separate from the processor 4100 . Also, the memory controller 1200 may be implemented through the example of the controller 1200 illustrated in FIG. 1 .

11 is a diagram for describing another embodiment of a memory system.

Referring to FIG. 11 , a memory system 50000 may be implemented as an image processing device, for example, a digital camera, a mobile phone with a digital camera, a smart phone with a digital camera, or a tablet PC with a digital camera.

The memory system 50000 includes a memory device 1100 and a memory controller 1200 that can control a data processing operation of the memory device 1100 , for example, a program operation, an erase operation, or a read operation.

The image sensor 5200 of the memory system 50000 may convert the optical image into digital signals, and the converted digital signals may be transmitted to the processor 5100 or the memory controller 1200 . Under the control of the processor 5100 , the converted digital signals may be output through a display 5300 or stored in the memory device 1100 through the controller 1200 . Also, data stored in the memory device 1100 may be output through the display 5300 under the control of the processor 5100 or the memory controller 1200 .

According to an embodiment, the memory controller 1200 that can control the operation of the memory device 1100 may be implemented as a part of the processor 5100 or as a chip separate from the processor 5100 . Also, the memory controller 1200 may be implemented through the example of the controller 1200 illustrated in FIG. 1 .

12 is a diagram for describing another embodiment of a memory system.

Referring to FIG. 12 , a memory system 70000 may be implemented as a memory card or a smart card. The memory system 70000 may include a memory device 1100 , a memory controller 1200 , and a card interface 7100 .

The memory controller 1200 may control data exchange between the memory device 1100 and the card interface 7100 . According to an embodiment, the card interface 7100 may be a secure digital (SD) card interface or a multi-media card (MMC) interface, but is not limited thereto. Also, the memory controller 1200 may be implemented through the example of the controller 1200 illustrated in FIG. 1 .

The card interface 7100 may interface data exchange between the host 60000 and the memory controller 1200 according to a protocol of the host (HOST) 60000 . According to an embodiment, the card interface 7100 may support a Universal Serial Bus (USB) protocol and an InterChip (IC)-USB protocol. Here, the card interface may refer to hardware capable of supporting a protocol used by the host 60000, software installed in the hardware, or a signal transmission method.

When the memory system 70000 is connected with the host interface 6200 of the host 60000, such as a PC, tablet PC, digital camera, digital audio player, mobile phone, console video game hardware, or digital set-top box, the host The interface 6200 may perform data communication with the memory device 1100 through the card interface 7100 and the memory controller 1200 under the control of the microprocessor 6100 .

100: semiconductor memory device
110: memory cell array
120: address decoder
130: read and write circuit
140: control logic
150: voltage generation circuit
160: peripheral circuit

Claims (20)

a memory block coupled to a plurality of word lines and a plurality of bit lines;
a peripheral circuit for performing a program operation or a read operation on the memory block; and
and a control logic for controlling the peripheral circuit so that a word line overdrive section and a bit line overdrive section overlap during a bit line precharge operation during the program operation or the read operation.
The method of claim 1,
The control logic controls the peripheral circuit to apply a first overdrive voltage higher than a first target voltage to a selected word line among the plurality of word lines in the word line overdrive period.
3. The method of claim 2,
and the control logic controls the peripheral circuit to apply a first amount of current to the bit lines in the bit line overdrive period.
4. The method of claim 3,
the control logic controls the peripheral circuit to apply a second amount of current to the bit lines after the bit line overdrive period ends;
The second amount of current is smaller than the first amount of current.
3. The method of claim 2,
the control logic controls the peripheral circuit to apply a second overdrive voltage to the bit lines in the bit line overdrive period;
The second overdrive voltage is lower than the first overdrive voltage.
6. The method of claim 5,
In a section where the word line overdrive section and the bit line overdrive section overlap, the bit lines are precharged to a voltage level lower than a second target voltage.
7. The method of claim 6,
and the bit lines are precharged to the second target voltage when an overlapping period of the word line overdrive period and the bit line overdrive period ends.
7. The method of claim 6,
The peripheral circuit may include a voltage generation circuit for applying the first overdrive voltage to the selected one of the word lines; and
a bit line precharge circuit for applying the second overdrive voltage to the bit lines;
The bit line precharge circuit applies the second overdrive voltage to the bit lines in response to a control signal having an overdrive potential level in the bit line overdrive period, and after the bit line overdrive period ends The semiconductor memory device controls the potential of the bit lines to become the second target voltage in response to the control signal lowered to a target level lower than the overdrive potential level.
The method of claim 1,
The control logic controls the peripheral circuit to start the bit line overdrive period after the word line overdrive period starts and before the word line overdrive period ends.
a memory block coupled to a plurality of word lines and a plurality of bit lines;
a peripheral circuit for applying a set voltage to the plurality of word lines and the plurality of bit lines; and
During the bit line precharge operation, a word line overdrive section in which a first overdrive voltage is applied to a selected word line among the plurality of word lines and a bit line overdrive period in which a second overdrive voltage is applied to the plurality of bit lines and a control logic for controlling the peripheral circuit so that sections partially overlap.
11. The method of claim 10,
The control logic applies the first overdrive voltage higher than a first target voltage to the selected word line in the word line overdrive period, and applies the first target voltage to the selected word line after the word line overdrive period ends. A semiconductor memory device for controlling the peripheral circuit to be applied to a word line.
11. The method of claim 10,
and the control logic controls the peripheral circuit to apply the second overdrive voltage having a first amount of current to the bit lines in the bit line overdrive period.
13. The method of claim 12,
and the control logic controls the peripheral circuit to decrease the amount of current of the second overdrive voltage to a second amount of current smaller than the first amount of current after the bit line overdrive period ends.
11. The method of claim 10,
The second overdrive voltage is lower than the first overdrive voltage.
11. The method of claim 10,
In a section in which the word line overdrive section and the bit line overdrive overlap, the bit lines are precharged to a voltage level lower than a second target voltage;
When the bit line overdrive period ends, the bit lines are precharged to the second target voltage.
16. The method of claim 15,
The peripheral circuit may include: a voltage generation circuit for applying the first overdrive voltage to the selected word line; and
a bit line precharge circuit for applying the second overdrive voltage to the bit lines;
The bit line precharge circuit applies the second overdrive voltage to the bit lines in response to a control signal having an overdrive potential level in the bit line overdrive period, and after the bit line overdrive period ends The semiconductor memory device controls the potential of the bit lines to become the second target voltage in response to the control signal lowered to a target level lower than the overdrive potential level.
applying a first overdrive voltage to a selected word line in a word line overdrive period;
applying a second overdrive voltage to the bit lines in a bit line overdrive period;
applying a first target voltage to the selected word line after the word line overdrive period; and
precharging the bit lines to a second target voltage after the bit line overdrive period;
The method of operating a semiconductor memory device in which the word line overdrive section and the bit line overdrive section partially overlap.
18. The method of claim 17,
The method of operating a semiconductor memory device, wherein the first overdrive voltage is higher than the second overdrive voltage.
18. The method of claim 17,
In the bit line overdrive period, the bit lines are precharged with a pre bit line voltage lower than the second target voltage while the first overdrive voltage is applied.
20. The method of claim 19,
When the bit line overdrive period ends, the bit lines are precharged by increasing from the pre bit line voltage to the second target voltage.

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