KR20210082272A - Three-dimensional memory die including stress-compensating slit trench structures or stress-absorbing seal ring structures and method of manufacturing the same - Google Patents

Abstract

The semiconductor die includes a plurality of alternating stacks of insulating and electrically conductive layers positioned over a substrate, and memory stack structures extending through the plurality of alternating stacks. The plurality of slit trench fill structures may laterally extend further along the horizontal direction than a set of at least two neighboring alternating stacks of the plurality of alternating stacks. Each divider trench fill structure and each slit trench fill structure may have a respective set of at least one material portion having the same material composition. Further, a plurality of nested nested structures comprising a first seal ring structure having a first seal ring width, and a second seal ring structure having a second seal ring width, wherein the first seal ring width is less than the second seal ring width. Seal ring structures may be provided.

Description

Three-dimensional memory die including stress-compensating slit trench structures or stress-absorbing seal ring structures and method of manufacturing the same

Related applications

This application claims priority from U.S. Application Serial No. 16/594,892, filed October 7, 2019, and U.S. Application Serial No. 16/594,959, filed October 7, 2019.

technical field

TECHNICAL FIELD The present disclosure relates generally to the field of semiconductor devices, and more particularly to three-dimensional memory dies including stress-compensating slit trench structures or stress-absorbing seal ring structures for reducing wafer warpage and methods for forming the same. will be.

A three-dimensional memory device comprising three-dimensional vertical NAND strings with one bit per cell is disclosed in a paper by T. Endoh et al. entitled: "Novel Ultra High Density Memory With A Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell", IEDM Proc. (2001) 33-36.

According to one embodiment of the present disclosure, a semiconductor die is provided, the semiconductor die being laterally spaced apart by a plurality of divider trench fill structures positioned over a substrate and extending laterally along a first horizontal direction. a plurality of alternating stacks of insulating layers and electrically conductive layers, wherein the plurality of alternating stacks and the plurality of divider trench fill structures are alternately interlaced along a second horizontal direction perpendicular to the first horizontal direction; a plurality of sets of memory stack structures, each set of memory stack structures extending vertically through a respective alternating stack of the plurality of alternating stacks, each of the memory stack structures having a respective vertical semiconductor channel and a respective memory including film -; and a plurality of slit trench fill structures extending laterally along the second horizontal direction by a lateral distance greater than a lateral extent along the second horizontal direction of at least two neighboring sets of alternating stacks of the plurality of alternating stacks. wherein each of the plurality of divider trench fill structures and each of the plurality of slit trench fill structures comprises a respective set of at least one material portion having the same material composition.

According to another embodiment of the present disclosure, a method of forming a semiconductor structure is provided, the method comprising: forming a vertically alternating sequence of successive insulating layers and successive sacrificial material layers over a substrate; forming a plurality of sets of memory stack structures, each set of memory stack structures extending vertically through a respective region in a vertically alternating sequence, each of the memory stack structures having a respective vertical semiconductor channel and a respective respective vertical semiconductor channel including memory film -; forming divider trenches and slit trenches, the divider trenches extending laterally along a first horizontal direction, dividing the vertically alternating sequence into a plurality of alternating stacks of insulating layers and sacrificial material layers, the slit the trenches extend laterally along a second horizontal direction perpendicular to the first horizontal direction; replacing the sacrificial material layers in the plurality of alternating stacks with electrically conductive layers using divider trenches as conduits for an etchant that etches the sacrificial material layers and a reactant that deposits the conductive material of the electrically conductive layers; and depositing one or more sets of material in each of the divider trenches and the slit trenches, wherein a plurality of divider trench fill structures are formed in the divider trenches and a plurality of slit trench fill structures are formed in the slit trenches. .

In accordance with one embodiment of the present disclosure, a semiconductor die is disposed over a substrate and has electrical and insulating layers extending laterally along a first horizontal direction and laterally spaced apart along a second horizontal direction perpendicular to the first horizontal direction. a plurality of alternating stacks of conductive layers, a plurality of sets of memory stack structures extending through the plurality of alternating stacks, and a plurality of nested seal ring structures, the plurality of nested seal ring structures comprising: , a first seal ring structure having a first seal ring width between the inner sidewall and the outer sidewall, and a second seal ring width between the inner sidewall and the outer sidewall such that the first seal ring width is less than the second seal ring width and a second seal ring structure.

According to another embodiment of the present disclosure, a method of forming a semiconductor structure is provided, the method comprising: forming a vertically alternating sequence of successive insulating layers and successive sacrificial material layers over a substrate; forming a plurality of sets of memory stack structures extending through respective regions of a vertically alternating sequence; dividing the vertically alternating sequence into a plurality of alternating stacks of insulating layers and sacrificial material layers by forming backside trenches extending laterally along a first horizontal direction through the vertically alternating sequence; replacing the sacrificial material layers with electrically conductive layers using the backside trenches as conduits for an etchant that etches the sacrificial material layers and a reactant that deposits the conductive material of the electrically conductive layers; forming portions of dielectric material over the insulating layers and the electrically conductive layers; and forming a plurality of nested seal ring structures extending from a top surface of the dielectric material portions to the substrate and laterally surrounding and enclosing the alternating stacks and inner regions of the dielectric material portions; The plurality of nested seal ring structures comprises: a first seal ring structure having a first seal ring width between an inner sidewall and an outer sidewall; and a second seal ring structure laterally enclosing or laterally enclosed by the first seal ring structure, the second seal ring structure having a second seal ring width between the inner sidewall and the outer sidewall; The seal ring width is less than the second seal ring width.

1A is a first exemplary diagram for forming a semiconductor die after formation of various doped semiconductor regions, field effect transistors, a planarization dielectric layer, an etch stop dielectric layer, and sacrificial via structures, in accordance with an embodiment of the present disclosure; A vertical cross-sectional view of an area of a structure.
1B is a plan view of a unit die area of the first exemplary structure of FIG. 1A ;
2 is a first diagram after formation of an alternating stack of first-tiers of first insulating layers and first spacer material layers and after patterning the first-tier stepped region, in accordance with one embodiment of the present disclosure; A vertical cross-sectional view of an area of an exemplary structure.
3 is a vertical cross-sectional view of an area of a first exemplary structure after formation of a first reverse-stepped dielectric material portion and an inter-tier dielectric layer, in accordance with an embodiment of the present disclosure.
4A is a vertical cross-sectional view of an area of a first exemplary structure after formation of first-tier memory openings and first-tier support openings, in accordance with one embodiment of the present disclosure.
4B is a horizontal cross-sectional view of an area of the first exemplary structure of FIG. 4A ; The hinged vertical plane A - A' corresponds to the plane of the vertical cross-sectional view of FIG. 4A .
5 is a vertical cross-sectional view of an area of a first exemplary structure after formation of various sacrificial fill structures, in accordance with one embodiment of the present disclosure.
6 is after formation of a second-tier alternating stack of second insulating layers and second spacer material layers, second stepped surfaces and a second stepped dielectric material portion, in accordance with an embodiment of the present disclosure; A vertical cross-sectional view of an area of the first exemplary structure.
7A is a vertical cross-sectional view of an area of the first exemplary structure after formation of second-tier memory openings and second-tier support openings, in accordance with one embodiment of the present disclosure.
FIG. 7B is a horizontal cross-section of an area of the first exemplary structure along horizontal plane B - B′ of FIG. 7A . The hinged vertical plane A - A' corresponds to the plane of the vertical cross-sectional view of FIG. 7A .
8 is a vertical cross-sectional view of an area of the first exemplary structure after formation of inter-tier memory openings and inter-tier support openings, in accordance with an embodiment of the present disclosure.
9A-9D illustrate sequential vertical cross-sectional views of a memory opening during formation of a memory opening filling structure, in accordance with one embodiment of the present disclosure.
10 is a vertical cross-sectional view of an area of the first exemplary structure after formation of memory aperture filling structures and support pillar structures, in accordance with one embodiment of the present disclosure.
11A is a vertical cross-sectional view of an area of a first exemplary structure after formation of a contact level dielectric layer and divider trenches, in accordance with an embodiment of the present disclosure.
FIG. 11B is a horizontal cross-section of an area of the first exemplary structure along horizontal plane B - B′ of FIG. 11A . The hinged vertical plane A - A' corresponds to the plane of the vertical cross-sectional view of FIG. 11A .
11C is a plan view of a unit die area of the first exemplary structure of FIGS. 11A-11D ; The hinged vertical plane A - A' corresponds to the plane of the vertical cross-sectional view of FIG. 11A .
11D is a vertical cross-sectional view of the first exemplary structure along the vertical plane D-D′ of FIG. 11C .
11E is a top view of a unit die area of a first alternative embodiment of the first exemplary structure of FIGS. 11A-11D ;
11F is a top view of a unit die area of a second alternative embodiment of the first exemplary structure of FIGS. 11A-11D ;
12 is a vertical cross-sectional view of an area of the first exemplary structure after formation of back recesses in accordance with an embodiment of the present disclosure.
13A is a vertical cross-sectional view of an area of a first exemplary structure after formation of electrically conductive layers in accordance with an embodiment of the present disclosure.
FIG. 13B is a horizontal cross-section of an area of the first exemplary structure along horizontal plane B-B′ of FIG. 13A . The hinged vertical plane A - A' corresponds to the plane of the vertical cross-sectional view of FIG. 13A .
14A is a vertical cross-sectional view of an area of the first exemplary structure after formation of divider trench fill structures and slit trench fill structures, in accordance with one embodiment of the present disclosure.
14B is a horizontal cross-section of an area of the first exemplary structure along horizontal plane B - B' of FIG. 14A . The hinged vertical plane A - A' corresponds to the plane of the vertical cross-sectional view of FIG. 14A .
14C is a vertical cross-sectional view of the first exemplary structure along the vertical plane C-C' of FIG. 14B .
14D is a top view of a unit die area of the first exemplary structure of FIGS. 14A-14C ;
14E is a vertical cross-sectional view of the first exemplary structure along vertical plane E - E' of FIG. 14D . The hinged vertical plane A - A' corresponds to the plane of the vertical cross-sectional view of FIG. 14A .
14F is a top view of a unit die area of a first alternative embodiment of the first exemplary structure of FIGS. 14A-14C ;
14G is a top view of a unit die area of a second alternative embodiment of the first exemplary structure of FIGS. 14A-14C ;
15A is a vertical cross-sectional view of an area of a first exemplary structure after formation of peripheral device contact via structures, in accordance with an embodiment of the present disclosure.
15B is a horizontal cross-sectional view of an area of the first exemplary structure of FIG. 15A .
16A is a top view of a unit die area of a first exemplary structure after formation of a seal ring structure, in accordance with an embodiment of the present disclosure.
16B is a top view of a unit die area of a first alternative embodiment of a first exemplary structure after formation of a seal ring structure, in accordance with an embodiment of the present disclosure.
16C is a top view of a unit die area of a second alternative embodiment of the first exemplary structure after formation of the seal ring structure, in accordance with one embodiment of the present disclosure.
16D is a vertical cross-sectional view of a second alternative embodiment of the first exemplary structure of FIG. 16C ;
17A is a second exemplary diagram for forming a semiconductor die after formation of various doped semiconductor regions, field effect transistors, planarization dielectric layer, etch stop dielectric layer, and sacrificial via structures, in accordance with an embodiment of the present disclosure; A vertical cross-sectional view of an area of a structure.
17B is a plan view of a unit die area of the second exemplary structure of FIG. 17A ;
18 is a second diagram after formation of an alternating stack of first-tier of first insulating layers and first spacer material layers and after patterning the first-tier stepped region, in accordance with an embodiment of the present disclosure; A vertical cross-sectional view of an area of an exemplary structure.
19 is a vertical cross-sectional view of an area of a second exemplary structure after formation of a first reverse-stepped dielectric material portion and an inter-tier dielectric layer, in accordance with an embodiment of the present disclosure.
20A is a vertical cross-sectional view of an area of a second exemplary structure after formation of first-tier memory openings and first-tier support openings, in accordance with one embodiment of the present disclosure.
FIG. 20B is a horizontal cross-sectional view of an area of the second exemplary structure of FIG. 20A . The hinged vertical plane A - A' corresponds to the plane of the vertical cross-sectional view of FIG. 20A .
21 is a vertical cross-sectional view of an area of a second exemplary structure after formation of various sacrificial fill structures, in accordance with one embodiment of the present disclosure.
22 is after formation of a second two-tier alternating stack of second insulating layers and second spacer material layers, second stepped surfaces and a second stepped dielectric material portion, in accordance with an embodiment of the present disclosure; A vertical cross-sectional view of an area of a second exemplary structure.
23A is a vertical cross-sectional view of an area of a second exemplary structure after formation of second-tier memory openings and second-tier support openings, in accordance with one embodiment of the present disclosure.
23B is a horizontal cross-section of an area of the second exemplary structure along horizontal plane B-B' of FIG. 23A . The hinged vertical plane A - A' corresponds to the plane of the vertical cross-sectional view of FIG. 23A .
24 is a vertical cross-sectional view of an area of a second exemplary structure after formation of inter-tier memory openings and inter-tier support openings, in accordance with one embodiment of the present disclosure.
25A-25D illustrate sequential vertical cross-sectional views of a memory opening during formation of a memory opening filling structure, in accordance with one embodiment of the present disclosure.
26 is a vertical cross-sectional view of an area of a second exemplary structure after formation of memory aperture fill structures and support pillar structures, in accordance with one embodiment of the present disclosure.
27A is a vertical cross-sectional view of an area of a second exemplary structure after formation of a contact first level dielectric layer and backside trenches, in accordance with an embodiment of the present disclosure.
FIG. 27B is a horizontal cross-section of an area of the second exemplary structure along horizontal plane B-B′ of FIG. 27A . The hinged vertical plane A - A' corresponds to the plane of the vertical cross-sectional view of FIG. 27A .
27C is a top view of a unit die area of the second exemplary structure of FIGS. 27A and 27B ; The hinged vertical plane A - A' corresponds to the plane of the vertical cross-sectional view of FIG. 27A .
28 is a vertical cross-sectional view of an area of a second exemplary structure after formation of back recesses in accordance with an embodiment of the present disclosure.
29A is a vertical cross-sectional view of an area of a second exemplary structure after formation of electrically conductive layers in accordance with an embodiment of the present disclosure.
29B is a horizontal cross-section of an area of the second exemplary structure along horizontal plane B - B' of FIG. 29A . The hinged vertical plane A - A' corresponds to the plane of the vertical cross-sectional view of FIG. 29A .
30A is a vertical cross-sectional view of an area of a second exemplary structure after formation of back trench fill structures and slit trench fill structures, in accordance with an embodiment of the present disclosure.
FIG. 30B is a horizontal cross-section of an area of the second exemplary structure along horizontal plane B-B′ of FIG. 30A ; The hinged vertical plane A - A' corresponds to the plane of the vertical cross-sectional view of FIG. 30A .
30C is a vertical cross-sectional view of the second exemplary structure along the vertical plane C-C' of FIG. 30B .
30D is a top view of a unit die area of the second exemplary structure of FIGS. 30A-30C ;
31 is a vertical cross-sectional view of an area of a second exemplary structure after formation of through memory level contact via structures, bit line level dielectric layer, and bit line level metal interconnect structures, in accordance with one embodiment of the present disclosure.
32 is a vertical cross-sectional view of an area of a second exemplary structure after formation of top dielectric material layers and top metal interconnect structures, in accordance with an embodiment of the present disclosure.
33A is a first vertical cross-sectional view of an area of a second exemplary structure after formation of seal ring cavities in accordance with an embodiment of the present disclosure.
33B is a second vertical cross-sectional view of an area of a second exemplary structure after formation of seal ring cavities in accordance with an embodiment of the present disclosure.
33C is a top view of a unit die area of a second exemplary structure after formation of seal ring cavities, in accordance with an embodiment of the present disclosure. The vertical planes A - A and B - B correspond to the planes of the vertical cross-sectional view of FIGS. 33A and 33B , respectively.
Fig. 33D is an enlarged view of area D of Fig. 33C.
33E is a top view of a unit die area of an alternative configuration of a second exemplary structure after formation of seal ring cavities, in accordance with an embodiment of the present disclosure.
Fig. 33E is an enlarged view of area F in Fig. 33D.
34A is a vertical cross-sectional view of an area of a second exemplary structure after formation of seal ring structures in accordance with an embodiment of the present disclosure.
34B is a top view of a unit die area of a second exemplary structure after formation of the seal ring structures, in accordance with an embodiment of the present disclosure.
Fig. 34C is an enlarged view of region C of Fig. 34B;
34D is a top view of a unit die area of an alternative configuration of a second exemplary structure after formation of the seal ring structures, in accordance with an embodiment of the present disclosure.
Fig. 34E is an enlarged view of area E of Fig. 34D.
35 is a vertical cross-sectional view of an area of a second exemplary structure after formation of a dielectric passivation layer in accordance with an embodiment of the present disclosure.
36 is a vertical cross-sectional view of an area of a second exemplary structure after formation of bonding pads in accordance with an embodiment of the present disclosure.

In three-dimensional memory devices, slit trenches extending laterally along a horizontal direction perpendicular to vertical steps of an alternating stack of insulating layers and sacrificial material layers may be used to provide conduits, recessed through the conduits. A liquid etchant is provided to remove the sacrificial material layers to form the etchants, and a reactant is provided to form electrically conductive layers (eg, word lines) in the recesses through the conduits. Because the slit trenches extend laterally along the same horizontal direction (eg, word line direction), mechanical stress in three-dimensional memory devices causes the wafer into a saddleback shape when replacing the sacrificial material layers with electrically conductive layers. induce the transformation of The saddle shape deformation of the wafer introduces various difficulties during the subsequent formation of metal interconnect structures. Embodiments of the present disclosure relate to three-dimensional memory dies including stress-compensating slit trench structures for reducing wafer warpage and methods for forming the same, including a stress-absorbing seal ring structure for reducing wafer warpage to three-dimensional memory devices, the various aspects of which are described in detail.

The drawings are not drawn to scale. Multiple instances of an element may be duplicated when a single instance of an element is illustrated, unless the absence of duplication of elements is explicitly stated or clearly indicated otherwise. Ordinal numbers such as “first,” “second,” and “third” are merely used to identify similar elements, and different ordinal numbers may be used throughout the specification and claims of this disclosure. Like reference numbers refer to like elements or like elements. Unless otherwise indicated, elements having the same reference number are assumed to have the same composition and the same function. Unless otherwise indicated, “contact” between elements refers to direct contact between elements that provides an edge or surface shared by the elements. As used herein, a first element positioned “on” a second element may be positioned on the outer surface of the surface of the second element or on the inner surface of the second element. As used herein, a first element is positioned “directly on” a second element when there is physical contact between the surface of the first element and the surface of the second element. As used herein, a “prototype” structure or “in-process” structure refers to a temporary structure in which the shape or composition of at least one component therein is subsequently modified.

As used herein, “layer” refers to a portion of a material comprising a region having a thickness. A layer may extend over the entirety of the underlying or overlying structure, or it may have an extent that is less than the extent of the underlying or overlying structure. Further, the layer may be a region of a homogeneous or heterogeneous continuous structure having a thickness less than the thickness of the continuous structure. For example, the layer may be positioned between any pair of horizontal planes at or between the top and bottom surfaces of the continuous structure. The layer may extend horizontally, vertically, and/or along a tapered surface. The substrate may be one layer, may include one or more layers therein, or may have one or more layers thereon, above, and/or below.

As used herein, when a second surface overlies or underlies a first surface, and when there is a vertical or substantially vertical plane comprising the first surface and the second surface, a first The surface and the second surface are "perpendicularly coincident" with each other. A substantially vertical plane is a plane extending straight along a direction deviating from the vertical direction by an angle of less than 5 degrees. A vertical or substantially perpendicular plane is a straight line along a vertical or substantially perpendicular direction, and may or may not include a curvature along a direction perpendicular to the vertical or substantially perpendicular direction.

As used herein, “memory level” or “memory array level” refers to an array of memory elements and a first horizontal plane that includes the top surfaces of the array of memory elements (ie, a plane parallel to the top surface of the substrate). refers to the level corresponding to the general area between the second horizontal planes including the lowermost surfaces of As used herein, a “through stack” element refers to an element that extends vertically through a memory level.

As used herein, “semiconducting material” refers to a material having an electrical conductivity in the range of ^{1.0×10 −5} S/m to 1.0×10 ^{5 S/m.} As used herein, "semiconductor material" refers to a material having an electrical conductivity in the range of ^{1.0 × 10 -5 S/m to 1.0 S/m when no electrical dopant is present therein, and} Suitable doping can produce doped materials having electrical conductivity in the range of 1.0 S/m to 1.0 x 10 ^{5 S/m.} As used herein, “electrical dopant” refers to a p-type dopant that adds holes to the valence band in the band structure, or an n-type dopant adds electrons to the conduction band in the band structure. As used herein, “conductive material” refers to a material having an electrical conductivity greater than ^{1.0×10 5 S/m.} As used herein, “insulator material” or “dielectric material” refers to a material having an electrical conductivity of less than ^{1.0×10 −5 S/m.} As used herein, "heavily doped semiconductor material" means a conductive material as formed as a crystalline material or when converted to a crystalline material via an annealing process (e.g., from an initial amorphous state); It refers to a semiconductor material doped with an electrical dopant at a sufficiently high atomic concentration to have an electrical conductivity greater than 1.0×10 ^{5 S/m.} A “doped semiconductor material” may be a highly doped semiconductor material, or an electrical dopant (i.e., p) at a concentration that provides an electrical conductivity ranging from ^{1.0×10 −5} S/m to 1.0×10 ^{5 S/m.} -type dopants and/or n-type dopants). “Intrinsic semiconductor material” refers to a semiconductor material that is not doped with an electrical dopant. Accordingly, the semiconductor material may be semiconducting or conductive, and may be an intrinsic semiconducting material or a doped semiconducting material. The doped semiconductor material may be semiconducting or conductive, depending on the atomic concentration of the electrical dopant therein. As used herein, “metallic material” refers to a conductive material having therein at least one metallic element. All measurements of electrical conductivity are made under standard conditions.

A monolithic three-dimensional memory array is one in which multiple memory levels are formed on a single substrate, such as a semiconductor wafer, without an intervening substrate. The term “monolithic” means that the layers of each level of the array are deposited directly on the layers of each underlying level of the array. In contrast, two-dimensional arrays can be formed separately and then packaged together to form a non-monolithic memory device. For example, as described in U.S. Patent No. 5,915,167 entitled "Three-dimensional Structure Memory," the non-monolithic structure is formed by forming memory levels on separate substrates and vertically stacking the memory levels. Stacked memories were constructed. Substrates may be thinned or removed from the memory levels prior to bonding, but since the memory levels are initially formed over separate substrates, such memories are not truly monolithic three-dimensional memory arrays. The substrate may include integrated circuits fabricated thereon, such as driver circuits for a memory device.

The various three-dimensional memory devices of the present disclosure include a monolithic three-dimensional NAND string memory device, and can be fabricated using the various embodiments described herein. A monolithic three-dimensional NAND string is positioned within a monolithic three-dimensional array of NAND strings positioned over a substrate. At least one memory cell of a first device level of the three-dimensional array of NAND strings is located above another memory cell of a second device level of the three-dimensional array of NAND strings.

In general, a semiconductor package (or “package”) refers to a unit semiconductor device that can be attached to a circuit board through a set of pins or solder balls. A semiconductor package consists of a semiconductor chip (or "chip") or a plurality of semiconductor chips generally bonded by, for example, flip-chip bonding or other chip-to-chip bonding. may include A package or chip may include a single semiconductor die (or “die”) or a plurality of semiconductor dies. A die is the smallest unit that can independently execute external commands or report status. Typically, a package or chip with multiple dies can simultaneously execute as many external commands as the total number of planes therein. Each die includes one or more planes. The same simultaneous operations may be performed in each plane within the same die, but with some limitations. In the case where the die is a memory die, that is, a die comprising memory elements, simultaneous read operations, simultaneous write operations, or simultaneous erase operations may be performed in each plane within the same memory die. In a memory die, each plane contains a number of memory blocks (or “blocks”), which are the smallest units that can be erased in a single erase operation. Each memory block contains a number of pages, which are the smallest units that can be selected for programming. A page is also the smallest unit that can be selected for a read operation.

1A and 1B , a first exemplary structure for forming a semiconductor die is illustrated. 1B illustrates the layout of various regions within a unit die area of a first exemplary structure, and FIG. 1A is a vertical cross-sectional view of the first exemplary structure. In one embodiment, the first exemplary structure may include a substrate 908 , which may be a semiconductor wafer (which may be, for example, a single crystal silicon wafer, such as a 300 mm silicon wafer or a 200 mm silicon wafer). ) may be provided by forming various doped semiconductor regions (eg, doped wells) in the upper portion of the . For example, the substrate 908 may include a substrate layer 909 , a semiconductor material layer 910 , a first doped well 6 buried within the semiconductor material layer 910 , and a second doped well 6 buried within the semiconductor material layer 910 . A second doped well 10 may be included. In the illustrative example, the semiconductor material layer 910 and the second doped well 10 may have a p-type doping, and the first doped well 6 may have an n-type doping. The substrate layer 909 may be a semiconductor substrate (eg, a silicon wafer), a layer of semiconductor material (eg, an epitaxial silicon layer on a silicon wafer), or an insulating layer (as in the case of a semiconductor-on-insulator substrate). Additional doped wells may be formed as needed to provide various semiconductor devices thereon. Each of the doped wells may be p-doped or n-doped and may ^{have electrical dopants at an atomic concentration ranging from 1.0 × 10 14} /cm 3 to 1.0 × 10 ¹⁸ /cm 3 , although smaller and larger atomic concentrations may also be used. can be used

Various semiconductor devices 710 may be formed on a substrate. The various semiconductor devices 710 may include complementary metal oxide semiconductor (CMOS) devices for operating a three-dimensional array of memory elements to be subsequently formed on the substrate 908 in cell array regions. It may include various peripheral circuits (ie, driver circuits) that may be used. As used herein, “cell array region” refers to a region in which a three-dimensional array of memory elements is formed, such as a memory plane. The cell array region (eg, memory plane) is also referred to as memory array region 100 . The semiconductor devices 710 may include field effect transistors formed on a top surface of the substrate 908 .

In general, semiconductor devices 710 may include any circuitry that may be used to control the operation of at least one three-dimensional array of memory elements to be subsequently formed. For example, semiconductor devices 710 may include peripheral devices used to control the operation of a three-dimensional array of memory elements to be subsequently formed. The regions in which peripheral devices are formed are collectively referred to as peripheral device region 300 . Peripheral device area 300 may include various areas configured to provide specific types of peripheral devices. In an illustrative example, sense amplifier circuits may be formed in sense amplifier regions denoted “S/A” in FIG. 1B . The bit line driver circuits may be formed in bit line driver regions denoted by “BD” in FIG. 1B . Word line switches and select gate electrode switch may be formed in the word line and select gate electrode switch regions, denoted as “WL/SG SW” in FIG. 1B . Additional other peripheral devices may be formed in the Other Peripheral Device area labeled “PERI” in FIG. 1B . Each three-dimensional array of memory elements may be subsequently formed using alternating stacks of insulating layers and electrically conductive layers (eg, word lines). In this case, the layers in the alternating stacks may be patterned to provide stepped surfaces, and contact via structures in contact with a respective one of the electrically conductive layers may be formed in those stepped surfaces. Such regions are referred to as word line hookup stair regions and are denoted “WLHU stair” in FIG. 1B . The word line hookup step areas are also referred to as step areas 200 . Dummy stepped surfaces that are not used to provide electrical contacts to the electrically conductive layers may be formed around each cell array region (ie, memory array region 100 ). Regions comprising such dummy stepped surfaces are referred to herein as dummy stepped regions and are denoted as “dummy stair” in FIG. 1B . Additional dummy step areas may be formed within the perimeter of the die area. The additional dummy stair areas are referred to herein as “dummy stair tracks”. Then, seal ring structures and guard ring structures are formed at the outer edges of the dummy step tracks, which define the outer boundary of the semiconductor chip.

The region in which the seal ring structures and the guard ring structure are subsequently formed is referred to herein as the seal ring and guard ring region 400 . Kerf regions 500 are provided outside the regions of the seal ring structures. Regions within the outer periphery of the seal ring and guard ring regions define regions of the semiconductor die to be subsequently formed. The region of the semiconductor die may have a generally rectangular shape. The horizontal direction of the sidewalls of the first pair of semiconductor dies is referred to herein as the first horizontal direction hd1 (eg, word line direction), and the horizontal direction of the sidewalls of the second pair of semiconductor dies is herein A second horizontal direction hd2 (eg, a bit line direction) perpendicular to the first horizontal direction hd1 is referred to. The kerf regions may include various test structures and alignment structures that may or may not be destroyed during singulation of the substrate 908 and semiconductor devices thereon into a plurality of semiconductor dies. The unit die area includes half the width of each kerf area.

A planarization dielectric layer 760 may be formed over the semiconductor devices 710 . For example, a planarization dielectric layer 760 may be formed over the gate structures and active regions (eg, source regions and drain regions) of the field effect transistors. The planarization dielectric layer 760 may include a planarable dielectric material such as silicate glass. The top surface of planarization dielectric layer 760 may be planarized, for example, by chemical mechanical planarization.

An etch stop dielectric layer 790 may be formed over the planarization dielectric layer 760 . Etch stop dielectric layer 790 may comprise a dielectric material that may be employed as an etch stop material during etching of an overlying dielectric material portion to be subsequently formed. In one embodiment, the etch stop dielectric layer 70 may include at least one dielectric material sublayer comprising a material different from the material of the sacrificial material layers in a vertically alternating sequence of insulating layers and sacrificial material layers. . For example, where the overlying portion of dielectric material comprises silicon oxide, etch stop dielectric layer 790 may comprise a layer stack of a dielectric metal oxide layer and a silicon nitride layer. In one embodiment, the etch stop dielectric layer 790 may include a layer stack of a silicon nitride layer and an aluminum oxide layer.

Sacrificial via structures 477 may be formed on the top surface of a respective element of semiconductor devices 710 through etch stop dielectric layer 790 and planarization dielectric layer 760 . For example, a photoresist layer (not shown) may be applied over the etch stop dielectric layer 790 and lithographically patterned to form openings over the components of the semiconductor devices 710 . An anisotropic etch process may be performed to form via cavities under openings in the photoresist layer through the etch stop dielectric layer 790 and the planarization dielectric layer 760 . Via cavities may extend to a top surface of a respective underlying component of semiconductor devices 710 . The photoresist layer may be removed, for example, by ashing, and a sacrificial fill material (eg, amorphous silicon, silicon-germanium alloy, polymeric material, borosilicate glass, or organosilicate glass) is deposited within the via cavities. to form sacrificial via structures 477 . Excess portions of the sacrificial fill material may be removed from above a horizontal plane including the top surface of the etch stop dielectric layer 790 . Each of the sacrificial via structures 477 may contact a respective one component of the semiconductor devices 710 . For example, a subset of sacrificial via structures 477 may contact a respective gate electrode, and another subset of sacrificial via structures may contact a respective active region (eg, source region or drain region). have. In general, the electrically active nodes of the semiconductor devices 710 may be contacted by a respective sacrificial via structure 477 . The top surfaces of the sacrificial via structures 477 may be coplanar with the top surfaces of the etch stop dielectric layer 790 .

Referring to FIG. 2 , etch stop dielectric layer 790 and planarization dielectric layer 760 may be removed from each memory array region 100 and from each step region 200 . For example, a photoresist layer (not shown) may cover each region including the semiconductor devices 710 , a planarization dielectric layer 760 not covered by the photoresist layer and an etch stop dielectric layer ( Portions of 790 may be removed by at least one etching process, which may include an isotropic etching process (eg, a wet etching process) and/or an anisotropic etching process (eg, a reactive ion etching process). The top surface of the substrate 908 (eg, the top surface of the second doped well 10 ) may be physically exposed within the memory array region 100 and adjacent step regions 200 .

An alternating stack of first and second material layers is subsequently formed. Each layer of first material may include a first material, and each layer of second material may include a second material that is different from the first material. When at least another alternating stack of material layers is subsequently formed over the alternating stack of first and second material layers, the alternating stack is referred to herein as a first-tier alternating stack. The level of the alternating stack of the first-tier is referred to herein as the first-tier level, and the level of the alternating stack to be subsequently formed immediately above the first-tier level is referred to herein as the second-tier level. is the way it is referred to.

The first-tier alternating stack may include a first insulating layer 132 as first material layers, and first spacer material layers as second material layers. In one embodiment, the first spacer material layers may be sacrificial material layers that are subsequently replaced with electrically conductive layers. In another embodiment, the first spacer material layers may be electrically conductive layers that are not subsequently replaced with other layers. While the present disclosure is described using embodiments in which the sacrificial material layers are replaced with electrically conductive layers, embodiments in which the spacer material layers are formed as electrically conductive layers, thereby excluding the need to perform replacement processes, are It is explicitly contemplated in the specification.

In one embodiment, the first material layers and the second material layers may be first insulating layers 132 and first sacrificial material layers 142 , respectively. In one embodiment, each first insulating layer 132 may include a first insulating material, and each first sacrificial material layer 142 may include a first sacrificial material. An alternating plurality of first insulating layers 132 and first sacrificial material layers 142 are formed over the substrate 908 . As used herein, “sacrificial material” refers to material that is removed during subsequent processing steps.

As used herein, an alternating stack of first elements and second elements refers to a structure in which instances of first elements and instances of second elements alternate. each instance of the first elements that are not the alternating plurality of end elements is adjacent on both sides by two instances of the second elements, each instance of the second elements that are not the alternating plurality of end elements is disposed at both ends adjoined by two instances of the first elements on the poles. The first elements may have the same overall thickness, or they may have different thicknesses. The second elements may have the same overall thickness, or they may have different thicknesses. An alternating plurality of first material layers and second material layers may begin with an instance of first material layers or with an instance of second material layers, and may end with an instance of first material layers or second material layers. have. In one embodiment, the instances of the first elements and the instances of the second elements may form units that repeat with periodicity within an alternating plurality.

The first-tier alternating stack 132 , 142 may include first insulating layers 132 composed of a first material, and first sacrificial material layers 142 composed of a second material different from the first material. can The first material of the first insulating layers 132 may be at least one insulating material. Insulating materials that may be used for the first insulating layers 132 include silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric material, high dielectric metal oxides and silicates thereof, dielectric metal oxynitrides and silicates thereof, and organic insulating materials commonly known as dielectric constant (high-k) dielectric oxides (eg, aluminum oxide, hafnium oxide, etc.) not limited In one embodiment, the first material of the first insulating layers 132 may be silicon oxide.

The second material of the first sacrificial material layers 142 may be a sacrificial material that may be selectively removed with respect to the first material of the first insulating layers 132 . As used herein, removal of the first material is “selective” with respect to the second material if the removal process removes the first material at a rate that is at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the “selectivity” of the removal process of the first material over the second material.

The first sacrificial material layers 142 may include an insulating material, a semiconductor material, or a conductive material. The second material of the first sacrificial material layers 142 may subsequently be replaced with electrically conductive electrodes that may serve, for example, as control gate electrodes of a vertical NAND device. In one embodiment, the first sacrificial material layers 142 may be material layers comprising silicon nitride.

In one embodiment, the first insulating layers 132 may include silicon oxide and the sacrificial material layers may include silicon nitride sacrificial material layers. The first material of the first insulating layers 132 may be deposited by chemical vapor deposition (CVD), for example. For example, when silicon oxide is used for the first insulating layers 132 , tetraethylorthosilicate (TEOS) may be used as a precursor material for the CVD process. The second material of the first sacrificial material layers 142 may be formed, for example, by CVD or atomic layer deposition (ALD).

The thicknesses of the first insulating layers 132 and the first sacrificial material layers 142 may be in the range of 20 nm to 50 nm, but each first insulating layer 132 and each first sacrificial material layer 142 . Smaller and larger thicknesses may be used for . The number of repetitions of the pairs of first insulating layer 132 and first sacrificial material layer 142 may range from 2 to 1,024, and typically from 8 to 256, although higher repetition numbers may also be used. In one embodiment, each first sacrificial material layer 142 in the first-tier alternating stack 132 , 142 has a substantially constant uniform thickness within each respective first sacrificial material layer 142 . can have

A first insulating cap layer 170 is subsequently formed over the first alternating stacks 132 , 142 . The first insulating cap layer 170 includes a dielectric material, which can be any dielectric material that can be used for the first insulating layer 132 . In one embodiment, the first insulating cap layer 170 includes the same dielectric material as the first insulating layer 132 . The thickness of the first insulating cap layer 170 may range from 20 nm to 300 nm, although smaller and larger thicknesses may also be used.

The first insulating cap layer 170 and the first-tier alternating stack 132 , 142 may be patterned to form first stepped surfaces within the stepped region 200 . Each layer of the first-tier alternating stack 132 , 142 may be removed from above the etch stop dielectric layer 790 . The stepped region 200 is a respective first stepped region in which first stepped surfaces are formed, and a second-tier structure (to be subsequently formed over the first-tier structure) and/or a respective first stepped region in which additional stepped surfaces are formed. or a second stepped region formed of additional tier structures. The first stepped surfaces, for example, form a mask layer having an opening therein, etch a cavity within the levels of the first insulating cap layer 170 , iteratively expand the etched area and etch the etched area may be formed by vertically recessing the cavity by etching each pair of the first sacrificial material layer 142 and the first insulating layer 132 located directly below the bottom surface of the etched cavity within. In one embodiment, the top surfaces of the first sacrificial material layers 142 may be physically exposed at the first stepped surfaces. The cavity overlying the first stepped surfaces is referred to herein as the first stepped cavity.

The first insulating layers 132 and the first sacrificial material layers 142 extend continuously over the entire area of the memory array region 100 , and thus also as first continuous insulating layers and first continuous sacrificial material layers, respectively. is referred to A vertically alternating sequence of first successive insulating layers and first successive layers of sacrificial material may be formed over the substrate 908 . First stepped surfaces are formed in peripheral portions of a vertically alternating sequence. Each layer in a vertically alternating sequence resides within the memory array region 100 . The lateral extent of the first successive layers of sacrificial material decreases with vertical distance from the substrate 908 in each step region 200 . In one embodiment, all layers of the vertically alternating sequence are removed from above the etch stop dielectric layer 790 , and the stepped surfaces of the remaining portions of the vertically alternating sequence are the regions where the etch stop dielectric layer 790 is present. does not extend to

Referring to FIG. 3 , a dielectric filling material (eg, undoped silicate glass or doped silicate glass) may be deposited to fill the first stepped cavity. Excess portions of dielectric filling material may be removed from above a horizontal plane comprising a top surface of first insulating cap layer 170 . The remainder of the dielectric fill material filling the region overlying the first stepped surfaces constitutes the first stepped dielectric material portion 165 . As used herein, a “stepped” element refers to an element having stepped surfaces and a horizontal cross-sectional area that monotonically increases as a function of the vertical distance from the upper surface of the substrate on which the element is present. A first counter-stepped portion of dielectric material overlies and contacts the etch stop dielectric layer 790 . The first-tier alternating stacks 132 , 142 and the first stepped dielectric material portion 165 collectively constitute a first-tier structure, which is a subsequently modified in-process structure.

An inter-tier dielectric layer 180 may optionally be deposited over the first-tier structures 132 , 142 , 170 , 165 . Inter-tier dielectric layer 180 includes a dielectric material such as silicon oxide. In one embodiment, the inter-tier dielectric layer 180 may include doped silicate glass having a greater etch rate than the material of the first insulating layers 132 (which may include undoped silicate glass). have. For example, the inter-tier dielectric layer 180 may include phosphosilicate glass. The thickness of the inter-tier dielectric layer 180 may range from 30 nm to 300 nm, although smaller and larger thicknesses may also be used.

4A and 4B , various first-tier openings 149 , 129 pass through inter-tier dielectric layer 180 and first-tier structures 132 , 142 , 170 , 165 through substrate 908 . ) can be formed into A layer of photoresist (not shown) may be applied over the inter-tier dielectric layer 180 and lithographically patterned to form various openings therethrough. The pattern of openings in the photoresist layer is transferred to the substrate 908 by a first anisotropic etch process through the inter-tier dielectric layer 180 and the first-tier structures 132 , 142 , 170 , and 165 , to form a variety of second-order substrates. One-tier openings 149 and 129 are formed simultaneously, ie during the first isotropic etching process. The various first-tier openings 149 , 129 may include first-tier memory openings 149 and first-tier support openings 129 . The positions of steps S in the first alternating stack 132 , 142 are illustrated by dashed lines in FIG. 4B .

The first-tier memory openings 149 are openings formed in the memory array region 100 through respective layers in the first alternating stack 132 , 142 and subsequently used to form memory stack structures. The first-tier memory openings 149 may be formed as clusters of the first-tier memory openings 149 that are laterally spaced apart along the second horizontal direction hd2 . Each cluster of first-tier memory openings 149 may be formed as a two-dimensional array of first-tier memory openings 149 .

The first-tier support openings 129 are openings formed in the stepped region 200 . A subset of the first-tier support openings 129 formed through the first stepped dielectric material portion 165 may be formed through respective horizontal surfaces of the first stepped surfaces.

In one embodiment, the first anisotropic etching process may include an initial step in which the materials of the first-tier alternating stack 132 , 142 are etched concurrently with the material of the first stepped dielectric material portion 165 . . The chemistry of the initial etch step etches the first and second materials of the first-tier alternating stack 132 , 142 while providing an average etch rate comparable to that of the first stepped dielectric material portion 165 . can be alternated to optimize The first anisotropic etch process may use, for example, a series of reactive ion etch processes or a single reactive etch process (eg, CF ₄ /O ₂ /Ar etch). The sidewalls of the various first-tier openings 149 , 129 may be substantially vertical or may be tapered. In one embodiment, the terminal portion of the anisotropic etching process may include an overetching step that is etched into the upper portion of the second doped well 10 . The photoresist layer may be subsequently removed, for example, by ashing.

Optionally, portions of first-tier memory openings 149 and first-tier support openings 129 at the level of inter-tier dielectric layer 180 may be laterally expanded by isotropic etching. . In this case, the inter-tier dielectric layer 180 is a dielectric material having a greater etch rate than the first insulating layer 132 (which may include undoped silicate glass) in diluted hydrofluoric acid (eg, borosilicate glass). An isotropic etch (eg, wet etch using HF) may be used to expand the lateral dimensions of the first-tier memory openings 149 at the level of the inter-tier dielectric layer 180 . Portions of first-tier memory openings 149 located at the level of inter-tier dielectric layer 180 are optionally subsequently to be formed through an alternating stack of second-tier (subsequently second second) tiers. can be enlarged to provide a larger landing pad for the second-tier memory openings - to be formed prior to formation of the tier memory openings

Referring to FIG. 5 , sacrificial first-tier opening filling portions 148 , 128 may be formed in various first-tier openings 149 , 129 . For example, a sacrificial first-tier fill material is deposited simultaneously onto each of the first-tier openings 149 and 129 . The sacrificial first-tier filling material includes a material that can be subsequently removed selectively with respect to the materials of the first insulating layers 132 and the first sacrificial material layers 142 .

In one embodiment, the sacrificial first-tier fill material comprises a semiconductor material such as silicon (eg, a-Si or polysilicon), a silicon-germanium alloy, germanium, a group III-V compound semiconductor material, or a combination thereof. can do. Optionally, a thin etch stop liner (eg, a silicon oxide layer or a silicon nitride layer having a thickness in the range of 1 nm to 3 nm) may be used prior to depositing the sacrificial first-tier fill material. The sacrificial first-tier fill material may be formed by non-conformal deposition or conformal deposition methods.

In another embodiment, the sacrificial first-tier fill material is silicon oxide having a higher etch rate than the materials of the first insulating layers 132 , the first insulating cap layer 170 , and the inter-tier dielectric layer 180 . material may be included. For example, the sacrificial first-tier fill material is formed by decomposition of tetraethylorthosilicate glass in a 100:1 diluted hydrofluoric acid densified TEOS oxide (i.e., tetraethylorthosilicate glass in a chemical vapor deposition process and subsequently in an annealing process). borosilicate glass, or porous or non-porous organosilicate glass having an etch rate at least 100 times higher than the etch rate of the densified silicon oxide material. In this case, a thin etch stop liner (eg, a silicon nitride layer having a thickness in the range of 1 nm to 3 nm) may be used prior to depositing the sacrificial first-tier fill material. The sacrificial first-tier fill material may be formed by non-conformal deposition or conformal deposition methods.

In another embodiment, the sacrificial first-tier fill material is an amorphous carbon-containing material (eg, amorphous carbon or diamond-like carbon) or a first alternating stack 132 that may be subsequently removed by ashing. 142) may include a silicone-based polymer that can be selectively removed subsequently.

Portions of the deposited sacrificial material may be removed from over the top layer of the first-tier alternating stack 132 , 142 , such as from over the inter-tier dielectric layer 180 . For example, the sacrificial first-tier fill material may be recessed into the top surface of the inter-tier dielectric layer 180 using a planarization process. The planarization process may include a recess etch, chemical mechanical planarization (CMP), or a combination thereof. The top surface of the inter-tier dielectric layer 180 may be used as an etch stop layer or a planarization stop layer.

The remaining portions of the sacrificial first-tier fill material include sacrificial first-tier opening fill portions 148 , 128 . Specifically, each remaining portion of the sacrificial material in the first-tier memory opening 149 constitutes the sacrificial first-tier memory opening filling portion 148 . Each remaining portion of the sacrificial material in the first-tier support opening 129 constitutes a sacrificial first-tier support opening filling portion 128 . The various sacrificial first-tier opening fill portions 148 , 128 simultaneously, ie, a deposition process that deposits the sacrificial first-tier fill material and from above the first alternating stack 132 , 142 (eg, inter- formed during the same set of processes including a planarization process that removes the first-tier deposition process (from above the top surface of the tier dielectric layer 180 ). The top surfaces of the sacrificial first-tier opening filling portions 148 , 128 may be coplanar with the top surface of the inter-tier dielectric layer 180 . Each of the sacrificial first-tier opening filling portions 148 , 128 may or may not include cavities therein.

Referring to FIG. 6 , a second-tier structure may be formed on the first-tier structures 132 , 142 , 170 , and 148 . The second-tier structure may include an additional alternating stack of insulating layers and spacer material layers, which may be sacrificial material layers. For example, a second alternating stack 232 , 242 of material layers may subsequently be formed on the top surface of the first alternating stack 132 , 142 . The second alternating stack 232 , 242 may include an alternating plurality of third and fourth material layers. Each layer of third material may include a third material, and each layer of fourth material may include a fourth material that is different from the third material. In one embodiment, the third material may be the same as the first material of the first insulating layer 132 , and the fourth material may be the same as the second material of the first sacrificial material layers 142 .

In one embodiment, the third material layers may be second insulating layers 232 , wherein the fourth material layers provide a second vertical spacing between each vertically neighboring pair of second insulating layers 232 . spacer material layers. In one embodiment, the third material layers and the fourth material layers may be second insulating layers 232 and second sacrificial material layers 242 , respectively. The third material of the second insulating layers 232 may be at least one insulating material. The fourth material of the second sacrificial material layers 242 may be a sacrificial material that may be selectively removed with respect to the third material of the second insulating layers 232 . The second sacrificial material layers 242 may include an insulating material, a semiconductor material, or a conductive material. The fourth material of the second sacrificial material layers 242 may subsequently be replaced with electrically conductive electrodes that may serve, for example, as control gate electrodes of a vertical NAND device.

In one embodiment, each second insulating layer 232 can include a second insulating material, and each second sacrificial material layer 242 can include a second sacrificial material. In this case, the second alternating stack 232 , 242 may include an alternating plurality of second insulating layers 232 and second sacrificial material layers 242 . The third material of the second insulating layers 232 may be deposited by chemical vapor deposition (CVD), for example. The fourth material of the second sacrificial material layers 242 may be formed, for example, by CVD or atomic layer deposition (ALD).

The third material of the second insulating layers 232 may be at least one insulating material. The insulating materials that can be used for the second insulating layers 232 can be any material that can be used for the first insulating layers 132 . The fourth material of the second sacrificial material layers 242 is a sacrificial material that can be selectively removed with respect to the third material of the second insulating layers 232 . The sacrificial materials that may be used for the second sacrificial material layers 242 may be any material that may be used for the first sacrificial material layers 142 . In one embodiment, the second insulating material may be the same as the first insulating material, and the second sacrificial material may be the same as the first sacrificial material.

The thicknesses of the second insulating layers 232 and the second sacrificial material layers 242 may range from 20 nm to 50 nm, but each second insulating layer 232 and each second sacrificial material layer 242 Smaller and larger thicknesses may be used for . The number of repetitions of the pairs of the second insulating layer 232 and the second sacrificial material layer 242 may range from 2 to 1,024, and typically from 8 to 256, although higher repetition numbers may also be used. In one embodiment, each second sacrificial material layer 242 in the second alternating stacks 232 , 242 may have a substantially invariant uniform thickness within each respective second sacrificial material layer 242 . have.

The second stepped surfaces in the second stepped region may undergo the same set of processing steps as those used to form the first stepped surfaces in the first stepped region, with adjustments suitable for the pattern of the at least one masking layer. It can be formed in the step area 200 using A second stepped dielectric material portion 265 may be formed over the second stepped surfaces in the stepped region 200 .

A second insulating cap layer 270 may subsequently be formed over the second alternating stacks 232 , 242 . The second insulating cap layer 270 includes a dielectric material that is different from the material of the second sacrificial material layers 242 . In one embodiment, the second insulating cap layer 270 may include silicon oxide. In one embodiment, the first and second sacrificial material layers 142 , 242 may include silicon nitride.

The second insulating layers 232 and the second sacrificial material layers 242 extend continuously over the entire area of the memory array region 100 , and thus also as second continuous insulating layers and second consecutive sacrificial material layers, respectively. is referred to A vertically alternating sequence of second successive insulating layers and second successive layers of sacrificial material may be formed over the substrate 908 . Second stepped surfaces are formed in peripheral portions of a vertically alternating sequence. Each layer in a vertically alternating sequence resides within the memory array region 100 . The lateral extent of the second successive layers of sacrificial material 242 decreases with vertical distance from the substrate 908 in each step region 200 . In one embodiment, all layers of the vertically alternating sequence are removed from above the etch stop dielectric layer 790 , and the stepped surfaces of the remaining portions of the vertically alternating sequence are the regions where the etch stop dielectric layer 790 is present. does not extend to

Generally speaking, at least one vertically alternating sequence of successive insulating layers 132 , 232 and successive spacer material layers (eg, successive sacrificial material layers 142 , 242 ) is to be formed over the substrate 908 . and at least one stepped dielectric material portion 165 , 265 may be formed over the stepped regions on the at least one vertically alternating sequence 132 , 142 , 232 , 242 .

Optionally, drain select level isolation structures 72 may be formed through a subset of the layers in the upper portion of the second two-tier alternating stack 232 , 242 . The second sacrificial material layers 242 cut by the drain select level isolation structures 72 correspond to the levels at which the drain select level electrically conductive layers are subsequently formed. Drain select level isolation structures 72 include a dielectric material such as silicon oxide. The drain select level isolation structures 72 may extend laterally in a first horizontal direction hd1 and are laterally spaced apart in a second horizontal direction hd2 perpendicular to the first horizontal direction hd1 . can be The second alternating stack 232 , 242 , the second stepped dielectric material portion 265 , the second insulating cap layer 270 , and the optional drain select level isolation structures 72 are collectively a second- tier structures 232 , 242 , 265 , 270 and 72

7A and 7B , various second-tier openings 249 and 229 may be formed through the second-tier structures 232 , 242 , 265 , 270 , and 72 . A photoresist layer (not shown) may be applied over the second insulating cap layer 270 and lithographically patterned to form various openings therethrough. The pattern of the second-tier memory openings 249 in the memory array region 100 may be the same as the pattern of the first-tier memory openings 149 that is the same as the pattern of the first-tier memory opening filling portion 148 . can The lateral extent of the pattern of second-tier support openings 229 in stepped region 200 may be limited into regions of stepped surfaces of second-tier alternating stack 232 , 242 . In other words, the second-tier support openings 229 may not be in the region where the second counter-stepped dielectric material portion 265 contacts the top surface of the inter-stack dielectric layer 180 . Accordingly, the lithographic mask used to pattern the first-tier openings 149 , 129 may be used to pattern the photoresist layer.

The pattern of openings in the photoresist layer is transferred through the second-tier structures 232 , 242 , 265 , 270 , 72 by a second anisotropic etch process, simultaneously, i.e., during the second anisotropic etch process, various second tiers. Openings 249 and 229 may be formed. The various second-tier openings 249 , 229 may include second-tier memory openings 249 and second-tier support openings 229 .

The second-tier memory openings 249 are formed directly on the top surface of each one of the sacrificial first-tier memory opening filling portions 148 . The second-tier support openings 229 are formed directly on the top surface of each one of the sacrificial first-tier support opening filling portions 128 . Also, each of the second-tier support openings 229 may be formed through a horizontal surface within the second stepped surfaces, which includes a second alternating stack 232 , 242 and a second stepped dielectric material portion. interfacial surfaces between 265 . The positions of steps S in the first-tier alternating stack 132 , 142 and the second tier alternating stack 232 , 242 are illustrated by dashed lines in FIG. 7B .

The second anisotropic etching process may include an etching step in which the materials of the second tier of alternating stacks 232 , 242 are etched simultaneously with the material of the second stepped dielectric material portion 265 . The chemistry of the etching step may be alternated to optimize the etching of the materials of the second-tier alternating stack 232 , 242 while providing an average etch rate comparable to that of the second stepped dielectric material portion 265 . can The second anisotropic etch process may use, for example, a series of reactive ion etch processes or a single reactive etch process (eg, CF ₄ /O ₂ /Ar etch). The sidewalls of the various second-tier openings 249 , 229 may be substantially vertical or may be tapered. The bottom perimeter of each second-tier opening 249 , 229 may be laterally offset and/or located entirely within the perimeter of the top surface of the underlying sacrificial first-tier opening filling portion 148 , 128 . can be The photoresist layer may be subsequently removed, for example, by ashing.

Referring to FIG. 8 , the sacrificial first-tier filling material of the sacrificial first-tier opening filling portions 148 , 128 includes the first and second insulating layers 132 , 232 , the first and second sacrificial material an etching process that etches the sacrificial first-tier fill material selective to the materials of the layers 142 , 242 , the first and second insulating cap layers 170 , 270 , and the inter-tier dielectric layer 180 . It can be removed using Memory opening 49 , also referred to as inter-tier memory opening 49 , is each combination of second-tier memory openings 249 and the volume from which sacrificial first-tier memory opening filling portion 148 is removed. is formed with Support opening 19 , also referred to as inter-tier support opening 19 , is each combination of second-tier support openings 229 and the volume from which sacrificial first-tier support opening fill portion 128 is removed therefrom. is formed with

9A-9D provide sequential cross-sectional views of the memory opening 49 during formation of the memory opening filling structure. The same structural change occurs in each of the memory openings 49 and the support openings 19 .

Referring to FIG. 9A , the pedestal channel portion 11 may be formed by a selective semiconductor material deposition process at the bottom of each memory opening 49 and at the bottom of each support opening 19 . A doped semiconductor material having a doping of a first conductivity type may be selectively grown from physically exposed surfaces of the second doped well 10, whereas growth of the doped semiconductor material from dielectric surfaces is a selective semiconductor. suppressed during the material deposition process. A semiconductor precursor gas, a dopant gas comprising dopant atoms of a first conductivity type, and an etchant may be flowed into a process chamber comprising the first exemplary structure, either simultaneously or alternately. Each pedestal channel portion 11 of the periphery of the top surface may be in contact with a sidewall of the first insulating layer 132 overlying and in contact with the lowermost first sacrificial material layer 142 . The atomic concentration of the first conductivity type dopants in the pedestal channel portions 11 may range from 1.0×10 ¹⁴ /cm 3 to 1.0×10 ¹⁸ /cm 3 , although smaller and larger dopant atomic concentrations may also be used. A pn junction may be formed at each interface between the second doped well 10 and the pedestal channel portion 11 .

Referring to FIG. 9B , a stack of layers including a blocking dielectric layer 52 , a charge storage layer 54 , a tunneling dielectric layer 56 , and a semiconductor channel material layer 60L is sequentially within the memory openings 49 . can be settled with The blocking dielectric layer 52 may include a single layer of dielectric material or a stack of multiple layers of dielectric material. In one embodiment, the blocking dielectric layer may include a dielectric metal oxide layer consisting essentially of a dielectric metal oxide. As used herein, dielectric metal oxide refers to a dielectric material comprising at least one metallic element and at least oxygen. The dielectric metal oxide may consist essentially of at least one metallic element and oxygen, or may consist essentially of at least one metallic element, oxygen, and at least one non-metallic element such as nitrogen. In one embodiment, the blocking dielectric layer 52 may include a dielectric metal oxide having a dielectric constant greater than 7.9, ie, a dielectric constant greater than that of silicon nitride. The thickness of the dielectric metal oxide layer may range from 1 nm to 20 nm, although smaller and larger thicknesses may also be used. The dielectric metal oxide layer may subsequently function as a portion of the dielectric material that blocks stored electrical charges from leaking to the control gate electrodes. In one embodiment, the blocking dielectric layer 52 includes aluminum oxide. Alternatively or additionally, the blocking dielectric layer 52 may include a dielectric semiconductor compound such as silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof.

Subsequently, a charge storage layer 54 may be formed. In one embodiment, charge storage layer 54 may be a continuous layer or patterned discrete portions of charge trapping material including a dielectric charge trapping material, which may be, for example, silicon nitride. Alternatively, the charge storage layer 54 is patterned into multiple electrically isolated portions (eg, floating gates) by being formed into the sacrificial material layers 142 , 242 , for example in lateral recesses. patterned discrete portions or continuous layers of a conductive material such as doped polysilicon or metallic material to be crystallized. In one embodiment, the charge storage layer 54 comprises a silicon nitride layer. In one embodiment, the sacrificial material layers 142 , 242 and the insulating layers 132 , 232 may have vertically matching sidewalls, and the charge storage layer 54 may be formed as a single continuous layer. Alternatively, the sacrificial material layers 142 , 242 may be laterally recessed with respect to the sidewalls of the insulating layers 132 , 232 , wherein a combination of the deposition process and the anisotropic etching process comprises a plurality of vertically spaced It can be used to form the charge storage layer 54 as portions of memory material. The thickness of the charge storage layer 54 may range from 2 nm to 20 nm, although smaller and larger thicknesses may also be used.

Tunneling dielectric layer 56 comprises a dielectric material capable of charge tunneling under suitable electrical bias conditions. Charge tunneling can be performed via hot-carrier injection or by Fowler-Nordheim tunneling induced charge transfer, depending on the mode of operation of the monolithic three-dimensional NAND string memory device to be formed. Tunneling dielectric layer 56 is formed of silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (e.g., aluminum oxide and hafnium oxide), dielectric metal oxynitride, dielectric metal silicate, alloys thereof, and/or combinations thereof. may include In one embodiment, tunneling dielectric layer 56 may include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, commonly known as an ONO stack. In one embodiment, tunneling dielectric layer 56 may include a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the tunneling dielectric layer 56 may range from 2 nm to 20 nm, although smaller and larger thicknesses may be used. The stack of blocking dielectric layer 52 , charge storage layer 54 , and tunneling dielectric layer 56 constitutes a memory film 50 that stores memory bits.

The semiconductor channel material layer 60L is a p-doped semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel material layer 60L may have uniform doping. In one embodiment, the semiconductor channel material layer 60L has a p-type doping, wherein the p-type dopants (eg, boron atoms) are from 1.0 × 10 ¹² /cm 3 to 1.0 × 10 ¹⁸ /cm 3 , e.g. For example, it is present in atomic concentrations ranging from 1.0 × 10 ¹⁴ /cm 3 to 1.0 × 10 ^{17 /cm 3 .} In one embodiment, the semiconductor channel material layer 60L comprises and/or consists essentially of boron-doped amorphous silicon or boron-doped polysilicon. In another embodiment, the semiconductor channel material layer 60L has an n-type doping, wherein the n-type dopants (eg, phosphorus atoms or arsenic atoms) are 1.0 × 10 ¹⁵ /cm 3 to 1.0 × 10 ¹⁹ / It is present in atomic concentrations in cm 3 , for example in the range from 1.0 × 10 ¹⁶ /cm 3 to 1.0 × 10 ^{18 /cm 3 .} The semiconductor channel material layer 60L may be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel material layer 60L may range from 2 nm to 10 nm, although smaller and larger thicknesses may be used. A cavity 49' is formed in the volume of each memory opening 49 not filled with the deposited material layers 52, 54, 56, 60L.

Referring to FIG. 9C , if the cavities 49' in each memory opening are not completely filled by the semiconductor channel material layer 60L, filling any remaining portions of the cavities 49' in each memory opening is performed. A dielectric core layer may be deposited within the cavity 49'. The dielectric core layer includes a dielectric material such as silicon oxide or organosilicate glass. The dielectric core layer may be deposited by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD), or by a self-planarizing deposition process such as spin coating. A horizontal portion of the dielectric core layer overlying the second insulating cap layer 270 may be removed by, for example, a recess etch. The recess etch continues until the top surfaces of the remaining portions of the dielectric core layer are recessed to a height between the top surface of the second insulating cap layer 270 and the bottom surface of the second insulating cap layer 270 . Each remaining portion of the dielectric core layer constitutes the dielectric core 62 .

Referring to FIG. 9D , doped semiconductor material may be deposited in the cavities overlying the dielectric core 62 . The doped semiconductor material has a doping of a conductivity type opposite to that of the semiconductor channel material layer 60L. Thus, the doped semiconductor material has an n-type doping. Deposited doped semiconductor material, semiconductor channel material layer 60L, tunneling dielectric layer 56, charge storage layer 54 and blocking dielectric layer overlying a horizontal plane comprising the top surface of the second insulating cap layer 270 ( Portions of 52 may be removed by a planarization process, such as a chemical mechanical planarization (CMP) process.

Each remaining portion of the n-doped semiconductor material constitutes the drain region 63 . The dopant concentration in drain regions 63 may range from 5.0 x 10 ¹⁹ /cm 3 to 2.0 x 10 ²¹ /cm 3 , although lower or higher dopant concentrations may also be used. The doped semiconductor material may be, for example, doped polysilicon.

Each remaining portion of the semiconductor channel material layer 60L constitutes a vertical semiconductor channel 60 through which current may flow when a vertical NAND device comprising the vertical semiconductor channel 60 is turned on. Tunneling dielectric layer 56 is surrounded by charge storage layer 54 and laterally surrounds vertical semiconductor channel 60 . Each adjacent set of blocking dielectric layer 52 , charge storage layer 54 , and tunneling dielectric layer 56 collectively constitutes memory film 50 , which is capable of storing electrical charges with a macroscopic hold time. . In some embodiments, blocking dielectric layer 52 may not be present in memory film 50 at this stage, and blocking dielectric layer may be formed subsequently after formation of the backside recesses. As used herein, macroscopic hold time refers to a hold time suitable for operation of a memory device as a permanent memory device, such as a hold time in excess of 24 hours.

Each combination of memory film 50 and vertical semiconductor channel 60 (which is a vertical semiconductor channel) in memory opening 49 constitutes memory stack structure 55 . The memory stack structure 55 is a combination of a vertical semiconductor channel 60 , a tunneling dielectric layer 56 , a plurality of memory elements comprising portions of a charge storage layer 54 , and an optional blocking dielectric layer 52 . . Each combination of memory stack structure 55 , dielectric core 62 , and drain region 63 within memory opening 49 constitutes memory opening filling structure 58 . semiconductor material layer 910 and doped wells buried therein, first-tier structures 132, 142, 170, 165, second-tier structures 232, 242, 270, 265, 72, inter-tier dielectric Layer 180, and memory aperture filling structures 58 collectively constitute a memory level assembly.

Referring to FIG. 10 , a first exemplary structure is illustrated after formation of the memory aperture filling structure 58 . The support pillar structures 20 are formed in the support openings 19 concurrently with the formation of the memory opening filling structures 58 . Each support pillar structure 20 may have the same set of components as the memory aperture filling structure 58 . Generally, the plurality of sets of memory stack structures 55 are formed through a vertically alternating sequence of first successive insulating layers 132 and first successive sacrificial material layers 142 and second successive insulating layers. 232 and second successive layers of sacrificial material 242 may be formed through a vertically alternating sequence. The first successive insulating layers 132 and the second successive insulating layers 232 may be considered a set of successive insulating layers 132 , 232 and a set of successive sacrificial material layers 142 , 242 . Thus, each set of memory stack structures 55 may extend vertically through a vertically alternating sequence of successive insulating layers 132 , 232 and successive sacrificial material layers 142 , 242 . Each set of memory stack structures 55 extends vertically through respective regions in a vertically alternating sequence spaced laterally along a second horizontal direction hd2 . Each of the memory stack structures 55 includes a respective vertical semiconductor channel 60 and a respective memory film 60 .

11A-11F , various views of a first exemplary structure are illustrated after formation of contact level dielectric layer 280 , divider trenches 79 , and slit trenches 179 . 11A-11D illustrate the configuration of a first exemplary structure. 11E illustrates a first alternative embodiment of the first exemplary structure of FIGS. 11A-11D . 11F illustrates a second alternative embodiment of the first exemplary structure of FIGS. 11A-11D . The first and second alternative embodiments differ from the structure illustrated in FIGS. 11A-11D by the presence of additional slit trenches 179 .

Specifically, a contact level dielectric layer 280 may be formed over the second-tier structures 232 , 242 , 270 , 265 , 72 . Contact level dielectric layer 280 includes a dielectric material such as silicon oxide and may be formed by a conformal or non-conformal deposition process. For example, contact level dielectric layer 280 may include undoped silicate glass and may have a thickness in the range of 100 nm to 600 nm, although smaller and larger thicknesses may also be used.

A photoresist layer (not shown) may be applied over the contact level dielectric layer 280 , forming elongate openings extending along the first horizontal direction hd1 between the clusters of memory aperture filling structures 58 . It can be patterned in a lithographic manner so as to 11C and 11D , divider trenches 79 and slit trenches 179 form a pattern in the photoresist layer with the contact level dielectric layer 280 , the second tier structures 232 , 242 , 270 . , 265 , 72 , and first-tier structures 132 , 142 , 170 , 165 through transfer to the top surface of the substrate 908 . As used herein, a “divider trench” is a vertically alternating sequence of successive insulating layers 132 , 232 and laterally dividing successive sacrificial material layers 142 , 242 into a plurality of memory blocks. refers to a trench that As used herein, “slit trench” refers to a trench having the shape of a slit. In one embodiment, slit trenches 179 are outside (ie, memory array region) regions of a vertically alternating sequence of successive insulating layers 132 , 232 and successive sacrificial material layers 142 , 242 . 100) may be formed externally. Contact level dielectric layer 280 underlying openings in the photoresist layer, second tier structures 232 , 242 , 270 , 265 , 72 , first tier structures 132 , 142 , 170 , 165 and substrate Portions of 908 may be removed to form divider trenches 79 . A contact level dielectric layer 280 underlying the openings in the photoresist layer, a second insulating cap layer 270 , a second counter-stepped dielectric material portion 265 , an inter-tier dielectric layer 180 , and a first Inverse-stepped dielectric material portion 165 may be removed to form slit trenches 179 .

The anisotropic etch process forming the divider trenches 79 and the slit trenches 179 may stop on the etch stop dielectric layer 790 . Accordingly, the planarization dielectric layer 760 and underlying semiconductor devices 710 may be protected from the anisotropic etch process by the remaining portions of the etch stop dielectric layer 790 . Each divider trench 79 may extend vertically from a top surface of the contact level dielectric layer 280 to a top surface of the substrate 908 (eg, a top surface of the second doped well 10 ). At least one slit trench 179 may extend vertically from the top surface of the contact level dielectric layer 280 to the surface of the etch stop dielectric layer 790 , which is a recessed horizontal of the etch stop dielectric layer 790 . It may be a surface. In one embodiment, one or more slit trenches 179 may be formed in the perimeter region 300 , such as in the space between overlying bit line drivers and sense amplifiers as shown in FIGS. 11C and 11D . . In another embodiment, one or more slit trenches 179 may be formed in a region where the etch stop dielectric layer 790 is not present. For example, slit trenches 179 may be formed in the cuff regions 500 (outside the region of the semiconductor die) as illustrated in FIG. 11F .

In one embodiment, divider trenches 79 may be formed between clusters (eg, memory blocks of memory stack structures 55 ). According to one embodiment of the present disclosure, the divider trenches 79 may extend laterally along a first horizontal (eg, word line) direction hd1 and form a vertically alternating sequence of insulating layers 132 . , 232 ) and a plurality of alternating stacks of sacrificial material layers 142 , 242 . Each alternating stack of insulating layers 132 , 232 and sacrificial material layers 142 , 242 is an alternating stack of first insulating layers 132 and a first-tier of first sacrificial material layers 142 , and a second two-tier alternating stack of second insulating layers 232 and second sacrificial material layers 242 . Clusters of memory stack structures 55 may be laterally spaced along a second horizontal (eg, bit line) direction hd2 by divider trenches 79 .

According to one aspect of the present disclosure, all slit trenches 179 or a subset of slit trenches 179 are perpendicular to a first horizontal direction hd1 in which divider trenches 79 laterally extend. It extends laterally along the second horizontal direction hd2 . The longitudinal alignment of the subset of slit trenches 179 with respect to the direction perpendicular to the longitudinal direction of the divider trenches 79 is created by the divider trenches 79 and separates the sacrificial material layers 142 , 242 . Compensate for unidirectional stress to be subsequently created by the electrically conductive layers to be replaced (eg word lines). Specifically, the electrically conductive layers subsequently replacing the sacrificial material layers 142 , 242 extend laterally along a longitudinal direction, which is a first horizontal direction, and divider trench filling structures filling the divider trenches 79 . spaced laterally by The material(s) of the divider trench fill structures may absorb a component of the mechanical stress applied along the second horizontal direction hd2 by the electrically conductive layers. However, the material(s) of the divider trench fill structures do not absorb a component of the mechanical stress applied along the first horizontal direction hd1 by the electrically conductive layers. The longitudinal direction of the slit trenches 179 along the second horizontal direction hd2 is such that the slit trench filling structures absorb a component of the mechanical stress applied along the first horizontal direction hd1 by the electrically conductive layers and the substrate 908 ) and the device structures formed thereon to reduce or eliminate warpage.

In one embodiment, the slit trenches 179 do not contact the plurality of alternating stacks of insulating layers 132 , 232 and sacrificial material layers 142 , 242 . In one embodiment, at least one of the slit trenches 179 may be formed through the first inverse-stepped dielectric material portion 165 and the second inverse-stepped dielectric material portion 265 , the contact level dielectric It may extend vertically from the top surface of layer 280 to the surface of etch stop dielectric layer 290 .

In one embodiment, a further subset of slit trenches 179 may extend laterally along the first horizontal direction hd1 as illustrated in FIGS. 11E and 11F . A further subset of slit trenches 179 may be located outside areas of alternating stacks {(132, 142), (232, 2342)} outside memory array area 100, the second horizontal It may or may not be connected to the slit trench 179 extending laterally along the direction hd2 .

In one embodiment, at least one of the slit trenches 179 may be formed in the cuff region 500 as illustrated in FIG. 11F . The cuff region may be located outside the outer perimeter of the seal ring structure in the region 400 to be subsequently formed.

In one embodiment, each alternating stack {(132, 142), (232, 2342)} of the plurality of alternating stacks {(132, 142), (232, 2342)} comprises layers of spacer material 142, 242 includes a respective step region 200 having lateral extents that decrease with increasing vertical distance from substrate 908 . In one embodiment, each of the plurality of slit trenches 179 may be located outside and not adjacent to the area of the plurality of divider trenches 79 .

In one embodiment, each of the plurality of divider trenches 79 may be laterally bounded by sidewalls of at least one alternating stack {(132, 142), (232, 2342)}. A first subset of divider trenches 79 may extend laterally along a first horizontal direction hd1 between a pair of alternating stacks {(132, 142), (232, 2342)}. . The second subset of divider trenches 79 are to extend laterally along the first horizontal direction hd1 adjacent the outermost one of the alternating stacks {(132, 142, (232, 2342)}). can In one embodiment, the plurality of slit trenches 179 is provided in a plurality of alternating stacks of insulating layers 132 , 232 and spacer material layers 142 , 242 {(132, 142), (232, 2342)} do not come in direct contact with any of

In one embodiment, a first plurality of alternating stacks of insulating layers 132 , 232 and spacer material layers 142 , 242 may be provided in first memory array region 100 (eg, first memory plane). and a second plurality of alternating stacks of insulating layers 132 , 232 and spacer material layers 142 , 242 are laterally spaced apart from the first memory array region 100 ( For example, in the first memory plane). In one embodiment, one of the plurality of slit trenches 179 includes a first plurality of alternating stacks and a second plurality of alternating stacks in a peripheral region 300 positioned between the memory array regions 100 . can be located between In one embodiment, each of the slit trenches 179 has a rectangular horizontal cross-sectional area with a length to width ratio greater than 30.

12 , sacrificial material layers 142 , 242 include insulating layers 132 , 232 , first and second insulating cap layers 170 , 270 , contact level dielectric layer 280 , and substrate 908 . can be selectively removed. For example, the materials of the insulating layers 132 , 232 , the first and second insulating cap layers 170 , 270 , the stepped dielectric material portions 165 , 265 , and the outermost of the memory films 50 . An etchant that selectively etches the materials of the sacrificial material layers 142 , 242 with respect to the material of the outer layer may be introduced into the divider trenches 79 using, for example, an isotropic etch process. For example, the sacrificial material layers 142 , 242 may include silicon nitride, the materials of the insulating layers 132 , 232 , the first and second insulating cap layers 170 , 270 , a stepped dielectric material. The portions 165 , 265 and the outermost layer of the memory films 50 may include silicon oxide materials.

The isotropic etch process may be a wet etch process using a wet etch solution, or it may be a vapor phase (dry) etch process in which the etchant is introduced into the divider trench 79 in the vapor phase. For example, where the sacrificial material layers 142 , 242 include silicon nitride, the etching process may be a wet etching process in which the first exemplary structure is immersed in a wet etching tank comprising phosphoric acid, which is silicon oxide. , silicon, and a variety of other materials used in the art to selectively etch silicon nitride. The slit trenches 179 do not contact any alternating stack 132 , 142 , 232 , 242 , so the slit trenches 179 do not expand laterally during the isotropic etch process.

Back recesses 143 , 243 are formed in the volumes from which the sacrificial material layers 142 , 242 have been removed. The back recesses 143 and 243 are the first back recesses 143 formed in the volumes from which the first sacrificial material layers 142 have been removed and the volumes from which the second sacrificial material layers 242 have been removed. and second rear recesses 243 formed in the . Each of the back recesses 143 , 243 may be a laterally extending cavity, which has a lateral dimension greater than the vertical extent of the cavity. In other words, the lateral dimension of each of the back recesses 143 , 243 may be greater than the height of the respective back recess 143 , 243 . A plurality of back recesses 143 , 243 may be formed in the volumes from which the material of the sacrificial material layers 142 , 242 has been removed. Each of the backside recesses 143 , 243 may extend substantially parallel to a top surface of the semiconductor substrate layer 909 . The back recesses 143 , 243 may be vertically bounded by the top surface of the underlying insulating layer 132 , 232 and the bottom surface of the overlying insulating layer 132 , 232 . In one embodiment, each of the back recesses 143 and 243 may have a uniform height throughout.

13A and 13B , an oxidation process may be performed to oxidize physically exposed portions of the pedestal channel portion 11 . Tubular insulating spacers (not explicitly shown) may be formed around each pedestal channel portion 11 . A back blocking dielectric layer (not shown) may optionally be deposited in the back recesses 143 , 243 and divider trenches 79 and over the contact level dielectric layer 280 . The back blocking dielectric layer includes a dielectric material, such as a dielectric metal oxide, silicon oxide, or a combination thereof. For example, the back blocking dielectric layer may include aluminum oxide. The back blocking dielectric layer may be formed by a conformal deposition process such as chemical vapor deposition or atomic layer deposition. The thickness of the back blocking dielectric layer may range from 1 nm to 20 nm, such as 2 nm to 10 nm, although smaller and larger thicknesses may also be used.

At least one conductive material may be deposited within the plurality of backside recesses 243 , 243 , on the sidewalls of the divider trench 79 , and over the contact level dielectric layer 280 . The at least one conductive material may be deposited by a conformal deposition method, which may be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or combinations thereof. The at least one conductive material is an elemental metal, an intermetallic alloy of at least two elemental metals, a conductive nitride of at least one elemental metal, a conductive metal oxide, a conductive doped semiconductor material, a conductive metal-semiconductor alloy such as a metal silicide, alloys, and combinations thereof or stacks thereof.

In an embodiment, the at least one conductive material may comprise at least one metallic material, ie an electrically conductive material comprising at least one metallic element. Non-limiting exemplary metallic materials that may be deposited in the back recesses 143 , 243 include tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, and ruthenium. For example, the at least one conductive material may include a conductive metallic nitride material such as TiN, TaN, WN, or combinations thereof, and a conductive filler material such as W, Co, Ru, Mo, Cu, or combinations thereof. and a conductive metallic nitride liner comprising In one embodiment, the at least one conductive material for filling the back recesses 143 , 243 may be a combination of a titanium nitride layer and a tungsten filling material.

The electrically conductive layers 146 , 246 may be formed in the back recesses 143 , 243 by deposition of at least one conductive material. A plurality of first electrically conductive layers 146 may be formed in the plurality of first back recesses 143 , and a plurality of second electrically conductive layers 246 may be formed in the plurality of second back recesses 243 . A continuous layer of metallic material (not shown) may be formed on the sidewalls of each divider trench 79 and over the contact level dielectric layer 280 . Each of the first electrically conductive layers 146 and the second electrically conductive layers 246 may include a respective conductive metallic nitride liner and a respective conductive filler material. Accordingly, the first and second sacrificial material layers 142 and 242 may be replaced with first and second electrically conductive layers 146 and 246 , respectively. Specifically, each first sacrificial material layer 142 may be replaced with an optional portion of a backside blocking dielectric layer and a first electrically conductive layer 146 , each second sacrificial material layer 242 being a backside blocking An optional portion of the dielectric layer and a second electrically conductive layer 246 may be replaced. A back cavity exists within the portion of each divider trench 79 that is not filled with a continuous layer of metallic material.

Residual conductive material may be removed from inside the divider trenches 79 . Specifically, the deposited metallic material of the continuous metallic material layer is etched back from the sidewalls of each divider trench 79 and from above the contact level dielectric layer 280 , for example by anisotropic or isotropic etching. ) can be Each remaining portion of the deposited metallic material in the first back recesses constitutes a first electrically conductive layer 146 . Each remaining portion of the deposited metallic material in the second back recesses constitutes a second electrically conductive layer 246 . The sidewalls of the first electrically conductive material layers 146 and the second electrically conductive layers may be physically exposed in respective divider trenches 79 . The divider trenches may have a pair of curved sidewalls having a non-periodic width variation along the first horizontal direction hd1 and a non-linear width variation along the vertical direction.

Each electrically conductive layer 146 , 246 may be a conductive sheet including openings. A first subset of the openings through each electrically conductive layer 146 , 246 may be filled with memory opening filling structures 58 . A second subset of the openings through each electrically conductive layer 146 , 246 may be filled with support column structures 20 . Each electrically conductive layer 146 , 246 may have a smaller area than any underlying electrically conductive layer 146 , 246 because of the first and second stepped surfaces. Each electrically conductive layer 146 , 246 may have a larger area than any overlying electrically conductive layer 146 , 246 because of the first and second stepped surfaces.

In some embodiments, drain select level isolation structures 72 may be provided at the top levels of the second electrically conductive layers 246 . A subset of the second electrically conductive layers 246 located at the levels of the drain select level isolation structures 72 constitute the drain select gate electrodes. The subset of electrically conductive layers 146 and 246 located below the drain select gate electrodes may function as combinations of a control gate and a word line located at the same level. The control gate electrodes in each electrically conductive layer 146 , 246 are control gate electrodes for a vertical memory device that includes a memory stack structure 55 .

Each of the memory stack structures 55 includes a vertical stack of memory elements located at a respective level of electrically conductive layers 146 , 246 . The subset of electrically conductive layers 146 and 246 may include word lines for memory elements. The memory level assembly is positioned over the semiconductor substrate layer 909 . The memory level assembly includes at least one alternating stack 132 , 146 , 232 , 246 and memory stack structures 55 extending vertically through the at least one alternating stack 132 , 146 , 232 , 246 . do.

Generally, the sacrificial material layers 142 , 242 in the plurality of alternating stacks { ( 132 , 142 , ( 232 , 242 ) ) are for an etchant that etches the sacrificial material layers 142 , 242 and

may be replaced with electrically conductive layers 1'46, 246 employing divider trenches 79 as conduits for a reactant depositing at least one conductive material of electrically conductive layers 146, 246. A plurality of alternating stacks of insulating layers 132 , 232 and electrically conductive layers 146 , 246 may be positioned on the substrate 908 , and a plurality of laterally extending along the first horizontal direction hd1 . They may be laterally spaced apart by divider trenches 79 .

14A-14G , various views of a first exemplary structure are illustrated after formation of divider trench fill structures in divider trenches 79 and formation of slit trench fill structures in slit trenches 179 are illustrated. 14A-14E illustrate the configuration of a first exemplary structure. 14F illustrates a first alternative embodiment of the first exemplary structure of FIGS. 14A-14E . 14G illustrates a second alternative embodiment of the first exemplary structure of FIGS. 14A-14E . The first and second alternative embodiments differ from the structures illustrated in FIGS. 14A-14E by the presence of additional slit trench fill structures.

In general, divider trench fill structures and slit trench fill structures may include at least one material capable of absorbing mechanical stress generated by electrically conductive layers 146 , 246 . The divider trench fill structures and the slit trench fill structures may be comprised of at least one dielectric material, or may comprise a combination of a conductive material laterally surrounded by a dielectric material. For example, a conformal dielectric material layer (eg, a silicon oxide layer) may be deposited in peripheral portions of divider trenches 79 and slit trenches 179 , wherein an anisotropic etch process is performed on a horizontal portion of the conformal dielectric material layer can be performed to remove them. Each remaining vertical portion of the conformal dielectric material layer in divider trenches 79 constitutes divider trench dielectric spacer 74 , and each remaining portion of the conformal dielectric material layer in slit trenches 179 constitutes a slit trench dielectric spacer. (174).

Electrical dopants may be implanted into physically exposed portions of second doped wells 10 to form source regions 61 . In one embodiment, the second doped wells 10 and the vertical semiconductor channels 60 may have doping of a first conductivity type, and the source regions 61 are of a second conductivity type opposite to the first conductivity type. may have doping of For example, the first conductivity type may be p-type, the second conductivity type may be n-type, or vice versa. When the source regions 61 are formed, the source regions 61 may have an atomic concentration of electrical dopants of the second conductivity type in the range of ^{5.0×10 19} /cm 3 to 2.0×10 ^{21 /cm 3 .}

At least one conductive fill material may be deposited in the remaining volumes of the divider trenches 79 and the slit trenches 179 . The at least one conductive filling material may include a material having a lower Young's modulus than the material of the electrically conductive layers 146 , 246 . For example, the electrically conductive layers 146 , 246 may include tungsten, and the at least one conductive filling material comprises a doped polysilicon or doped polysilicon region and a metal or metal alloy region (eg, TiN and / or tungsten regions). Excess portions of the at least one conductive fill material may be removed from above a horizontal plane comprising a top surface of the contact level dielectric layer 280 . Each remaining portion of the at least one conductive fill material in the divider trenches 79 may constitute a source contact via structure 76 , and a respective remaining portion of the at least one conductive fill material in the slit trenches 179 . makes up the slit trench conductive fill material portion 176 . Each of the source contact via structures 76 and the slit trench conductive fill material portions 176 is a conductive fill material portion. In one embodiment, source contact via structures 76 include source electrodes or local interconnects that electrically connect source region 61 to peripheral devices 710 and include slit trench conductive filling material portions ( 176) may be electrically floating.

The set of all material portions that fill divider trench 79 constitute divider trench fill structures 74 , 76 , and the set of all material portions that fill slit trench 179 constitute slit trench fill structures 174 , 176 . make up In one embodiment, divider trench fill structures 74 , 76 may include divider trench dielectric spacers 74 and source contact via structures 76 , wherein slit trench fill structures 174 , 176 are slit trench dielectric spacers. 174 and a slit trench conductive fill material portion 176 . The present disclosure employs an embodiment wherein the divider trench fill structures and the slit trench fill structures each include a respective dielectric spacer and conductive fill material portion, wherein the divider trench fill structures and the slit trench fill structures each comprise a dielectric material; Embodiments made of, for example, undoped silicate glass, doped silicate glass, organosilicate glass, or polymeric material (eg polyimide) are expressly contemplated herein.

In general, at least one set of material may be deposited in each of the divider trenches 79 and the slit trenches 179 . A plurality of divider trench fill structures may be formed in the divider trenches 79 , and a plurality of slit trench fill structures may be formed in the slit trenches 179 . In one embodiment, the set of at least one material in each of the plurality of divider trench fill structures 74 , 76 and each of the plurality of slit trench fill structures 174 , 176 comprises a dielectric material and includes a a dielectric spacer 74 or 174 extending vertically through the entire height of each of the fill structures 74 and 76 and the plurality of slit trench fill structures 174 and 176, and at least one conductive material and conductive filling material portions 76 and 176 laterally surrounded by dielectric spacers 74 and 174 . In one embodiment, each of the plurality of divider trench fill structures 74 , 76 includes a semiconductor material layer 910 , first doped wells 6 , second doped wells 10 , and source regions 61 . may be formed on each one of the plurality of doped semiconductor material portions. For example, divider trench fill structures 74 , 76 may be formed on each source region 61 .

Divider trench fill structures 74 , 76 and slit trench fill structures 174 , 176 may be formed simultaneously employing the same set of processing steps. Each of the plurality of divider trench fill structures 74 , 76 and each of the plurality of slit trench fill structures 174 , 176 may include a respective set of at least one material portion having the same material composition. A plurality of alternating stacks {(132, 146), (232, 246)} and a plurality of divider trench fill structures 74, 76 are alternately interlaced along a second horizontal direction hd2. The slit trench fill structures 174 , 176 have a length greater than the width of the alternating stack {(132, 146), (232, 246)}, and include multiple alternating stacks {(132, 146), ( 232, 246)}. The plurality of slit trench fill structures 174 , 176 comprises at least two neighboring alternating stacks { ( 132 , 146 ), ( 232 , 246 )] and extend laterally along the second horizontal direction hd2 by a lateral distance greater than a lateral extent along the second horizontal direction hd2 of the set. As used herein, neighboring alternating stacks {(132, 146), (232, 246)} are any intervening alternating stack {(132, 146), (232, 246)} Refers to a set of alternating stacks {(132, 146), (232, 246)} without

In one embodiment, each of the plurality of slit trench fill structures 174 , 176 is located outside, and not adjacent to, an area of the plurality of divider trench fill structures 74 , 76 . In one embodiment, each of the plurality of divider trench fill structures 74 , 76 comprises a plurality of alternating stacks { (132, 146), (232, 246) extending laterally along a first horizontal direction (hd1). ))))). In one embodiment, the plurality of slit trench fill structures 174 , 176 are formed in a plurality of alternating stacks { ( 132 , 146 ), ( 232 ) of insulating layers 132 , 232 and electrically conductive layers 146 , 246 . , 246)} are not in direct contact with any of the

In one embodiment, each of the slit trench fill structures 174 , 176 has a rectangular horizontal cross-sectional area with a length to width ratio greater than 30. In one embodiment, at least one of the conductive filling material portions of the plurality of slit trench filling structures 174 , 176 (ie, the slit trench conductive filling material portion 176 ) is electrically floating.

15A and 15B, a photoresist layer (not shown) may be applied over the contact level dielectric layer 280 and lithographically patterned therethrough to form various contact via openings. For example, openings for forming drain contact via structures may be formed over drain regions 63 in memory array regions 100 , and openings for forming step region contact via structures may be formed in step regions 200 . ) can be formed. An anisotropic etch process is performed to transfer the pattern in the photoresist layer through the contact level dielectric layer 280 and the underlying dielectric material portions. Drain regions 63 and electrically conductive layers 146 , 246 may be used as etch stop structures. Drain contact via cavities may be formed over each drain region 63 , wherein the stepped region contact via cavities are respectively at the stepped surface underlying the first and second counter-stepped dielectric material portions 165 , 265 . may be formed over the electrically conductive layers 146 and 246 of The photoresist layer may be subsequently removed, for example by ashing.

Drain contact via structures 88 may be formed in the drain contact via cavities and on the top surface of each one of the drain regions 63 . Step area contact via structures 86 are formed within the step area contact via cavities and on the top surface of one respective one of electrically conductive layers 146 , 246 . The stepped region contact via structures 86 may include drain select level contact via structures that contact a subset of the second electrically conductive layers 246 that function as drain select level gate electrodes. In addition, step area contact via structures 86 are word line contact below the drain select level gate electrodes and in contact with electrically conductive layers 146 , 246 serving as word lines for memory stack structures 55 . Via structures may be included.

Peripheral device contact via cavities are on a respective one top surface of sacrificial via structures 477 through contact level dielectric layer 280 and second and first counter-stepped dielectric material portions 265 , 165 . can be formed. Peripheral device contact via cavities are perpendicular to the top surface of a respective component of semiconductor devices 710 by removing sacrificial via structures 477 optional for etch stop dielectric layer 790 and planarization dielectric layer 760 . can be extended to At least one conductive material may be deposited within the peripheral device contact via cavities. Excess portions of the at least one conductive material may be removed from above a horizontal plane comprising a top surface of the contact level dielectric layer 280 . Each remaining portion of the at least one conductive material within the peripheral device contact via cavity constitutes a peripheral device contact via structure 488 . The regions in which peripheral device contact via structures 488 are formed are collectively referred to herein as peripheral device region 300 . Peripheral device regions 300 may include sense amplifier circuits, word line and select gate electrode switch regions, and other peripheral device regions.

A bit line level dielectric layer 290 may be formed over the contact level dielectric layer 280 . Bit line level metal interconnect structures 98 , 96 may be formed in bit line level dielectric layer 290 . Bit line level metal interconnect structures 98 , 96 include bit lines 98 in contact with a respective one of drain contact via structures 88 , and step area contact via structures 86 and/or perimeter. interconnect line structures 96 in contact with and/or electrically coupled to at least one of the device contact via structures 488 .

16A-16D , additional layers of dielectric material (referred to herein as upper level dielectric material layers 960 ) may be formed over the bit line level dielectric layer 290 . Each of the upper level dielectric material layers 960 may include a dielectric material such as silicon oxide. The top layer of the upper level dielectric material layers 960 may include a diffusion barrier dielectric material such as silicon nitride. Additional metal interconnect structures (referred to herein as top level metal interconnect structures 980 ) may be formed in the top level dielectric material layers 960 . Top level metal interconnect structures 980 include metal line structures that provide electrical connections between semiconductor devices 710 and various nodes of a three-dimensional array of memory elements including memory stack structures 55 and It may include metal via structures.

At least one seal ring structure 588 may be formed in region 400 along a perimeter of a semiconductor die region within kerf region 500 . Each seal ring structure 588 may include a diffusion barrier material, such as titanium nitride, tungsten, and/or silicon nitride, including upper level dielectric material layers 960 , bit line level dielectric layer 290 , contact level It may extend vertically through dielectric layer 280 , and counter-stepped dielectric material portions 165 , 265 , and may contact a top surface of substrate 908 . Each seal ring structure 588 laterally encapsulates alternating stacks of insulating layers 132 , 232 and electrically conductive layers 146 , 246 . In one embodiment, at least one of the slit trench fill structures 174 , 176 may be located within the region 500 outside the seal ring structure(s) 588 located within the region 400 .

1A-16D and in accordance with various embodiments of the present disclosure, a semiconductor die is provided, the semiconductor die positioned over a substrate 908 and extending laterally along a first horizontal direction hd1 a plurality of alternating stacks of insulating layers 132 , 232 and electrically conductive layers 146 , 246 laterally spaced apart by a plurality of divider trench fill structures 74 , 76 being {(132, 146), (232, 246)} and the plurality of divider trench fill structures 74, 76 are alternately interlaced along a second horizontal direction hd2 perpendicular to the first horizontal direction hd1. become -; a plurality of sets of memory stack structures 55 - each set of memory stack structures 55 extending vertically through a respective alternating stack of a plurality of alternating stacks, each set of memory stack structures 55 each comprising a respective vertical semiconductor channel 60 and a respective memory film 50; and a second horizontal direction of the set of at least two neighboring alternating stacks {(132, 146), (232, 246)} of the plurality of alternating stacks {(132, 146), (232, 246)} a plurality of slit trench fill structures (174, 176) extending laterally along the second horizontal direction (hd2) by a lateral distance greater than the lateral extent along (hd2); Each of s 74 , 76 and each of plurality of slit trench fill structures 174 , 176 includes a respective set of at least one material portion having the same material composition. In one embodiment, the set of at least one material portion may be a set of dielectric spacers 74 or 174 and conductive filling material portions 76 or 176 .

In one embodiment, each of the plurality of slit trench fill structures 174 , 176 is located outside, and not adjacent to, an area of the plurality of divider trench fill structures 74 , 76 . In one embodiment, each of the plurality of divider trench fill structures 74 , 76 may be located entirely within the memory array regions 100 and the step regions 200 .

In one embodiment, each of the plurality of divider trench fill structures 74 , 76 comprises a plurality of alternating stacks { (132, 146), (232, 246) extending laterally along a first horizontal direction (hd1). ))))). In one embodiment, the plurality of slit trench fill structures 174 , 176 do not directly contact any of the plurality of alternating stacks of insulating layers 132 , 232 and electrically conductive layers 146 , 246 .

In one embodiment, the semiconductor die is located in the insulating layers 132 , 232 and electrically conductive layers 146 , 246 (the second memory array region 200 ) along the first horizontal direction hd1 and the step regions 200 . ) laterally spaced apart from a plurality of alternating stacks of insulating layers 132 , 232 and electrically conductive layers 146 , 246 (located within the first memory array region 100 and located within the step region) may include a further plurality of alternating stacks of poles 200 (which may be adjacent to each other). One of the plurality of slit trench fill structures 174 , 176 may be positioned between the plurality of alternating stacks and a further plurality of alternating stacks.

In one embodiment, the semiconductor die includes a plurality of alternating stacks {(132, 146), (232, 246)} and a plurality of divider trench fill structures 174 laterally offset inward from the periphery of the semiconductor die. , 176 may include a seal ring structure 588 that laterally encloses. In one embodiment, at least one of the slit trench fill structures 174 , 176 may be located outside the seal ring structure. In one embodiment, each of the slit trench fill structures 174 , 176 has a rectangular horizontal cross-sectional area with a length to width ratio greater than 30.

In one embodiment, each of the plurality of divider trench fill structures 74 , 76 and each set of at least one material portion within each of the plurality of slit trench fill structures 174 , 176 comprises a dielectric material and comprises a plurality of a dielectric spacer 74 or 174 extending vertically through the entire height of each one of the divider trench fill structures 74, 76 and the plurality of slit trench fill structures 174, 176; and a conductive fill material portion 76 or 176 comprising at least one conductive material and laterally surrounded by a dielectric spacer 74 or 174 . In one embodiment, at least one of the conductive filling material portions 176 of the plurality of slit trench filling structures 174 , 176 is electrically floating.

In one embodiment, the semiconductor die is located on the top surface of the substrate 908 and is not in direct contact with the plurality of alternating stacks {(132, 146), (232, 246)} (semiconductor devices 710). field effect transistors (as a subset of); and an etch stop dielectric layer (790) overlying the field effect transistors, wherein at least one of the plurality of slit trench fill structures (174, 176) overlies the etch stop dielectric layer (790) and an etch stop dielectric layer (790) ) is in contact with

In one embodiment, the substrate 908 includes a semiconductor material layer 910 comprising a plurality of doped semiconductor material portions 6 , 10 , 61 ; Each of the plurality of divider trench fill structures 74 , 76 is in contact with a respective one of the plurality of doped semiconductor material portions 6 , 10 , 61 .

In one embodiment, each of the memory films 50 includes a plurality of electrically conductive layers 146, within a respective one of a plurality of alternating stacks of insulating layers 132 , 232 and electrically conductive layers 146 , 256 . a charge storage layer 54 extending through 246; and a tunneling dielectric layer 56 in contact with a charge storage layer 54 and a respective one of the vertical semiconductor channels 60 .

In one embodiment, each alternating stack {(132, 246), (232, 246)} of the plurality of alternating stacks {(132, 246), (232, 246)} comprises electrically conductive layers 146, 246 includes a respective step region 200 with lateral extents that decrease with increasing vertical distance from substrate 908 .

The various structures of the present disclosure provide slit trench fill structures 174 , 176 that extend laterally along a horizontal direction perpendicular to the longitudinal direction of the divider trench fill structures 74 , 76 . The slit trench fill structures 174 , 176 relieve and absorb mechanical stress generated by the electrically conductive layers 146 , 246 along the longitudinal direction of the divider trench fill structures 74 , 76 . By reducing the difference between the mechanical stress along the longitudinal direction of the divider trench fill structures 74 , 76 and the mechanical stress along the width direction of the divider trench fill structures 74 , 76 , the substrate 908 and the Warpage of structures can be reduced. For example, bonding a wafer comprising a substrate 908 and a two-dimensional array of semiconductor dies thereon to another wafer comprising a two-dimensional array of semiconductor dies, which may be logic dies or memory dies. This can be facilitated through reduction of wafer warpage, which is provided by utilization of the slit trench fill structures 174 , 176 of the present disclosure.

17A and 17B , a second exemplary structure for forming a semiconductor die is illustrated. 17B illustrates the layout of various regions within a unit die area of the second exemplary structure, and FIG. 17A is a vertical cross-sectional view of the second exemplary structure. In one embodiment, the second exemplary structure may include a substrate 908 , which may be a semiconductor wafer (which may be, for example, a single crystal silicon wafer, such as a 300 mm silicon wafer or a 200 mm silicon wafer). ) may be provided by forming various doped semiconductor regions (eg, doped wells) in the upper portion of the . For example, the substrate 908 may include a substrate layer 909 , a semiconductor material layer 910 , a first doped well 6 buried within the semiconductor material layer 910 , and a second doped well 6 buried within the semiconductor material layer 910 . A second doped well 10 may be included. In the illustrative example, the semiconductor material layer 910 and the second doped well 10 may have a p-type doping, and the first doped well 6 may have an n-type doping. The substrate layer 909 may be a semiconductor substrate (eg, a silicon wafer), a layer of semiconductor material (eg, an epitaxial silicon layer on a silicon wafer), or an insulating layer (as in the case of a semiconductor-on-insulator substrate). Additional doped wells may be formed as needed to provide various semiconductor devices thereon. Each of the doped wells may be p-doped or n-doped and may ^{have electrical dopants at an atomic concentration ranging from 1.0 × 10 14} /cm 3 to 1.0 × 10 ¹⁸ /cm 3 , although smaller and larger atomic concentrations may also be used. can be used

Various semiconductor devices 710 may be formed on a substrate. The various semiconductor devices 710 may include complementary metal oxide semiconductor (CMOS) devices for operating a three-dimensional array of memory elements to be subsequently formed on the substrate 908 in cell array regions. It may include various peripheral circuits (ie, driver circuits) that may be used. As used herein, “cell array region” refers to a region in which a three-dimensional array of memory elements is formed, such as a memory plane. The cell array region (eg, memory plane) is also referred to as memory array region 100 . The semiconductor devices 710 may include field effect transistors formed on a top surface of the substrate 908 .

In general, semiconductor devices 710 may include any circuitry that may be used to control the operation of at least one three-dimensional array of memory elements to be subsequently formed. For example, semiconductor devices 710 may include peripheral devices used to control the operation of a three-dimensional array of memory elements to be subsequently formed. The regions in which peripheral devices are formed are collectively referred to as peripheral device region 300 . Peripheral device area 300 may include various areas configured to provide specific types of peripheral devices. In an illustrative example, sense amplifier circuits may be formed in sense amplifier regions denoted “S/A” in FIG. 17B . The bit line driver circuits may be formed in the bit line driver regions indicated by "BD" in FIG. 17B. Word line switches and select gate electrode switch may be formed in the word line and select gate electrode switch regions, denoted as “WL/SG SW” in FIG. 17B . Additional other peripheral devices may be formed in the Other Peripheral Device area indicated as “PERI” in FIG. 17B . Each three-dimensional array of memory elements may be subsequently formed using alternating stacks of insulating layers and electrically conductive layers (eg, word lines). In this case, the layers in the alternating stacks may be patterned to provide stepped surfaces, and contact via structures in contact with a respective one of the electrically conductive layers may be formed in those stepped surfaces. Such regions are referred to as word line hookup stair regions and are denoted as “WLHU stair” in FIG. 17B . The word line hookup step areas are also referred to as step areas 200 . Dummy stepped surfaces that are not used to provide electrical contacts to the electrically conductive layers may be formed around each cell array region (ie, memory array region 100 ). Regions comprising such dummy stepped surfaces are referred to herein as dummy stepped regions and are denoted “dummy stair” in FIG. 17B . Additional dummy step areas may be formed within the perimeter of the die area. The additional dummy stair areas are referred to herein as “dummy stair tracks”. Then, seal ring structures and guard ring structures are formed at the outer edges of the dummy step tracks, which define the outer boundary of the semiconductor chip.

The region in which the seal ring structures and the guard ring structure are subsequently formed is referred to herein as the seal ring and guard ring region 400 . Cuff regions 500 are provided outside the regions of the seal ring structures. Regions within the outer periphery of the seal ring and guard ring regions define regions of the semiconductor die to be subsequently formed. The region of the semiconductor die may have a generally rectangular shape. The horizontal direction of the sidewalls of the first pair of semiconductor dies is referred to herein as the first horizontal direction hd1 (eg, word line direction), and the horizontal direction of the sidewalls of the second pair of semiconductor dies is herein A second horizontal direction hd2 (eg, a bit line direction) perpendicular to the first horizontal direction hd1 is referred to. The kerf regions may include various test structures and alignment structures that may or may not be destroyed during singulation of the substrate 908 and semiconductor devices thereon into a plurality of semiconductor dies. The unit die area includes half the width of each kerf area.

A planarization dielectric layer 760 may be formed over the semiconductor devices 710 . For example, a planarization dielectric layer 760 may be formed over the gate structures and active regions (eg, source regions and drain regions) of the field effect transistors. The planarization dielectric layer 760 may include a planarable dielectric material such as silicate glass. The top surface of planarization dielectric layer 760 may be planarized, for example, by chemical mechanical planarization.

An etch stop dielectric layer 790 may be formed over the planarization dielectric layer 760 . Etch stop dielectric layer 790 may comprise a dielectric material that may be employed as an etch stop material during etching of an overlying dielectric material portion to be subsequently formed. In one embodiment, the etch stop dielectric layer 70 may include at least one dielectric material sublayer comprising a material different from the material of the sacrificial material layers in a vertically alternating sequence of insulating layers and sacrificial material layers. . For example, where the overlying portion of dielectric material comprises silicon oxide, etch stop dielectric layer 790 may comprise a layer stack of a dielectric metal oxide layer and a silicon nitride layer. In one embodiment, the etch stop dielectric layer 790 may include a layer stack of a silicon nitride layer and an aluminum oxide layer.

Sacrificial via structures 477 may be formed on the top surface of a respective element of semiconductor devices 710 through etch stop dielectric layer 790 and planarization dielectric layer 760 . For example, a photoresist layer (not shown) may be applied over the etch stop dielectric layer 790 and lithographically patterned to form openings over the components of the semiconductor devices 710 . An anisotropic etch process may be performed to form via cavities under openings in the photoresist layer through the etch stop dielectric layer 790 and the planarization dielectric layer 760 . Via cavities may extend to a top surface of a respective underlying component of semiconductor devices 710 . The photoresist layer may be removed, for example, by ashing, and a sacrificial fill material (eg, amorphous silicon, silicon-germanium alloy, polymeric material, borosilicate glass, or organosilicate glass) is deposited within the via cavities. to form sacrificial via structures 477 . Excess portions of the sacrificial fill material may be removed from above a horizontal plane including the top surface of the etch stop dielectric layer 790 . Each of the sacrificial via structures 477 may contact a respective one component of the semiconductor devices 710 . For example, a subset of sacrificial via structures 477 may contact a respective gate electrode, and another subset of sacrificial via structures may contact a respective active region (eg, source region or drain region). have. In general, the electrically active nodes of the semiconductor devices 710 may be contacted by a respective sacrificial via structure 477 . The top surfaces of the sacrificial via structures 477 may be coplanar with the top surfaces of the etch stop dielectric layer 790 .

Referring to FIG. 18 , etch stop dielectric layer 790 and planarization dielectric layer 760 may be removed from each memory array region 100 and from each step region 200 . For example, a photoresist layer (not shown) may cover each region including the semiconductor devices 710 , a planarization dielectric layer 760 not covered by the photoresist layer and an etch stop dielectric layer ( Portions of 790 may be removed by at least one etching process, which may include an isotropic etching process (eg, a wet etching process) and/or an anisotropic etching process (eg, a reactive ion etching process). The top surface of the substrate 908 (eg, the top surface of the second doped well 10 ) may be physically exposed within the memory array region 100 and adjacent step regions 200 . The etch stop dielectric layer 790 and the planarization dielectric layer 760 may remain in the peripheral device region 300 and may be removed from the seal ring and guard ring region 400 .

An alternating stack of first and second material layers is subsequently formed. Each layer of first material may include a first material, and each layer of second material may include a second material that is different from the first material. When at least another alternating stack of material layers is subsequently formed over the alternating stack of first and second material layers, the alternating stack is referred to herein as a first-tier alternating stack. The level of the alternating stack of the first-tier is referred to herein as the first-tier level, and the level of the alternating stack to be subsequently formed immediately above the first-tier level is referred to herein as the second-tier level. is the way it is referred to.

The first-tier alternating stack may include a first insulating layer 132 as first material layers, and first spacer material layers as second material layers. In one embodiment, the first spacer material layers may be sacrificial material layers that are subsequently replaced with electrically conductive layers. In another embodiment, the first spacer material layers may be electrically conductive layers that are not subsequently replaced with other layers. While the present disclosure is described using embodiments in which the sacrificial material layers are replaced with electrically conductive layers, embodiments in which the spacer material layers are formed as electrically conductive layers, thereby excluding the need to perform replacement processes, are It is explicitly contemplated in the specification.

In one embodiment, the first material layers and the second material layers may be first insulating layers 132 and first sacrificial material layers 142 , respectively. In one embodiment, each first insulating layer 132 may include a first insulating material, and each first sacrificial material layer 142 may include a first sacrificial material. An alternating plurality of first insulating layers 132 and first sacrificial material layers 142 are formed over the substrate 908 . As used herein, “sacrificial material” refers to material that is removed during subsequent processing steps.

As used herein, an alternating stack of first elements and second elements refers to a structure in which instances of first elements and instances of second elements alternate. each instance of the first elements that are not the alternating plurality of end elements is adjacent on both sides by two instances of the second elements, each instance of the second elements that are not the alternating plurality of end elements is disposed at both ends adjoined by two instances of the first elements on the poles. The first elements may have the same overall thickness, or they may have different thicknesses. The second elements may have the same overall thickness, or they may have different thicknesses. An alternating plurality of first material layers and second material layers may begin with an instance of first material layers or with an instance of second material layers, and may end with an instance of first material layers or second material layers. have. In one embodiment, the instances of the first elements and the instances of the second elements may form units that repeat with periodicity within an alternating plurality.

The first-tier alternating stack 132 , 142 may include first insulating layers 132 composed of a first material, and first sacrificial material layers 142 composed of a second material different from the first material. can The first material of the first insulating layers 132 may be at least one insulating material. Insulating materials that may be used for the first insulating layers 132 include silicon oxide (including doped or undoped silicate glass), silicon nitride, silicon oxynitride, organosilicate glass (OSG), spin-on dielectric material, high dielectric material. dielectric metal oxides and silicates thereof commonly known as constant (high-k) dielectric oxides (eg, aluminum oxide, hafnium oxide, etc.), dielectric metal oxynitrides and silicates thereof, and organic insulating materials, including, but not limited to doesn't happen In one embodiment, the first material of the first insulating layers 132 may be silicon oxide.

The second material of the first sacrificial material layers 142 may be a sacrificial material that may be selectively removed with respect to the first material of the first insulating layers 132 . As used herein, removal of the first material is “selective” with respect to the second material if the removal process removes the first material at a rate that is at least twice the removal rate of the second material. The ratio of the removal rate of the first material to the removal rate of the second material is referred to herein as the “selectivity” of the removal process of the first material over the second material.

The first sacrificial material layers 142 may include an insulating material, a semiconductor material, or a conductive material. The second material of the first sacrificial material layers 142 may subsequently be replaced with electrically conductive electrodes that may serve, for example, as control gate electrodes of a vertical NAND device. In one embodiment, the first sacrificial material layers 142 may be material layers comprising silicon nitride.

In one embodiment, the first insulating layers 132 may include silicon oxide and the sacrificial material layers may include silicon nitride sacrificial material layers. The first material of the first insulating layers 132 may be deposited by chemical vapor deposition (CVD), for example. For example, when silicon oxide is used for the first insulating layers 132 , tetraethylorthosilicate (TEOS) may be used as a precursor material for the CVD process. The second material of the first sacrificial material layers 142 may be formed, for example, by CVD or atomic layer deposition (ALD).

The thicknesses of the first insulating layers 132 and the first sacrificial material layers 142 may be in the range of 20 nm to 50 nm, but each first insulating layer 132 and each first sacrificial material layer 142 . Smaller and larger thicknesses may be used for . The number of repetitions of the pairs of first insulating layer 132 and first sacrificial material layer 142 may range from 2 to 1,024, and typically from 8 to 256, although higher repetition numbers may also be used. In one embodiment, each first sacrificial material layer 142 in the first-tier alternating stack 132 , 142 has a substantially constant uniform thickness within each respective first sacrificial material layer 142 . can have

A first insulating cap layer 170 is subsequently formed over the first alternating stacks 132 , 142 . The first insulating cap layer 170 includes a dielectric material, which can be any dielectric material that can be used for the first insulating layer 132 . In one embodiment, the first insulating cap layer 170 includes the same dielectric material as the first insulating layer 132 . The thickness of the first insulating cap layer 170 may range from 20 nm to 300 nm, although smaller and larger thicknesses may also be used.

The first insulating cap layer 170 and the first-tier alternating stack 132 , 142 may be patterned to form first stepped surfaces within the stepped region 200 . Each layer of the first-tier alternating stack 132 , 142 may be removed from above the etch stop dielectric layer 790 . The stepped region 200 is a respective first stepped region in which first stepped surfaces are formed, and a second-tier structure (to be subsequently formed over the first-tier structure) and/or a respective first stepped region in which additional stepped surfaces are formed. or a second stepped region formed of additional tier structures. The first stepped surfaces, for example, form a mask layer having an opening therein, etch a cavity within the levels of the first insulating cap layer 170 , iteratively expand the etched area and etch the etched area may be formed by vertically recessing the cavity by etching each pair of the first sacrificial material layer 142 and the first insulating layer 132 located directly below the bottom surface of the etched cavity within. In one embodiment, the top surfaces of the first sacrificial material layers 142 may be physically exposed at the first stepped surfaces. The cavity overlying the first stepped surfaces is referred to herein as the first stepped cavity.

The first insulating layers 132 and the first sacrificial material layers 142 extend continuously over the entire area of the memory array region 100 , and thus also as first continuous insulating layers and first continuous sacrificial material layers, respectively. is referred to A vertically alternating sequence of first successive insulating layers and first successive layers of sacrificial material may be formed over the substrate 908 . First stepped surfaces are formed in peripheral portions of a vertically alternating sequence. Each layer in a vertically alternating sequence resides within the memory array region 100 . The lateral extent of the first successive layers of sacrificial material decreases with vertical distance from the substrate 908 in each step region 200 . In one embodiment, all layers of the vertically alternating sequence are removed from above the etch stop dielectric layer 790 , and the stepped surfaces of the remaining portions of the vertically alternating sequence are the regions where the etch stop dielectric layer 790 is present. does not extend to

Referring to FIG. 19 , a dielectric filling material (eg, undoped silicate glass or doped silicate glass) may be deposited to fill the first stepped cavity. Excess portions of dielectric filling material may be removed from above a horizontal plane comprising a top surface of first insulating cap layer 170 . The remainder of the dielectric fill material filling the region overlying the first stepped surfaces constitutes the first stepped dielectric material portion 165 . As used herein, a “stepped” element refers to an element having stepped surfaces and a horizontal cross-sectional area that monotonically increases as a function of the vertical distance from the upper surface of the substrate on which the element is present. A first counter-stepped portion of dielectric material overlies and contacts the etch stop dielectric layer 790 . The first-tier alternating stacks 132 , 142 and the first stepped dielectric material portion 165 collectively constitute a first-tier structure, which is a subsequently modified in-process structure.

An inter-tier dielectric layer 180 may optionally be deposited over the first-tier structures 132 , 142 , 170 , 165 . Inter-tier dielectric layer 180 includes a dielectric material such as silicon oxide. In one embodiment, the inter-tier dielectric layer 180 may include doped silicate glass having a greater etch rate than the material of the first insulating layers 132 (which may include undoped silicate glass). have. For example, the inter-tier dielectric layer 180 may include phosphosilicate glass. The thickness of the inter-tier dielectric layer 180 may range from 30 nm to 300 nm, although smaller and larger thicknesses may also be used.

20A and 20B , various first-tier openings 149 , 129 pass through inter-tier dielectric layer 180 and first-tier structures 132 , 142 , 170 , 165 through substrate 908 . ) can be formed into A layer of photoresist (not shown) may be applied over the inter-tier dielectric layer 180 and lithographically patterned to form various openings therethrough. The pattern of openings in the photoresist layer is transferred to the substrate 908 by a first anisotropic etch process through the inter-tier dielectric layer 180 and the first-tier structures 132 , 142 , 170 , and 165 , to form a variety of second-order substrates. One-tier openings 149 and 129 are formed simultaneously, ie during the first isotropic etching process. The various first-tier openings 149 , 129 may include first-tier memory openings 149 and first-tier support openings 129 . The positions of steps S in the first alternating stack 132 , 142 are illustrated by dashed lines in FIG. 20B .

The first-tier memory openings 149 are openings formed in the memory array region 100 through respective layers in the first alternating stack 132 , 142 and subsequently used to form memory stack structures. The first-tier memory openings 149 may be formed as clusters of the first-tier memory openings 149 that are laterally spaced apart along the second horizontal direction hd2 . Each cluster of first-tier memory openings 149 may be formed as a two-dimensional array of first-tier memory openings 149 .

The first-tier support openings 129 are openings formed in the stepped region 200 . A subset of the first-tier support openings 129 formed through the first stepped dielectric material portion 165 may be formed through respective horizontal surfaces of the first stepped surfaces.

In one embodiment, the first anisotropic etching process may include an initial step in which the materials of the first-tier alternating stack 132 , 142 are etched concurrently with the material of the first stepped dielectric material portion 165 . . The chemistry of the initial etch step etches the first and second materials of the first-tier alternating stack 132 , 142 while providing an average etch rate comparable to that of the first stepped dielectric material portion 165 . can be alternated to optimize The first anisotropic etch process may use, for example, a series of reactive ion etch processes or a single reactive etch process (eg, CF ₄ /O ₂ /Ar etch). The sidewalls of the various first-tier openings 149 , 129 may be substantially vertical or may be tapered. In one embodiment, the terminal portion of the anisotropic etching process may include an overetching step that is etched into the upper portion of the second doped well 10 . The photoresist layer may be subsequently removed, for example, by ashing.

Optionally, portions of first-tier memory openings 149 and first-tier support openings 129 at the level of inter-tier dielectric layer 180 may be laterally expanded by isotropic etching. . In this case, the inter-tier dielectric layer 180 is a dielectric material having a greater etch rate than the first insulating layer 132 (which may include undoped silicate glass) in diluted hydrofluoric acid (eg, borosilicate glass). An isotropic etch (eg, wet etch using HF) may be used to expand the lateral dimensions of the first-tier memory openings 149 at the level of the inter-tier dielectric layer 180 . Portions of first-tier memory openings 149 located at the level of inter-tier dielectric layer 180 are optionally subsequently to be formed through an alternating stack of second-tier (subsequently second second) tiers. can be enlarged to provide a larger landing pad for the second-tier memory openings - to be formed prior to formation of the tier memory openings

Referring to FIG. 21 , sacrificial first-tier opening filling portions 148 , 128 may be formed in various first-tier openings 149 , 129 . For example, a sacrificial first-tier fill material is deposited simultaneously onto each of the first-tier openings 149 and 129 . The sacrificial first-tier filling material includes a material that can be subsequently removed selectively with respect to the materials of the first insulating layers 132 and the first sacrificial material layers 142 .

In one embodiment, the sacrificial first-tier fill material comprises a semiconductor material such as silicon (eg, a-Si or polysilicon), a silicon-germanium alloy, germanium, a group III-V compound semiconductor material, or a combination thereof. can do. Optionally, a thin etch stop liner (eg, a silicon oxide layer or a silicon nitride layer having a thickness in the range of 1 nm to 3 nm) may be used prior to depositing the sacrificial first-tier fill material. The sacrificial first-tier fill material may be formed by non-conformal deposition or conformal deposition methods.

In another embodiment, the sacrificial first-tier fill material is silicon oxide having a higher etch rate than the materials of the first insulating layers 132 , the first insulating cap layer 170 , and the inter-tier dielectric layer 180 . material may be included. For example, the sacrificial first-tier fill material is formed by decomposition of tetraethylorthosilicate glass in a 100:1 diluted hydrofluoric acid densified TEOS oxide (i.e., tetraethylorthosilicate glass in a chemical vapor deposition process and subsequently in an annealing process). borosilicate glass, or porous or non-porous organosilicate glass having an etch rate at least 100 times higher than the etch rate of the densified silicon oxide material. In this case, a thin etch stop liner (eg, a silicon nitride layer having a thickness in the range of 1 nm to 3 nm) may be used prior to depositing the sacrificial first-tier fill material. The sacrificial first-tier fill material may be formed by non-conformal deposition or conformal deposition methods.

In another embodiment, the sacrificial first-tier fill material is an amorphous carbon-containing material (eg, amorphous carbon or diamond-like carbon) or a first alternating stack 132 that may be subsequently removed by ashing. 142) may include a silicone-based polymer that can be selectively removed subsequently.

Portions of the deposited sacrificial material may be removed from over the top layer of the first-tier alternating stack 132 , 142 , such as from over the inter-tier dielectric layer 180 . For example, the sacrificial first-tier fill material may be recessed into the top surface of the inter-tier dielectric layer 180 using a planarization process. The planarization process may include a recess etch, chemical mechanical planarization (CMP), or a combination thereof. The top surface of the inter-tier dielectric layer 180 may be used as an etch stop layer or a planarization stop layer.

The remaining portions of the sacrificial first-tier fill material include sacrificial first-tier opening fill portions 148 , 128 . Specifically, each remaining portion of the sacrificial material in the first-tier memory opening 149 constitutes the sacrificial first-tier memory opening filling portion 148 . Each remaining portion of the sacrificial material in the first-tier support opening 129 constitutes a sacrificial first-tier support opening filling portion 128 . The various sacrificial first-tier opening fill portions 148 , 128 simultaneously, ie, a deposition process that deposits the sacrificial first-tier fill material and from above the first alternating stack 132 , 142 (eg, inter- formed during the same set of processes including a planarization process that removes the first-tier deposition process (from above the top surface of the tier dielectric layer 180 ). The top surfaces of the sacrificial first-tier opening filling portions 148 , 128 may be coplanar with the top surface of the inter-tier dielectric layer 180 . Each of the sacrificial first-tier opening filling portions 148 , 128 may or may not include cavities therein.

Referring to FIG. 22 , a second-tier structure may be formed on the first-tier structures 132 , 142 , 170 , and 148 . The second-tier structure may include an additional alternating stack of insulating layers and spacer material layers, which may be sacrificial material layers. For example, a second alternating stack 232 , 242 of material layers may subsequently be formed on the top surface of the first alternating stack 132 , 142 . The second alternating stack 232 , 242 may include an alternating plurality of third and fourth material layers. Each layer of third material may include a third material, and each layer of fourth material may include a fourth material that is different from the third material. In one embodiment, the third material may be the same as the first material of the first insulating layer 132 , and the fourth material may be the same as the second material of the first sacrificial material layers 142 .

In one embodiment, the third material layers may be second insulating layers 232 , wherein the fourth material layers provide a second vertical spacing between each vertically neighboring pair of second insulating layers 232 . spacer material layers. In one embodiment, the third material layers and the fourth material layers may be second insulating layers 232 and second sacrificial material layers 242 , respectively. The third material of the second insulating layers 232 may be at least one insulating material. The fourth material of the second sacrificial material layers 242 may be a sacrificial material that may be selectively removed with respect to the third material of the second insulating layers 232 . The second sacrificial material layers 242 may include an insulating material, a semiconductor material, or a conductive material. The fourth material of the second sacrificial material layers 242 may subsequently be replaced with electrically conductive electrodes that may serve, for example, as control gate electrodes of a vertical NAND device.

In one embodiment, each second insulating layer 232 can include a second insulating material, and each second sacrificial material layer 242 can include a second sacrificial material. In this case, the second alternating stack 232 , 242 may include an alternating plurality of second insulating layers 232 and second sacrificial material layers 242 . The third material of the second insulating layers 232 may be deposited by chemical vapor deposition (CVD), for example. The fourth material of the second sacrificial material layers 242 may be formed, for example, by CVD or atomic layer deposition (ALD).

The third material of the second insulating layers 232 may be at least one insulating material. The insulating materials that can be used for the second insulating layers 232 can be any material that can be used for the first insulating layers 132 . The fourth material of the second sacrificial material layers 242 is a sacrificial material that can be selectively removed with respect to the third material of the second insulating layers 232 . The sacrificial materials that may be used for the second sacrificial material layers 242 may be any material that may be used for the first sacrificial material layers 142 . In one embodiment, the second insulating material may be the same as the first insulating material, and the second sacrificial material may be the same as the first sacrificial material.

The thicknesses of the second insulating layers 232 and the second sacrificial material layers 242 may range from 20 nm to 50 nm, but each second insulating layer 232 and each second sacrificial material layer 242 Smaller and larger thicknesses may be used for . The number of repetitions of the pairs of the second insulating layer 232 and the second sacrificial material layer 242 may range from 2 to 1,024, and typically from 8 to 256, although higher repetition numbers may also be used. In one embodiment, each second sacrificial material layer 242 in the second alternating stacks 232 , 242 may have a substantially invariant uniform thickness within each respective second sacrificial material layer 242 . have.

The second stepped surfaces in the second stepped region may undergo the same set of processing steps as those used to form the first stepped surfaces in the first stepped region, with adjustments suitable for the pattern of the at least one masking layer. It can be formed in the step area 200 using A second stepped dielectric material portion 265 may be formed over the second stepped surfaces in the stepped region 200 .

A second insulating cap layer 270 may subsequently be formed over the second alternating stacks 232 , 242 . The second insulating cap layer 270 includes a dielectric material that is different from the material of the second sacrificial material layers 242 . In one embodiment, the second insulating cap layer 270 may include silicon oxide. In one embodiment, the first and second sacrificial material layers 142 , 242 may include silicon nitride.

The second insulating layers 232 and the second sacrificial material layers 242 extend continuously over the entire area of the memory array region 100 , and thus also as second continuous insulating layers and second consecutive sacrificial material layers, respectively. is referred to A vertically alternating sequence of second successive insulating layers and second successive layers of sacrificial material may be formed over the substrate 908 . Second stepped surfaces are formed in peripheral portions of a vertically alternating sequence. Each layer in a vertically alternating sequence resides within the memory array region 100 . The lateral extent of the second successive layers of sacrificial material 242 decreases with vertical distance from the substrate 908 in each step region 200 . In one embodiment, all layers of the vertically alternating sequence are removed from above the etch stop dielectric layer 790 , and the stepped surfaces of the remaining portions of the vertically alternating sequence are the regions where the etch stop dielectric layer 790 is present. does not extend to

Generally speaking, at least one vertically alternating sequence of successive insulating layers 132 , 232 and successive spacer material layers (eg, successive sacrificial material layers 142 , 242 ) is to be formed over the substrate 908 . and at least one stepped dielectric material portion 165 , 265 may be formed over the stepped regions on the at least one vertically alternating sequence 132 , 142 , 232 , 242 .

Optionally, drain select level isolation structures 72 may be formed through a subset of the layers in the upper portion of the second two-tier alternating stack 232 , 242 . The second sacrificial material layers 242 cut by the drain select level isolation structures 72 correspond to the levels at which the drain select level electrically conductive layers are subsequently formed. Drain select level isolation structures 72 include a dielectric material such as silicon oxide. The drain select level isolation structures 72 may extend laterally in a first horizontal direction hd1 and are laterally spaced apart in a second horizontal direction hd2 perpendicular to the first horizontal direction hd1 . can be The second alternating stack 232 , 242 , the second stepped dielectric material portion 265 , the second insulating cap layer 270 , and the optional drain select level isolation structures 72 are collectively a second- tier structures 232 , 242 , 265 , 270 and 72

23A and 23B , various second-tier openings 249 and 229 may be formed through the second-tier structures 232 , 242 , 265 , 270 , and 72 . A photoresist layer (not shown) may be applied over the second insulating cap layer 270 and lithographically patterned to form various openings therethrough. The pattern of the second-tier memory openings 249 in the memory array region 100 may be the same as the pattern of the first-tier memory openings 149 that is the same as the pattern of the first-tier memory opening filling portion 148 . can The lateral extent of the pattern of second-tier support openings 229 in stepped region 200 may be limited into regions of stepped surfaces of second-tier alternating stack 232 , 242 . In other words, the second-tier support openings 229 may not be in the region where the second counter-stepped dielectric material portion 265 contacts the top surface of the inter-stack dielectric layer 180 . Accordingly, the lithographic mask used to pattern the first-tier openings 149 , 129 may be used to pattern the photoresist layer.

The pattern of openings in the photoresist layer is transferred through the second-tier structures 232 , 242 , 265 , 270 , 72 by a second anisotropic etch process, simultaneously, i.e., during the second anisotropic etch process, various second tiers. Openings 249 and 229 may be formed. The various second-tier openings 249 , 229 may include second-tier memory openings 249 and second-tier support openings 229 .

The second-tier memory openings 249 are formed directly on the top surface of each one of the sacrificial first-tier memory opening filling portions 148 . The second-tier support openings 229 are formed directly on the top surface of each one of the sacrificial first-tier support opening filling portions 128 . Also, each of the second-tier support openings 229 may be formed through a horizontal surface within the second stepped surfaces, which includes a second alternating stack 232 , 242 and a second stepped dielectric material portion. interfacial surfaces between 265 . The positions of steps S in the first-tier alternating stack 132 , 142 and the second tier alternating stack 232 , 242 are illustrated by dashed lines in FIG. 23B .

The second anisotropic etching process may include an etching step in which the materials of the second tier of alternating stacks 232 , 242 are etched simultaneously with the material of the second stepped dielectric material portion 265 . The chemistry of the etching step may be alternated to optimize the etching of the materials of the second-tier alternating stack 232 , 242 while providing an average etch rate comparable to that of the second stepped dielectric material portion 265 . can The second anisotropic etch process may use, for example, a series of reactive ion etch processes or a single reactive etch process (eg, CF ₄ /O ₂ /Ar etch). The sidewalls of the various second-tier openings 249 , 229 may be substantially vertical or may be tapered. The bottom perimeter of each second-tier opening 249 , 229 may be laterally offset and/or located entirely within the perimeter of the top surface of the underlying sacrificial first-tier opening filling portion 148 , 128 . can be The photoresist layer may be subsequently removed, for example, by ashing.

Referring to FIG. 24 , the sacrificial first-tier filling material of the sacrificial first-tier opening filling portions 148 , 128 includes the first and second insulating layers 132 , 232 , the first and second sacrificial material an etching process that etches the sacrificial first-tier fill material selective to the materials of the layers 142 , 242 , the first and second insulating cap layers 170 , 270 , and the inter-tier dielectric layer 180 . It can be removed using Memory opening 49 , also referred to as inter-tier memory opening 49 , is each combination of second-tier memory openings 249 and the volume from which sacrificial first-tier memory opening filling portion 148 is removed. is formed with Support opening 19 , also referred to as inter-tier support opening 19 , is each combination of second-tier support openings 229 and the volume from which sacrificial first-tier support opening fill portion 128 is removed therefrom. is formed with

25A-25D provide sequential cross-sectional views of the memory opening 49 during formation of the memory opening filling structure. The same structural change occurs in each of the memory openings 49 and the support openings 19 .

Referring to FIG. 25A , the pedestal channel portion 11 may be formed by a selective semiconductor material deposition process at the bottom of each memory opening 49 and at the bottom of each support opening 19 . A doped semiconductor material having a doping of a first conductivity type may be selectively grown from physically exposed surfaces of the second doped well 10, whereas growth of the doped semiconductor material from dielectric surfaces is a selective semiconductor. suppressed during the material deposition process. A semiconductor precursor gas, a dopant gas comprising dopant atoms of a first conductivity type, and an etchant may be flowed into a process chamber comprising the second exemplary structure, either simultaneously or alternately. Each pedestal channel portion 11 of the periphery of the top surface may be in contact with a sidewall of the first insulating layer 132 overlying and in contact with the lowermost first sacrificial material layer 142 . The atomic concentration of the first conductivity type dopants in the pedestal channel portions 11 may range from 1.0×10 ¹⁴ /cm 3 to 1.0×10 ¹⁸ /cm 3 , although smaller and larger dopant atomic concentrations may also be used. A pn junction may be formed at each interface between the second doped well 10 and the pedestal channel portion 11 .

Referring to FIG. 25B , a stack of layers including a blocking dielectric layer 52 , a charge storage layer 54 , a tunneling dielectric layer 56 , and a semiconductor channel material layer 60L is sequentially within the memory openings 49 . can be settled with The blocking dielectric layer 52 may include a single layer of dielectric material or a stack of multiple layers of dielectric material. In one embodiment, the blocking dielectric layer may include a dielectric metal oxide layer consisting essentially of a dielectric metal oxide. As used herein, dielectric metal oxide refers to a dielectric material comprising at least one metallic element and at least oxygen. The dielectric metal oxide may consist essentially of at least one metallic element and oxygen, or may consist essentially of at least one metallic element, oxygen, and at least one non-metallic element such as nitrogen. In one embodiment, the blocking dielectric layer 52 may include a dielectric metal oxide having a dielectric constant greater than 7.9, ie, a dielectric constant greater than that of silicon nitride. The thickness of the dielectric metal oxide layer may range from 1 nm to 20 nm, although smaller and larger thicknesses may also be used. The dielectric metal oxide layer may subsequently function as a portion of the dielectric material that blocks stored electrical charges from leaking to the control gate electrodes. In one embodiment, the blocking dielectric layer 52 includes aluminum oxide. Alternatively or additionally, the blocking dielectric layer 52 may include a dielectric semiconductor compound such as silicon oxide, silicon oxynitride, silicon nitride, or combinations thereof.

Subsequently, a charge storage layer 54 may be formed. In one embodiment, charge storage layer 54 may be a continuous layer or patterned discrete portions of charge trapping material including a dielectric charge trapping material, which may be, for example, silicon nitride. Alternatively, the charge storage layer 54 is patterned into multiple electrically isolated portions (eg, floating gates) by being formed into the sacrificial material layers 142 , 242 , for example in lateral recesses. patterned discrete portions or continuous layers of a conductive material such as doped polysilicon or metallic material to be crystallized. In one embodiment, the charge storage layer 54 comprises a silicon nitride layer. In one embodiment, the sacrificial material layers 142 , 242 and the insulating layers 132 , 232 may have vertically matching sidewalls, and the charge storage layer 54 may be formed as a single continuous layer. Alternatively, the sacrificial material layers 142 , 242 may be laterally recessed with respect to the sidewalls of the insulating layers 132 , 232 , wherein a combination of the deposition process and the anisotropic etching process comprises a plurality of vertically spaced It can be used to form the charge storage layer 54 as portions of memory material. The thickness of the charge storage layer 54 may range from 2 nm to 20 nm, although smaller and larger thicknesses may also be used.

Tunneling dielectric layer 56 comprises a dielectric material capable of charge tunneling under suitable electrical bias conditions. Charge tunneling can be performed via hot-carrier injection or by Fowler-Nordheim tunneling induced charge transfer, depending on the mode of operation of the monolithic three-dimensional NAND string memory device to be formed. Tunneling dielectric layer 56 is formed of silicon oxide, silicon nitride, silicon oxynitride, dielectric metal oxides (e.g., aluminum oxide and hafnium oxide), dielectric metal oxynitride, dielectric metal silicate, alloys thereof, and/or combinations thereof. may include In one embodiment, tunneling dielectric layer 56 may include a stack of a first silicon oxide layer, a silicon oxynitride layer, and a second silicon oxide layer, commonly known as an ONO stack. In one embodiment, tunneling dielectric layer 56 may include a substantially carbon-free silicon oxide layer or a substantially carbon-free silicon oxynitride layer. The thickness of the tunneling dielectric layer 56 may range from 2 nm to 20 nm, although smaller and larger thicknesses may be used. The stack of blocking dielectric layer 52 , charge storage layer 54 , and tunneling dielectric layer 56 constitutes a memory film 50 that stores memory bits.

The semiconductor channel material layer 60L is a p-doped semiconductor material, such as at least one elemental semiconductor material, at least one III-V compound semiconductor material, at least one II-VI compound semiconductor material, at least one organic semiconductor material, or other semiconductor materials known in the art. In one embodiment, the semiconductor channel material layer 60L may have uniform doping. In one embodiment, the semiconductor channel material layer 60L has a p-type doping, wherein the p-type dopants (eg, boron atoms) are from 1.0 × 10 ¹² /cm 3 to 1.0 × 10 ¹⁸ /cm 3 , e.g. For example, it is present in atomic concentrations ranging from 1.0 × 10 ¹⁴ /cm 3 to 1.0 × 10 ^{17 /cm 3 .} In one embodiment, the semiconductor channel material layer 60L comprises and/or consists essentially of boron-doped amorphous silicon or boron-doped polysilicon. In another embodiment, the semiconductor channel material layer 60L has an n-type doping, wherein the n-type dopants (eg, phosphorus atoms or arsenic atoms) are 1.0 × 10 ¹⁵ /cm 3 to 1.0 × 10 ¹⁹ / It is present in atomic concentrations in cm 3 , for example in the range from 1.0 × 10 ¹⁶ /cm 3 to 1.0 × 10 ^{18 /cm 3 .} The semiconductor channel material layer 60L may be formed by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD). The thickness of the semiconductor channel material layer 60L may range from 2 nm to 10 nm, although smaller and larger thicknesses may be used. A cavity 49' is formed in the volume of each memory opening 49 not filled with the deposited material layers 52, 54, 56, 60L.

Referring to FIG. 25C , if the cavities 49' in each memory opening are not completely filled by the semiconductor channel material layer 60L, filling any remaining portions of the cavities 49' in each memory opening is performed. A dielectric core layer may be deposited within the cavity 49'. The dielectric core layer includes a dielectric material such as silicon oxide or organosilicate glass. The dielectric core layer may be deposited by a conformal deposition method such as low pressure chemical vapor deposition (LPCVD), or by a self-planarizing deposition process such as spin coating. A horizontal portion of the dielectric core layer overlying the second insulating cap layer 270 may be removed by, for example, a recess etch. The recess etch continues until the top surfaces of the remaining portions of the dielectric core layer are recessed to a height between the top surface of the second insulating cap layer 270 and the bottom surface of the second insulating cap layer 270 . Each remaining portion of the dielectric core layer constitutes the dielectric core 62 .

Referring to FIG. 25D , doped semiconductor material may be deposited in the cavities overlying the dielectric core 62 . The doped semiconductor material has a doping of a conductivity type opposite to that of the semiconductor channel material layer 60L. Thus, the doped semiconductor material has an n-type doping. Deposited doped semiconductor material, semiconductor channel material layer 60L, tunneling dielectric layer 56, charge storage layer 54 and blocking dielectric layer overlying a horizontal plane comprising the top surface of the second insulating cap layer 270 ( Portions of 52 may be removed by a planarization process, such as a chemical mechanical planarization (CMP) process.

Each remaining portion of the n-doped semiconductor material constitutes the drain region 63 . The dopant concentration in drain regions 63 may range from 5.0 x 10 ¹⁹ /cm 3 to 2.0 x 10 ²¹ /cm 3 , although lower or higher dopant concentrations may also be used. The doped semiconductor material may be, for example, doped polysilicon.

Each remaining portion of the semiconductor channel material layer 60L constitutes a vertical semiconductor channel 60 through which current may flow when a vertical NAND device comprising the vertical semiconductor channel 60 is turned on. Tunneling dielectric layer 56 is surrounded by charge storage layer 54 and laterally surrounds vertical semiconductor channel 60 . Each adjacent set of blocking dielectric layer 52 , charge storage layer 54 , and tunneling dielectric layer 56 collectively constitutes memory film 50 , which is capable of storing electrical charges with a macroscopic hold time. . In some embodiments, blocking dielectric layer 52 may not be present in memory film 50 at this stage, and blocking dielectric layer may be formed subsequently after formation of the backside recesses. As used herein, macroscopic hold time refers to a hold time suitable for operation of a memory device as a permanent memory device, such as a hold time in excess of 24 hours.

Each combination of memory film 50 and vertical semiconductor channel 60 (which is a vertical semiconductor channel) in memory opening 49 constitutes memory stack structure 55 . The memory stack structure 55 is a combination of a vertical semiconductor channel 60 , a tunneling dielectric layer 56 , a plurality of memory elements comprising portions of a charge storage layer 54 , and an optional blocking dielectric layer 52 . . Each combination of memory stack structure 55 , dielectric core 62 , and drain region 63 within memory opening 49 is comprised of a memory opening filling structure 58 . semiconductor material layer 910 and doped wells buried therein, first-tier structures 132, 142, 170, 165, second-tier structures 232, 242, 270, 265, 72, inter-tier dielectric Layer 180, and memory aperture filling structures 58 collectively constitute a memory level assembly.

Referring to FIG. 26 , a second exemplary structure is illustrated after formation of the memory aperture filling structure 58 . The support pillar structures 20 are formed in the support openings 19 concurrently with the formation of the memory opening filling structures 58 . Each support pillar structure 20 may have the same set of components as the memory aperture filling structure 58 . Generally, the plurality of sets of memory stack structures 55 are formed through a vertically alternating sequence of first successive insulating layers 132 and first successive sacrificial material layers 142 and second successive insulating layers. 232 and second successive layers of sacrificial material 242 may be formed through a vertically alternating sequence. The first successive insulating layers 132 and the second successive insulating layers 232 may be considered a set of successive insulating layers 132 , 232 and a set of successive sacrificial material layers 142 , 242 . Thus, each set of memory stack structures 55 may extend vertically through a vertically alternating sequence of successive insulating layers 132 , 232 and successive sacrificial material layers 142 , 242 . Each set of memory stack structures 55 extends vertically through respective regions in a vertically alternating sequence spaced laterally along a second horizontal direction hd2 . Each of the memory stack structures 55 includes a respective vertical semiconductor channel 60 and a respective memory film 60 .

27A-27C , a first contact level dielectric layer 280 may be formed over the second-tier structures 232 , 242 , 270 , 265 , and 72 . The first contact level dielectric layer 280 includes a dielectric material such as silicon oxide and may be formed by a conformal or non-conformal deposition process. For example, the first contact level dielectric layer 280 may include undoped silicate glass and may have a thickness in the range of 100 nm to 600 nm, although smaller and larger thicknesses may also be used.

A photoresist layer (not shown) may be applied over the first contact level dielectric layer 280 , and an elongate opening extending along a first horizontal direction hd1 between clusters of memory opening filling structures 58 . can be lithographically patterned to form The backside trenches 79 form a pattern in the photoresist layer with the first contact level dielectric layer 280 , the second tier structures 232 , 242 , 270 , 265 , 72 , and the first tier structures 132 , 142 . , 170 , 165 to the top surface of the substrate 908 . As used herein, “back trench” refers to a trench that laterally divides a vertically alternating sequence of successive insulating layers 132 , 232 and successive sacrificial material layers 142 , 242 . Accordingly, the first contact level dielectric layer 280 underlying the openings in the photoresist layer, the second tier structures 232 , 242 , 270 , 265 , 72 , the first tier structures 132 , 142 , 170 , Portions of 165 and substrate 908 may be removed to form backside trenches 79 . Each of the back trenches 79 may be formed entirely in the memory array region 100 and adjacent step regions 200 .

In one embodiment, backside trenches 79 may be formed between clusters of memory stack structures 55 . According to an embodiment of the present disclosure, the backside trenches 79 may extend laterally along a first horizontal direction hd1 , in a vertically alternating sequence with the insulating layers 132 , 232 and the sacrificial material. It may be partitioned into a plurality of alternating stacks of layers 142 , 242 . Each alternating stack of insulating layers 132 , 232 and sacrificial material layers 142 , 242 is an alternating stack of first insulating layers 132 and a first-tier of first sacrificial material layers 142 , and a second two-tier alternating stack of second insulating layers 232 and second sacrificial material layers 242 . The clusters of the memory stack structures 55 may be laterally spaced apart along the second horizontal direction hd2 by the rear trenches 79 .

In one embodiment, each alternating stack {(132, 142), (232, 2342)} of the plurality of alternating stacks {(132, 142), (232, 2342)} comprises layers of spacer material 132, 232 includes a respective step region 200 with lateral extents that decrease with increasing vertical distance from substrate 908 . In one embodiment, each of the plurality of backside trenches 79 may be laterally bounded by sidewalls of at least one alternating stack {(132, 142), (232, 2342)}. A first subset of divider trenches 79 may extend laterally along a first horizontal direction hd1 between a pair of alternating stacks {(132, 142), (232, 2342)}. .

Referring to FIG. 28 , the sacrificial material layers 142 , 242 include insulating layers 132 , 232 , first and second insulating cap layers 170 , 270 , a first contact level dielectric layer 280 , and a substrate ( 908) can be selectively removed. For example, the materials of the insulating layers 132 , 232 , the first and second insulating cap layers 170 , 270 , the stepped dielectric material portions 165 , 265 , and the outermost of the memory films 50 . An etchant that selectively etches the materials of the sacrificial material layers 142 , 242 with respect to the material of the outer layer may be introduced into the backside trenches 79 using, for example, an isotropic etch process. For example, the sacrificial material layers 142 , 242 may include silicon nitride, the materials of the insulating layers 132 , 232 , the first and second insulating cap layers 170 , 270 , a stepped dielectric material. The portions 165 , 265 and the outermost layer of the memory films 50 may include silicon oxide materials.

The isotropic etch process may be a wet etch process using a wet etch solution, or it may be a vapor phase (dry) etch process in which the etchant is introduced into the backside trench 79 in the vapor phase. For example, where the sacrificial material layers 142 , 242 include silicon nitride, the etching process may be a wet etching process in which the second exemplary structure is immersed in a wet etching tank comprising phosphoric acid, which is silicon oxide. , silicon, and silicon nitride selectively to various other materials used in the art.

Back recesses 143 , 243 are formed in the volumes from which the sacrificial material layers 142 , 242 have been removed. The back recesses 143 and 243 are the first back recesses 143 formed in the volumes from which the first sacrificial material layers 142 have been removed and the volumes from which the second sacrificial material layers 242 have been removed. and second rear recesses 243 formed in the . Each of the back recesses 143 , 243 may be a laterally extending cavity, which has a lateral dimension greater than the vertical extent of the cavity. In other words, the lateral dimension of each of the back recesses 143 , 243 may be greater than the height of the respective back recess 143 , 243 . A plurality of back recesses 143 , 243 may be formed in the volumes from which the material of the sacrificial material layers 142 , 242 has been removed. Each of the backside recesses 143 , 243 may extend substantially parallel to a top surface of the semiconductor substrate layer 909 . The back recesses 143 , 243 may be vertically bounded by the top surface of the underlying insulating layer 132 , 232 and the bottom surface of the overlying insulating layer 132 , 232 . In one embodiment, each of the back recesses 143 and 243 may have a uniform height throughout.

29A and 29B , an oxidation process may be performed to oxidize physically exposed portions of the pedestal channel portion 11 . Tubular insulating spacers (not explicitly shown) may be formed around each pedestal channel portion 11 . A back blocking dielectric layer (not shown) may optionally be deposited in the back recesses 143 , 243 and back trenches 79 and over the first contact level dielectric layer 280 . The back blocking dielectric layer includes a dielectric material, such as a dielectric metal oxide, silicon oxide, or a combination thereof. For example, the back blocking dielectric layer may include aluminum oxide. The back blocking dielectric layer may be formed by a conformal deposition process such as chemical vapor deposition or atomic layer deposition. The thickness of the back blocking dielectric layer may range from 1 nm to 20 nm, such as 2 nm to 10 nm, although smaller and larger thicknesses may also be used.

At least one conductive material may be deposited in the plurality of backside recesses 243 , 243 , on the sidewalls of the backside trench 79 , and over the first contact level dielectric layer 280 . The at least one conductive material may be deposited by a conformal deposition method, which may be, for example, chemical vapor deposition (CVD), atomic layer deposition (ALD), electroless plating, electroplating, or combinations thereof. The at least one conductive material is an elemental metal, an intermetallic alloy of at least two elemental metals, a conductive nitride of at least one elemental metal, a conductive metal oxide, a conductive doped semiconductor material, a conductive metal-semiconductor alloy such as a metal silicide, alloys, and combinations thereof or stacks thereof.

In an embodiment, the at least one conductive material may comprise at least one metallic material, ie an electrically conductive material comprising at least one metallic element. Non-limiting exemplary metallic materials that may be deposited in the back recesses 143 , 243 include tungsten, tungsten nitride, titanium, titanium nitride, tantalum, tantalum nitride, cobalt, and ruthenium. For example, the at least one conductive material may include a conductive metallic nitride material such as TiN, TaN, WN, or combinations thereof, and a conductive filler material such as W, Co, Ru, Mo, Cu, or combinations thereof. and a conductive metallic nitride liner comprising In one embodiment, the at least one conductive material for filling the back recesses 143 , 243 may be a combination of a titanium nitride layer and a tungsten filling material.

The electrically conductive layers 146 , 246 may be formed in the back recesses 143 , 243 by deposition of at least one conductive material. A plurality of first electrically conductive layers 146 may be formed in the plurality of first back recesses 143 , and a plurality of second electrically conductive layers 246 may be formed in the plurality of second back recesses 243 . A continuous layer of metallic material (not shown) may be formed on the sidewalls of each backside trench 79 and over the first contact level dielectric layer 280 . Each of the first electrically conductive layers 146 and the second electrically conductive layers 246 may include a respective conductive metallic nitride liner and a respective conductive filler material. Accordingly, the first and second sacrificial material layers 142 and 242 may be replaced with first and second electrically conductive layers 146 and 246 , respectively. Specifically, each first sacrificial material layer 142 may be replaced with an optional portion of a backside blocking dielectric layer and a first electrically conductive layer 146 , each second sacrificial material layer 242 being a backside blocking An optional portion of the dielectric layer and a second electrically conductive layer 246 may be replaced. A backside cavity exists within the portion of each backside trench 79 that is not filled with a continuous layer of metallic material.

Residual conductive material may be removed from inside the backside trenches 79 . Specifically, the deposited metallic material of the continuous metallic material layer may be etched back from the sidewalls of each backside trench 79 and from above the first contact level dielectric layer 280, for example by anisotropic or isotropic etching. have. Each remaining portion of the deposited metallic material in the first back recesses constitutes a first electrically conductive layer 146 . Each remaining portion of the deposited metallic material in the second back recesses constitutes a second electrically conductive layer 246 . The sidewalls of the first electrically conductive material layers 146 and the second electrically conductive layers may be physically exposed in their respective backside trenches 79 . The rear trenches may have a pair of curved sidewalls having a non-periodic width variation along the first horizontal direction hd1 and a non-linear width variation along the vertical direction.

Each electrically conductive layer 146 , 246 may be a conductive sheet including openings. A first subset of the openings through each electrically conductive layer 146 , 246 may be filled with memory opening filling structures 58 . A second subset of the openings through each electrically conductive layer 146 , 246 may be filled with support column structures 20 . Each electrically conductive layer 146 , 246 may have a smaller area than any underlying electrically conductive layer 146 , 246 because of the first and second stepped surfaces. Each electrically conductive layer 146 , 246 may have a larger area than any overlying electrically conductive layer 146 , 246 because of the first and second stepped surfaces.

In some embodiments, drain select level isolation structures 72 may be provided at the top levels of the second electrically conductive layers 246 . A subset of the second electrically conductive layers 246 located at the levels of the drain select level isolation structures 72 constitute the drain select gate electrodes. The subset of electrically conductive layers 146 and 246 located below the drain select gate electrodes may function as combinations of a control gate and a word line located at the same level. The control gate electrodes in each electrically conductive layer 146 , 246 are control gate electrodes for a vertical memory device that includes a memory stack structure 55 .

Each of the memory stack structures 55 includes a vertical stack of memory elements located at a respective level of electrically conductive layers 146 , 246 . The subset of electrically conductive layers 146 and 246 may include word lines for memory elements. The memory level assembly is positioned over the semiconductor substrate layer 909 . The memory level assembly includes at least one alternating stack 132 , 146 , 232 , 246 and memory stack structures 55 extending vertically through the at least one alternating stack 132 , 146 , 232 , 246 . do.

Generally, the sacrificial material layers 142 , 242 in the plurality of alternating stacks { ( 132 , 142 , ( 232 , 242 ) ) are for an etchant that etches the sacrificial material layers 142 , 242 and

may be replaced by electrically conductive layers 1'46, 246 employing backside trenches 79 as conduits for a reactant depositing at least one conductive material of electrically conductive layers 146,246. A plurality of alternating stacks of insulating layers 132 , 232 and electrically conductive layers 146 , 246 may be positioned on substrate 908 , and a plurality of laterally extending along a first horizontal direction hd1 . They may be laterally spaced apart by backside trenches 79 .

30A-30D , a conformal dielectric material layer (eg, a silicon oxide layer) may be deposited in peripheral portions of the backside trenches 79 , and an anisotropic etch process removes horizontal portions of the conformal dielectric material layer can be performed to Each remaining vertical portion of the conformal dielectric material layer in the back trenches 79 constitutes a back trench dielectric spacer 74 .

Electrical dopants may be implanted into physically exposed portions of second doped wells 10 to form source regions 61 . In one embodiment, the second doped wells 10 and the vertical semiconductor channels 60 may have doping of a first conductivity type, and the source regions 61 are of a second conductivity type opposite to the first conductivity type. may have doping of For example, the first conductivity type may be p-type, the second conductivity type may be n-type, or vice versa. When the source regions 61 are formed, the source regions 61 may have an atomic concentration of electrical dopants of the second conductivity type in the range of ^{5.0×10 19} /cm 3 to 2.0×10 ^{21 /cm 3 .}

At least one conductive fill material may be deposited in the remaining volumes of the backside trenches 79 . For example, the at least one conductive filling material may include doped polysilicon, conductive metallic nitride, and/or a metal filling material (eg, tungsten). Excess portions of the at least one conductive fill material may be removed from above a horizontal plane comprising a top surface of the first contact level dielectric layer 280 . Each remaining portion of the at least one conductive fill material in the backside trenches 79 may constitute a source contact via structure 76 . Each of the source contact via structures 76 is a portion of a conductive fill material. The set of all material portions that fill the back trench 79 constitute the back trench fill structures 74 , 76 . In one embodiment, the back trench fill structures 74 , 76 may include a back trench dielectric spacer 74 and a source contact via structure 76 .

A plurality of alternating stacks {(132, 146), (232, 246)} and a plurality of back trench fill structures 74, 76 are alternately interlaced along the second horizontal direction hd2. In one embodiment, each of the plurality of back trench fill structures 74 , 76 comprises a plurality of alternating stacks { (132, 146), (232, 246) extending laterally along a first horizontal direction (hd1). )} in contact with the sidewalls of the alternating stack {(132, 146), (232, 246)}.

Referring to FIG. 31 , a second contact level dielectric layer 282 may be selectively formed over the first contact level dielectric layer 280 . The second contact level dielectric layer 282 includes a dielectric material such as silicon oxide. A layer of photoresist (not shown) may be applied over the contact level dielectric layers 280 and 282 and lithographically patterned therethrough to form various contact via openings. For example, openings for forming drain contact via structures may be formed over drain regions 63 in memory array regions 100 , and openings for forming step region contact via structures may be formed in step regions 200 . ) can be formed. An anisotropic etch process is performed to transfer the pattern in the photoresist layer through the contact level dielectric layers 280 and 282 and the underlying dielectric material portions. Drain regions 63 and electrically conductive layers 146 , 246 may be used as etch stop structures. Drain contact via cavities may be formed over each drain region 63 , wherein the stepped region contact via cavities are respectively at the stepped surface underlying the first and second counter-stepped dielectric material portions 165 , 265 . may be formed over the electrically conductive layers 146 and 246 of The photoresist layer may be subsequently removed, for example by ashing.

Drain contact via structures 88 may be formed in the drain contact via cavities and on the top surface of each one of the drain regions 63 . Step area contact via structures 86 are formed within the step area contact via cavities and on the top surface of one respective one of electrically conductive layers 146 , 246 . The stepped region contact via structures 86 may include drain select level contact via structures that contact a subset of the second electrically conductive layers 246 that function as drain select level gate electrodes. In addition, step area contact via structures 86 are word line contact below the drain select level gate electrodes and in contact with electrically conductive layers 146 , 246 serving as word lines for memory stack structures 55 . Via structures may be included.

Peripheral device contact via cavities via contact level dielectric layers 280 , 282 and second and first counter-stepped dielectric material portions 265 , 165 through respective one top surface of sacrificial via structures 477 . may be formed on the Peripheral device contact via cavities are perpendicular to the top surface of a respective component of semiconductor devices 710 by removing sacrificial via structures 477 optional for etch stop dielectric layer 790 and planarization dielectric layer 760 . can be extended to At least one conductive material may be deposited within the peripheral device contact via cavities. Excess portions of the at least one conductive material may be removed from above a horizontal plane comprising a top surface of the contact level dielectric layer 280 . Each remaining portion of the at least one conductive material within the peripheral device contact via cavity constitutes a peripheral device contact via structure 488 . Peripheral device contact via structures 488 may be formed in peripheral device regions 300 . Peripheral device regions 300 may include sense amplifier circuits, word line and select gate electrode switch regions, and other peripheral device regions.

A bit line level dielectric layer 290 may be formed over the contact level dielectric layers 280 , 282 . Bit line level metal interconnect structures 98 , 96 may be formed in bit line level dielectric layer 290 . Bit line level metal interconnect structures 98 , 96 include bit lines 98 in contact with a respective one of drain contact via structures 88 , and step area contact via structures 86 and/or perimeter. interconnect line structures 96 in contact with and/or electrically coupled to at least one of the device contact via structures 488 .

Referring to FIG. 32 , top dielectric material portions may be formed over the bit line level dielectric layer 290 . For example, additional layers of dielectric material (referred to herein as upper level dielectric material layers 960 ) may be formed over the bit line level dielectric layer 290 . Each of the upper level dielectric material layers 960 may include a dielectric material such as silicon oxide. The top of the upper level dielectric material layers 960 may include a diffusion barrier dielectric material such as silicon nitride. Additional metal interconnect structures (referred to herein as top level metal interconnect structures 980 ) may be formed in the top level dielectric material layers 960 . Top level metal interconnect structures 980 include metal line structures that provide electrical connections between semiconductor devices 710 and various nodes of a three-dimensional array of memory elements including memory stack structures 55 and It may include metal via structures.

33A-33F , various views of the second exemplary structure are illustrated after formation of the seal ring cavities 71 and the guard ring cavity 77 . 33A-33D illustrate the construction of a second exemplary structure. 33E and 33F illustrate an alternative embodiment of the second exemplary structure of FIGS. 33A-33D .

For example, a photoresist layer may be applied over the top level dielectric material layers 960 and lithographically patterned to form a set of nested openings therein. Each of the openings in the photoresist layer can have the general shape of a rectangle with or without rounded corners, or a polygon derived from a rectangle with the addition of small sides. Each of the openings in the photoresist layer may be formed in the seal ring and guard ring region 400 .

An anisotropic etch process is performed to form a pattern of openings in the photoresist layer into upper dielectric material portions (eg, upper level dielectric material layers 960 ), bit line level dielectric layer 290 , contact level dielectric layers 280 , 282 . ), and the reverse-stepped dielectric material layers 165 , 265 through the top surface of the substrate 908 . A plurality of nested seal ring cavities 71 extend from a top surface of the upper dielectric material portions (eg, upper level dielectric material layers 960 ) to the substrate 908 . Each of the plurality of nested seal ring cavities 71 has a respective pair of first sidewall segments parallel to first sidewalls of the semiconductor die to be subsequently formed, and a respective pair of first sidewall segments perpendicular to the first sidewalls of the semiconductor die. a respective pair of second sidewall segments. In one embodiment, the first sidewall segments of the nested seal ring cavities 71 may extend laterally along the first horizontal direction hd1 , and the first sidewall segments of the nested seal ring cavities 71 may extend laterally along the first horizontal direction hd1 . The two sidewall segments may extend laterally along the second horizontal direction hd2 . Each of the nested seal ring cavities 71 may have the configuration of a moat trench that laterally surrounds and encloses a respective inner structure bounded therein.

In the illustrative example, the plurality of nested seal ring cavities 71 include an inner seal ring cavity 711 that is an innermost portion of the plurality of nested seal ring cavities 71 , an inner seal ring cavity 711 . may include an intermediate seal ring cavity 712 that laterally surrounds the , and an outer seal ring cavity 713 that laterally surrounds the intermediate seal ring cavity 712 . Additional seal ring cavities (not shown) may be formed around the outer seal ring cavity 713 . In one embodiment, the guard ring cavity 77 may be formed outside the outermost cavity 713 of the nested seal ring cavities 71 concurrently with the formation of the nested seal ring cavities 71 . Guard ring cavity 77 may extend vertically from a top surface of the upper dielectric material portions (eg, upper level dielectric material layers 960 ) to substrate 908 .

Each of the nested seal ring cavities 71 may include straight segments extending laterally along the first horizontal direction hd1 or along the second horizontal direction hd2 . In one embodiment, at least one of the nested seal ring cavities (eg, 712 ) can have a width that induces formation of voids (eg, air gaps) upon deposition of the fill material. In one embodiment, at least another of the nested seal ring cavities (eg, 711 and/or 713 ) may have a width conducive to conformal filling thereof. Generally, the plurality of nested seal ring cavities 71 comprise at least one first seal ring cavity having a smaller width conducive to the formation of a first void therein when depositing fill material therein. 712 , and at least one second seal ring cavity 711 , 713 having a greater width conducive to conformal filling with the filling material with a second void free of voids or having a void volume smaller than the first void. can As used herein, the width of a cavity or segment of a cavity refers to the average width of a cavity or segment of a cavity. The height of the seal ring cavities 71 may range from 5 micrometers to 40 micrometers, such as from 10 micrometers to 20 micrometers.

In one embodiment, each segment of the seal ring cavity 71 may have a respective width that is the same throughout. For example, as shown in FIG. 33D , the inner seal ring cavity 711 may have an overall inner cavity width WI, and the intermediate seal ring cavity 712 may have an overall intermediate cavity width WT. ), and the outer seal ring cavity 713 may have an outer cavity width WO throughout. In one embodiment, the median cavity width WT may be less than the inner cavity width WI and may be less than the outer cavity width WO. In one embodiment, the median cavity width WT may be less than 1/2 the inner cavity width WI and less than 1/2 the outer cavity width WO. In one embodiment, the median cavity width WT is less than 1/4 of the medial cavity width WI and the outer cavity width WO, such as 1/5 of the medial cavity width WI and the outer-cavity width WO to 1/10. The outer cavity width WO may be equal to, greater than, or smaller than the inner cavity width WI. The ratio of the height of the seal ring cavity 71 to the width of the seal ring cavity 71 is referred to herein as the aspect ratio of the seal ring cavity 71 . The aspect ratio of the inner seal ring cavity 711 and the aspect ratio of the outer seal ring cavity 713 may range from 5 to 40, such as from 10 to 20. The aspect ratio of the intermediate seal ring cavity 712 may be between 10 and 160, such as between 20 and 80, although smaller and larger aspect ratios may also be employed. The guard ring cavity 77 may have a guard ring width WG throughout. The guard ring width WG may be equal to or greater than the inner cavity width WI and/or the outer cavity width WO. Although the intermediate seal ring cavity 712 is illustrated as having a smaller width than the inner and outer seal ring cavities 711 , 713 , in alternative embodiments, the inner and/or outer seal ring cavities may include at least one other It may have a smaller width than the seal ring cavity. Also, while three seal ring cavities are illustrated, two or more than three seal ring cavities may be used instead, one or more of which has a smaller width than at least one other seal ring cavity.

The alternative configuration illustrated in FIGS. 33E and 33F is a seal extending along a second horizontal direction hd2 relative to the width of the first segments of the seal ring cavity 71 relative to at least one of the seal ring cavities 71 . It can be derived from the second exemplary structure of FIGS. 33A-33D by varying the width of the second segments of the ring cavity 71 . In this case, for at least one of the seal ring cavities (eg, 712 ), the first segments of the seal ring cavity 712 extending along the first horizontal direction hd1 may have a respective first segment width. and the second segments of the seal ring cavity 712 extending along the second horizontal direction hd2 may have respective second segment widths different from the cavity first segment widths. For example, first segments of the inner seal ring cavity 711 extending laterally along a first horizontal direction hd1 may have an inner cavity first segment width WIA, and a second horizontal direction hd2 The second segments of the inner seal ring cavity 711 extending laterally along ) may have an inner cavity second segment width WIB. The first segments of the intermediate seal ring cavity 712 extending laterally along the first horizontal direction hd1 may have an intermediate cavity first segment width WTA and laterally extending along the second horizontal direction hd2 . The second segments of the intermediate seal ring cavity 712 extending in the direction may have an intermediate cavity second segment width WTB. The first segments of the outer seal ring cavity 713 extending laterally along the first horizontal direction hd1 may have an outer cavity first segment width WOA and laterally along the second horizontal direction hd2 . The second segments of the outer seal ring cavity 713 extending in the direction may have an outer cavity second segment width WOB. The intermediate cavity first segment width WTA may be different from the intermediate cavity second segment width WTB. The inner cavity first segment width WIA may be the same as or different from the inner cavity second segment width WIB. The outer cavity first segment width WOA may be the same as or different from the outer cavity second segment width WOB. In one embodiment, the intermediate cavity first segment width WTA may be less than the inner cavity first segment width WIA and may be less than the outer cavity first segment width WOA. Although a first segment of the seal ring cavity extending in a first horizontal direction is illustrated as having a smaller width than a second segment of the same seal ring cavity extending in a second horizontal direction, in an alternative embodiment, in the second horizontal direction Note that the second segment of the extending seal ring cavity may have a smaller width than the first segment, depending on whether the layers of the device exert a greater concave deflection on the substrate in the second or first horizontal direction, respectively. Should be.

34A-35E , various views of a second exemplary structure are illustrated after formation of the seal ring structures 73 and the guard ring 78 . 35A-34C illustrate the construction of a second exemplary structure. 34D and 34E illustrate an alternative embodiment of the second exemplary structure of FIGS. 34A-34C .

At least one diffusion barrier material is deposited in each of the plurality of nested seal ring cavities 71 and guard ring cavity 77 . The at least one diffusion barrier material comprises a material that blocks diffusion of moisture, hydrogen and/or impurity metals. For example, the at least one diffusion barrier material may comprise and/or consist of at least one material selected from tungsten, conductive metal nitride (eg, titanium nitride) and/or silicon nitride. In one embodiment, the at least one diffusion barrier material may consist of a layer stack of conductive metal nitride (eg, titanium nitride) and tungsten. Where the at least one diffusion barrier material comprises a conductive material such as tungsten, excess portions of the at least one diffusion barrier material are removed from above the top surface of the upper level dielectric layers 960 by a planarization process, such as a chemical mechanical planarization process. can be removed.

Each portion of the at least one diffusion barrier material filling a respective one of the seal ring cavities 71 constitutes the seal ring structure 73 . A portion of the at least one diffusion barrier material filling the guard ring cavity 77 constitutes the guard ring structure 78 . A plurality of nested seal ring structures 73 are formed, which include portions of at least one diffusion barrier material disposed within the plurality of nested seal ring cavities 71 . A plurality of nested seal ring structures 73 extend from a top surface of the upper dielectric material portions (eg, upper level dielectric material layers 960 ) to the substrate 908 . The plurality of nested seal ring structures 73 include alternating stacks of insulating layers 132 , 232 and electrically conductive layers 146 , 246 , and an innermost sidewall of the nested seal ring structures 73 . Laterally surrounds and encloses the inner region of the upper dielectric material portions located inside them. The plurality of nested seal ring structures 73 include an inner seal ring structure 731 formed within the inner seal ring cavity 711 , an intermediate seal ring structure 732 formed within the intermediate seal ring cavity 712 , and may include an outer seal ring structure 733 formed within the outer seal ring cavity 713 .

In one embodiment, the plurality of nested seal ring structures 73 includes a first seal ring structure (eg, intermediate seal ring structure 732 ) having a first void 742 (eg, air gap) therein. , and a second seal ring structure (eg, inner seal ring structure 731 ) comprising a portion of a second material that laterally encloses or is laterally encapsulated by the first seal ring structure and includes at least one diffusion barrier material. ) or an outer seal ring structure 733 ). A first seal ring structure (eg, intermediate seal ring structure 732 ) may have a first seal ring width (eg, intermediate cavity width WT) and a second seal ring structure (eg, outer seal ring structure ( WT)) 733 ) or inner seal ring structure 731 ) may have a second seal ring width (eg, outer cavity width WO or inner cavity width WI) between the inner sidewall and the outer sidewall thereof. The first seal ring width may be less than the second seal ring width. In this case, the second seal ring structure (eg, outer seal ring structure 733 or inner seal ring structure 731 ) may have second voids 741 or 743 therein, or may have no voids therein. can When present, the second void 741 or 743 has a smaller width than the first void 742 .

Each seal ring structure (eg, outer seal ring structure 733 and inner seal ring structure 731 ) is void free or has smaller void functions as a conventional seal ring structure. Each seal ring structure (eg, intermediate seal ring structure 732 ) having a larger void 742 functions as a mechanical stress absorber structure, which in the second example by deformation of the at least one diffusion barrier material around the void. It can reduce the mechanical stress in the structural structure.

In one embodiment shown in FIG. 34C , the intermediate seal ring structure 732 may include a first void 742 having a width referred to herein as an intermediate void width V2 . Outer seal ring structure 733 may have no voids therein, or may include voids 743 , referred to herein as outer void width V3 , and having a width less than intermediate void width V2 . The inner seal ring structure 731 may be free of voids therein, or may include voids 741 , referred to herein as the inner void width V1 , and having a width less than the intermediate void width V2 . The larger void width V2 tunes and/or offsets the warpage imparted on the substrate by the layers of the device, such as the electrically conductive layers 146 , 246 and/or the layers of the seal ring structures 73 .

In one embodiment shown in FIG. 18C , each of the plurality of nested seal ring structures 73 includes a respective pair of first sidewall segments 752A parallel to the first horizontal direction hd1 , and a second and a respective pair of second sidewall segments 752B parallel to the horizontal direction hd2 . The void 742 in the intermediate seal ring structure 732 may extend continuously around the entirety of the intermediate seal ring structure 732 , or the first void 742 may be defined within a segment of the intermediate seal ring structure 732 . can In one embodiment, the first void 742 is a sidewall segment selected from first sidewall segments 752A or second sidewall segments 752B of a first seal ring structure (eg, intermediate seal ring structure 732 ). It may extend inwardly and has a lateral extent that is at least 98% of the lateral extent of the sidewall segment in which the first void is present.

In the alternative embodiment shown in FIGS. 34D and 34E , the first sidewall segments 752A of the first seal ring structure (eg, the intermediate seal ring structure 732 ) have a first seal ring width (eg, the intermediate cavity). may have a first segment width WTA), wherein the second sidewall segments 752B of the first seal ring structure have an additional seal ring width greater than the first seal ring width (eg, the intermediate cavity second segment width WTA). WTB)). Accordingly, the first void 742A in the first segment of the intermediate seal ring structure 732 extending in the first horizontal direction hd1 may have a second width V2, and may have a second width V2 in the second horizontal direction hd2. The second void 742B in the second segment of the extending intermediate seal ring structure 732 is less than the second void width V2 if the layers of the device exert a greater concave deflection on the substrate in the second horizontal direction. It may have a fourth pore width V4. Alternatively, the fourth width V4 may be greater than the second void width V2 if the layers of the device exert a greater concave deflection on the substrate in the first horizontal direction. The larger void width V2 is defined on the substrate by the device layers in a direction perpendicular to the longitudinal direction of the voids (ie, the horizontal direction perpendicular to the width of the voids and parallel to the direction of the segment of the seal ring structure comprising the voids). Offset the applied deflection.

In one embodiment, the first void 742 is in alternating stacks {(132, 146), (232, 246)} and an inner region of the upper dielectric material portions (eg, upper level dielectric material layers 960). It extends continuously as a single continuous void around the perimeter. Alternatively, each segment 752A, 752B may have a separate enclosed void 742A, 742B.

In the embodiment illustrated in FIGS. 34A-E , the seal ring structures 73 are formed separately from the sacrificial via structures 477 and the peripheral device contact via structures 488 . In an alternative embodiment, the seal ring structures 73 (eg, the inner seal ring structure 731 , the intermediate seal ring structure 732 , and the outer seal ring structure 733 ) are connected to the sacrificial via structures 477 and the perimeter. It may be formed simultaneously with the device contact via structures 488 . For example, the bottom portions of the seal ring structures 73 may be formed concurrently with the sacrificial via structures 477 shown in FIG. 1 . Likewise, upper portions of the seal ring structures 73 may be formed concurrently with the peripheral device contact via structures 488 shown in FIG. 32 . In this embodiment, the seal ring cavities 71 are formed simultaneously with the peripheral device contact via cavities of FIG. 32 , and then both the seal ring cavities 71 and the peripheral device contact via cavities are made of an electrically conductive material. Filling forms respective peripheral device contact via structures 488 and seal ring structures 73 .

Referring to FIG. 35 , a dielectric passivation layer 990 may be formed over the top surfaces of the seal ring structures 73 and the guard ring structure 78 . Dielectric passivation layer 990 includes a dielectric material that can function as a diffusion barrier layer for moisture, hydrogen, and metal impurities. For example, dielectric passivation layer 990 may include silicon nitride. The thickness of the dielectric passivation layer 990 may range from 30 nm to 300 nm, although smaller and larger thicknesses may also be employed.

Referring to FIG. 36 , bonding pads 996 may be formed through a dielectric passivation layer 990 on each one of the top level metal interconnect structures 980 . Bonding pads 996 may include a metallic material that may be employed for a metal-to-metal bond (eg, copper) or for bonding with a solder ball or bonding wire.

Subsequently, the substrate 908 may be singulated along the dicing channels on the substrate 908 . The dicing channels may be cuff regions 500 . Each of the diced portions of the substrate 908 and the material portions attached thereto have a pair of first sidewalls parallel to the first horizontal direction hd1 and a pair of second sidewalls parallel to the second horizontal direction hd2 . Construct a semiconductor die that may have two sidewalls.

17A-36 and in accordance with various embodiments of the present disclosure, a semiconductor die is provided, which laterally extends along a first horizontal direction hd1 and laterally along a second horizontal direction A plurality of alternating stacks of insulating layers 132 , 232 and electrically conductive layers 146 , 246 positioned on spaced-apart substrate 908 , respective alternating stacks { ( 132 , 146 ), ( 232 , 246 ) )); and a first seal ring structure (712) having a first seal ring width (WT or WTA) between the inner and outer sidewalls, and a plurality of sets of memory stack structures (55) extending through the a plurality of nested seal ring structures 73 , and a second seal ring width between the inner sidewall and the outer sidewall such that the first seal ring width WT or WTA is less than the second seal ring width WI or WO a second seal ring structure 711 or 713 having (WI or WO).

In one embodiment, each of the plurality of nested seal ring structures 73 comprises a respective one of the first sidewall segments parallel to the first sidewalls of the semiconductor die (which may be parallel to the first horizontal direction hd1 ). pair of; and a respective pair of second sidewall segments perpendicular to the first sidewalls of the semiconductor die (and may be parallel to the second horizontal direction hd2 ).

In one embodiment, a first void 742 extends within at least one of the first sidewall segments 752A of the first seal ring structure 732 .

In one embodiment, the semiconductor die overlies the substrate 908 and includes portions 165, 265, 960 of dielectric material that laterally surround alternating stacks {(132, 146), (232, 246)}; and back trench fill structures (74, 76) positioned between the alternative stacks. A plurality of nested seal ring structures 73 extend from a top surface of the dielectric material portions 165 , 265 , 960 to the substrate 908 , in alternating stacks { ( 132 , 146 ), ( 232 , 246)) and laterally surrounds and encloses the inner regions of the dielectric material portions 165 , 265 , 960 .

In one embodiment, the first sidewall segments 752A of the first seal ring structure 732 have a first seal ring width (eg, an intermediate cavity first segment width WTA), the first seal ring structure ( The second sidewall segments 752B of 732 have an additional seal ring width (eg, intermediate cavity second segment width WTB) that is greater than the first seal ring width.

In one embodiment, first void 742A has a first void width (such as median void width V2 ), and each of the second sidewall segments 752B has a first void width as illustrated in FIG. 34E . and an additional void 742B having a void width V4 that is less than (V2). In another embodiment, the second sidewall segments 752B are void-free.

In one embodiment, the entirety of the first seal ring structure 732 has a first seal ring width (eg, the intermediate cavity width WT) and the second seal ring structure (eg, the inner seal ring structure 731 ) or The entirety of outer seal ring structure 733 has a second seal ring width (eg, inner cavity width WI or outer cavity width WO) as illustrated in FIG. 34D .

In one embodiment, the first void 742 is continuous around the inner region of the dielectric material portions 165 , 265 , 960 as a single continuous void in alternating stacks, and the configuration illustrated in FIGS. 34C and 34D . is extended

In one embodiment, the first void 742 has a vertical extent that is at least 80% of the vertical extent of the first seal ring structure 732 . In one embodiment, the second seal ring structure (eg, the inner seal ring structure 731 or the outer seal ring structure 733 ) has a smaller seal ring width (eg, the outer void width V3 ) than the first air gap 742 . or a second void 741 or 743 having an inner void width V1). In another embodiment, the second seal ring structure (eg, inner seal ring structure 731 or outer seal ring structure 733 ) has no voids therein.

In one embodiment, the plurality of nested seal ring structures 73 includes a third portion of at least one diffusion barrier material and includes a third seal ring width (eg, an outer cavity width) between the inner sidewall and the outer sidewall thereof. and a third seal ring structure (eg, outer seal ring structure 733 or inner seal ring structure 731 ) having (WO) or inner cavity width (WI). The first seal ring structure 732 is positioned between the second seal ring structure (eg, 731 or 733) and the third seal ring structure (eg, 733 or 731), the third seal ring width being the first seal ring width bigger than

In one embodiment, the plurality of nested seal ring structures 73 include at least one diffusion barrier material selected from tungsten, conductive metal nitride, or silicon nitride.

In one embodiment, each of the memory stack structures 55 is provided via a plurality of electrically conductive layers 146 , 246 in a respective one of a plurality of alternating stacks { ( 132 , 232 , ( 146 , 246 ) ). a memory film 50 extending therefrom, and a vertical semiconductor channel 60 in contact with the memory film 50 .

Each seal ring structure 73 comprising a void 742 is deformed under mechanical stress by the electrically conductive layers 146 , 246 in the memory array regions 100 and step regions 200 and/or by deformation of the void under mechanical stress. Alternatively, it may be used to reduce or balance the mechanical stress generated by the seal ring structures 73 . Accordingly, the void(s) in the seal ring structure 73 may advantageously be employed to reduce warpage of the substrate 908 . Bonding of substrates 908 to other substrates may be facilitated by reduced wafer warpage. In this case, dicing of the semiconductor die may be performed after the wafer including the substrate 908 and the devices thereon are bonded to another wafer. Accordingly, reduced warpage of the substrate through the use of seal ring structures 73 can be utilized in a variety of ways to facilitate fabrication of semiconductor dies with less warpage, and increased die yield and device reliability.

Although the foregoing refers to specific embodiments, it will be understood that the present disclosure is not so limited. It will occur to those skilled in the art that various modifications may be made to the disclosed embodiments and that such modifications are intended to be within the scope of the present disclosure. Compatibility is assumed between all embodiments that are not alternatives to each other. The word “comprise or include” means that, unless explicitly stated otherwise, the word “consist essentially of” or the word “consisting of” replaces the word “comprise”. All embodiments are considered. Where an embodiment using a particular structure and/or configuration is illustrated in this disclosure, the disclosure may be practiced with any other compatible structures and/or configurations that are functionally equivalent - such substitution is expressly prohibited or otherwise. It is understood that - unless it is known to the person skilled in the art as impossible. All publications, patent applications and patents cited herein are incorporated herein by reference in their entirety.

Claims (40)

A semiconductor die comprising:
a plurality of alternating stacks of insulating and electrically conductive layers positioned over a substrate and laterally spaced apart by a plurality of divider trench fill structures extending laterally along a first horizontal direction, the plurality of alternating stacks and the plurality of divider trench fill structures are alternately interlaced along a second horizontal direction perpendicular to the first horizontal direction;
a plurality of sets of memory stack structures, each set of memory stack structures extending vertically through a respective alternating stack of the plurality of alternating stacks; and
a plurality of slit trenches extending laterally along the second horizontal direction by a lateral distance greater than a lateral extent along the second horizontal direction of at least two neighboring sets of alternating stacks of the plurality of alternating stacks filling structures,
wherein each of the plurality of divider trench fill structures and each of the plurality of slit trench fill structures comprises a respective set of at least one material portion having the same material composition. The semiconductor die of claim 1 , wherein each of the plurality of slit trench fill structures is located outside a region of the plurality of divider trench fill structures and is not adjacent to the plurality of divider trench fill structures. The semiconductor die of claim 1 , wherein each of the plurality of divider trench fill structures is in contact with sidewalls of at least one alternating stack of the plurality of alternating stacks extending laterally along the first horizontal direction. . The semiconductor die of claim 3 , wherein the plurality of slit trench fill structures do not directly contact any of the plurality of alternating stacks of insulating and electrically conductive layers. The method of claim 1 , further comprising a further plurality of alternating stacks of insulating layers and electrically conductive layers laterally spaced apart from the plurality of alternating stacks of insulating layers and electrically conductive layers along the first horizontal direction. wherein one of the plurality of slit trench fill structures is positioned between the plurality of alternating stacks and the further plurality of alternating stacks. 5. The semiconductor die of claim 1, further comprising a seal ring structure laterally offset inward from a periphery of the semiconductor die and laterally enclosing the plurality of alternating stacks and the plurality of divider trench fill structures. and at least one of the slit trench fill structures is located external to the seal ring structure. The semiconductor die of claim 1 , wherein each of the slit trench fill structures has a rectangular horizontal cross-sectional area with a length to width ratio greater than 30. The method of claim 1 , wherein each set of at least one material portion within each of the plurality of divider trench fill structures and each of the plurality of slit trench fill structures comprises:
a dielectric spacer comprising a dielectric material and extending vertically through the entire height of a respective one of the plurality of divider trench fill structures and the plurality of slit trench fill structures; and
and a portion of conductive fill material comprising at least one conductive material and laterally surrounded by the dielectric spacer. The semiconductor die of claim 8 , wherein at least one of the conductive fill material portions of the plurality of slit trench fill structures is electrically floating. According to claim 1,
field effect transistors located on the substrate and not in direct contact with the plurality of alternating stacks; and
and an etch stop dielectric layer overlying the field effect transistors, wherein at least one of the plurality of slit trench fill structures overlies and contacts the etch stop dielectric layer. According to claim 1,
the substrate comprises a semiconductor material layer comprising a plurality of doped semiconductor material portions;
wherein each of the plurality of divider trench fill structures is in contact with a respective one of the plurality of doped semiconductor material portions. The method of claim 1 , wherein each of the memory stack structures comprises:
a memory film extending through the plurality of electrically conductive layers in a respective one of the plurality of alternating stacks of insulating layers and electrically conductive layers; and
and a vertical semiconductor channel in contact with the memory film. The semiconductor die of claim 1 , wherein each alternating stack of the plurality of alternating stacks includes a respective stepped region having lateral extents in which the electrically conductive layers decrease with increasing vertical distance from the substrate. . A method of forming a semiconductor structure comprising:
forming a vertically alternating sequence of successive insulating layers and successive sacrificial material layers over a substrate;
forming a plurality of sets of memory stack structures, each set of memory stack structures extending vertically through a respective region of the vertically alternating sequence;
forming divider trenches and slit trenches, the divider trenches extending laterally along a first horizontal direction, dividing the vertically alternating sequence into a plurality of alternating stacks of insulating layers and sacrificial material layers; , the slit trenches extend laterally along a second horizontal direction perpendicular to the first horizontal direction;
replacing the sacrificial material layers in the plurality of alternating stacks with electrically conductive layers that use the divider trenches as conduits for an etchant that etches the sacrificial material layers and a reactant that deposits the conductive material of the electrically conductive layers step; and
depositing one or more sets of material in each of the divider trenches and the slit trenches, wherein a plurality of divider trench fill structures are formed in the divider trenches, and a plurality of slit trench fill structures are formed in the slit trenches. formed in the method. 15. The method of claim 14, wherein the slit trenches do not contact the plurality of alternating stacks. 15. The method of claim 14,
forming stepped surfaces in peripheral portions of the vertically alternating sequence; and
and forming a portion of dielectric material over the stepped surfaces, wherein at least one of the slit trenches is formed through the portion of dielectric material. 17. The method of claim 16,
forming field effect transistors on the substrate; and
further comprising forming an etch stop dielectric layer over the field effect transistors, wherein the portion of dielectric material overlies and contacts the etch stop dielectric layer, wherein one of the slit trenches comprises the A method formed through a portion of dielectric material and extending to a surface of the etch stop dielectric layer. 15. The method of claim 14, further comprising: forming a seal ring structure after formation of the plurality of divider trench fill structures and the plurality of slit trench fill structures, the seal ring structure comprising the insulating layers and the electrically conductive and laterally encapsulating alternating stacks of layers, wherein at least one of the slit trench fill structures is located external to the seal ring structure. 15. The method of claim 14, wherein the set of at least one material in each of the plurality of divider trench fill structures and each of the plurality of slit trench fill structures comprises:
a dielectric spacer comprising a dielectric material and extending vertically through an entire height of the plurality of divider trench fill structures and one of each of the plurality of slit trench fill structures; and
a conductive fill material portion comprising at least one conductive material and laterally surrounded by the dielectric spacer. 20. The method of claim 19,
the substrate comprises a semiconductor material layer comprising a plurality of doped semiconductor material portions;
wherein each of the plurality of divider trench fill structures is formed on a respective one of the plurality of doped semiconductor material portions. A semiconductor die comprising:
a plurality of alternating stacks of electrically conductive layers and insulating layers positioned over the substrate and extending laterally along a first horizontal direction and laterally spaced apart along a second horizontal direction perpendicular to the first horizontal direction;
a plurality of sets of memory stack structures extending through the plurality of alternating stacks; and
a plurality of nested seal ring structures, the plurality of nested seal ring structures comprising:
a first seal ring structure having a first seal ring width between the inner sidewall and the outer sidewall; and
a second seal ring structure having a second seal ring width between the inner sidewall and the outer sidewall, wherein the first seal ring width is less than the second seal ring width. 22. The semiconductor die of claim 21, wherein each of the plurality of nested seal ring structures is perpendicular to the first sidewalls of the semiconductor die and a respective pair of first sidewall segments parallel to the first sidewalls of the semiconductor die. and a respective pair of second sidewall segments. 23. The semiconductor die of claim 22, further comprising a first void extending within at least one of the first sidewall segments of the first seal ring structure. 23. The method of claim 22,
portions of dielectric material overlying the substrate and laterally surrounding the alternating stacks; and
further comprising back trench fill structures positioned between the alternative stacks;
wherein the plurality of nested seal ring structures extend from a top surface of the portions of dielectric material to the substrate and laterally surround and encapsulate the alternating stacks and inner regions of the portions of dielectric material. 24. The semiconductor die of claim 23, wherein the second seal ring structure includes a second void having a width less than the first void. 24. The semiconductor die of claim 23, wherein the second seal ring structure has no voids therein. 24. The method of claim 23,
the first sidewall segments of the first seal ring structure have the first seal ring width;
and the second sidewall segments of the first seal ring structure have an additional seal ring width that is greater than the first seal ring width. 28. The method of claim 27,
the first void has a first void width;
wherein each of the second sidewall segments comprises a second void having a second void width less than the first void width. 28. The semiconductor die of claim 27, wherein each of the second sidewall segments is void-free. 24. The method of claim 23, wherein said first void extends continuously as a single continuous void around an inner region of said alternating stacks and said dielectric material portions, said first void being perpendicular to said first seal ring structure. A semiconductor die having a vertical extent that is at least 80% of the extent. 22. The method of claim 21,
wherein the plurality of nested seal ring structures include a third seal ring structure comprising a third portion of the at least one diffusion barrier material and having a third seal ring width between the inner sidewall and the outer sidewall;
the first seal ring structure is located between the second seal ring structure and the third seal ring structure;
and the third seal ring width is greater than the first seal ring width. 22. The semiconductor die of claim 21, wherein the plurality of nested seal ring structures comprise at least one diffusion barrier material selected from tungsten, conductive metal nitride, or silicon nitride. 22. The method of claim 21, wherein each of the memory stack structures comprises:
a memory film extending through a plurality of electrically conductive layers in a respective one of the plurality of alternating; and
and a vertical semiconductor channel in contact with the memory film. A method of forming a semiconductor structure comprising:
forming a vertically alternating sequence of successive insulating layers and successive sacrificial material layers over a substrate;
forming a plurality of sets of memory stack structures extending through respective regions of the vertically alternating sequence;
dividing the vertically alternating sequence into a plurality of alternating stacks of insulating layers and sacrificial material layers by forming backside trenches extending laterally along a first horizontal direction through the vertically alternating sequence;
replacing the sacrificial material layers with electrically conductive layers using the backside trenches as conduits for an etchant that etches the sacrificial material layers and a reactant that deposits the conductive material of the electrically conductive layers;
forming portions of dielectric material over the insulating layers and the electrically conductive layers; and
forming a plurality of nested seal ring structures extending from a top surface of the dielectric material portions to the substrate and laterally surrounding and enclosing the alternating stacks and an inner region of the dielectric material portions;
The plurality of nested seal ring structures,
a first seal ring structure having a first seal ring width between the inner sidewall and the outer sidewall; and
a second seal ring structure laterally enclosing or laterally encapsulated by the first seal ring structure, the second seal ring structure having a second seal ring width between an inner sidewall and an outer sidewall; wherein the first seal ring width is less than the second seal ring width. 35. The method of claim 34, wherein the first seal ring structure has a first void therein. 36. The method of claim 35,
forming a plurality of nested seal ring cavities extending from the top surface of the portions of dielectric material to the substrate; and
further comprising depositing at least one diffusion barrier material within each of the plurality of nested seal ring cavities, wherein the plurality of nested seal ring structures are deposited within the plurality of nested seal ring cavities. portions of the at least one diffusion barrier material being 36. The method of claim 35, wherein each of the plurality of nested seal ring structures comprises:
a respective pair of first sidewall segments parallel to first sidewalls of the semiconductor die; and
and a respective pair of second sidewall segments perpendicular to the first sidewalls of the semiconductor die. 38. The method of claim 37, wherein the first void extends within the at least one first sidewall segment. 38. The method of claim 37,
the first sidewall segments of the first seal ring structure have the first seal ring width;
and the second sidewall segments of the first seal ring structure have an additional seal ring width that is greater than the first seal ring width. 36. The method of claim 35,
the first void has a first void width;
wherein each of the second sidewall segments comprises a second void having no void therein, or having a second void width less than the first void width.

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