KR20210082065A - Light emitting display panel and light emitting display apparatus using the same - Google Patents

Abstract

The present invention provides a light emitting display panel and a light emitting display device using the same. The light emitting display panel has three light emitting layers and three electrodes which can be used as an anode or a cathode in each pixel. Therefore, consumption power of the light emitting display panel can be reduced.

Description

A light emitting display panel and a light emitting display device using the same {LIGHT EMITTING DISPLAY PANEL AND LIGHT EMITTING DISPLAY APPARATUS USING THE SAME}

The present invention relates to a structure of a light emitting display panel.

A display panel applied to an augmented reality (AR) device or a virtual reality (VR) device, which is a recent issue, requires ultra-high resolution, low power consumption, and high color reproducibility.

However, it is difficult to realize super high resolution with a conventional mask having a patterned shape.

In addition, a display panel using white pixels and a color filter, which is easily manufactured by using an open mask, can be manufactured to have an ultra-high resolution and a large area. However, in such a display panel, a driving voltage is increased, and thus, power consumption is increased. This increasing problem is occurring.

An object of the present invention, which has been proposed to solve the above problems, is a light emitting display panel and a light emitting display device using the same, in which each pixel is provided with three light emitting layers and three electrodes that can be used as anodes or cathodes is to provide

A light emitting display panel according to the present invention for achieving the above technical problem,

A passivation layer covering the pixel driving circuits provided on a substrate, a planarization layer provided on the passivation layer and planarizing top surfaces of the pixel driving circuits, the passivation layer and the planarization layer in each of boundary regions between pixels The connection electrode exposed from the pixel driving electrode is provided at a position corresponding to the light emitting region among the upper ends of the protective layer, the pixel driving electrode connected to any one of the pixel driving circuits, and the connection electrode among the top of the protective layer is exposed. an undercut line provided on one side of the undercut region, and three light emitting layers and three common electrodes alternately disposed on the top of the pixel driving electrode or alternately disposed on the top of the planarization layer.

According to an aspect of the present invention, there is provided a light emitting display device for achieving the above technical problem, including the light emitting display panel, a gate driver supplying gate signals to gate lines provided in the light emitting display panel, and a data line provided in the light emitting display panel and a data driver supplying data voltages to the controllers and a controller controlling functions of the gate driver and the data driver.

In the present invention, a light emitting layer is provided between three electrodes used as an anode or a cathode.

According to the present invention, a light emitting display panel having a three stack structure can be driven with a voltage of a single stack level, and thus power consumption of the light emitting display panel can be reduced.

The light emitting display panel according to the present invention can be manufactured using an open mask, and according to the present invention, high luminance and ultra-high resolution can be realized even without a color filter.

According to the present invention, the pixel electrode may be omitted in at least two pixels among pixels constituting the unit pixel, and thus, transmittance and aperture ratio in at least two pixels may be improved.

Accordingly, the luminance of the light emitting display panel may be increased, and thus, power consumption of the light emitting display panel may be reduced.

1 is an exemplary view showing the configuration of a light emitting display device according to the present invention.
2 is an exemplary view showing the configuration of a control unit applied to a light emitting display device according to the present invention.
3 is an exemplary view showing the structure of pixels included in the light emitting display device according to the present invention.
4 is an exemplary view showing a cross-section taken along line A-A' shown in FIG. 1 .
FIG. 5 is an exemplary view for explaining the undercut region shown in FIG. 4;
FIG. 6 is an enlarged view of the first undercut region shown in FIG. 4;
FIG. 7 is an enlarged view of the second undercut region shown in FIG. 4;
FIG. 8 is an enlarged view of a third undercut area shown in FIG. 4;
FIG. 9 is another exemplary view showing a cross-section taken along line A-A' shown in FIG. 1. FIG.
FIG. 10 is another exemplary view showing a cross-section taken along line A-A' shown in FIG. 1;
11 is an exemplary view specifically showing the structure of the substrate shown in FIG.
12 is an exemplary view for explaining the positions of the connection electrodes shown in FIG.
13 is an exemplary view for explaining the undercut region shown in FIG. 10 .
14 is an enlarged view of the first undercut region shown in FIG. 10;
FIG. 15 is an enlarged view of the second undercut region shown in FIG. 10;
FIG. 16 is an enlarged view of the third undercut area shown in FIG. 10;
17 is an exemplary view showing opening regions of pixels included in a light emitting display panel according to the present invention;

Advantages and features of the present invention, and a method for achieving them will become apparent with reference to the embodiments described below in detail in conjunction with the accompanying drawings. However, the present invention is not limited to the embodiments disclosed below, but will be implemented in a variety of different forms, and only these embodiments allow the disclosure of the present invention to be complete, and those of ordinary skill in the art to which the present invention pertains. It is provided to fully inform the person of the scope of the invention, and the present invention is only defined by the scope of the claims.

It should be noted that in the present specification, in adding reference numbers to the components of each drawing, the same numbers are used for the same components, even if they are indicated on different drawings, as much as possible.

The shapes, sizes, proportions, angles, numbers, etc. disclosed in the drawings for explaining the embodiments of the present invention are exemplary, and thus the present invention is not limited to the illustrated matters. Like reference numerals refer to like elements throughout. In addition, in describing the present invention, if it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. When 'including', 'having', 'consisting', etc. mentioned in this specification are used, other parts may be added unless 'only' is used. When a component is expressed in the singular, the case in which the plural is included is included unless otherwise explicitly stated.

In interpreting the components, it is interpreted as including an error range even if there is no separate explicit description.

In the case of a description of the positional relationship, for example, when the positional relationship of two parts is described as 'on', 'on', 'on', 'beside', etc., 'right' Alternatively, one or more other parts may be positioned between the two parts unless 'directly' is used.

In the case of a description of a temporal relationship, for example, 'immediately' or 'directly' when a temporal relationship is described with 'after', 'following', 'after', 'before', etc. It may include cases that are not continuous unless this is used.

The term 'at least one' should be understood to include all possible combinations of one or more related items. For example, the meaning of 'at least one of the first item, the second item and the third item' means not only the first item, the second item, or the third item, respectively, but also two of the first item, the second item and the third item. It means a combination of all items that can be presented from more than one.

Although the first, second, etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from another. Accordingly, the first component mentioned below may be the second component within the spirit of the present invention.

Each feature of the various embodiments of the present invention can be partially or wholly combined or combined with each other, technically various interlocking and driving are possible, and each embodiment may be independently implemented with respect to each other or implemented together in a related relationship. may be

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

1 is an exemplary diagram showing the configuration of a light emitting display device according to the present invention, and FIG. 2 is an exemplary diagram showing the configuration of a control unit applied to the light emitting display device according to the present invention.

The light emitting display device according to the present invention may constitute an electronic device. The electronic device may be, for example, a smartphone, a tablet PC, a TV, or a monitor.

As shown in FIG. 1, the light emitting display device according to the present invention includes a light emitting display panel 100 including a display area AA through which an image is output and a non-display area NAA provided outside the display area, and light emission. The gate driver 200 supplies a gate signal to the gate lines GL1 to GLg provided in the display panel, and the data driver 300 supplies data voltages to the data lines DL1 to DLd provided in the light emitting display panel. and a control unit 400 for controlling driving of the gate driver 200 and the data driver 300 .

As shown in FIG. 2 , the controller 400 rearranges and rearranges the input image data Ri, Gi, Bi transmitted from the external system using the timing synchronization signal TSS transmitted from the external system. A control signal for generating the gate control signal GCS and the data control signal DCS using the data alignment unit 430 for supplying the image data to the data driver 300 and the timing synchronization signal TSS The generation unit 420 receives the timing synchronization signal TSS and the input image data Ri, Gi, Bi transmitted from the external system and transmits them to the data alignment unit 430 and the control signal generation unit 420 . The image data (Data) generated by the input unit 410 and the data alignment unit 430 and the control signals DCS and GCS generated by the control signal generation unit 420 are combined with the data driver 300 or the gate driver ( 200) and includes an output unit 440 for outputting it.

The gate driver 200 may be configured as an integrated circuit and then mounted in the non-display area NAA, or may be directly embedded in the non-display area NAA in a gate in panel (GIP) method. have.

The data driver 300 may be provided on a chip-on film attached to the light emitting display panel 100 . The chip-on film is also connected to the main board on which the control unit 400 is provided. In this case, the chip-on-film includes lines for electrically connecting the control unit 400 , the data driver 300 , and the light emitting display panel 100 , and for this purpose, the lines are connected to the main substrate and the light emitting display panel 100 . It is electrically connected to the pads provided in the . The main board is electrically connected to an external board on which an external system is mounted. The data driver 300 may be directly mounted on the light emitting display panel 100 and then electrically connected to the main board.

The external system performs a function of driving the control unit 400 and the electronic device. That is, when the electronic device is a smartphone, the external system performs various types of voice information, image information, and text information through a wireless communication network, and transmits the image information to the controller 400 .

The light emitting display panel 100 includes pixels 110 including a light emitting device and a pixel driving circuit for driving the light emitting device. In addition, signal lines are formed in the light emitting display panel 100 to define a pixel region in which the pixels 110 are formed and to supply a driving signal to the pixel driving circuit.

The signal lines include various types of lines in addition to the gate lines GL1 to GLg and the data lines DL1 to DLd.

3 is an exemplary view showing the structure of pixels included in the light emitting display device according to the present invention.

Pixels 110 including a light emitting device ED and a pixel driving circuit PDC for driving the light emitting device ED are provided in the display area AA of the light emitting display panel 100 . In addition, signal lines for supplying driving signals to the pixel driving circuit PDC are formed on the light emitting display panel 100 to define a pixel region in which the pixels 110 are formed.

The signal lines are the gate line GL, the data lines DL, the sensing pulse line SPL, the sensing line SL, the first driving power line PLA, the second driving power line PLB, and the emission line. (EL) and the like.

The gate lines GL may be formed in parallel to have a constant interval along the second direction, for example, a horizontal direction, of the light emitting display panel 100 .

The sensing pulse lines SPL may be formed at regular intervals to be parallel to the gate lines GL.

The data lines DL are parallel to each other so as to intersect the gate lines GL and the sensing pulse lines SPL in a first direction, for example, a vertical direction, of the light emitting display panel 100 to have a constant interval. can be

The sensing lines SL may be formed at regular intervals to be parallel to the data lines DL.

The first driving power line PLA may be formed at regular intervals to be parallel to the data line DL and the sensing line SL. The first driving power line PLA is connected to the power supply unit 500 to supply the first driving power ELVDD supplied from the power supply unit 500 to each pixel 110 .

The second driving power line PLB supplies the second driving power ELVSS supplied from the power supply unit 500 to each pixel 110 .

The emission lines EL may be formed parallel to the gate lines.

The pixel driving circuit PDC includes a driving transistor Tdr for controlling the amount of current flowing through the light emitting device ED, and a switching transistor Tsw1 connected between the data line DL and the driving transistor Tdr and the gate line GL. ) and an emission transistor Tsw3 for controlling current flow to the driving transistor Tdr. Also, a capacitor Cst and a sensing transistor Tsw2 may be provided in the pixel driving circuit PDC. In the following description, reference numeral Tdr is used as a generic term for driving transistors included in the light emitting display panel, and specific driving transistors included in a pixel may be represented by reference numerals Tdr1, Tdr2, and Tdr3.

The switching transistor Tsw1 is turned on by a gate pulse constituting a gate signal transmitted through the gate line GL, and outputs the data voltage Vdata supplied from the data line DL to the gate of the driving transistor Tdr. do.

The sensing transistor Tsw2 is switched by the scan signal SS transmitted through the sensing pulse line SPL to supply the sensing line voltage supplied through the sensing line SL to the source electrode of the driving transistor Tdr or , the voltage applied to the source electrode may be transmitted to the sensing line SL.

The emission transistor Tsw3 is turned on by an emission turn-on pulse constituting an emission signal transmitted through the emission line EL, and a current flows through the driving transistor Tdr to the light emitting device ED, It is turned off by the emission turn-off pulse constituting the emission signal, thereby preventing the current from flowing to the light emitting device ED.

The capacitor Cst is formed between the gate and the source of the driving transistor Tdr to charge the data voltage transferred through the switching transistor Tsw1, and the driving transistor Tdr is charged according to the voltage charged in the capacitor Cst. is driven

That is, the driving transistor Tdr is turned on by the voltage charged in the capacitor Cst to control the amount of data current flowing from the first driving power line PLA to the light emitting device ED.

The light emitting device ED emits light by the data current supplied from the driving transistor Tdr to emit light having a luminance corresponding to the data current.

The structure of the pixel driving circuit PDC may be formed in various structures other than the structure shown in FIG. 3 .

For example, in FIG. 3 , a pixel driving circuit PDC in which transistors are formed in a P-type and four transistors is illustrated, but the pixel driving circuit PDC includes two transistors or three transistors. , or five or more transistors may be provided.

That is, in order to compensate for a change in threshold voltage or mobility due to deterioration of the driving transistor Tdr, the pixel driving circuit PDC may further include at least one transistor in addition to the sensing transistor Tsw2 and the driving transistor Tdr. can

In more detail, the pixel driving circuit PDC may include at least two transistors to perform internal compensation or external compensation.

Here, the internal compensation means that even if the threshold voltage or mobility of the driving transistor Tdr is changed due to deterioration of the driving transistor Tdr, the current supplied to the light emitting device ED is not affected by the change in the threshold voltage or the mobility. It refers to a method of controlling the voltage of the gate of the driving transistor Tdr so as not to be affected.

The external compensation is to determine the amount of change in the threshold voltage or mobility of the driving transistor Tdr due to deterioration of the driving transistor Tdr, and according to the change amount, determine the size of the data voltage Vdata supplied to the data line DL. It means how to change.

4 is an exemplary view showing a cross-section taken along line A-A' shown in FIG. 1 . That is, FIG. 4 is an exemplary diagram schematically illustrating a cross-section of three consecutively arranged pixels.

1 to 4 , the light emitting display panel 100 according to the present invention includes a substrate 111 , a pixel driving circuit PDC including a driving transistor Tdr, and a substrate 111 provided on the substrate 111 . A passivation layer 112 covering the pixel driving circuit PDC, a planarization layer 113 provided on the passivation layer 112 to planarize top surfaces of the pixel driving circuits, and boundary regions BL between pixels The connection electrode CL exposed from the protective layer and the planarization layer, respectively, is provided at a position corresponding to the light emitting area PX among the upper ends of the protective layer, and the pixel driving electrode PE is connected to any one of the pixel driving circuits. ), the undercut line UL provided on one side of the undercut region UC where the connection electrode is exposed among the upper ends of the protective layer, and the pixel driving electrode are alternately disposed on the upper end, or on the upper end of the flattening layer 113 . It includes three light emitting layers EL1 , EL2 , EL3 and three common electrodes CE1 , CE2 , CE3 which are alternately disposed.

In the following description, reference numeral PE is used to collectively refer to pixel driving electrodes included in the light emitting display panel, and specific pixel driving electrodes included in each pixel may be represented by reference numerals PE1, PE2, and PE3. In addition, reference numeral CL is used as a generic term for connection electrodes provided in the light emitting display panel, and specific connection electrodes provided between each pixel may be represented by reference numerals CL1, CL2, and CL3. In addition, the reference numeral UL is used as a generic term for undercut lines provided in the light emitting display panel, and specific undercut lines provided between each pixel may be represented by reference numerals UL1, UL2, and UL3. In addition, reference numeral UC is used as a generic term for undercut areas provided in the light emitting display panel, and specific undercut areas provided between each pixel may be represented by reference numerals UC1, UC2, and UC3.

The substrate 111 may include a base substrate formed of a plastic material or a glass material, various insulating layers provided on the base substrate, and metals provided between the base substrate and the insulating layers. Various lines and transistors may be formed by insulating films and metals.

The substrate 111 may have a flat rectangular shape, a rectangular shape in which each corner is rounded with a constant radius of curvature, or a non-rectangular shape having at least six sides. Here, the substrate having a non-rectangular shape may include at least one protrusion or at least one notch portion.

The base substrate constituting the substrate 111 may include an opaque or colored polyimide material. For example, the polyimide base substrate may be a cured polyimide resin coated with a predetermined thickness on the front surface of a release layer provided on a relatively thick carrier substrate. In this case, the carrier substrate is separated from the substrate by release of the release layer using a laser release process.

A back plate may be further provided on the rear surface of the base substrate. The back plate holds the base substrate in a planar state. The back plate may include a plastic material, for example, a polyethylene terephthalate material. This back plate may be laminated to the back side of the base substrate after being separated from the carrier substrate.

The base substrate may be a flexible glass substrate. For example, the base substrate is a thin glass substrate having a thickness of 100 micrometers or less, or is etched to have a thickness of 100 micrometers or less by a substrate etching process performed after the manufacturing process of the light emitting display panel 100 is completed. It may be a carrier glass substrate.

A pixel driving circuit (PDC) including various lines and transistors is provided on the upper end of the base substrate. The pixel driving circuit PDC may have the structure described with reference to FIG. 3 , and in addition to this, may be configured in various forms.

The pixel driving circuit PDC includes a driving transistor Tdr connected to the pixel driving electrode PE. FIG. 4 simply shows electrodes connected to the driving transistors Tdr1 , Tdr2 , and Tdr3 among various transistors and capacitors constituting the pixel driving circuit PDC.

That is, in FIG. 4 , the overall configuration of the driving transistors Tdr1 , Tdr2 , and Tdr3 is omitted, and electrodes connecting the driving transistors Tdr1 , Tdr2 and Tdr3 and the pixel driving electrodes PE1 , PE2 , and PE3 are omitted. are shown briefly. In particular, for convenience of explanation, in FIG. 4 , electrodes connecting the driving transistors Tdr1 , Tdr2 and Tdr3 and the pixel driving electrodes PE1 , PE2 , and PE3 are shown as driving transistors Tdr1 , Tdr2 and Tdr3 . has been

Each of the driving transistors Tdr1 , Tdr2 , and Tdr3 may include a plurality of electrodes, a semiconductor layer, and a plurality of insulating layers provided between the electrodes and the semiconductor layer. That is, the driving transistor Tdr may include a semiconductor layer, a source, a drain, a gate, and at least one insulating layer.

The pixel driving circuit PDC including the driving transistor Tdr may be provided on the substrate 111 , and the substrate 111 may further include at least one buffer in addition to the base substrate, various insulating layers, and metals. . The buffer may be various types of organic or inorganic layers.

A protective layer 112 for protecting the pixel driving circuit PDC is provided on the upper end of the pixel driving circuit PDC, that is, on the upper end of the substrate 111 .

A planarization layer 113 is provided on the upper end of the protective layer 112 . The planarization layer 113 is disposed on the substrate 111 to cover the pixel driving circuit PDC, and accordingly, a flat surface may be provided on the top of the pixel driving circuit PDC.

The connection electrode CL is exposed from the passivation layer 112 and the planarization layer 113 in each of the boundary regions BL between the pixels. The pixel driving voltage supplied from the pixel driving electrode PE may be supplied to the connection electrode CL, or the second driving power ELVSS supplied from the power supply unit 500 may be supplied.

The undercut line UL is provided at one side of the undercut region UC to which the connection electrode CL is exposed among the upper ends of the protective layer 112 .

A light emitting device ED is provided on the top of the flattening layer. The light emitting device ED includes a pixel driving circuit PDC, in particular, a pixel driving electrode PE electrically connected to the driving transistor Tdr, a light emitting layer EL provided on top of the pixel driving electrode, and a common provided on top of the light emitting layer. electrode CE.

The pixel driving electrode PE may be an anode. The pixel driving electrode PE is provided at a position corresponding to the pixel among the upper ends of the protective layer, and is connected to any one of the pixel driving circuits. That is, the pixel driving electrode PE is disposed on the light emitting region of the pixel 110 and is electrically connected to the driving transistor Tdr provided in the pixel driving circuit PDC. The light emitting area PX may be formed by the bank 114 .

That is, the bank 114 surrounds the periphery of the pixel driving electrode PE, covers one side of the undercut line UL, and functions to distinguish positions of pixels. The bank 114 may be provided in all pixels as shown in FIG. 4 , but in the light emitting display panel described below with reference to FIG. 10 , the bank 114 may be provided in only some of the pixels.

The pixel driving electrode PE may be formed of a transparent metal such as indium tin oxide (ITO) or zinc oxide (IZO).

On the upper end of the pixel driving electrode PE, the bank 114 and the three light emitting layers EL1, EL2, EL3 are alternately disposed on the upper end of the pixel driving electrode PE, and the three common electrodes CE1, CE2, CE3) is provided.

The emission layers EL1 , EL2 , and EL3 may be formed in the entire display area AA of the substrate 111 to cover the pixel driving electrode PE and the bank 114 .

The light emitting layers EL1, EL2, and EL3 include a first light emitting layer EL1 emitting a first light (eg, red light), a second light emitting layer EL2 emitting a second light (eg, green light), and A third light emitting layer EL3 emitting third light (eg, blue light) may be included.

Each of the light emitting layers EL1 , EL2 , and EL3 may include a hole transport layer, a light emitting part, and an electron transport layer.

The emission layers EL1 , EL2 , and EL3 may include any one of an organic emission layer, an inorganic emission layer, and a quantum dot emission layer, or may include a stacked or mixed structure of an organic emission layer (or an inorganic emission layer) and a quantum dot emission layer.

The bank 114 surrounds the periphery of the pixel driving electrode PE, covers one side of the undercut line UL, and identifies positions of pixels.

That is, the edge of the pixel driving electrode PE may be covered by the bank 114 as shown in FIG. 4 . The bank 114 is disposed on the remaining area except for the emission area of the pixel 110 to cover the edge of the pixel driving electrode PE. Accordingly, the emission area of the pixel 110 may be defined. In FIG. 4 , each of the pixels 110 is divided into a boundary area BL and a light emitting area PX. Light may be output through the light emitting area PX.

The bank 114 may define the light emitting area of the pixel 110 as a pentile structure or a stripe structure.

The common electrodes CE1 , CE2 , and CE3 are alternately provided with the three light emitting layers EL1 , EL2 , and EL3 at the top of the bank 114 and the pixel driving electrode PE.

Among the common electrodes CE1 , CE2 , and CE3 , the first common electrode CE1 and the second common electrode CE2 may be formed of a transparent metal such as indium tin oxide (ITO) or zinc oxide (IZO). Among the common electrodes, the third common electrode CE3 has to function as a reflective plate, so a stacked structure of aluminum (Al) and titanium (Ti) (Ti/Al/Ti) and a stacked structure of aluminum (Al) and ITO (ITO/Al/ITO), APC (Ag/Pd/Cu) formed in a multilayer structure such as alloy, silver (Ag), aluminum (Al), molybdenum (Mo), gold (Au), magnesium (Mg), It may include a single layer structure made of any one material selected from calcium (Ca) and barium (Ba) or two or more alloy materials.

An encapsulation layer may be provided on the upper end of the common electrode CA.

In the following description, the pixel that outputs the first light is referred to as a first pixel 110a, the pixel that outputs the second light is referred to as a second pixel 110b, and the pixel 110 that outputs the third light is referred to as a first pixel 110a. It is referred to as a third pixel 110c. Also, as described above, each of the pixels includes a boundary area BL and a light emitting area PX.

An undercut area UC to which the connection electrode CL is exposed is provided in the boundary area BL, and an undercut line UL is provided at one side of the undercut area UC. The undercut line UL may be provided on the same layer as the pixel electrodes PE1 , PE2 , and PE3 , and may be made of the same material.

Among the undercut areas provided in the light emitting display panel 100 , an undercut area provided between the first pixel 110a and the third pixel is referred to as a first undercut area UC1 , and the first pixel 110a and the second undercut area are referred to as the first undercut area UC1 . The undercut area provided between the pixels 110b is referred to as a second undercut area UC2 , and the undercut area provided between the second pixel 110b and the third pixel 110c is referred to as a third undercut area UC3 . . Here, the third pixel forming the first undercut region UC1 is a pixel that outputs light of the same color as the third pixel forming the third undercut region UC3 , that is, the third light. However, the third pixel forming the first undercut region UC1 and the third pixel forming the third undercut region UC3 are different pixels that are spaced apart from each other. Accordingly, in FIG. 4 , the third pixel forming the first undercut region UC1 is denoted by reference numeral 110c'. In this case, in FIG. 4 , another first pixel may be provided on the right side of the third pixel 100c forming the third undercut region UC3 .

A first undercut line UL1 is provided in the first undercut area UC1 , a second undercut line UL2 is provided in the second undercut area UC2 , and a third undercut line is provided in the third undercut area UC3 . (UL3) is provided.

A first connection electrode CL1 is provided in the first undercut region UC1 , a second connection electrode CL2 is provided in the second undercut region UC2 , and a third connection electrode is provided in the third undercut region UL3 . (CL3) is provided.

The light emitting display panel according to the present invention described above with reference to FIGS. 1 to 4 and the light emitting display panel according to the present invention described below with reference to FIGS. 5 to 9 further include the following features. .

For example, a pixel driving electrode PE is provided in each of the pixels. That is, the pixel driving electrode PE may be provided in all of the first pixel 110a, the second pixel 110b, and the third pixel 110c, as shown in FIG. 4 .

At least three pixels among the pixels constitute a unit pixel. For example, the unit pixel may include a red pixel, a blue pixel, and a green pixel. In the above description, a light emitting display panel including a first pixel 110a, a second pixel 110b, and a third pixel 110c as a unit pixel as shown in FIG. 4 has been described as an example of the present invention. .

The bank 114 for dividing the positions of the pixels may surround the pixel driving electrode PE and cover one side of the undercut line UL. That is, as shown in FIG. 4 , the bank 114 provided in each pixel surrounds the periphery of the pixel driving electrode PE provided in each pixel and covers one side of the undercut line UL.

The three emission layers EL1 , EL2 , EL3 and the three common electrodes CE1 , CE2 , and CE3 may be alternately disposed on top of the bank 114 and the pixel driving electrode PE.

The pixel driving electrode (hereinafter, simply referred to as the first pixel driving electrode PE1) provided in the first pixel 110a is separated from the first connection electrode CL1 provided in the first undercut region UC1, The pixel driving electrode (hereinafter, simply referred to as the second pixel driving electrode PE2) provided in the second pixel 110b is connected to the second connection electrode CL2 provided in the second undercut region UC2, A pixel driving electrode (hereinafter, simply referred to as a third pixel driving electrode PE3 ) provided in the third pixel 110c is connected to the third connection electrode CL3 provided in the third undercut region UC3 .

As described above, the unit pixel includes a first pixel 110a, a second pixel 110b, and a third pixel 110c adjacent to each other among the pixels, and the first pixel 110a, the second pixel One of the connection electrodes CL1 , CL2 , and CL3 provided between the pixel 110 and the third pixel 110c is connected to a shorting bar to which a common voltage is supplied. That is, one of the connection electrodes CL1 , CL2 , and CL3 provided in the unit pixel is connected to the shorting bar through a common voltage line, and the shorting bar is connected to the common voltage pad. A common voltage supplied from the power supply unit 500 through the common electrode line 510 is supplied to the common voltage pad.

In particular, as in the above example, when the first pixel driving electrode PE1 provided in the first pixel 110a is separated from the first connection electrode CL1 provided in the first undercut region UC1, the first The first connection electrode CL1 is connected to the shorting bar through a common voltage line.

FIG. 5 is an exemplary view for explaining the undercut region shown in FIG. 4 .

In the light emitting display panel 100 according to the present invention, a method of forming the undercut regions UC1 , UC2 , and UC3 as shown in FIGS. 4 and 5 is as follows.

For example, after the connection electrodes CL1 , CL2 , CL3 and the driving transistors Tdr1 , Tdr2 , and Tdr3 are provided on the substrate 111 , the protective layer 112 is formed on the entire surface of the substrate 111 . is applied

A planarization layer 113 is applied on the protective layer 112 .

A metal material for forming the pixel driving electrode PE is coated on the top of the planarization layer 113 .

A metal material is patterned using a mask, so that the pixel driving electrodes PE1, PE2, PE3 are formed in the light emitting areas PX1, PX2, and PX3, and the first undercut line UL1 is formed in the boundary areas BL. ), a second undercut line UL2 and a third undercut line UL3 are formed.

When the undercut lines UL1 , UL2 , and UL3 are formed, the planarization layer 113 may also be patterned.

In this case, the flat layer 113 provided at the lower ends of the undercut lines UL1 , UL2 , and UL3 is further etched inward of the lower ends of the undercut lines UL1 , UL2 and UL3 , so that the first undercut region UC1 ), a second undercut region UC2 and a third undercut region UC3 may be formed. The undercut regions as described above may be formed using at least one of a method using a halftone mask, a method using a dry etching method, and a method using a wet etching method.

The protective layer 112 under the undercut lines UL1 , UL2 and UL3 is patterned using the undercut lines UL1 , UL2 , and UL3 as a mask. However, the protective layer 112 may be patterned and formed together with at least one of the undercut lines or the planarization layer.

Accordingly, a portion of the protective layer 112 is etched to expose the first connection electrode CL1 , the second connection electrode CL1 , and the third connection electrode CL3 through the undercut regions UC1 , UC2 , and UC3 . can be

In particular, as described above, the flat layer 113 provided at the lower ends of the undercut lines UL1, UL2, and UL3 is further etched in the inner direction of the lower ends of the undercut lines UL1, UL2, and UL3. A first undercut region UC1 , a second undercut region UC2 , and a third undercut region UC3 are formed, so that each of the undercut lines UL1 , UL2 , and UL3 moves from the flat layer 113 to the undercut region direction. A protruding shape may be formed.

However, the undercut region UC may be formed through another process in addition to the process described above. That is, the undercut region as shown in FIGS. 4 and 5 may be formed on the light emitting display panel 100 through any one of various processes.

In more detail, the undercut region UC is formed by the undercut line UL, the connection electrode CL, and the protective layer 112 provided between the pixels.

In this case, the second undercut region UC2 is provided between the first pixel 110a and the second pixel 110b, and the third undercut region UC3 is the second pixel 110b and the third pixel 110c. The first undercut region UC1 is provided between the first pixel 110 and another third pixel 110c ′ adjacent to the first pixel 110a.

More specifically, the second undercut area UC2 is a second light emitting area PX1 provided between the first light emitting area PX1 of the first pixel 110a and the second light emitting area PX2 of the second pixel 110b. It is provided in the boundary area BL2, and the third undercut area UC3 is provided between the second light-emitting area PX2 of the second pixel 110b and the third light-emitting area PX3 of the third pixel 110c. It is provided in the third boundary area BL3, and the first undercut area UC1 includes the third emission area PX3' and the first light emitting area PX3' of another third pixel 110c' adjacent to the first pixel 110a. It is provided between the first emission areas PX1 of the pixels 110a.

After the undercut regions are formed, a material forming the bank 114 is applied on the substrate 111 and then patterned to form the bank 114 as shown in FIG. 4 .

The three light emitting layers EL1, EL2, EL3 and the three common electrodes CE1, CE2, CE3 are alternately disposed on the bank 114 and the bank and the top of the pixel driving electrode, and finally, as shown in FIG. The light emitting display panel 100 as shown is formed.

Each of the undercut regions UC1 , UC2 , and UC3 described below is substantially a space recessed by the connection electrode CL, the protective layer 112 , the planarization layer 113 , and the undercut line UL. means

Hereinafter, a connection relationship between the light emitting layers EL1 , EL2 , and EL3 and the common electrodes CE1 , CE2 and CE3 will be described in detail with reference to FIGS. 1 to 9 .

6 is an enlarged view of the first undercut region shown in FIG. 4 , FIG. 7 is an enlarged view of the second undercut region shown in FIG. 4 , and FIG. 8 is the third undercut region shown in FIG. 4 . is an enlarged exemplary view, and FIG. 9 is another exemplary view showing a cross-section cut along the line A-A' shown in FIG. 1 .

As described above, on top of the bank 114 and the pixel driving electrode PE, the three light emitting layers EL1 , EL2 , EL3 and the three common electrodes CE1 , CE2 and CE3 are alternately disposed. do.

One side of at least one of the three light-emitting layers EL1, EL2, and EL3 and one side of at least one of the three common electrodes CE1, CE2, and CE3 are provided in the undercut region.

That is, one side of the at least one light emitting layer and one side of the at least one common electrode are connected to the connection electrode exposed in the undercut region.

First, for example, in the first undercut region UC1 , as shown in FIG. 6 , a first emission layer EL1 and a second emission layer EL2 among the three emission layers, and a first emission layer among the three common electrodes Common electrodes CE1 and CE2 and a second common electrode are provided.

A first light emitting layer EL1 is provided in the first undercut region UC1, a first common electrode CE1 is provided on top of the first light emitting layer EL1, and a second light emitting layer is provided on top of the first common electrode CE1 ( EL2) is provided, and a second common electrode CE2 is provided on an upper end of the second light emitting layer EL2. The first light emitting layer EL1 , the first common electrode CE1 , the second light emitting layer EL2 , and the second common electrode CE2 are formed in the first light emitting area PX1 in the same order.

In this case, the first common electrode CE1 is connected to the first connection electrode CL1 , and the second common electrode CE2 is connected to the first common electrode CE1 . In addition, the first light emitting layer EL1 is directly connected to the upper end of the first connection electrode CL1 , and the second light emitting layer EL2 is connected to the first common electrode CLE1 . Accordingly, the voltage supplied through the first connection electrode CL1 may be simultaneously applied to the first common electrode CE1 and the second common electrode CE2 .

A third light emitting layer EL3 is provided on an upper end of the second common electrode CE2 , and a third common electrode CE3 is provided on an upper end of the third light emitting layer EL3 . In this case, since the first undercut region UC1 is covered by the third light emitting layer EL3 , the third common electrode CE3 provided on the upper end of the third light emitting layer EL3 is connected to the first connection electrode CL1 and CL1 . is not connected

At the lower end of the first undercut line UL1 provided in the first undercut region UC1 , as described above, the first light emitting layer EL1 , the first common electrode CE1 , the second light emitting layer EL2 and A second common electrode CE2 is provided.

A first light emitting layer EL1 , a first common electrode CE1 , a second light emitting layer EL2 , and a second common electrode CE2 are also provided on the upper end of the first undercut line UL1 , and a second common electrode CE2 is provided. ), the third light emitting layer EL3 and the third common electrode CE3 are provided on the upper end, and the third light emitting layer EL3 and the third common electrode CE3 provided on the upper end of the first undercut line UL1 are In the boundary area BL1 , it is connected to the third light emitting layer EL3 and the third common electrode CE3 provided in the first light emitting area PX1 .

That is, the third light emitting layer EL3 and the third common electrode CE3 provided on the upper end of the first undercut line UL1 continuously pass through the first boundary area BL1 to the first light emitting area PX1 . is formed However, the first light emitting layer EL1 , the first common electrode CE1 , the second light emitting layer EL2 , and the second common electrode CE2 provided on the upper end of the first undercut line UL1 is formed in the first boundary area BL1 . ) is formed only. Accordingly, the first light emitting layer EL1, the first common electrode CE1, the second light emitting layer EL2, and the second common electrode CE2 provided on the upper end of the first undercut line UL1 are formed on the first undercut line ( It is not connected to the first emission layer EL1, the first common electrode CE1, the second emission layer EL2, and the second common electrode CE2 extending from the lower end of the UL1 to the first emission region PX1. not.

However, the first emission layer EL1 , the first common electrode CE1 , and the second emission layer EL2 provided in the first boundary region BL1 and the first emission region PX1 from the third emission region PX3 ′. ), the second common electrode CE2 , the third emission layer EL3 , and the third common electrode CE3 are formed by the same deposition process.

For example, when the first light emitting material forming the first light emitting layer EL1 is deposited on the bank 114 , the first pixel driving electrode PE1 and the first undercut region UC1 , A portion flows into the first undercut region UC1 and is provided on the upper end of the first connection electrode CL1 , another portion is provided on the upper end of the first undercut line UL1 , and the remaining portion is provided on the third light emitting region ( PX3 ′), the first pixel driving electrode PE1 and the bank 114 . That is, due to the height difference between the first undercut line UL1 and the first connection electrode CL1 , the first light emitting layer EL1 provided on the first undercut line UL1 and the first connection electrode CL1 The first light emitting layers EL1 provided thereon are shifted from each other.

For the same reason as the first light emitting layer EL1 , the first common electrode CE1 , the second light emitting layer EL2 , and the second common electrode CE2 provided on the first undercut line UL1 also have a first connection electrode ( The first common electrode CE1 , the second light emitting layer EL2 , and the second common electrode CE2 provided on the CL1 are shifted from each other.

However, since the third light emitting layer EL3 provided in the first undercut region UC1 may be formed at the same or similar height to the first undercut line UL1 , the third light emitting layer EL3 and the third light emitting layer EL3 may be formed. ) The third common electrode CE3 provided on the upper end does not deviate from each other in the first undercut region UC1 .

Second, for example, as shown in FIG. 7 , the first light emitting layer EL1 , the first common electrode CE1 , and the second light emitting layer EL2 are provided in the second undercut region UC2 .

A first light emitting layer EL1 is provided in the second undercut region UC2, a first common electrode CE1 is provided on top of the first light emitting layer EL1, and a second light emitting layer is provided on top of the first common electrode CE1 ( EL2) is provided. The first emission layer EL1 , the first common electrode CE1 , and the second emission layer EL2 are formed in the second emission region PX2 in the same order.

In this case, the first light emitting layer EL1 is directly connected to the upper end of the first connection electrode CL1 , and the first common electrode CE1 is connected to the first connecting electrode CL1 at the upper end of the first light emitting layer EL1 . connected, and the second light emitting layer EL2 covers the second undercut region UC2 .

A second common electrode CE2 is provided on an upper end of the second light emitting layer EL2 , a third light emitting layer EL3 is provided on an upper end of the second common electrode CE2 , and a third common electrode is provided on an upper end of the third light emitting layer EL3 . An electrode CE3 is provided. In this case, since the second undercut region UC2 is covered by the second light emitting layer EL2 , the second common electrode CE2 and the third common electrode CE3 provided on the upper end of the second light emitting layer EL2 are It is not connected to the second connection electrode CL2.

At the lower end of the second undercut line UL2 provided in the second undercut region UC2 , as described above, the first light emitting layer EL1 , the first common electrode CE1 , and the second light emitting layer EL2 are provided. provided

The first light emitting layer EL1 , the first common electrode CE1 , and the second light emitting layer EL2 are also provided on the upper end of the second undercut line UL2 , and the second common electrode CE2 is provided on the upper end of the second light emitting layer EL2 . ), a third light emitting layer EL3 and a third common electrode CE3 are provided, and the second common electrode CE2 , the third light emitting layer EL3 , and the third common are provided on the upper end of the second undercut line UL2 . The electrode CE3 is connected to the second common electrode CE2 , the third emission layer EL3 , and the third common electrode CE3 provided in the second emission region PX2 in the second boundary region BL2 .

That is, the second common electrode CE2 , the third light emitting layer EL3 , and the third common electrode CE3 provided on the upper end of the second undercut line UL2 pass through the second boundary region BL2 to provide the first It is continuously formed up to the light emitting area PX1. However, the first light emitting layer EL1 , the first common electrode CE1 , and the second light emitting layer EL2 provided on the upper end of the second undercut line UL2 are formed only up to the second boundary area BL2 . Accordingly, the first light emitting layer EL1 , the first common electrode CE1 , and the second light emitting layer EL2 provided on the upper end of the second undercut line UL2 emits second light from the lower end of the second undercut line UL2 . It is not connected to the first emission layer EL1 , the first common electrode CE1 , and the second emission layer EL2 extending to the area PX2 .

However, the first emission layer EL1 , the first common electrode CE1 , and the second emission layer EL2 are provided in the second boundary region BL2 and the second emission region PX2 from the first emission region PX1 . , the second common electrode CE2 , the third emission layer EL3 , and the third common electrode CE3 are formed by the same deposition process as described with reference to FIG. 6 .

For example, when the first light emitting material forming the first light emitting layer EL1 is deposited on the bank 114 , the second pixel driving electrode PE2 and the second undercut region UC2 , the A portion flows into the second undercut region UC2 and is provided on the upper end of the second connection electrode CL2 , another portion is provided on the upper end of the second undercut line UL2 , and the remaining portion is provided on the first light emitting region ( PX1 ), the second pixel driving electrode PE2 , and the bank 114 . That is, due to the height difference between the second undercut line UL2 and the second connection electrode CL2 , the first light emitting layer EL1 and the second connection electrode CL2 provided on the second undercut line UL2 . The first light emitting layers EL1 provided thereon are shifted from each other.

For the same reason as the first light emitting layer EL1 , the first common electrode CE1 and the second light emitting layer EL2 provided on the second undercut line UL2 are also provided on the second connection electrode CL2 . The common electrode CE1 and the second light emitting layer EL2 are displaced from each other.

However, since the second common layer CE2 provided in the second undercut region UC2 may be formed at the same or similar height to the second undercut line UL2 , the second common electrode CE2 and the third light emitting layer may be formed. EL3 and the third common electrode CE3 do not deviate from each other in the second undercut region UC2 .

Third, for example, a first light emitting layer and a second light emitting layer, and a first common electrode and a second common electrode are provided in the third undercut region UC3 .

A first light emitting layer EL1 is provided in the third undercut region UC3, a first common electrode CE1 is provided on an upper end of the first light emitting layer EL1, and a second light emitting layer is provided on an upper end of the first common electrode CE1 ( EL2) is provided, and a second common electrode CE2 is provided on an upper end of the second light emitting layer EL2. The first emission layer EL1 , the first common electrode CE1 , the second emission layer EL2 , and the second common electrode CE2 are formed in the third emission region PX3 in the same order.

In this case, the first common electrode CE1 is connected to the third connection electrode CL3 , and the second common electrode CE2 is connected to the first common electrode CE1 . In addition, the first light emitting layer EL1 is directly connected to the upper end of the third connection electrode CL3 , and the second light emitting layer EL2 is connected to the first common electrode CLE1 . Accordingly, the voltage supplied through the third connection electrode CL3 may be simultaneously applied to the first common electrode CE1 and the second common electrode CE2 .

A third light emitting layer EL3 is provided on an upper end of the second common electrode CE2 , and a third common electrode CE3 is provided on an upper end of the third light emitting layer EL3 . In this case, since the third undercut region UC3 is covered by the third light emitting layer EL3 , the third common electrode CE3 provided on the upper end of the third light emitting layer EL3 is connected to the third connection electrode CL3 and is not connected

At the lower end of the third undercut line UL3 provided in the third undercut region UC3 , as described above, the first light emitting layer EL1 , the first common electrode CE1 , the second light emitting layer EL2 and A second common electrode CE2 is provided.

The first light emitting layer EL1 , the first common electrode CE1 , the second light emitting layer EL2 , and the second common electrode CE2 are also provided on the upper end of the third undercut line UL3 , and the second common electrode CE2 ), the third light emitting layer EL3 and the third common electrode CE3 are provided on the upper end, and the third light emitting layer EL3 and the third common electrode CE3 provided on the upper end of the third undercut line UL3 are the third In the boundary area BL3 , it is connected to the third light emitting layer EL3 and the third common electrode CE3 provided in the third light emitting area PX3 .

That is, the third light emitting layer EL3 and the third common electrode CE3 provided on the upper end of the third undercut line UL3 continuously pass through the third boundary area BL3 to the third light emitting area PX3 . is formed However, the first light emitting layer EL1 , the first common electrode CE1 , the second light emitting layer EL2 , and the second common electrode CE2 provided on the upper end of the third undercut line UL3 is formed in the third boundary area BL3 . ) is formed only. Accordingly, the first light emitting layer EL1 , the first common electrode CE1 , the second light emitting layer EL2 , and the second common electrode CE2 provided on the upper end of the third undercut line UL3 includes the third undercut line ( The first light emitting layer EL1, the first common electrode CE1, the second light emitting layer EL2, and the second common electrode CE2 extending from the lower end of the UL3 to the third light emitting region PX3 are not connected. not.

However, the first emission layer EL1 , the first common electrode CE1 , and the second emission layer EL2 are provided in the third boundary region BL3 and the third emission region PX3 from the second emission region PX2 . , the second common electrode CE2 , the third light emitting layer EL3 , and the third common electrode CE3 are formed by the same deposition process.

For example, when the first light emitting material forming the first light emitting layer EL1 is deposited on the bank 114 , the first pixel driving electrode PE1 and the third undercut region UC3 , A portion flows into the third undercut region UC3 and is provided on the upper end of the third connection electrode CL3, another portion is provided on the upper end of the third undercut line UL3, and the remaining portion is provided on the second light emitting region ( PX2 ), the third pixel driving electrode PE3 , and the bank 114 . That is, due to a height difference between the third undercut line UL3 and the third connection electrode CL3 , the first light emitting layer EL1 and the third connection electrode CL3 provided on the third undercut line UL3 . The first light emitting layers EL1 provided thereon are shifted from each other.

For the same reason as the first light emitting layer EL1 , the first common electrode CE1 , the second light emitting layer EL2 , and the second common electrode CE2 provided on the third undercut line UL3 also have a third connection electrode ( The first common electrode CE1 , the second light emitting layer EL2 , and the second common electrode CE2 provided on the CL3 are shifted from each other.

However, since the third light emitting layer EL3 provided in the third undercut region UC3 may be formed at the same or similar height to the third undercut line UL3 , the third light emitting layer EL3 and the third light emitting layer EL3 may be formed. ) The third common electrode CE3 provided on the upper end does not deviate from each other in the third undercut region UC3 .

In this case, the first to third light emitting layers EL1 , EL2 , EL3 and the first to third common electrodes CE1 , CE2 and CE2 in the third undercut region UC3 described with reference to FIG. 8 . The arrangement structure includes the first to third light emitting layers EL1 , EL2 and EL3 and the first to third common electrodes CE1 , CE2 and CE2 in the first undercut region UC1 described with reference to FIG. 6 . It is the same as the layout structure of

However, the first to third light emitting layers EL1 , EL2 , EL3 and the first to third common in the first undercut region UC1 and the third undercut region UC3 described with reference to FIGS. 6 and 8 . The arrangement structure of the electrodes CE1 , CE2 , and CE2 is the first to third light emitting layers EL1 , EL2 , EL3 and the first to third light emitting layers EL1 , EL2 , EL3 in the second undercut region UC3 described with reference to FIG. 7 . It is different from the arrangement structure of the common electrodes CE1 , CE2 , and CE2 .

The difference in the arrangement structure as described above is that the difference in height between the second undercut line UL2 and the second connection electrode CL2 in the second undercut region UC2 is the first undercut region UC1 (or the third This is because the difference in height between the first undercut line UL1 (or the third undercut line UL3) and the first connection electrode CL1 (or the third connection electrode CL3) in the undercut region UC3 is different. .

For example, in the first undercut region UC1 , as shown in FIG. 6 , the flattening layer 113 is provided on the protective layer 112 , and the first undercut line UL1 is provided on the flattening layer 113 . ) is provided. However, in the second undercut region UC2 , as shown in FIG. 7 , the second undercut line UL2 is provided on the protective layer 112 . Accordingly, as described above, the height of the first undercut region may be greater than the height of the second undercut region UC2 . Accordingly, the first undercut region UC1 has a height of the second undercut region UC2 when compared to that of the second undercut region UC2 . , a second light emitting layer EL2 and a second common electrode CE2 may be further provided.

The structures described above are briefly summarized as follows.

The second undercut area UC2 is provided between the first pixel 110a and the second pixel 110b, and the third undercut area UC3 is provided between the second pixel 110b and the third pixel 110c. The first undercut region UC1 is provided between the first pixel 110a and another third pixel 110c ′ adjacent to the first pixel 110a.

The first common electrode CE1 provided on the upper end of the first light emitting layer EL1 and the second common electrode CE2 provided on the upper end of the second light emitting layer EL2 are connected to the first connection exposed in the first undercut region UC1 . It is connected to the electrode CL1 , and the first common electrode CE1 is connected to the second connection electrode CL2 exposed in the second undercut region UC2 , and the first common electrode CE1 and the second The common electrode CE2 is connected to the third connection electrode CL3 exposed in the third undercut region UC3 .

In this case, the three emission layers EL1 , EL2 , and EL3 are provided in all of the first pixel 110a , the second pixel 110b , and the third pixel 110c .

Among the three light-emitting layers, the first light-emitting layer EL1 and the second light-emitting layer EL2 are between the first pixel 110a and the second pixel 110b, between the second pixel 110b and the third pixel 110c, and It is separated from each other between one pixel 110a and another third pixel. However, of the three emission layers, the third emission layer EL3 is continuously formed in the first pixel 110a, the second pixel 110b, and the third pixel 110c.

The first common electrode CE1 of the three common electrodes is separated from each other in the first pixel, the second pixel, and the third pixel, and the second common electrode CE2 of the three common electrodes is the first pixel and the second pixel. The second pixel is connected to the third pixel, and the third common electrode CE3 of the three common electrodes is connected to the first pixel, the second pixel, and the third pixel.

One side of the first common electrode CE1 is connected to the first connection electrode CL1 exposed in the first undercut region UC1 formed between the first pixel 110a and another third pixel 110c' , the other side is provided on the upper end of the second undercut line UL2 formed between the first pixel 110a and the second pixel 110b. One side of the second common electrode CE2 is connected to the first connection electrode CL1 , and the other side is on the upper end of the third undercut line UL3 formed between the second pixel 110b and the third pixel 110c. provided The third common electrode CE3 is connected to the common electrode line 510 provided in the non-display area of the substrate. The common electrode line 510 is connected to the second driving power line PLB provided in the pixel driver PDC.

Among the three light emitting layers, the first light emitting layer EL1 is formed from the first undercut area UC1 through the upper end of the first pixel driving electrode PE1 provided in the first pixel 110a and is provided in the second undercut area. 2 It extends to the top of the undercut line UL2. The first light emitting layer EL1 is a third undercut line provided in the third undercut area UC3 from the second undercut area UC2 through the upper end of the second pixel driving electrode PE2 provided in the second pixel 110b. (UL3) extends to the top. The first light emitting layer EL1 is formed from the third undercut area UC3 through the upper end of the third pixel driving electrode PE3 provided in the third pixel 110c to the first undercut line provided in another first undercut area. extended to the top In each of the first to third undercut regions, the first emission layer EL1 is separated from each other.

In this case, among the three common electrodes, the first common electrode CE1 extends from the first undercut region UC1 to the upper end of the second undercut line UL2 along the first emission layer, and the second undercut region UC2 ) extending to the upper end of the third undercut line UL3 along the first light emitting layer provided in the second pixel, and from the third undercut region UC3 along the first light emitting layer provided in the third pixel, another first undercut It extends to the top of another first undercut line provided in the region. In each of the first to third undercut regions, the first common electrode CE1 is separated from each other.

That is, in each of the first to third undercut regions UC1 , UC2 , and UC3 , the first emission layer EL1 is separated from each other, the second emission layer EL2 is separated from each other, and the third emission layer EL3 is separated from each other. are separated from each other. Also, in each of the first to third undercut regions, the first common electrode CE1 is separated from each other.

Among the three common electrodes, the second common electrode CE2 is provided in the first to third pixels from the first undercut region UC1 through the second undercut region UC2 and the third undercut region UC3. , separated from the third undercut region UC3 .

Among the three common electrodes, the third common electrode CE3 is continuous from the first undercut region UC1 to the first to third pixels through the second undercut region UC2 and the third undercut region UC3 . is provided with

Hereinafter, a method of driving a light emitting display device including a light emitting display panel having the above-described structure will be described.

When data voltages are supplied to the data lines DL, voltages corresponding to the data voltages are applied to the driving transistors Tdr1, Tdr2, and Tdr3 provided in the first to third pixels 110a, 110b, and 110c. is supplied, and pixel driving voltages according to voltages supplied to the driving transistors are supplied to the pixel driving electrodes PE1, PE2, and PE3.

In this case, the second driving power ELVSS is supplied to the first connection electrode CL1 through the common electrode line 510 , the shorting bar and the common voltage line, and the second pixel is supplied to the second connection electrode CL2 . The second pixel driving voltage supplied to the driving electrode PE2 is supplied, the third pixel driving voltage supplied to the third pixel driving electrode PE3 is supplied to the third connection electrode CL3, and the first pixel driving voltage is supplied. The first pixel driving voltage is supplied to the electrode PE1 .

First, as shown in FIG. 6 , the second driving power ELVSS supplied to the first connection electrode CL1 is supplied to the first common electrode CE1 , and the second driving power supply ELVSS is supplied to the first pixel driving electrode PE1 . One pixel driving voltage is supplied.

Accordingly, the first light is output from the first light emitting layer EL1 provided between the first pixel driving electrode PE1 and the first common electrode CE1 . The first light may be reflected by the second common electrode CE2 and the third common electrode CE3 and output through the substrate 111 to the outside as shown in FIG. 4 .

Next, as shown in FIG. 7 , the second pixel driving voltage supplied to the second connection electrode CL2 is supplied to the first common electrode CE1 and the second common electrode provided in the second pixel 110b. The second driving power ELVSS is supplied to CE2. That is, since the second common electrode CE2 connected to the first connection electrode CL1 in the first undercut region UC1 extends to the second pixel 110b through the second undercut region UC2, The second driving power ELVSS is supplied to the second common electrode CE2 provided in the second pixel 110b.

Accordingly, the second light is output from the second light emitting layer EL2 provided between the first common electrode CE1 and the second common electrode CE2 . The second light may be reflected by the second common electrode CE2 and the third common electrode CE3 and output through the substrate 111 to the outside as shown in FIG. 4 .

Finally, as shown in FIG. 8 , the third pixel driving voltage supplied to the third connection electrode CL3 is supplied to the second common electrode CE2 , and the third common voltage provided in the third pixel 110c . The second driving power ELVSS is supplied to the electrode CE3 . That is, in the first undercut region UC1 , the third common electrode CE3 connected to the first connection electrode CL1 is connected to the third pixel ( UC2 ) through the second undercut region UC2 and the third undercut region UC3 . 110c), the second driving power ELVSS is supplied to the third common electrode CE3 provided in the third pixel 110c.

Accordingly, the third light is output from the third light emitting layer EL3 provided between the second common electrode CE2 and the third common electrode CE3 . The third light may be reflected by the third common electrode CE3 and output to the outside through the substrate 111 as shown in FIG. 4 .

That is, in the present invention, the first light is output from the first emission layer EL1 by the first pixel driving electrode PE1 and the first common electrode CE1 provided in the first pixel 110a, and the second light The second light is output from the second light emitting layer EL2 by the first common electrode CE1 and the second common electrode CE2 provided in the pixel 110b, and the second light provided in the third pixel 110c The third light is output from the third light emitting layer EL3 by the common electrode CE2 and the third common electrode CE3 . In the following, the features of the invention described above are briefly described.

First, in the present invention, through an undercut structure, as shown in FIG. 6 , in the first pixel 110a , the first common electrode CE1 is connected to the common electrode line 510 , and the first common electrode CE1 is connected to the first common electrode line 510 . The first light is output from the first light emitting layer EL1 by the electrode CE1 and the first pixel driving electrode PE1 .

In the second pixel 110b, as shown in FIG. 7 , the first common electrode CE1 is connected to the second pixel driving electrode PE2 , and the second common electrode CE2 is connected to the common electrode line 510 . connected, and the second light is output from the second light emitting layer EL2 by the first common electrode CE1 and the second common electrode CE2 .

In the third pixel 110c, as shown in FIG. 8 , the first common electrode CE1 and the second common electrode CE2 are connected to the third pixel driving electrode PE3, and the third common electrode CE3 It is connected to the common electrode line 510 , and the third light is output from the third light emitting layer EL3 by the second common electrode CE2 and the third common electrode CE3 .

Next, the present invention combines the advantages of a conventional method having an independent pixel structure for each R, G, and B (hereinafter referred to as an RGB method) and a conventional method having white pixels and a color filter, thereby providing a low voltage of the RGB method. It is possible to realize a light emitting display panel with mass production that can be driven in

The present invention can be applied to low power consumption, high resolution and large area, and therefore is common to all types of display devices (PO, AR/VR, IT, TV, etc.) regardless of resolution, product type, and product size. can be applied as

Next, in the undercut region of the light emitting display panel according to the present invention, due to the difference in characteristics of step-coverage of evaporation and sputtering, the organic material (the light emitting layer (EL)) is A structure in which a short circuit is performed and the cathode (common electrode CE) is connected may be formed. In particular, in the present invention, by adjusting the height of the undercut for each pixel, the first common electrode CE1 and the second common electrode CE2 are different from each other, that is, the common electrode line 510 or the pixel driving. It can be connected to an electrode.

Next, the first common electrode CE1 and the second common electrode CE2 may be formed of a transparent metal such as ITO or IZO, and the third common electrode CE3 may be formed of an opaque metal such as aluminum (Al). can The third common electrode CE3 may be used as a reflector. In the first pixel 110a, the first common electrode CE1 functions as a cathode, in the second pixel 110b, the second common electrode CE2 functions as a cathode, and in the third pixel 110c In , the third common electrode CE3 may function as a cathode, and in all pixels, the third common electrode CE3 may function as a reflector.

Next, the light emitting display panel according to the present invention may be formed in a structure without a color filter as shown in FIGS. 4 to 8 , or as shown in FIG. 9 , a color corresponding to the color of each pixel The filter CF may be formed in a structure provided on the substrate 111 of each pixel. That is, light output from the light emitting layers EL1 , EL2 , and EL3 may be emitted to the outside after passing through the color filters corresponding to the light emitting layers.

That is, the light emitting display panel according to the present invention may further include a color filter CF according to the color coordinate of the target blue.

Finally, according to the present invention, since the common electrodes and the light emitting layers can be formed using an open mask instead of a patterned mask (FMM), a large area and ultra high resolution light emitting display panel can be easily formed. can be manufactured.

According to the present invention, since the light emitting display panel can be driven by a voltage of one-stack level, power consumption can be reduced.

According to the present invention, the optimal characteristics of the light emitting device ED for each color can be easily secured.

In the present invention, according to the height between the undercut line UL and the connection electrode CL in the undercut region UC, only the first common electrode CE1 among the common electrodes CE1, CE2, CE3 is the connection electrode ( CL), or the first common electrode CE1 and the second common electrode CE2 may be connected to the connection electrode CL.

The features of the present invention as described above are briefly summarized as follows.

A light emitting display panel according to the present invention includes a passivation layer covering pixel driving circuits provided on a substrate, a planarization layer provided on the passivation layer, and planarizing top surfaces of the pixel driving circuits, respectively, in boundary regions between pixels. The connection electrode exposed from the protective layer and the planarization layer is provided at a position corresponding to the light emitting regions among the upper ends of the protective layer, and the pixel driving electrode connected to each of the pixel driving circuits and the connection electrode among the upper ends of the protective layer are exposed. The undercut line provided on one side of the undercut region, surrounds the periphery of the pixel driving electrode, covers one side of the undercut line, and a bank and a bank that distinguishes the positions of pixels and three light emitting layers alternately disposed on the top of the bank and the pixel driving electrode and three common electrodes.

The undercut region may be formed by an undercut line provided between the pixels, a connection electrode, and a protective layer.

A second undercut region is provided between the first pixel and the second pixel, a third undercut region is provided between the second pixel and the third pixel, and the first undercut region is provided between the first pixel and another third adjacent pixel. It is provided between the pixel and the first pixel.

One side of at least one emission layer among the three emission layers and one side of at least one common electrode among the three common electrodes may be provided in the undercut region.

One side of the at least one light emitting layer and one side of the at least one common electrode may be connected to the connection electrode exposed in the undercut region.

The first undercut region includes a first emission layer and a second emission layer among the three emission layers, and a first common electrode and a second common electrode among the three common electrodes, and the second undercut region includes the first emission layer and the first common electrode. An electrode is provided, and a first light emitting layer and a second light emitting layer, and a first common electrode and a second common electrode are provided in the third undercut region.

A second undercut region is provided between the first pixel and the second pixel, a third undercut region is provided between the second pixel and the third pixel, and the first undercut region is provided between the first pixel and another third adjacent pixel. It is provided between the pixel and the first pixel.

The first common electrode provided on the upper end of the first light emitting layer and the second common electrode provided on the upper end of the second light emitting layer are connected to the first connection electrode exposed in the first undercut region, and the first common electrode is connected to the second undercut region It is connected to the second connection electrode exposed to the , and the first common electrode and the second common electrode are connected to the third connection electrode exposed to the third undercut region.

The three emission layers may be provided in all of the first pixel, the second pixel, and the third pixel.

A first light emitting layer and a second light emitting layer of the three light emitting layers are separated from each other between the first pixel and the second pixel, between the second pixel and the third pixel, and between the first pixel and another third pixel, the three light emitting layers Among them, the third light emitting layer is continuously formed in the first pixel, the second pixel, and the third pixel.

A first common electrode of the three common electrodes is separated from each other in the first pixel, the second pixel, and the third pixel, and a second common electrode of the three common electrodes is connected in the first pixel and the second pixel and is connected to the second pixel. The three pixels are separated, and a third common electrode among the three common electrodes is connected to the first pixel, the second pixel, and the third pixel.

One side of the first common electrode is connected to the first connection electrode exposed in the first undercut region formed between the first pixel and another third pixel, and the other side of the first common electrode is connected to the second undercut line formed between the first pixel and the second pixel. is provided on the upper end of the second common electrode, one side of the second common electrode is connected to the first connection electrode, the other side is provided on the upper end of the third undercut line formed between the second pixel and the third pixel, and the third common electrode is the third common electrode of the substrate. It is connected to the common electrode line provided in the non-display area.

Among the three light emitting layers, the first light emitting layer extends from the first undercut area through the upper end of the first pixel driving electrode provided in the first pixel to the upper end of the second undercut line provided in the second undercut area, and the first light emitting layer extends from the second undercut area to the upper end of the third undercut line provided in the third undercut area through the upper end of the second pixel driving electrode provided in the second pixel, and the first emission layer extends from the third undercut area to the third pixel It extends to the upper end of the first undercut line provided in another first undercut region through the upper end of the third pixel driving electrode provided in the The light emitting layer extends to the top of the second undercut line, the first common electrode extends from the second undercut region to the upper end of the third undercut line along the first light emitting layer provided in the second pixel, and the first common electrode It extends from the 3 undercut region to the upper end of the other first undercut line provided in the other first undercut region along the first light emitting layer provided in the third pixel.

In each of the first to third undercut regions, the first light emitting layer is separated from each other, the second light emitting layer is isolated from each other, and the third light emitting layer is connected to each other, and in each of the first to third undercut regions, 1 The common electrode CE1 is separated from each other.

Among the three common electrodes, a second common electrode is provided in the first to third pixels from the first undercut region through the second undercut region and the third undercut region, and is separated from the first undercut region and the third undercut region. has been

Among the three common electrodes, a third common electrode may be continuously provided in the first to third pixels from the first undercut region through the second undercut region and the third undercut region.

In addition, in the present invention, as shown in FIG. 4 , the heights of the first undercut region UC1 , the second undercut region UC2 , and the third undercut region UC3 may be different from each other. A structure as described in may be formed. However, the heights of the at least two undercut regions may be formed to be the same or similar. For example, in the light emitting display panel shown in FIG. 4 , the structures of the light emitting layers and common electrodes provided in the first undercut region UC1 and the third undercut region UC3 are similar, and thus, the first undercut region ( UC1) and the third undercut region UC3 may have the same or similar heights.

A light emitting display device according to the present invention includes a light emitting display panel, a gate driver supplying gate signals to gate lines provided in the light emitting display panel, a data driver supplying data voltages to data lines provided in the light emitting display panel, and a gate It includes a control unit for controlling the functions of the driver and data driver.

FIG. 10 is another exemplary view showing a cross-section taken along line A-A' shown in FIG. 1 , FIG. 11 is an exemplary view showing the structure of the substrate shown in FIG. 10 in detail, and FIG. 12 is FIG. It is an exemplary view for explaining the positions of the connecting electrodes shown in . That is, FIG. 10 schematically shows a cross-section of three consecutively arranged pixels, FIG. 11 shows driving transistors Tdr1 , Tdr2 , and Tdr3 provided in the substrate 111 , and FIG. The light emitting display panel 100 provided with the connection electrodes CL1, CL2, and CL3 shown in FIG. 10 is shown.

The light emitting display panel 100 according to the present invention includes a substrate 111 , a pixel driving circuit PDC including a driving transistor Tdr, and a substrate 111 as described with reference to FIGS. 1 to 9 . A passivation layer 112 covering the provided pixel driving circuit PDC, a planarization layer 113 provided on the passivation layer 112 and planarizing top surfaces of the pixel driving circuits, and a boundary region BL between pixels ), the connection electrode CL exposed from the protective layer and the planarization layer, provided at a position corresponding to the light emitting region PX among the upper ends of the protective layer, and connected to any one of the pixel driving circuits. (PE), the undercut line UL provided on one side of the undercut region UC where the connection electrode is exposed among the upper ends of the protective layer, and the pixel driving electrode are alternately disposed on the upper end, or of the planarization layer 113 . It includes three light emitting layers EL1 , EL2 , EL3 and three common electrodes CE1 , CE2 , CE3 which are alternately disposed on the top.

In this case, in the light emitting display panel described with reference to FIGS. 1 to 9 , the pixel driving electrode PE is provided in each of the pixels, and the three light emitting layers EL1 , EL2 , EL3 and the three common electrodes are provided. The fields CE1 , CE2 , and CE3 are alternately disposed on the bank 114 and the top of the pixel driving electrode PE. The first pixel driving electrode PE1 provided in the first pixel 110a is separated from the first connection electrode CL1 provided in the first undercut region UC1, and the first pixel driving electrode PE1 provided in the second pixel 110b. The second pixel driving electrode PE2 is connected to the second connection electrode CL2 provided in the second undercut region UC2, and the third pixel driving electrode PE3 provided in the third pixel 110c is the third It is connected to the third connection electrode CL3 provided in the undercut region UC3 . In this case, the first connection electrode CL1 is connected to the shorting bar through a common voltage line, and a common voltage is supplied to the first connection electrode CL1 .

However, the light emitting display panel shown in FIG. 10 has the following characteristics compared to the light emitting display panel shown in FIG. 4 .

First, when a unit pixel includes a first pixel 110a, a second pixel 110b, and a third pixel 110c that are adjacent to each other among pixels, the first pixel 110a has a first pixel driving electrode ( PE1), and the pixel driving electrode is not provided in the second pixel 110b and the third pixel 110c. That is, in the light emitting display panel shown in FIG. 10, only one pixel among the three pixels 110a, 110b, and 110c constituting the unit pixel is provided with the pixel driving electrode.

Next, the bank 114 for dividing the positions of the pixels 110 surrounds the periphery of the first pixel driving electrode PE1 provided in the first pixel 110a and covers one side of the first undercut line UL1 . do. That is, in the light emitting display panel shown in FIG. 10 , the bank 114 is provided only in any one of the three pixels 110a , 110b and 110c constituting the unit pixel, for example, the first pixel 110a only. can be However, the present invention is not limited thereto. Accordingly, the bank 114 may be provided to surround the perimeter of the remaining two pixels PX2 and PX3 as well.

Next, the first pixel driving electrode PE1 provided in the first pixel 110a is separated from the first connection electrode CL1 provided in the first undercut region UC1, and is provided in the second pixel 110b. The second driving transistor Tdr2 constituting the pixel driving circuit PDC is connected to the second connection electrode CL2 provided in the second undercut region UC2, and the pixel provided in the third pixel 110c. The third driving transistor Tdr3 constituting the driving circuit PDC is connected to the third connection electrode CL3 provided in the third undercut region UC3 .

That is, in the light emitting display panel shown in FIG. 10 , the first connection electrode CL1 is connected to the shorting bar SB through the common voltage line CVL, and as the first connection electrode CL1, the power supply unit ( A common voltage transmitted from the common electrode line 510 , the shorting bar SB and the common voltage line CVL is supplied from the 500 . In this case, the first connection electrode CL1 may be the common voltage line CVL or may be connected to the common voltage line CVL through a contact hole.

The second connection electrode CL2 is connected to the second driving transistor Tdr2 constituting the pixel driving circuit PDC provided in the second pixel 110b. In this case, the second connection electrode CL2 is connected to the anode function can be performed.

The third connection electrode CL3 is connected to the third driving transistor Tdr3 constituting the pixel driving circuit PDC provided in the third pixel 110c, and in this case, the third connection electrode CL3 is the anode function can be performed.

Finally, the three light emitting layers EL1 , EL2 , EL3 and the three common electrodes CE1 , CE2 and CE3 provided in the first pixel 110a are alternately disposed on top of the first pixel driving electrode PE1 . The three light emitting layers EL1 , EL2 , EL3 and the three common electrodes CE1 , CE2 , CE3 provided in the second pixel 110b and the flat layer are provided in the second pixel 110b. The three light emitting layers EL1 , EL2 , EL3 and the three common electrodes CE1 , CE2 and CE3 provided in the third pixel 110c are alternately arranged on top of the third pixel 110c. It is alternately disposed on top of the planarization layer 113 provided in 110c).

That is, in the light emitting display panel shown in FIG. 10 , the first pixel driving electrode PE1 is provided only in the first pixel 110a. Accordingly, in the first pixel 110a, the three light emitting layers EL1, EL2, EL3) and the three common electrodes CE1, CE2, and CE3 are alternately disposed on top of the first pixel driving electrode PE1. However, the pixel driving electrode is not provided in the second pixel 110b and the third pixel 110c. Therefore, in the second pixel 110b and the third pixel 110c, the three light emitting layers EL1 and EL2 are not provided. , EL3 ) and the three common electrodes CE1 , CE2 , and CE3 are alternately disposed on top of the flattening layer 113 .

Hereinafter, the light emitting display panel shown in FIG. 10 will be described in detail based on the above characteristics. In this case, the same or similar contents to those described with reference to FIGS. 1 to 9 are omitted or simply described.

The substrate 111 includes a base substrate 111a formed of a plastic material or a glass material, various insulating films 111b and 111c provided on the base substrate 111a, and between the base substrate 111a and the insulating films 111b and 111c. It may include provided metals. Various lines and transistors may be formed by insulating films and metals. For example, as illustrated in FIG. 11 , driving transistors Tdr1 , Tdr2 , and Tdr3 provided in each pixel may be formed by insulating layers and metals.

Each of the insulating layers 111b and 111c may be formed of at least one inorganic layer or at least one organic layer, or may be formed of at least one inorganic layer and at least one organic layer.

As shown in FIG. 11 , the first driving transistor Tdr1 provided in the first pixel 110a among the driving transistors Tdr1 , Tdr2 , and Tdr3 provided on the substrate 111 is a first pixel driving electrode PE1 . ), the second driving transistor Tdr2 provided in the second pixel 110b is connected to the second connection electrode CL2, and the third driving transistor Tdr3 provided in the third pixel 110c is It is connected to the third connection electrode CL3.

That is, as described above, in the light emitting display panel shown in FIG. 10 , the first connection electrode CL1 is connected to the shorting bar SB through the common voltage line CVL, and the second connection electrode CL2 ) is connected to the second driving transistor Tdr2 provided in the second pixel 110b, and the third connection electrode CL3 is connected to the third driving transistor Tdr3 provided in the third pixel 110c.

As described above, the pixel driving circuit PDC including various lines and transistors is provided on the upper end of the base substrate 111a. The pixel driving circuit PDC may have the structure described with reference to FIG. 3 , and in addition to this, may be configured in various forms.

A protective layer 112 for protecting the pixel driving circuit PDC is provided on the upper end of the pixel driving circuit PDC, that is, on the upper end of the substrate 111 .

A planarization layer 113 is provided on the upper end of the protective layer 112 . The planarization layer 113 is disposed on the substrate 111 to cover the pixel driving circuit PDC, and accordingly, a flat surface may be provided on the top of the pixel driving circuit PDC.

The connection electrode CL is exposed from the passivation layer 112 and the planarization layer 113 in each of the boundary regions BL between the pixels.

The pixel driving voltage supplied from the pixel driving electrode PE may be supplied to the connection electrode CL, or the second driving power ELVSS supplied from the power supply unit 500 may be supplied.

The undercut line UL is provided at one side of the undercut region UC to which the connection electrode CL is exposed among the upper ends of the protective layer 112 .

A light emitting device ED is provided on the top of the flattening layer. The light emitting device ED includes a pixel driving circuit PDC, in particular, a pixel driving electrode PE electrically connected to the driving transistor Tdr, a light emitting layer EL provided on top of the pixel driving electrode, and a common provided on top of the light emitting layer. electrode CE.

The pixel driving electrode PE may be an anode. The pixel driving electrode PE is provided at a position corresponding to the pixel among the upper ends of the protective layer, and is connected to the pixel driving circuit. In particular, in the light emitting display panel shown in FIGS. 10 to 12 , the pixel driving electrode PE includes any one of the three pixels 110a , 110b and 110c forming the unit pixel, for example, the first pixel ( 110a) only. Accordingly, the pixel driving electrode is not provided in the second pixel 110b and the third pixel 110c.

When the pixel driving electrode PE is provided in the pixel, the pixel driving electrode PE is disposed on the light emitting area PX of the pixel 110 and is connected to the driving transistor Tdr provided in the pixel driving circuit PDC. electrically connected.

The light emitting area PX may be formed by the bank 114 . The bank 114 surrounds the periphery of the pixel driving electrode PE, covers one side of the undercut line UL, and functions to distinguish positions of pixels. The bank 114 may be provided in all pixels as shown in FIG. 4 , but may be provided in only some of the pixels as shown in FIGS. 10 to 12 .

The pixel driving electrode PE may be formed of a transparent metal such as indium tin oxide (ITO) or zinc oxide (IZO).

The three light emitting layers EL1 , EL2 , EL3 and the three common electrodes CE1 , CE2 and CE3 provided in the first pixel 110a are alternately disposed on top of the first pixel driving electrode PE1 , , the three light emitting layers EL1 , EL2 , EL3 provided in the second pixel 110b and the three common electrodes CE1 , CE2 and CE3 provided in the second pixel 110b include a flattening layer 113 provided in the second pixel 110b. The three light emitting layers EL1 , EL2 , EL3 and the three common electrodes CE1 , CE2 , CE3 provided in the third pixel 110c and are alternately disposed on the top of the third pixel 110c are provided on the third pixel 110c. It is alternately disposed on top of the provided planarization layer 113 .

In the pixel provided with the pixel driving electrode (eg, the first pixel 110a ), the light emitting layers EL1 , EL2 , and EL3 are formed on the substrate 111 to cover the pixel driving electrode PE and the bank 114 . It may be formed in the entire display area AA, and in a pixel (eg, the second pixel PX2 and the third pixel PX3 ) in which the pixel driving electrode is not provided, the emission layers EL1 , EL2 , and EL3 . Silver may be formed in the entire display area AA of the substrate 111 to cover the planarization layer 113 .

The light emitting layers EL1, EL2, and EL3 include a first light emitting layer EL1 emitting a first light (eg, red light), a second light emitting layer EL2 emitting a second light (eg, green light), and A third light emitting layer EL3 emitting third light (eg, blue light) may be included.

The bank 114 surrounds the periphery of the pixel driving electrode PE, covers one side of the undercut line UL, and identifies positions of pixels. However, in the light emitting display panel shown in FIG. 10 , the bank 114 may not be provided in all pixels.

For example, the bank 114 may be provided only in any one of the three pixels 110a, 110b, and 110c constituting the unit pixel, for example, the first pixel 110a. However, the present invention is not limited thereto. Accordingly, a bank may be provided to surround the perimeter of the remaining two pixels PX2 and PX3 as well.

In this case, in FIG. 10 , each of the pixels 110 is divided into a boundary area BL and a light emitting area PX. Light may be output through the light emitting area PX.

The common electrodes CE1 , CE2 , and CE3 may be alternately provided with the three light emitting layers EL1 , EL2 , and EL3 at the top of the bank 114 and the pixel driving electrode PE, or the planarization layer 113 . ), the three light emitting layers EL1, EL2, and EL3 may be alternately provided.

Among the common electrodes CE1 , CE2 , and CE3 , the first common electrode CE1 and the second common electrode CE2 may be formed of a transparent metal such as indium tin oxide (ITO) or zinc oxide (IZO). Among the common electrodes, the third common electrode CE3 has to function as a reflective plate, so a stacked structure of aluminum (Al) and titanium (Ti) (Ti/Al/Ti) and a stacked structure of aluminum (Al) and ITO (ITO/Al/ITO), APC (Ag/Pd/Cu) formed in a multilayer structure such as alloy, silver (Ag), aluminum (Al), molybdenum (Mo), gold (Au), magnesium (Mg), It may include a single layer structure made of any one material selected from calcium (Ca) and barium (Ba) or two or more alloy materials.

An encapsulation layer may be provided on the upper end of the common electrode CA.

In the following description, the pixel that outputs the first light is referred to as a first pixel 110a, the pixel that outputs the second light is referred to as a second pixel 110b, and the pixel 110 that outputs the third light is referred to as a first pixel 110a. It is referred to as a third pixel 110c. Also, as described above, each of the pixels includes a boundary area BL and a light emitting area PX. Also, hereinafter, the opening region refers to a region in which light generated in the light emitting area PX is substantially output to the outside of the light emitting display panel. Accordingly, the aperture area may be equal to or smaller than the light emitting area.

An undercut area UC to which the connection electrode CL is exposed is provided in the boundary area BL, and an undercut line UL is provided at one side of the undercut area UC. The undercut line UL may be provided on the same layer as the pixel electrodes PE1 , PE2 , and PE3 , and may be made of the same material.

Among the undercut areas provided in the light emitting display panel 100 , an undercut area provided between the first pixel 110a and the third pixel is referred to as a first undercut area UC1 , and the first pixel 110a and the second undercut area are referred to as the first undercut area UC1 . The undercut area provided between the pixels 110b is referred to as a second undercut area UC2 , and the undercut area provided between the second pixel 110b and the third pixel 110c is referred to as a third undercut area UC3 . . Here, the third pixel forming the first undercut region UC1 is a pixel that outputs light of the same color as the third pixel forming the third undercut region UC3 , that is, the third light. However, the third pixel forming the first undercut region UC1 and the third pixel forming the third undercut region UC3 are different pixels that are spaced apart from each other. Accordingly, in FIGS. 10 to 12 , the third pixel forming the first undercut region UC1 is denoted by reference numeral 110c'. In this case, another first pixel may be provided on the right side of the third pixel 110c forming the third undercut region UC3 in FIGS. 10 to 12 .

A first undercut line UL1 is provided in the first undercut area UC1 , a second undercut line UL2 is provided in the second undercut area UC2 , and a third undercut line is provided in the third undercut area UC3 . (UL3) is provided.

A first connection electrode CL1 is provided in the first undercut region UC1 , a second connection electrode CL2 is provided in the second undercut region UC2 , and a third connection electrode is provided in the third undercut region UL3 . (CL3) is provided.

13 is an exemplary view for explaining the undercut region shown in FIG. 10 . In the following description, the same or similar contents to those described with reference to FIGS. 1 to 12 are omitted or simply described.

In the light emitting display panel 100 according to the present invention, a method of forming the undercut regions UC1 , UC2 , and UC3 as shown in FIGS. 10 and 13 is as follows.

For example, after the connection electrodes CL1 , CL2 , CL3 and the driving transistors Tdr1 , Tdr2 , and Tdr3 are provided on the substrate 111 , the protective layer 112 is formed on the entire surface of the substrate 111 . is applied

A planarization layer 113 is applied on the protective layer 112 .

A metal material for forming the pixel driving electrode PE is coated on the top of the planarization layer 113 . As described above, the pixel driving electrode PE may be formed only in any one of the pixels constituting the unit pixel. 11 and 13 show a light emitting display panel in which a pixel driving electrode PE, that is, a first pixel driving electrode PE1, is formed only on the first pixel 110a as an example of the present invention. Accordingly, a metal material for forming the pixel driving electrode PE is applied only to an area corresponding to the first pixels 110a among the upper ends of the planarization layer.

A metal material is patterned using a mask to form a first pixel driving electrode PE1 in some of the light emitting areas PX1 , PX2 , and PX3 , for example, the first light emitting area PX1 , and a boundary area A first undercut line UL1 , a second undercut line UL2 , and a third undercut line UL3 are formed in the BLs.

When the undercut lines UL1 , UL2 , and UL3 are formed, the planarization layer 113 may also be patterned.

In this case, the flat layer 113 provided at the lower ends of the undercut lines UL1 , UL2 , and UL3 is further etched inward of the lower ends of the undercut lines UL1 , UL2 and UL3 , so that the first undercut region UC1 ), a second undercut region UC2 and a third undercut region UC3 may be formed. The undercut regions as described above may be formed using at least one of a method using a halftone mask, a method using a dry etching method, and a method using a wet etching method.

The protective layer 112 under the undercut lines UL1 , UL2 and UL3 is patterned using the undercut lines UL1 , UL2 , and UL3 as a mask. However, the protective layer 112 may be patterned and formed together with at least one of the undercut lines or the planarization layer.

Accordingly, a portion of the protective layer 112 is etched to expose the first connection electrode CL1 , the second connection electrode CL1 , and the third connection electrode CL3 through the undercut regions UC1 , UC2 , and UC3 . can be

In particular, as described above, the flat layer 113 provided at the lower ends of the undercut lines UL1, UL2, and UL3 is further etched in the inner direction of the lower ends of the undercut lines UL1, UL2, and UL3. A first undercut region UC1 , a second undercut region UC2 , and a third undercut region UC3 are formed, so that each of the undercut lines UL1 , UL2 , and UL3 moves from the flat layer 113 to the undercut region direction. A protruding shape may be formed.

However, the undercut region UC may be formed through another process in addition to the process described above. That is, the undercut region as shown in FIGS. 4 and 5 may be formed on the light emitting display panel 100 through any one of various processes.

In more detail, the undercut region UC is formed by the undercut line UL, the connection electrode CL, and the protective layer 112 provided between the pixels.

In this case, the second undercut region UC2 is provided between the first pixel 110a and the second pixel 110b, and the third undercut region UC3 is the second pixel 110b and the third pixel 110c. The first undercut region UC1 is provided between the first pixel 110 and another third pixel 110c ′ adjacent to the first pixel 110a.

After the undercut regions are formed, a material forming the bank 114 is applied on the substrate 111 and then patterned to form the bank 114 as shown in FIG. 10 . In this case, as described above, the bank 114 may be provided in all pixels, but may be provided only in a specific pixel. For example, a light emitting display panel in which a bank 114 is formed only in the first pixel 110a is illustrated in FIGS. 10 to 12 as an example of the present invention.

The three light emitting layers EL1 , EL2 , EL3 and the three common electrodes CE1 , CE2 , CE3 are alternately disposed on the top of the pixel driving electrode PE or alternately on the top of the flattening layer 113 . may be disposed, and thus, finally, a light emitting display panel as shown in FIG. 10 is formed.

For example, the three light emitting layers EL1 , EL2 , EL3 and the three common electrodes CE1 , CE2 and CE3 provided in the first pixel 110a include the bank 114 and the first pixel driving electrode ( ). The three light emitting layers EL1 , EL2 , EL3 and the three common electrodes CE1 , CE2 and CE3 which are alternately disposed on the upper end of the PE1 and provided in the second pixel 110b are the second pixel 110b ) are alternately disposed on top of the flattening layer 113 provided in the third pixel 110c, and the three light emitting layers EL1, EL2, EL3 and the three common electrodes CE1, CE2, CE3 are provided in the third pixel 110c. is alternately disposed on the upper end of the planarization layer 113 provided in the third pixel 110c.

Each of the undercut regions UC1 , UC2 , and UC3 described below is substantially a space recessed by the connection electrode CL, the protective layer 112 , the planarization layer 113 , and the undercut line UL. means

Hereinafter, a connection relationship between the emission layers EL1 , EL2 , and EL3 and the common electrodes CE1 , CE2 , and CE3 will be described with reference to FIGS. 10 to 16 .

14 is an enlarged view of the first undercut region shown in FIG. 10 , FIG. 15 is an enlarged view of the second undercut region shown in FIG. 10 , and FIG. 16 is a third undercut region shown in FIG. 10 . It is an enlarged example of . Among the following descriptions, the same or similar contents to those described with reference to FIGS. 6 to 8 will be omitted or simply described.

As described above, the three light emitting layers EL1, EL2, EL3 and the three common electrodes CE1, CE2, CE3 are alternately disposed on top of the pixel driving electrode PE, or the flat layer ( 113) may be alternately disposed on top of the.

One side of at least one of the three light-emitting layers EL1, EL2, and EL3 and one side of at least one of the three common electrodes CE1, CE2, and CE3 are provided in the undercut region.

That is, one side of the at least one light emitting layer and one side of the at least one common electrode are connected to the connection electrode exposed in the undercut region.

First, for example, in the first undercut region UC1 , as shown in FIG. 14 , a first emission layer EL1 and a second emission layer EL2 among the three emission layers, and a first emission layer among the three common electrodes Common electrodes CE1 and CE2 and a second common electrode are provided.

Since the structure of the first undercut region UC1 is the same as that of the first undercut region UC1 described with reference to FIG. 6 , a detailed description thereof will be omitted.

In this case, the structure of the first light emitting area PX1 adjacent to the first undercut area UC1 shown in FIG. 14 is also the same as that of the first light emitting area PX1 shown in FIG. 6 .

That is, the first pixel driving electrode PE1 is provided in the emission region PX1 shown in FIG. 14 , and the first pixel driving electrode PE1 is connected to the first driving transistor Tdr1 .

Second, for example, as shown in FIG. 15 , the first light emitting layer EL1 , the first common electrode CE1 , and the second light emitting layer EL2 are provided in the second undercut region UC2 .

Since the structure of the second undercut region UC2 is the same as that of the second undercut region UC2 described with reference to FIG. 7 , a detailed description thereof will be omitted.

In this case, although the second pixel driving electrode PE2 is provided in the second light emitting region PX2 adjacent to the second undercut region UC2 shown in FIG. 7 , the second undercut region UC2 shown in FIG. 15 . The second pixel driving electrode PE2 is not provided in the second light emitting area PX2 adjacent to UC2 . In particular, in the second pixel 110b illustrated in FIG. 15 , the second driving transistor Tdr2 is connected to the second connection electrode CL2 .

Third, for example, a first light emitting layer and a second light emitting layer, and a first common electrode and a second common electrode are provided in the third undercut region UC3 .

Since the structure of the third undercut region UC3 is the same as that of the third undercut region UC3 described with reference to FIG. 8 , a detailed description thereof will be omitted.

In this case, the third pixel driving electrode PE3 is provided in the third light emitting region PX3 adjacent to the third undercut region UC3 shown in FIG. 8 , but the third undercut region UC3 shown in FIG. 16 . The third pixel driving electrode PE3 is not provided in the third light emitting area PX3 adjacent to UC3 . In particular, in the third pixel 110c illustrated in FIG. 16 , the third driving transistor Tdr3 is connected to the third connection electrode CL2 .

Hereinafter, a method of driving a light emitting display device including a light emitting display panel having the structure described with reference to FIGS. 10 to 16 will be described.

When data voltages are supplied to the data lines DL, voltages corresponding to the data voltages are applied to the driving transistors Tdr1, Tdr2, and Tdr3 provided in the first to third pixels 110a, 110b, and 110c. is supplied, and pixel driving voltages according to voltages supplied to the driving transistors are supplied to the pixel driving electrodes PE1, PE2, and PE3.

In this case, the second driving power ELVSS is supplied to the first connection electrode CL1 through the common electrode line 510 , the shorting bar SB and the common voltage line CVL, and the second connection electrode CL2 ) is supplied with the second pixel driving voltage supplied from the second driving transistor Tdr2, and the third pixel driving voltage supplied from the third driving transistor Tdr3 is supplied to the third connection electrode CL3, The first pixel driving voltage supplied from the first driving transistor Tdr1 is supplied to the first pixel driving electrode PE1 .

First, as shown in FIG. 14 , the second driving power ELVSS supplied to the first connection electrode CL1 is supplied to the first common electrode CE1 , and the second driving power supply ELVSS is supplied to the first pixel driving electrode PE1 . A first pixel driving voltage is supplied from the first driving transistor Tdr1.

Accordingly, the first light is output from the first light emitting layer EL1 provided between the first pixel driving electrode PE1 and the first common electrode CE1 . The first light may be reflected by the second common electrode CE2 and the third common electrode CE3 and output through the substrate 111 to the outside as shown in FIG. 10 .

Next, as shown in FIG. 15 , the second pixel driving voltage supplied from the second driving transistor Tdr2 to the second connection electrode CL2 is supplied to the first common electrode CE1 and the second pixel 110b ), the second driving power ELVSS is supplied to the second common electrode CE2 . That is, since the second common electrode CE2 connected to the first connection electrode CL1 in the first undercut region UC1 extends to the second pixel 110b through the second undercut region UC2, The second driving power ELVSS is supplied to the second common electrode CE2 provided in the second pixel 110b.

Accordingly, the second light is output from the second light emitting layer EL2 provided between the first common electrode CE1 and the second common electrode CE2 . The second light is reflected by the second common electrode CE2 and the third common electrode CE3 and may be output through the substrate 111 to the outside as shown in FIG. 10 .

Finally, as shown in FIG. 16 , the third pixel driving voltage supplied from the third driving transistor Tdr3 to the third connection electrode CL3 is supplied to the second common electrode CE2 and the third pixel ( The second driving power ELVSS is supplied to the third common electrode CE3 provided in 110c). That is, in the first undercut region UC1 , the third common electrode CE3 connected to the first connection electrode CL1 is connected to the third pixel ( UC2 ) through the second undercut region UC2 and the third undercut region UC3 . 110c), the second driving power ELVSS is supplied to the third common electrode CE3 provided in the third pixel 110c.

Accordingly, the third light is output from the third light emitting layer EL3 provided between the second common electrode CE2 and the third common electrode CE3 . The third light may be reflected by the third common electrode CE3 and output to the outside through the substrate 111 as shown in FIG. 10 .

That is, in the present invention, the first light is output from the first emission layer EL1 by the first pixel driving electrode PE1 and the first common electrode CE1 provided in the first pixel 110a, and the second light The second light is output from the second light emitting layer EL2 by the first common electrode CE1 and the second common electrode CE2 provided in the pixel 110b, and the second light provided in the third pixel 110c The third light is output from the third light emitting layer EL3 by the common electrode CE2 and the third common electrode CE3 .

In the above, the light emitting display panel according to the present invention described with reference to FIGS. 10 to 16 basically includes the characteristics and effects of the light emitting display panel according to the present invention described with reference to FIGS. 1 to 9 . .

Also, the light emitting display panel shown in FIG. 10 may further include a color filter CF as shown in FIG. 9 .

Hereinafter, the characteristics of the light emitting display panel according to the present invention described with reference to FIGS. 10 to 16 will be described with reference to FIGS. 10 to 17 .

17 is an exemplary view showing the opening regions of pixels included in the light emitting display panel according to the present invention.

In the light emitting display panel according to the present invention, as described above, when the unit pixel includes the first pixel 110a, the second pixel 110b, and the third pixel 110c adjacent to each other among the pixels, , The first pixel driving electrode PE1 is provided in the first pixel 110a, and the pixel driving electrode is not provided in the second pixel 110b and the third pixel 110c. That is, in the light emitting display panel shown in FIG. 10, only one pixel among the three pixels 110a, 110b, and 110c constituting the unit pixel is provided with the pixel driving electrode.

In more detail, in order to increase the efficiency of the second pixel 110b for outputting green and the third pixel 110c for outputting blue, the pixel driving electrode is provided in the second pixel 110b and the third pixel 110c. may be omitted. That is, in the present invention, the bank 114 and the pixel driving electrode PE may be omitted from the second pixel 110b for outputting green and the third pixel 110c for outputting blue, and thus the aperture ratio increases. In addition, transmittance may be improved, and device efficiency may be improved due to the removal of the pixel driving electrode PE having a refractive index different from that of the organic material.

In this case, in the first pixel 110a , light is output from the first light emitting layer EL1 by the first pixel driving electrode PE1 and the first common electrode CE1 , and in the second pixel 110b , the first common electrode CE1 . Light is output from the second light emitting layer EL2 by the electrode CE1 and the second common electrode CE2 , and in the third pixel 110c by the second common electrode CE2 and the third common electrode CE3 . Light is output from the third light emitting layer EL3 .

Accordingly, when the sizes of the first light emitting area PX1 , the second light emitting area PX2 , and the third light emitting area PX3 are the same, the generated light from the second light emitting area PX2 and the third light emitting area PX3 is the same. As shown in FIG. 17 , the size of the second opening area EA2 and the third opening area EA3 through which light is output to the outside of the light emitting display panel is determined by the amount of light emitted from the first light emitting area PX1 being emitted. It is larger than the first opening area EA1 output to the outside of the display panel.

That is, in the first pixel 110a , the area corresponding to the first pixel driving electrode PE1 may be the first opening area EA1 , but in the second pixel 110b , it is connected among the second light emitting areas PX2 . Areas other than the area in which the electrodes and undercut lines are provided may be the second opening area EA2 , and in the third pixel 110c , the area in which the connection electrodes and undercut lines are provided among the third light emitting area PX3 . Areas other than , may be the third opening area EA3 .

Accordingly, as illustrated in FIG. 17 , the sizes of the second and third opening areas EA2 and EA3 may be greater than those of the first opening area EA1 .

Accordingly, the opening area of the entire light emitting display panel 100 may be increased, and thus the luminance of the light emitting display panel may be increased, and power consumption of the light emitting display panel may be reduced.

That is, according to the light emitting display panel shown in FIG. 10 , transmittance and aperture ratio of at least two pixels among three pixels constituting a unit pixel may be increased, and thus, transmittance and aperture ratio of the entire light emitting display panel may be increased. can be Accordingly, the efficiency of each element constituting the light emitting display panel may be increased.

In more detail, the pixel driving electrode PE may be removed from the second pixel 110b and the third pixel 110c, and thus the aperture ratio may be increased. In addition, the transmittance may be increased by removing the pixel driving electrode PE. In addition, as the pixel driving electrode PE having a refractive index different from that of the organic material is removed, luminous efficiency may be improved.

In addition, since the transmittance and aperture ratio of the light emitting display panel are increased, the luminance of the light emitting display panel can be increased. Accordingly, even when the light emitting display panel is driven with low power consumption, luminance similar to that of the related art can be generated, and thus, light emission Power consumption of the display panel may be reduced.

In addition, since the pixel driving electrode PE may be provided in only one of the pixels constituting the unit pixel, the usable width of the design of the ratio of the aperture ratio between the pixels may be expanded. In addition, according to the present invention, the afterimage can be improved and the lifespan of the light emitting display panel can be improved because it can be driven with low power consumption.

The effect of the light emitting display panel shown in FIG. 10 described above is briefly summarized as follows.

First, transmittance and aperture ratio of the second pixel 110b for outputting green and the third pixel 110c for outputting blue may be increased, and thus device efficiency may be increased.

Second, the luminance of the light emitting display panel may be increased, and thus, power consumption of the light emitting display panel may be reduced.

Third, since the pixel driving electrode PE may be provided in only one pixel among at least three pixels constituting the unit pixel, the usable width of the design of the ratio of the aperture ratio between the pixels may be expanded. In addition, according to the present invention, the afterimage can be improved and the lifespan of the light emitting display panel can be improved because it can be driven with low power consumption.

Fourth, since the light emitting display panel according to the present invention can be patterned using an open mask, the present invention is advantageous for manufacturing a large area and ultra-high resolution light emitting display panel.

Fifth, according to the present invention, since the light emitting display panel can be driven with a voltage of one-stack level, power consumption can be reduced.

Sixth, according to the present invention, optimal characteristics can be secured for each pixel.

Those skilled in the art to which the present invention pertains will understand that the present invention may be embodied in other specific forms without changing the technical spirit or essential characteristics thereof. Therefore, it should be understood that the embodiments described above are illustrative in all respects and not restrictive. The scope of the present invention is indicated by the following claims rather than the above detailed description, and all changes or modifications derived from the meaning and scope of the claims and their equivalent concepts should be interpreted as being included in the scope of the present invention. do.

100: light emitting display panel 200: gate driver
300: data driver 400: control unit

Claims (25)

a protective layer covering the pixel driving circuits provided on the substrate;
a planarization layer provided on the passivation layer and planarizing top surfaces of the pixel driving circuits;
a connection electrode exposed from the passivation layer and the planarization layer in each of boundary regions between pixels;
a pixel driving electrode provided at a position corresponding to the light emitting region among the upper ends of the protective layer and connected to any one of the pixel driving circuits;
an undercut line provided at one side of an undercut region in which the connection electrode is exposed among the upper ends of the protective layer; and
A light emitting display panel comprising three light emitting layers and three common electrodes which are alternately disposed on the top of the pixel driving electrode or alternately disposed on the top of the flattening layer. The method of claim 1,
The undercut region is formed by the undercut line provided between the pixels, the connection electrode, and the protective layer. The method of claim 1,
a second undercut region is provided between the first pixel and the second pixel;
a third undercut region is provided between the second pixel and the third pixel;
The first undercut region is provided between the first pixel and another third pixel adjacent to the first pixel. The method of claim 1,
A light emitting display panel, wherein one side of at least one of the three light emitting layers and one side of at least one of the three common electrodes are provided in the undercut area. 5. The method of claim 4,
A light emitting display panel in which one side of the at least one light emitting layer and one side of the at least one common electrode are connected to a connection electrode exposed in the undercut region. 5. The method of claim 4,
A first light emitting layer and a second light emitting layer among the three light emitting layers and a first common electrode and a second common electrode among the three common electrodes are provided in the first undercut region;
The first light emitting layer and the first common electrode are provided in the second undercut region,
The light emitting display panel comprising the first light emitting layer and the second light emitting layer, and the first common electrode and the second common electrode in a third undercut region. 7. The method of claim 6,
the second undercut region is provided between the first pixel and the second pixel;
the third undercut region is provided between the second pixel and the third pixel;
The first undercut region is provided between the first pixel and another third pixel adjacent to the first pixel. 7. The method of claim 6,
The first common electrode provided on the upper end of the first light emitting layer and the second common electrode provided on the upper end of the second light emitting layer are connected to the first connection electrode exposed in the first undercut region;
the first common electrode is connected to a second connection electrode exposed in the second undercut region;
The first common electrode and the second common electrode are connected to a third connection electrode exposed in the third undercut region. The method of claim 1,
The three light emitting layers are provided in all of the first pixel, the second pixel, and the third pixel. 10. The method of claim 9,
A first light emitting layer and a second light emitting layer of the three light emitting layers are separated from each other between the first pixel and the second pixel, between the second pixel and the third pixel, and between the first pixel and another third pixel has been made,
A third emission layer among the three emission layers is continuously formed in the first pixel, the second pixel, and the third pixel. The method of claim 1,
a first common electrode among the three common electrodes is separated from each other in the first pixel, the second pixel, and the third pixel;
a second common electrode among the three common electrodes is connected to the first pixel and the second pixel and is separated from the third pixel;
A third common electrode among the three common electrodes is connected to the first pixel, the second pixel, and the third pixel. 12. The method of claim 11,
One side of the first common electrode is connected to a first connection electrode exposed in a first undercut region formed between the first pixel and another third pixel, and the other side is formed between the first pixel and the second pixel. provided at the upper end of the second undercut line,
One side of the second common electrode is connected to the first connection electrode, and the other side is provided at an upper end of a third undercut line formed between the second pixel and the third pixel,
and the third common electrode is connected to a common electrode line provided in a non-display area of the substrate. The method of claim 1,
Among the three light emitting layers, the first light emitting layer extends from the first undercut area to the upper end of the second undercut line provided in the second undercut area through the upper end of the first pixel driving electrode provided in the first pixel,
the first light emitting layer extends from the second undercut region to the upper end of the third undercut line provided in the third undercut region through the upper end of the second pixel driving electrode provided in the second pixel;
the first light emitting layer extends from the third undercut region through the upper end of the third pixel driving electrode provided in the third pixel to the upper end of the first undercut line provided in another first undercut region;
of the three common electrodes, a first common electrode extends from the first undercut region to an upper end of the second undercut line along a first light emitting layer;
the first common electrode extends from the second undercut region to an upper end of the third undercut line along the first emission layer provided in the second pixel;
The first common electrode extends from the third undercut area along the first light emitting layer provided in the third pixel to an upper end of another first undercut line provided in the another first undercut area. 14. The method of claim 13,
in each of the first to third undercut regions, the first light emitting layer is separated from each other, the second light emitting layer is separated from each other, and the third light emitting layer is connected to each other,
In each of the first to third undercut regions, the first common electrode CE1 is separated from each other. 14. The method of claim 13,
Among the three common electrodes, a second common electrode is provided in the first to third pixels from the first undercut region through the second undercut region and the third undercut region, and the first undercut region and a light emitting display panel separated from the third undercut region. 16. The method of claim 15,
Among the three common electrodes, a third common electrode is continuously provided in the first to third pixels from the first undercut region through the second undercut region and the third undercut region. The method of claim 1,
The pixel driving electrode is provided in each of the pixels,
A bank for dividing positions of the pixels surrounds a periphery of the pixel driving electrode and covers one side of the undercut line. 18. The method of claim 17,
The three light emitting layers and the three common electrodes are alternately disposed on top of the bank and the pixel driving electrode. 4. The method of claim 3,
a first pixel driving electrode provided in the first pixel is separated from a first connection electrode provided in the first undercut region;
a second pixel driving electrode provided in the second pixel is connected to a second connection electrode provided in the second undercut region;
A third pixel driving electrode provided in the third pixel is connected to a third connection electrode provided in the third undercut region. The method of claim 1,
The unit pixel includes a first pixel, a second pixel, and a third pixel adjacent to each other among the pixels,
The first pixel is provided with the pixel driving electrode,
A light emitting display panel in which a pixel driving electrode is not provided in the second pixel and the third pixel. 21. The method of claim 20,
A bank for dividing positions of the pixels surrounds a periphery of the pixel driving electrode provided in the first pixel and covers one side of the undercut line. 4. The method of claim 3,
a first pixel driving electrode provided in the first pixel is separated from a first connection electrode provided in the first undercut region;
The pixel driving circuit provided in the second pixel is connected to a second connection electrode provided in the second undercut region,
The pixel driving circuit provided in the third pixel is connected to a third connection electrode provided in the third undercut region. 23. The method of claim 22,
The three light emitting layers and the three common electrodes provided in the first pixel are alternately disposed on top of the first pixel driving electrode,
The three light emitting layers and the three common electrodes provided in the second pixel are alternately disposed on top of the planarization layer provided in the second pixel,
The three light emitting layers and the three common electrodes provided in the third pixel are alternately disposed on top of the flat layer provided in the third pixel. The method of claim 1,
The unit pixel includes a first pixel, a second pixel, and a third pixel adjacent to each other among the pixels,
One of the connection electrodes provided between the first pixel, the second pixel and the third pixel is connected to a shorting bar to which a common voltage is supplied. A light emitting display panel according to any one of claims 1 to 24;
a gate driver supplying gate signals to gate lines provided in the light emitting display panel;
a data driver supplying data voltages to data lines provided in the light emitting display panel; and
and a control unit controlling functions of the gate driver and the data driver.

Images