KR20210080171A - Zoned namespace with zone grouping - Google Patents

Abstract

An embodiment of an electronic device may include one or more substrates, and logic coupled to the one or more substrates, wherein the logic controls access to two or more persistent storage devices - at least one of the two or more persistent storage devices is logically organized into namespaces partitioned into two or more zones. The logic determines two or more different zone size dependent parameters associated with the two or more persistent storage devices, determines the smallest aligned boundary based on each of the two or more different zone size dependent parameters, and sets a zone group size for access to the two or more persistent storage devices based on the determined smallest aligned boundary. Other embodiments are disclosed and claimed.

Description

ZONED NAMESPACE WITH ZONE GROUPING

A conventional hard disk drive (HDD) may use a shingled magnetic recording (SMR) technology. A non-volatile memory (NVM) storage device, such as a NAND-based solid state drive (SSD), may use a flash transition layer (FTL) to manage NAND-based media. The NVM Express (NVMe) specification (NVMe 2.0 Base Specification, nvmexpress.org) provides for the use of Zoned Namespaces (ZNSs). The ZNS interface may require sequential writing of zones, and the SMR interface may support sequential required zones and sequential preferred zones.

The subject matter described herein is illustrated in the accompanying drawings by way of example and not limitation. For simplicity and clarity of illustration, elements illustrated in the drawings are not necessarily drawn to scale. For example, for clarity, the dimensions of some elements may be exaggerated relative to others. In addition, where deemed appropriate, reference labels have been repeated between the figures to indicate corresponding or similar elements. From the drawing:
1 is a block diagram of an example of an electronic system according to an embodiment;
2 is a block diagram of an example of an electronic device according to an embodiment;
3A-3C are flowcharts of examples of a method for controlling storage according to an embodiment;
4 is a block diagram of another example of a distributed electronic storage system according to an embodiment;
5 is an exemplary diagram of an example of a zoned namespace according to an embodiment;
6 is an exemplary diagram of an example of various size requirements and constraints in accordance with an embodiment;
7A and 7B are block diagrams of examples of zone groups according to an embodiment;
8 is a block diagram of an example of a computing system according to an embodiment;
9 is a block diagram of an example of an SSD according to an embodiment.

One or more embodiments or implementations are now described with reference to the accompanying drawings. While specific constructions and arrangements are discussed, it should be understood that this is done for illustrative purposes only. Those of ordinary skill in the art will recognize that other configurations and arrangements may be utilized without departing from the spirit and scope of this description. It will be apparent to those skilled in the art that the techniques and/or arrangements described herein may also be used in a variety of other systems and applications other than those described herein.

Although the following description describes various implementations that may appear in architectures, such as, for example, system-on-a-chip (SoC) architectures, implementations of the techniques and/or arrangements described herein are dependent on specific architectures and/or arrangements. or a computing system, and may be implemented by any architecture and/or computing system for similar purposes. For example, various architectures using multiple integrated circuit (IC) chips and/or packages, and/or various computing devices such as set-top boxes, smart phones, and/or consumer electronic (CE) devices, are described herein. and/or arrangement may be implemented. Furthermore, although the following description may set forth numerous specific details such as logic implementations, types and interrelationships of system components, logic partitioning/integration options, etc., claimed subject matter may be practiced without such specific details. In other instances, some content, such as, for example, control structures and entire software instruction sequences, may not be presented in detail in order not to obscure the subject matter disclosed herein.

The content disclosed herein may be implemented in hardware, firmware, software, or any combination thereof. The subject matter disclosed herein may also be implemented as instructions stored on a machine-readable medium, which may be read and executed by one or more processors. Machine-readable media may include any media and/or mechanism for storing or transmitting information in a form readable by a machine (eg, a computing device). For example, the machine-readable medium may include read only memory (ROM); random access memory (RAM); magnetic disk storage media; optical storage media; flash memory device; electrical, optical, acoustic or other forms of propagated signals (eg, carrier waves, infrared signals, digital signals, etc.) and others.

References herein to “one embodiment,” “an embodiment,” “an exemplary embodiment,” or the like, indicate that the described embodiment may include a particular feature, structure, or characteristic, but that all embodiments may not necessarily include the particular feature, structure, or characteristic. It indicates that it may not necessarily include the property. Moreover, such phrases are not necessarily referring to the same embodiment. Moreover, when a particular feature, structure, or characteristic is described in connection with an embodiment, the present technology refers to practicing that feature, structure, or characteristic in connection with another embodiment, whether or not explicitly described herein. It is believed to be known to one of ordinary skill in the art.

Various embodiments described herein may include memory components and/or interfaces to memory components. Such memory components may include volatile memory and/or non-volatile (NV) memory. Volatile memory may be a storage medium that requires power to maintain the state of data stored by the medium. Non-limiting examples of volatile memory may include various types of random access memory (RAM), such as dynamic RAM (DRAM) or static RAM (SRAM). One specific type of DRAM that may be used in memory modules is synchronous dynamic RAM (SDRAM). In certain embodiments, the DRAM of the memory component is: JESD79F for double data rate (DDR) SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for DDR4 SDRAM, Low Power (LPDDR) to the Joint Electron Device Engineering Council (JEDEC), such as JESD209 for DDR), JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4 (these standards are available at jedec.org). standards published by the Such standards (and similar standards) may be referred to as DDR-based standards, and communication interfaces of storage devices implementing such standards may be referred to as DDR-based interfaces.

NVM is a storage medium that does not require power to maintain the state of the data stored by the medium. In one embodiment, the memory device may comprise a block addressable memory device, such as based on NAND or NOR technology. Memory devices may also include future generations of non-volatile devices, such as three-dimensional (3D) crosspoint memory devices, or other byte addressable write-in-place non-volatile memory devices. In one embodiment, the memory device is chalcogenide glass, multi-threshold level NAND flash memory, NOR flash memory, single or multi-level phase change memory (PCM), resistive memory, nanowire memory, ferroelectric transistor RAM ( FeTRAM), antiferroelectric memory, magnetoresistive RAM (MRAM) memory with memristor technology, resistive and conductive bridge RAM (CB-RAM) with metal oxide base, oxygen vacancy base, or spin transfer torque (STT) -MRAM, spintronic magnetic junction memory based device, MTJ (magnetic tunneling junction) based device, DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, thyristor based memory device, or a combination of any of these, or other It may be or may include a memory device that uses memory. A memory device may refer to the die itself and/or to a packaged memory product. In certain embodiments, a memory component with non-volatile memory is configured such as JESD218, JESD219, JESD220-1, JESD223B, JESD223-1, or other suitable standard (the JEDEC standard cited herein is available at jedec.org). , can comply with one or more standards published by JEDEC.

Referring to FIG. 1 , an embodiment of an electronic system 10 may include a controller 11 , and logic 13 communicatively coupled to the controller 11 . According to some embodiments, logic 13 may be configured to control access to two or more persistent storage devices, wherein at least one of the two or more persistent storage devices includes a namespace partitioned into two or more zones (eg, For example, ZNS conforming to the NVMe specification). The logic 13 determines two or more different zone size dependent parameters associated with the two or more persistent storage devices, and determines a smallest aligned boundary based on each of the two or more different zone size dependent parameters, the determined and set the zone group size for access to the two or more persistent storage devices based on the minimum alignment boundary. For example, logic 13 determines a preferred region size for an application, determines a first erase block size for a first one of the two or more persistent storage devices, and determines a preferred region size and a first erase block size. may be configured to determine a minimum alignment boundary based on

In some embodiments, logic 13 determines a second erase block size for a second one of the two or more persistent storage devices, based on the preferred zone size, the first erase block size, and the second erase block size to determine the minimum alignment boundary. For example, the first storage device may include a first type of NAND media and the second storage device may include a second type of NAND media that is different from the first type of NAND media. In some embodiments, the logic 13 is further configured to determine a zone namespace sub-group capacity and to determine a minimum alignment boundary based on a preferred zone size, a first erase block size, and a zone namespace sub-group capacity. can be configured. In some embodiments, logic 13 additionally or alternatively determines a zone namespace zone capacity and determines a minimum alignment boundary based on a preferred zone size, a first erase block size, and a zone namespace zone capacity. can be configured to In any of the embodiments herein, the at least one persistent storage device may include an SSD (eg, a NAND-based SSD).

Each embodiment of the controller 11, persistent storage device, logic 13, and other system components may be implemented in hardware, software, or any suitable combination thereof. For example, a hardware implementation may include, for example, configurable logic such as a programmable logic array (PLA), a field programmable gate array (FPGA), a complex programmable logic device (CPLD), or, for example, an application specific (ASIC) integrated circuit), fixed function logic hardware using circuit technology such as complementary metal oxide semiconductor (CMOS) or transistor-transistor logic (TTL) technology, or any combination thereof. Embodiments of the controller 11 may include a general purpose controller, a special purpose controller, a memory controller, a storage controller, a microcontroller, a general purpose processor, a special purpose processor, a central processor unit (CPU), an execution unit, and the like. In some embodiments, persistent storage device(s), and/or logic 13 are located in or co-located with various components, including controller 11 (eg, on the same die) can do.

Alternatively or additionally, all or some of these components may be implemented by a processor or computing device on a machine or machine, such as random access memory (RAM), read only memory (ROM), programmable ROM (PROM), firmware, flash memory, or the like. It may be implemented in one or more modules as a set of logic instructions stored in a computer-readable storage medium. For example, computer program code for performing the operation of a component may be an object-oriented programming language such as PYTHON, PERL, JAVA, SMALLTALK, C++, C#, etc. and conventional procedural programming such as a "C" programming language or similar programming language. It may be written in any combination of programming languages applicable/suitable to one or more operating systems (OSs), including languages. For example, persistent storage device(s), other persistent storage media, or other system memory, when executed by controller 11 , cause system 10 to cause one or more components, features, or aspects of system 10 . (e.g., logic 13 determines two or more different zone size dependent parameters associated with the two or more persistent storage devices, and assigns to each of the two or more different zone size dependent parameters. determine a minimum alignment boundary based on the determined minimum alignment boundary, and set a zone group size for access to two or more persistent storage devices based on the determined minimum alignment boundary, etc.).

Referring now to FIG. 2 , an embodiment of an electronic device 15 may include one or more substrates 16 , and logic 17 coupled to the one or more substrates 16 . Logic 17 may be configured to control access to two or more persistent storage devices, wherein at least one of the two or more persistent storage devices is logically organized into a namespace partitioned into two or more zones. Logic 17 determines two or more different zone size dependent parameters associated with the two or more persistent storage devices, determines a minimum alignment boundary based on each of the two or more different zone size dependent parameters, and based on the determined minimum alignment boundary to set the zone group size for access to two or more persistent storage devices. For example, logic 17 determines a preferred region size for an application, determines a first erase block size for a first one of the two or more persistent storage devices, and determines a preferred region size and a first erase block size. may be configured to determine a minimum alignment boundary based on

In some embodiments, logic 17 determines a second erase block size for a second one of the two or more persistent storage devices, based on the preferred zone size, the first erase block size, and the second erase block size. to determine the minimum alignment boundary. For example, the first storage device may include a first type of NAND media and the second storage device may include a second type of NAND media that is different from the first type of NAND media. In some embodiments, logic 17 is further configured to determine a zone namespace sub-group capacity and to determine a minimum alignment boundary based on a preferred zone size, a first erase block size, and a zone namespace sub-group capacity. can be configured. In some embodiments, logic 17 additionally or alternatively determines a zone namespace zone capacity and determines a minimum alignment boundary based on a preferred zone size, a first erase block size, and a zone namespace zone capacity. can be configured to In any of the embodiments herein, the at least one persistent storage device may include an SSD (eg, a NAND-based SSD).

Embodiments of logic 17 may be implemented in, for example, a system, apparatus, computer, device, etc., as described herein. More specifically, the hardware implementation of logic 17 may be a configurable logic such as, for example, PLA, FPGA, CPLD, or fixed using circuit technology such as, for example, ASIC, CMOS, or TTL technology. functional logic hardware, or any combination thereof. Alternatively or additionally, logic 17 may be implemented in one or more modules as a set of logic instructions stored in a machine or computer readable storage medium such as RAM, ROM, PROM, firmware, flash memory, etc. to be executed by a processor or computing device. can be For example, computer program code for performing the operation of a component may be an object-oriented programming language such as PYTHON, PERL, JAVA, SMALLTALK, C++, C#, etc. and conventional procedural programming such as a "C" programming language or similar programming language. It may be written in any combination of programming languages applicable/suitable to one or more OSs, including languages.

For example, logic 17 may be implemented on a semiconductor device that may include one or more substrates 16 , and logic 17 is coupled to one or more substrates 16 . In some embodiments, logic 17 may be implemented at least in part in one or more of configurable logic and fixed function hardware logic on a semiconductor substrate(s) (eg, silicon, sapphire, gallium-arsenide, etc.). For example, logic 17 may include a transistor array and/or other integrated circuit component coupled to substrate(s) 16 having a transistor channel region disposed within substrate(s) 16 . The interface between logic 17 and substrate(s) 16 may not be an abrupt junction. Logic 17 may also be considered to include an epitaxial layer grown on the initial wafer of substrate(s) 16 .

Referring now to FIGS. 3A-3C , an embodiment of a method 20 for controlling storage includes, in block 21 , controlling access to two or more persistent storage devices, wherein at least one of the two or more persistent storage devices comprises: logically organized into a namespace partitioned into two or more zones, determining in block 22 two or more different zone size dependent parameters associated with the two or more persistent storage devices; determining a minimum alignment boundary based on each of the zone size dependent parameters, and setting a zone group size for access to the two or more persistent storage devices based on the minimum alignment boundary determined in block 24 . can For example, the method 20 may include determining a preferred zone size for an application at block 25 , and determining a first erase block size for a first one of the two or more persistent storage devices at block 26 . and determining a minimum alignment boundary at block 27 based on the preferred region size and the first erase block size.

Some embodiments of method 20 include determining, at block 28 , a second erase block size for a second one of the two or more persistent storage devices, and at block 29 , a preferred zone size, a first erase. The method may further include determining a minimum alignment boundary based on the block size and the second erase block size. For example, at block 30 the first storage device may include a first type of NAND media, and the second storage device may include a second type of NAND media that is different from the first type of NAND media. . Some embodiments of method 20 include determining, at block 31 , a zone namespace sub-group capacity, and at block 32 , a preferred zone size, a first erase block size, and a zone namespace sub-group capacity. The method may further include determining a minimum alignment boundary based on . The method 20 additionally or alternatively includes determining, at block 33, a zone namespace zone capacity, and at block 34, a preferred zone size, a first erase block size, and a zone namespace zone capacity. determining a minimum alignment boundary based on the In any of the embodiments herein, the at least one persistent storage device at block 35 may include an SSD.

Embodiments of method 20 may be implemented in, for example, a system, apparatus, computer, device, etc., as described herein. More specifically, the hardware implementation of method 20 may be fixed using configurable logic, such as, for example, PLA, FPGA, CPLD, or circuit technology, such as, for example, ASIC, CMOS, or TTL technology. functional logic hardware, or any combination thereof. Alternatively or additionally, method 20 may be implemented in one or more modules as a set of logic instructions stored in a machine or computer readable storage medium such as RAM, ROM, PROM, firmware, flash memory, etc. to be executed by a processor or computing device. can be For example, computer program code for performing the operation of a component may be an object-oriented programming language such as PYTHON, PERL, JAVA, SMALLTALK, C++, C#, etc. and conventional procedural programming such as a "C" programming language or similar programming language. It may be written in any combination of programming languages applicable/suitable to one or more OSs, including languages.

For example, method 20 may be implemented on a computer-readable medium as described in connection with Examples 22-28 below. Embodiments or portions of method 20 may be implemented in firmware, an application (eg, via an application programming interface (API)), or driver software running on an operating system (OS). Additionally, logic instructions may include assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, state setting data, configuration data for integrated circuits, state information that personalizes electronic circuits, and/or hardware It may include other architectural components specific to (eg, host processor, central processing unit/CPU, microcontroller, etc.).

4 , an embodiment of a distributed electronic storage system 40 may include one or more host devices 42 communicatively coupled to two or more persistent storage devices 44 . For example, one or more of persistent storage devices 44 may include an HDD, one or more of persistent storage devices 44 may include an SSD, and one or more of persistent storage devices 44 . may include a flash memory device and the like. For example, storage device 44 may include different types of NAND-based media including single level cell (SLC), multi-level cell (MLC), triple level cell (TLC), quad level cell (QLC), and the like. can One or more of the storage devices 44 may support ZNS technology compliant with the NVMe specification.

Each of host devices 42 and storage devices 44 may include controller logic 46 . According to some embodiments, controller logic 46 may be configured to control access to storage devices 44 , including at least one storage device 44 supporting ZNS technology. The controller logic 46 determines two or more different region size dependent parameters associated with the storage devices 44 , determines a minimum alignment boundary based on each of the two or more different region size dependent parameters, and determines the minimum alignment boundary at the determined minimum alignment boundary. It may be further configured to set a zone group size for access to storage devices 44 based on it. For example, controller logic 46 determines a preferred zone size for an application on one of host devices 42 , determines a first erase block size for a first one of storage devices 44 , and , determine the minimum alignment boundary based on the preferred region size and the first erase block size.

In some embodiments, the controller logic 46 determines a second erase block size for a second one of the storage devices 44 and is based on the preferred zone size, the first erase block size, and the second erase block size. and determine a minimum alignment boundary based on the For example, a first storage device may include a first type of NAND medium (eg, TLC) and a second storage device may include a second type of NAND medium (eg, QLC) have. In some embodiments, the controller logic 46 may be further configured to determine a ZNS sub-group capacity and to determine a minimum alignment boundary based on a preferred zone size, a first erase block size, and a ZNS sub-group capacity. have. In some embodiments, the controller logic 46 may additionally or alternatively be configured to determine a ZNS zone capacity and to determine a minimum alignment boundary based on a preferred zone size, a first erase block size, and a ZNS zone capacity. can As illustrated in FIG. 4 , various aspects of controller logic 46 may be distributed among host devices 42 and storage devices 44 .

Each embodiment of the host devices 42 , storage devices 44 , controller logic 46 , and other system components may be implemented in hardware, software, or any suitable combination thereof. For example, the hardware implementation may include, for example, configurable logic such as PLA, FPGA, CPLD, or fixed function logic hardware using, for example, circuit technology such as ASIC, CMOS, or TTL technology, or these may include any combination of Embodiments of controller logic 46 may be included in general purpose controllers, special purpose controllers, memory controllers, storage controllers, microcontrollers, general purpose processors, special purpose processors, central processor units (CPUs), execution units, and the like.

Alternatively or additionally, all or part of these components may be one or more modules as a set of logic instructions stored in a machine or computer readable storage medium such as RAM, ROM, PROM, firmware, flash memory, etc. to be executed by a processor or computing device. can be implemented in For example, computer program code for performing the operation of a component may be an object-oriented programming language such as PYTHON, PERL, JAVA, SMALLTALK, C++, C#, etc. and conventional procedural programming such as a "C" programming language or similar programming language. It may be written in any combination of programming languages applicable/suitable to one or more OSs, including languages.

Referring to FIG. 5 , an embodiment of a zoned namespace 50 may include a namespace scope partitioned into zones including zone N, zone N+1, zone N+2, etc., where N>0 to be. Each zone has a range of logical block addresses (LBA) starting from zone start logical block address (ZSLBA) to ZMAX, where ZMAX = ZSLBA + ZSIZE (size of zone). As described in the NVMe 2.0 Base Specification, ZNS technology may utilize zones that have one or more of the following requirements: Zones create fixed-size LBA partitions in a namespace; Zones support sequential write access and random read access; Zone data is not logically moved by the device (eg, physical location may change due to media management such as wear leveling, etc.); Zones must be explicitly reset to enable overwrite; and/or zones only support an integer number of LBAs, thus multiples of zone size in write/data. Some embodiments advantageously provide one or more additional functional capabilities to the zoned namespace.

Some embodiments may advantageously provide techniques for grouping zones to improve or optimize platform and SSD parameters. For example, by reducing the cost gap with QLC technology and HDDs, high-capacity storage in hyperscalers can make better use of SSDs. ZNS technology can solve a variety of NAND issues to enable the transition from HDD to SSD for high-capacity storage. For example, the HDD is a zoned block device (ZBD) interface based on SMR (eg, a zone block command (ZBC) and/or a zoned-device ATA command , ZAC)) can be used in a conventional manner. Existing ZBC/ZAC large-scale infrastructure can be utilized for efficient ZNS data management using QLC capabilities in a cost-effective manner. To achieve these cost and efficiency improvements, ZNS enables sequential data access where SSDs define LBAs on behalf of the host. Zones can be globally written and erased, thus eliminating the need for defragmentation as well as reducing internal data movement. The cost savings achieved with ZNS can be passed on to users, including reduced NAND costs as well as reduced DRAM and improved device durability to extend SSD lifespan.

However, there are various problems in using the conventional ZNS technology to replace the HDD with the SSD. For example, one problem is that the SMR ecosystem does not have any zone size constraints because SMR zones can be configured with any required capacity. Conventionally, the area capacity on flash devices supporting ZNS is constrained by "NAND Physical Erase Block Size". Platform or system level algorithms implement erasure coding to protect data. Because one erasure coded data blob cannot be split into multiple blobs, erasure coding granularity drives the regional capacity requirements. This means that the flash based zone capacity needs to be a multiple of the erase coding blob size. Each erase block capacity may be different for different NAND types (eg, TLC, QLC, etc.), including the number of pages per erase block and the number of planes per sub-block. These platform-level requirements, cross-platform SMR-level implementations, and NAND ability to configure the required zone size pose challenges for hyperscalers to generalize software and ZNS implementations. This problem is magnified as many NAND SSD vendors use erase block sizes with different capacities.

Referring to FIG. 6 , an exemplary diagram of various size requirements and constraints shows how different sizes can create difficult situations for application software implementation. For example, a particular software application or storage need may have a preferred or optimal zone size, which may or may not map well to the erase coding size deployed in the storage system, various erase block sizes for different types of NAND, etc. have. This problem can be particularly difficult to overcome when applying ZNS to standard block-based SSDs that are interchangeable across vendors, NAND types, and capacities. Advantageously, as described in more detail below, some embodiments may provide a zone grouping technique to overcome this problem.

Another problem is that low-cost hyperscalers may prefer the smallest feasible area capacity to achieve better performance. The small area size adds significant overhead for metadata (eg, which may exceed actual implementation capabilities), DRAM space requirements, and large log page sizes. For example, for a 32 TB drive, the log page defining the zone information is 32 MB in size and transferring all the information over the PCIe bus can take more than 10 ms. With command latency of hundreds of microseconds, the overall latency and overhead to manage a zone may not be acceptable for many applications. Advantageously, as described in more detail below, some embodiments may provide a zone grouping technique to overcome this problem.

Another problem is that if the expected region size and the NAND physical block size do not align, the region reset command cannot invalidate all data on the physical block. This results in unexpected write amplification that can reduce revenue in terms of cost and durability. Another problem is that if the region size is not aligned with the erase block size, some extra physical space is not used, thereby wasting a percentage of the NAND capacity for each region. As described in more detail below, some embodiments advantageously provide zone grouping techniques to overcome one or more of these problems.

Some embodiments advantageously provide zone grouping techniques for clustering zones on aligned boundaries that combine all or most important boundaries. For example, a host may create a zone group that facilitates including all desired variables within a single zone group. For example, NAND capacity is usually tailored to some binary capacity. Some embodiments provide that (1) data transmission and storage within zone group boundaries is seamless; (2) any internal variables such as NAND block size are hidden within the zone group; and/or (3) within each zone group, create zone groups based on NAND capacity in such a way that each zone follows the same rules defined in the NVMe standard. Advantageously, all the host does is define a group of zones for any working combination used by the host.

Tables 1-3 show different examples of zone grouping according to some embodiments. Table 1 shows an example of a first zone group with a NAND erase block size of 72 MB. Table 2 shows an example of a second zone group with a NAND erase block size of 96 MB. Table 3 shows an example of a third zone group with a NAND erase block size of 32 MB.

According to some embodiments, the zone grouping method may include finding a minimum alignment boundary of all zone size dependent parameters. For the first zone group, the zone group capacity may be 4608 MB for the SMR zone, which includes four (four) ZNS subgroups. For example, each ZNS subgroup may contain 9 zones as defined in the NVMe standard, where the ZNS zone size is 128 MB. Advantageously, the zones are constant across all variables, which facilitates seamless data transfer across zone group boundaries. For example, such seamless data transmission may be in the same zone group size as the basic unit of one ZNS zone capacity or within a different zone group size, constant across all zone groups 1 to 3 in the exemplary Tables 1-3. can be performed in

For purposes of illustration and not limitation, in another example, a hyperscaler data center provider has two geographically dispersed data center locations (eg, one in Europe and one in the United States). The data center stores data in SMR HDD and ZNS SSD based on data hotness. Depending on availability, data is transferred between the SMR zone and the SSD zone. Data is also transferred between two geographically dispersed data center locations during outages and during replication.

In this example, a data center location in the United States uses a NAND flash device with a block size of 32 MB and a data center location in Europe has an SSD with a block size of 96 MB. A consistent erasure coding algorithm may require an exemplary 128 MB region size. Conventional ZNS technology may not support a consistent erasure coding algorithm for both data center locations because different types of NAND have different block sizes. Conventionally, regions where flash block sizes are not aligned can increase write amplification, reducing many or all of the benefits provided by ZNS technology. Advantageously, embodiments of zone grouping techniques may enable different types of NAND technology to support 128 MB zone sizes and enable each data center location to use a consistent erasure coding algorithm. For example, when an SMR subgroup of 1536 MB is created as shown in the last two tables on the previous page, a zoned SSD in a European data center location may appear to the data center application software like a standard block device SSD. Using this group boundary, both NAND types can contain 12 zones with 128 MB capacity, enabling data transfer at 1536 MB granularity across data centers, across SMR zones and SSD zones. For example, a host can open one subgroup containing 12 ZNS zones with 128 MB capacity. All zones can then be written in parallel and, depending on the data lifetime, all zones within a zone group can be erased or sent to SMR zones simultaneously.

In the example below, the ZNS zone capacity may be 96 MB, and the following equation may be used to determine the various zone groups and sizes:

[Equation 1]

SMR zone size = n * NAND flash erase blocks

= m * ZNS zone capacity

7A and 7B , an embodiment of a zone group 70 is a multiple of the ZNS zone capacity (eg, m = 4) (eg, 4 * 96 MB = 384 MB) and also NAND flash erase It may include an SMR zone size that is any multiple of the block capacity (eg, for EB = 64 MB, n = 6 * 64 = 384 MB). The ZNS zone fits the SMR zone size as defined on the right side of equation (1). Advantageously, suitable zone groups created according to embodiments of zone grouping techniques described herein span any underlying hardware, including HDDs with SMR zones and/or SSDs with any block size and technology. may be transplantable. Some embodiments may advantageously allow for scalability and generalization, making zones more usable across a wide variety of platforms and applications. In other implementations, embodiments of the zone group technique may be used to align an SMR zone to an SSD zone, as well as align an SSD zone of one type of NAND to another type of NAND.

The techniques discussed herein can be applied to a variety of computing systems (eg, non-mobile computing devices such as desktops, workstations, servers, rack systems, etc., smartphones, tablets, Ultra-Mobile Personal Computers (UMPCs), laptop computers, ultra to be provided in mobile computing devices such as book computing devices, smart watches, smart glasses, smart bracelets, etc., and/or client/edge devices such as Internet of Things (IoT) devices (eg, sensors, cameras, etc.) can

Referring now to FIG. 8 , an embodiment of a computing system 100 is one or more processors 102-1 through 102-N (generally referred to herein as “processors 102” or “processor 102”). ) may be included. Processors 102 may communicate via an interconnection or bus 104 . Each processor 102 may include various components, some of which are discussed with reference to processor 102-1 for clarity. Accordingly, each of the remaining processors 102 - 2 through 102 -N may include the same or similar components discussed with reference to the processor 102-1 .

In some embodiments, processor 102-1 includes one or more processor cores 106-1 through 106-M (referred to herein as “cores 106” or more generally “core 106”). , a cache 108 (which may be a shared cache or a private cache in various embodiments), and/or a router 110 . The processor cores 106 may be implemented on a single integrated circuit (IC) chip. Moreover, the chip may include one or more shared and/or dedicated caches (eg, cache 108 ), a bus or interconnect (eg, bus or interconnect 112 ), logic 160 , a memory controller, or other components. can do.

In some embodiments, router 110 may be used to communicate between processor 102-1 and/or various components of system 100 . Moreover, the processor 102-1 may include more than one router 110 . Moreover, multiple routers 110 may communicate to facilitate data routing between various components inside or outside the processor 102-1.

Cache 108 may store data (eg, including instructions) used by one or more components of processor 102-1, such as cores 106 . For example, cache 108 may locally cache data stored in memory 114 for faster access by components of processor 102 . 8 , memory 114 may communicate with processors 102 via interconnect 104 . In some embodiments, cache 108 (which may be shared) may have various levels, for example, cache 108 may be a mid-level cache and/or a last-level cache. level cache, LLC). Additionally, each of the cores 106 may include a level 1 (L1) cache 116 - 1 (generally referred to herein as “L1 cache 116 ”). The various components of the processor 102-1 may communicate with the cache 108 directly, via a bus (eg, bus 112), and/or through a memory controller or hub.

8 , memory 114 may be coupled to other components of system 100 via memory controller 120 . Memory 114 may include volatile memory and may be referred to interchangeably as main memory. Although memory controller 120 is shown coupled between interconnect 104 and memory 114 , memory controller 120 may be located elsewhere in system 100 . For example, memory controller 120 or a portion thereof may be provided within one of processors 102 in some embodiments.

System 100 may communicate with other devices/systems/networks via network interface 128 (eg, communicates with computer networks and/or cloud 129 via wired or wireless interfaces). For example, network interface 128 includes network/cloud 129 and wireless (eg, Institute of Electrical and Electronics Engineers (IEEE) 802.11 interfaces (IEEE 802.11a/b/g/n/ac, etc.) ), and an antenna (not shown) for communicating via a cellular interface, 3G, 4G, LTE, Bluetooth, etc.).

System 100 may also include a storage device, such as SSD device 130 , coupled to interconnect 104 via SSD controller logic 125 . Accordingly, logic 125 may control access by various components of system 100 to SSD device 130 . Moreover, although logic 125 is shown coupled directly to interconnect 104 in FIG. 8 , logic 125 may alternatively be a storage bus/interconnect (eg, a Serial Advanced Technology Attachment (SATA) bus). , may communicate with one or more other components of system 100 via a Peripheral Component Interconnect (PCI) (or PCI EXPRESS interface (PCIe), NVM EXPRESS (NVMe), etc.) , when coupled to interconnect 104 via some other logic such as a chipset, etc.). Additionally, logic 125 may be integrated into memory controller logic (eg, discussed with reference to FIG. 9 ) or on the same integrated circuit (IC) device in various embodiments (eg, SSD device 130 ) ) on the same circuit board device or in the same enclosure as the SSD device 130 ).

In addition, logic 125 and/or SSD device 130 receives information (eg, in the form of one or more bits or signals) indicative of the status of or values detected by one or more sensors (not shown). It may be coupled to one or more sensors to These sensor(s) may be used to detect variations in various factors affecting the power/thermal behavior of the system/platform, such as temperature, operating frequency, operating voltage, power consumption, and/or inter-core communication activity, etc. System 100 (including 106 , interconnects 104 or 112 , components external to processor 102 , SSD device 130 , SSD bus, SATA bus, logic 125 , logic 160 , etc.) or other computing systems discussed herein).

9 illustrates a block diagram of various components of SSD device 130 , in accordance with an embodiment. As illustrated in FIG. 9 , logic 160 may be located in various locations, such as within SSD device 130 or controller 382 , etc., including techniques similar to those discussed with respect to FIG. 8 . can do. SSD device 130 includes controller 382 (controller 382 in turn includes one or more processor cores or processors 384 and memory controller logic 386), cache 138, RAM 388, firmware storage. 390, and one or more memory devices 392-1 through 392-N (collectively referred to as memory 392, which may include NAND flash, NOR flash, or other types of non-volatile memory); do. Memory 392 is coupled to memory controller logic 386 via one or more memory channels or buses. SSD device 130 also communicates with logic 125 via an interface (eg, SATA, SAS, PCIe, NVMe interface, etc.). One or more of the features/aspects/acts discussed with reference to FIGS. 1-7B may be performed by one or more of the components of FIGS. 8 and/or 9 . Processor 384 and/or controller 382 may compress/decompress (or otherwise cause compression/decompression thereof) data written to or read from memory devices 392-1 through 392-N. have. Additionally, one or more of the features/aspects/acts of FIGS. 1-7B may be programmed into firmware 390 . In addition, SSD controller logic 125 may also include logic 160 .

8 and 9 , the SSD device 130 may be in the same enclosure as the SSD device 130 and/or be fully integrated on a printed circuit board (PCB) of the SSD device 130 . , which may include logic 160 . System 100 may include additional logic 160 external to SSD device 130 . Advantageously, logic 160 includes system 10 , apparatus 15 , method 20 ( FIGS. 3A-3C ), system 40 ( FIG. 4 ), zoned namespace 50 ( FIG. 5 ). ), one or more aspects of zone group 70 ( FIGS. 7A and 7B ), and/or techniques for implementing any of the features discussed herein. For example, logic 160 may include techniques for implementing host device/computer system/agent aspects of the various embodiments described herein (eg, requesting information from SSD device 130 , sending information to an SSD). transmitting to device 130 , creating zone groups, etc.) and also techniques for implementing NVMe ZNS technology and logically organizing SSD device 130 into namespaces divided into two or more zones. can The logic 160 determines two or more different zone size dependent parameters associated with the two or more storage devices (eg, including the SSD device 130 ) and based on each of the two or more different zone size dependent parameters. determine a minimum alignment boundary, and set a zone group size for access to the storage devices based on the determined minimum alignment boundary. For example, logic 160 determines a preferred region size for an application on one of processors 102 , determines a first erase block size for a first one of the storage devices, and determines a preferred region size and and determine a minimum alignment boundary based on the first erase block size.

In some embodiments, logic 160 determines a second erase block size for a second one of the storage devices, and determines the minimum alignment based on the preferred region size, the first erase block size, and the second erase block size. may be configured to determine boundaries. For example, a first storage device may include a first type of NAND medium (eg, TLC) and a second storage device may include a second type of NAND medium (eg, QLC) have. In some embodiments, logic 160 may be further configured to determine a ZNS sub-group capacity and to determine a minimum alignment boundary based on a preferred zone size, a first erase block size, and a ZNS sub-group capacity. . In some embodiments, logic 160 may additionally or alternatively be configured to determine a ZNS zone capacity and to determine a minimum alignment boundary based on a preferred zone size, a first erase block size, and a ZNS zone capacity. have.

In other embodiments, SSD device 130 may be replaced with any suitable storage/memory technology/media. In some embodiments, logic 160 may be coupled to one or more substrates (eg, silicon, sapphire, gallium arsenide, printed circuit board (PCB), etc.) may include In other embodiments, SSD device 130 may include two or more types of storage media. For example, most of the storage may be NAND and may further include some faster, smaller granularity accessible (eg byte addressable) NVMs such as INTEL 3DXP media. SSD device 130 may alternatively or additionally include permanent volatile memory (eg, battery or capacitor backup DRAM or SRAM). For example, SSD device 130 may include POWER LOSS IMMINENT (PLI) technology with energy storage capacitors. The energy storage capacitor may provide sufficient energy (power) to complete any command in progress and cause any data in the DRAM/SRAM to be committed to the non-volatile NAND medium. The capacitor may serve as a backup battery for permanent volatile memory. As shown in FIG. 8 , features or aspects of logic 160 may be distributed throughout system 100 and/or coexist/integrate with various components of system 100 .

Additional remarks and examples

Example 1 includes an electronic apparatus, the electronic apparatus comprising one or more substrates, and logic coupled to the one or more substrates, the logic controlling access to the two or more persistent storage devices, and the two or more persistent storage devices. at least one of which is logically organized into a namespace partitioned into two or more zones, determining two or more different zone size dependent parameters associated with the two or more persistent storage devices, based on each of the two or more different zone size dependent parameters to determine a minimum alignment boundary, and set a zone group size for access to two or more persistent storage devices based on the determined minimum alignment boundary.

Example 2 includes the apparatus of example 1, wherein the logic further determines a preferred zone size for the application, determines a first erase block size for a first one of the two or more persistent storage devices, A minimum alignment boundary is determined based on the size and the first erase block size.

Example 3 includes the apparatus of example 2, wherein the logic further determines a second erase block size for a second one of the two or more persistent storage devices, a preferred zone size, a first erase block size, and a second erase block size. 2 Determine the minimum alignment boundary based on the erase block size.

Example 4 includes the apparatus of example 3, wherein the first storage device includes a first type of NAND medium, and the second storage device includes a second type of NAND medium that is different from the first type of NAND medium.

Example 5 includes the apparatus of any one of Examples 2-4, wherein the logic further determines a zone namespace sub-group capacity, a preferred zone size, a first erase block size, and a zone namespace sub-group Determine the minimum alignment boundary based on the capacity.

Example 6 includes the apparatus of any one of Examples 2-5, wherein the logic further determines a zone namespace zone capacity, based on the preferred zone size, the first erase block size, and the zone namespace zone capacity. Determines the minimum alignment boundary.

Example 7 includes the apparatus of any one of Examples 1-6, wherein the at least one persistent storage device comprises a solid state drive.

Example 8 includes an electronic system comprising a controller, and logic communicatively coupled to the controller, the logic to: control access to the two or more persistent storage devices - the two or more persistent storage devices at least one of which is logically organized into a namespace partitioned into two or more zones, determining two or more different zone size dependent parameters associated with the two or more persistent storage devices, based on each of the two or more different zone size dependent parameters to determine a minimum alignment boundary, and set a zone group size for access to two or more persistent storage devices based on the determined minimum alignment boundary.

Example 9 includes the system of example 8, wherein the logic is further to determine a preferred zone size for the application, to determine a first erase block size for a first of the two or more persistent storage devices, and to determine a preferred zone size for a first one of the two or more persistent storage devices. A minimum alignment boundary is determined based on the size and the first erase block size.

Example 10 includes the system of example 9, wherein the logic further determines a second erase block size for a second one of the two or more persistent storage devices, the preferred zone size, the first erase block size, and the second erase block size. 2 Determine the minimum alignment boundary based on the erase block size.

Example 11 includes the system of example 10, wherein the first storage device includes a first type of NAND medium, and the second storage device includes a second type of NAND medium that is different from the first type of NAND medium.

Example 12 includes the system of any one of Examples 9-11, wherein the logic further determines a zone namespace sub-group capacity, a preferred zone size, a first erase block size, and a zone namespace sub-group Determine the minimum alignment boundary based on the capacity.

Example 13 includes the system of any one of Examples 9-12, wherein the logic further determines a zone namespace zone capacity, based on the preferred zone size, the first erase block size, and the zone namespace zone capacity. Determines the minimum alignment boundary.

Example 14 includes the system of any one of Examples 8-13, wherein the at least one persistent storage device comprises a solid state drive.

Example 15 includes a method of controlling storage, the method comprising controlling access to two or more persistent storage devices, wherein at least one of the two or more persistent storage devices is logically divided into two or more zoned namespaces. comprising: determining at least two different zone size dependent parameters associated with the at least two persistent storage devices, determining a minimum alignment boundary based on each of the at least two different zone size dependent parameters, and the determined minimum alignment boundary and setting a zone group size for access to two or more persistent storage devices based on the

Example 16 includes the method of Example 15, comprising determining a preferred zone size for an application, determining a first erase block size for a first one of the two or more persistent storage devices, and a preferred zone size and The method further includes determining a minimum alignment boundary based on the first erase block size.

Example 17 includes the method of Example 16, determining a second erase block size for a second one of the two or more persistent storage devices, and a preferred zone size, a first erase block size, and a second erase block size. The method further includes determining a minimum alignment boundary based on the size.

Example 18 includes the method of Example 17, wherein the first storage device includes a first type of NAND medium, and the second storage device includes a second type of NAND medium that is different from the first type of NAND medium.

Example 19 includes the method of any one of Examples 16-18, comprising determining a zone namespace sub-group capacity, and based on a preferred zone size, a first erase block size, and a zone namespace sub-group capacity. to determine a minimum alignment boundary.

Example 20 includes the method of any one of Examples 16-19, comprising determining a zone namespace zone capacity, and a minimum alignment boundary based on a preferred zone size, a first erase block size, and a zone namespace zone capacity. It further comprises the step of determining.

Example 21 includes the method of any one of Examples 15-20, wherein the at least one persistent storage device comprises a solid state drive.

Example 22, in response to being executed on the computing device, causes the computing device to control access to the two or more persistent storage devices, wherein at least one of the two or more persistent storage devices is partitioned into a namespace divided into two or more zones. logically configured, cause to determine two or more different zone size dependent parameters associated with the two or more persistent storage devices, to determine a minimum alignment boundary based on each of the two or more different zone size dependent parameters, and to cause the determined minimum alignment boundary to be determined. and at least one non-transitory machine-readable medium comprising a plurality of instructions to set a zone group size for access to the two or more persistent storage devices based on the

Example 23 includes the at least one non-transitory machine-readable medium of Example 22, and in response to being executed on the computing device, cause the computing device to determine a preferred zone size for the application, one of the two or more persistent storage devices and a plurality of additional instructions to cause determining a first erase block size for the first storage device and to determine a minimum alignment boundary based on the preferred region size and the first erase block size.

Example 24 includes the at least one non-transitory machine-readable medium of Example 23, and in response to being executed on the computing device, causes the computing device to cause a second erase block size for a second one of the two or more persistent storage devices. and determine a minimum alignment boundary based on the preferred region size, the first erase block size, and the second erase block size.

Example 25 includes the at least one non-transitory machine-readable medium of Example 24, wherein the first storage device includes a first type of NAND medium, and wherein the second storage device is a second different than the first type of NAND medium. tangible NAND media.

Example 26 includes the at least one non-transitory machine-readable medium of any one of Examples 23-25, wherein in response to being executed on the computing device, cause the computing device to determine a zone namespace sub-group capacity; and a plurality of additional instructions to cause determining a minimum alignment boundary based on a preferred zone size, a first erase block size, and a zone namespace sub-group capacity.

Example 27 includes the at least one non-transitory machine readable medium of any one of Examples 23-26, and in response to being executed on a computing device, cause the computing device to determine a zone namespace zone capacity, and to: and a plurality of additional instructions to cause determining a minimum alignment boundary based on the size, the first erase block size, and the zone namespace zone capacity.

Example 28 includes the at least one non-transitory machine readable medium of any of Examples 22-27, wherein the at least one persistent storage device comprises a solid state drive.

Example 29 includes a storage controller apparatus, means for controlling access to two or more persistent storage devices, wherein at least one of the two or more persistent storage devices is logically configured into a namespace partitioned into two or more zones; means for determining two or more different zone size dependent parameters associated with the two or more persistent storage devices, means for determining a minimum alignment boundary based on each of the two or more different zone size dependent parameters, and based on the determined minimum alignment boundary and means for setting a zone group size for access to the two or more persistent storage devices.

Example 30 includes the apparatus of example 29, comprising means for determining a preferred zone size for an application, means for determining a first erase block size for a first of the two or more persistent storage devices, and a preferred zone Further comprising means for determining a minimum alignment boundary based on the size and the first erase block size.

Example 31 includes the apparatus of example 30, means for determining a second erase block size for a second one of the two or more persistent storage devices, and a preferred zone size, a first erase block size, and a second erase It further includes means for determining a minimum alignment boundary based on the block size.

Example 32 includes the apparatus of example 31, wherein the first storage device includes a first type of NAND medium, and the second storage device includes a second type of NAND medium that is different from the first type of NAND medium.

Example 33 includes the apparatus of any one of Examples 30-32, wherein the means for determining a zone namespace sub-group capacity, and a preferred zone size, a first erase block size, and a zone namespace sub-group capacity Further comprising means for determining a minimum alignment boundary based on the.

Example 34 includes the apparatus of any one of Examples 30-33, to determine a zone namespace zone capacity, and to determine a minimum alignment boundary based on a preferred zone size, a first erase block size, and a zone namespace zone capacity. It further includes means for

Example 35 includes the apparatus of any one of Examples 29-34, wherein the at least one persistent storage device comprises a solid state drive.

The term “coupled” may be used herein to refer to any type of relationship, direct or indirect, between the components in question, and is an electrical, mechanical, fluid, optical, electromagnetic, electromechanical or other connection. can be applied to In addition, the terms “first”, “second”, etc. may be used herein only to facilitate discussion, and have no specific temporal or chronological meaning unless otherwise noted.

As used in this application and in the claims, a list of items joined by the term “one or more of” may mean any combination of the listed terms. For example, the phrases “at least one of A, B, and C” and the phrase “at least one of A, B, or C” are both A; B; C; A and B; A and C; B and C; or A, B, and C. The various components of the systems described herein may be implemented in software, firmware and/or hardware and/or any combination thereof. For example, various components of a system or device discussed herein may be provided, at least in part, by hardware of a computing SoC, such as may be found in, for example, a computing system such as a smart phone. Those of ordinary skill in the art may recognize that the systems described herein may include additional components not depicted in the corresponding figures. For example, the systems discussed herein may include additional components, such as bit stream multiplexers or demultiplexer modules, which are not depicted for clarity.

Although implementation of the example processes discussed herein may include performing all of the acts presented in the order illustrated, the disclosure is not limited in this respect, and in various instances, implementation of the example processes herein may include: Only a subset of the actions presented may include actions performed in a different order than illustrated, or additional actions.

In addition, any one or more of the operations discussed herein may be performed in response to instructions provided by one or more computer program products. Such a program product may include, for example, signal bearing media that, when executed by a processor, provide instructions that may provide the functionality described herein. The computer program product may be provided in any form in one or more machine-readable media. Thus, for example, a processor including one or more graphics processing unit(s) or processor core(s) may be viewed in response to program code and/or instructions or sets of instructions conveyed to the processor by one or more machine-readable media. One or more of the blocks of the example processes in the specification may be performed. In general, a machine-readable medium may cause any of the devices and/or systems described herein to at least some of the operations discussed herein and/or any part of the devices, systems, and/or systems discussed herein. , or software in the form of program code and/or instructions or sets of instructions that may cause any module or component to be implemented.

As used in any implementation described herein, the term “module” refers to any combination of software logic, firmware logic, hardware logic, and/or circuitry configured to provide the functionality described herein. Software may be implemented as a software package, code and/or set of instructions or instructions, and "hardware" as used in any implementation described herein, for example, alone or in any combination, hard-wired circuitry, programmable circuitry, state machine circuitry, fixed function circuitry, execution unit circuitry, and/or firmware that stores instructions to be executed by the programmable circuitry. Modules, collectively or individually, may be implemented as circuits that form part of a larger system, eg, integrated circuits (ICs), systems on-chips (SoCs), and the like.

Various embodiments may be implemented using hardware elements, software elements, or a combination of the two. Examples of hardware elements include processors, microprocessors, circuits, circuit elements (eg, transistors, resistors, capacitors, inductors, etc.), integrated circuits, application specific integrated circuits (ASICs), programmable logic devices (PLDs), digital signal processor), field programmable gate array (FPGA), logic gates, registers, semiconductor devices, chips, microchips, chipsets, and the like. Examples of software include software components, programs, applications, computer programs, application programs, system programs, machine programs, operating system software, middleware, firmware, software modules, routines, subroutines, functions, methods, procedures, software interfaces, APIs. (application program interface), instruction set, computing code, computer code, code segment, computer code segment, word, value, symbol, or any combination thereof. Determining whether an embodiment is implemented using hardware elements and/or software elements depends on the desired computation rate, power level, thermal tolerance, processing cycle budget, input data rate, output data rate, memory resources, data bus speed and It may depend on any number of factors, such as other design or performance constraints.

One or more aspects of at least one embodiment are representative of, stored on a machine-readable medium, representing various logic within a processor that, when read by a machine, causes the machine to produce logic to perform the techniques described herein. It can be implemented by commands. Such representations, known as IP cores, may be stored on a tangible machine readable medium and supplied to various customers or manufacturing facilities for loading into a manufacturing machine that actually manufactures the logic or processor.

While certain features described herein have been described with reference to various implementations, this description is not intended to be construed in a limiting sense. Accordingly, various modifications of the implementations described herein, as well as other implementations apparent to those skilled in the art to which this disclosure pertains, are considered to fall within the spirit and scope of this disclosure.

It will be appreciated that the embodiments are not limited to the embodiments so described and can be practiced with modifications and variations without departing from the scope of the appended claims. For example, the embodiment may include a particular combination of features. However, the embodiment is not limited in this respect, and in various implementations, the embodiment implements only a subset of such features, implements a different order of such features, implements different combinations of such features , and/or implementing additional features other than those explicitly recited. Accordingly, the scope of embodiments should be determined with reference to the appended claims, along with the full scope of equivalents entitled to such claims.

Claims (20)

An electronic device comprising:
one or more substrates; and
logic coupled to the one or more substrates
, wherein the logic is:
control access to two or more persistent storage devices, wherein at least one of the two or more persistent storage devices is logically organized into a namespace partitioned into two or more zones;
determine at least two different zone size dependent parameters associated with the at least two persistent storage devices;
determine a smallest aligned boundary based on each of the two or more different zone size dependent parameters;
and set a zone group size for access to the two or more persistent storage devices based on the determined minimum alignment boundary. The method of claim 1 , wherein the logic further comprises:
determine a preferred zone size for the application;
determine a first erase block size for a first one of the two or more persistent storage devices;
determine the minimum alignment boundary based on the preferred region size and the first erase block size. 3. The method of claim 2, wherein the logic further comprises:
determine a second erase block size for a second storage device among the two or more persistent storage devices;
determine the minimum alignment boundary based on the preferred region size, the first erase block size, and the second erase block size. 4. The apparatus of claim 3, wherein the first storage device comprises a first type of NAND media and the second storage device comprises a second type of NAND media that is different from the first type of NAND media. 3. The method of claim 2, wherein the logic further comprises:
determine a zone namespace sub-group capacity;
determine the minimum alignment boundary based on the preferred zone size, the first erase block size, and the zone namespace sub-group capacity. 3. The method of claim 2, wherein the logic further comprises:
determine zone namespace zone capacity;
determine the minimum alignment boundary based on the preferred zone size, the first erase block size, and the zone namespace zone capacity. The apparatus of claim 1 , wherein the at least one persistent storage device comprises a solid state drive. An electronic system comprising:
controller; and
logic communicatively coupled to the controller
, wherein the logic is:
control access to two or more persistent storage devices, wherein at least one of the two or more persistent storage devices is logically organized into a namespace partitioned into two or more zones;
determine at least two different zone size dependent parameters associated with the at least two persistent storage devices;
determine a smallest aligned boundary based on each of the two or more different zone size dependent parameters;
and set a zone group size for access to the two or more persistent storage devices based on the determined minimum alignment boundary. 9. The method of claim 8, wherein the logic further comprises:
determine a preferred zone size for the application;
determine a first erase block size for a first one of the two or more persistent storage devices;
determine the minimum alignment boundary based on the preferred region size and the first erase block size. 10. The method of claim 9, wherein the logic further comprises:
determine a second erase block size for a second storage device among the two or more persistent storage devices;
determine the minimum alignment boundary based on the preferred region size, the first erase block size, and the second erase block size. The system of claim 10 , wherein the first storage device comprises a first type of NAND media and the second storage device comprises a second type of NAND media that is different from the first type of NAND media. 10. The method of claim 9, wherein the logic further comprises:
determine a zone namespace sub-group capacity;
determine the minimum alignment boundary based on the preferred zone size, the first erase block size, and the zone namespace sub-group capacity. 10. The method of claim 9, wherein the logic further comprises:
determine zone namespace zone capacity;
determine the minimum alignment boundary based on the preferred zone size, the first erase block size, and the zone namespace zone capacity. The system of claim 8 , wherein the at least one persistent storage device comprises a solid state drive. A method of controlling storage, comprising:
controlling access to two or more persistent storage devices, wherein at least one of the two or more persistent storage devices is logically organized into a namespace partitioned into two or more zones;
determining at least two different zone size dependent parameters associated with the at least two persistent storage devices;
determining a minimum alignment boundary based on each of the two or more different zone size dependent parameters; and
setting a zone group size for access to the two or more persistent storage devices based on the determined minimum alignment boundary;
A method comprising 16. The method of claim 15,
determining a preferred zone size for the application;
determining a first erase block size for a first one of the two or more persistent storage devices; and
and determining the minimum alignment boundary based on the preferred region size and the first erase block size. 17. The method of claim 16,
determining a second erase block size for a second one of the two or more persistent storage devices; and
determining the minimum alignment boundary based on the preferred region size, the first erase block size, and the second erase block size;
Further comprising a, method. 18. The method of claim 17, wherein the first storage device comprises a first type of NAND media and the second storage device comprises a second type of NAND media that is different from the first type of NAND media. 17. The method of claim 16,
determining a zone namespace sub-group capacity; and
determining the minimum alignment boundary based on the preferred zone size, the first erase block size, and the zone namespace sub-group capacity;
Further comprising a, method. 17. The method of claim 16,
determining a zone namespace zone capacity; and
determining the minimum alignment boundary based on the preferred zone size, the first erase block size, and the zone namespace zone capacity;
Further comprising a, method.

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