KR20210077213A - The sapphire substrate and method for manufacturing the same - Google Patents

Abstract

The present invention relates to a sapphire substrate and a manufacturing method thereof. Disclosed are a sapphire substrate including a double-side polished wafer (DSP) and a thin film layer formed on one surface of the double-side polished wafer, and a method for manufacturing the sapphire substrate.

Description

The sapphire substrate and method for manufacturing the same

The present invention relates to a sapphire substrate with improved easiness of subsequent processing and a method for manufacturing the same.

Sapphire is a single crystal of alumina (Alumina, Al ₂ O ₃ ) and has excellent optical, mechanical, and thermal properties, and is widely used in high-tech fields such as aerospace and military optical systems, radar, and wear-resistant materials, and tempered glass. Because of its high strength, it is excellent at preventing scratches on the surface, and it is attracting attention as an alternative to the existing glass market due to its high transmittance and reflectance. In particular, recently, as the demand for a sapphire substrate used in an LED substrate widely used as a light emitting display device is rapidly increasing, research on mass production is being conducted.

In general, a method of manufacturing a sapphire substrate includes the steps of forming a wafer by cutting a grown sapphire ingot; grinding an edge of the cut wafer; lapping both sides of the wafer to remove distortion of the wafer; diamond mechanical polishing (DMP) of any one surface of the wafer to remove roughness and stress on the surface generated during lapping; and chemical mechanical polishing (CMP) on the surface of the wafer to remove defects or stress layers due to mechanical processing.

On the other hand, the sapphire substrate used for LED devices is a single side polishing (SSP) substrate used as a horizontal chip and a double side polishing used as a vertical chip depending on the purpose. Polishing, DSP) substrates. The SSP substrate is polished on only one side of the wrapped substrate, and the DSP substrate is polished on both front and back surfaces. Here, in the case of the DSP substrate, both sides have the same surface roughness, so the flatness is very excellent compared to the SSP substrate. However, compared to having a higher manufacturing cost compared to the SSP substrate by repeating the polishing process twice, the post-process such as patterning and epi-growth of the substrate is difficult due to defocusing due to the transparent characteristics of the DSP substrate. there was.

US 10-1643342 B

In order to solve the above-mentioned problem, an object of the present invention is to provide a sapphire substrate capable of facilitating subsequent collaboration of a double-sided polished wafer.

In order to achieve the above technical problem, the present invention provides a double-side polishing wafer (Double Side Polishing Wafer, DSP Wafer); and forming a thin film layer on one surface of the double-sided polishing wafer, wherein the thin film layer is _{at least one selected from the group consisting of SiO 2} , a-Si (amorphous-Si), poly-Si, and W-Si. It provides a method of manufacturing a sapphire substrate comprising a.

In the present invention, the thin film layer may have a thickness of less than 5 μm.

In addition, the thin film layer may be formed to have an isolated pattern.

In the present invention, the thin film layer is formed using a chemical vapor deposition (CVD) method.

In addition, the present invention includes a double-side polished wafer (DSP), and a thin film layer formed on one side of the double-side polished wafer, wherein the thin film layer is SiO ₂ , a-Si (amorphous-Si), poly-Si And it provides a sapphire substrate comprising at least one selected from the group consisting of W-Si.

Since the sapphire substrate manufactured according to the present invention has high flatness characteristics, it is possible to improve the yield and productivity for post-processes such as substrate patterning and epitaxial growth.

1 is a flowchart schematically illustrating a method of manufacturing a sapphire substrate of the present invention as an embodiment.
2 is an SEM image of a sapphire substrate manufactured according to an embodiment of the present invention.
3 shows the component analysis results of the manufactured sapphire substrate manufactured according to an embodiment of the present invention.
4 shows the results of measuring the size and angle of _{each SiO 2} pattern on the sapphire substrate manufactured according to an embodiment of the present invention.
5 is SiO ₂ DSP wafer and SiO _{2 without thin film deposition} The results of measuring transmittance of the DSP wafer on which the thin film is deposited are shown.

Hereinafter, the present invention will be described in detail so that those of ordinary skill in the art to which the present invention pertains can easily carry out the present invention with reference to the accompanying technology. In describing the present invention, if it is determined that a detailed description of a related known configuration or function may obscure the gist of the present invention, the detailed description thereof will be omitted.

Also in the present application, terms such as "comprise" or "have" are intended to designate that a feature, number, step, operation, component, part, or a combination thereof described in the specification exists, but one or more other It is to be understood that this does not preclude the possibility of addition or presence of features or numbers, steps, operations, components, parts, or combinations thereof. In the present application, the singular expression may include the plural expression unless the context clearly dictates otherwise.

The present invention provides a double-sided polishing wafer (Double Side Polishing Wafer, DSP Wafer); and forming a thin film layer on one surface of the double-sided polished wafer.

In the present invention, the double-sided polishing wafer refers to a wafer in which both sides of a lapped wafer are polished, and is used to be distinguished from a double-side polishing wafer (SSP Wafer) in which only one side of the wafer is polished.

In general, the LED manufacturing process is the process of wafer creation, wafer planarization. It is manufactured through an epitaxial process, an LED chip process, and a chip modularization process.

The epitaxial process is a process for manufacturing an epi-wafer by growing a compound semiconductor on a sapphire substrate, which is a basic material, using Metal Organic Chemical Vapor Deposition (MOCVD) equipment, etc. ), etc., to grow epi within the equipment. When growing an epitaxial thin film, the thickness uniformity of the thin film layer and the uniformity of the half width at half maximum are factors that have an important influence on yield stabilization and quality improvement in the subsequent chip process.

When the epi uniformity of the single-sided polished (SSP) substrate and the double-sided polished (DSP) substrate was measured, it was found that the double-sided polished substrate had better thickness uniformity and half-width uniformity compared to the single-sided polished substrate. Table 1 below shows thickness uniformity and half-width uniformity measured in an embodiment in which an epitaxial layer is formed on the SSP substrate and the DSP substrate.

SSP DSP thickness uniformity 3.35% 3.03% Half width uniformity 1.68% 0.71%

The reason for the excellent uniformity of the epitaxial layer in the DSP substrate is that the DSP substrate is processed to a level of <0.2 nm by mirror-finishing the front and back surfaces of the DSP substrate, and it is understood that the residual stress of the sapphire substrate is minimized by this processing.

Accordingly, the present invention is characterized in that post-processes such as patterning and epi-growth of a substrate are facilitated by using a double-sided polished wafer.

1 is a flowchart schematically illustrating a method of manufacturing a sapphire substrate according to the present invention as an embodiment. The step of providing a double-sided polished wafer may be manufactured by a conventional double-sided polished wafer manufacturing method. As an embodiment, it may proceed by performing steps S1 to S5 of FIG. 1 , but is not limited thereto.

Specifically, the sapphire ingot is cut (S1) to form a wafer, and the edge of the cut wafer is grinded to make it non-sharp (S2). Wrapping (S3). Thereafter, both surfaces of the wafer are subjected to diamond mechanical polishing (DMP) (S4), and then chemical mechanical polishing (CMP) on both surfaces (S5) to manufacture a double-sided polished wafer. The method of polishing both sides of the wafer after lapping may be performed by repeating the process of performing diamond mechanical polishing on the single side and then chemical mechanical polishing on the single side by repeating twice.

Then, by forming a thin film layer on one surface of the double-sided polished wafer manufactured through the above step, the sapphire substrate of the present invention can be manufactured.

The present invention can facilitate the manufacture of a patterned sapphire substrate (PSS) by depositing a thin film layer on one side of the DSP wafer to lower the transparency of one side, and improve the quality of the epitaxial growth.

In the present invention, the thin film layer may _{include at least one selected from the group consisting of SiO 2} , a-Si (amorphous-Si), poly-Si, and W-Si.

In addition, in the present invention, the thin film layer may be formed to have a thickness of less than 5 μm. If it exceeds 5 μm, the thickness deviation of the thin film layer becomes large, which causes flatness defects of the final product (substrate + thin film layer).

In the present invention, the thin film layer is formed as a layer on one surface of the double-sided polishing wafer, is not limited to a specific shape, and may be formed in a form that the entire surface is covered (blanket). Preferably, the thin film layer may be formed in an isolated pattern in order to reduce thermal stress caused by a difference in thermal expansion coefficient between the sapphire substrate and the thin film layer. The isolated pattern refers to a pattern in which structures forming the thin film layer are disposed to be spaced apart from each other. As an example, as shown in FIG. 2 , they may be spaced apart from each other at regular intervals.

The isolated pattern may be manufactured by forming a thin film layer covering the entire surface and then etching a part thereof, or by using a molding method to form a pattern at the same time as the thin film layer is formed.

The thin film layer may be formed using chemical vapor deposition (CVD), but is not limited as long as it is a method of forming a thin film on one surface of the DSP wafer. Particularly preferably, plasma-enhanced chemical vapor deposition (PECVD) or low pressure chemical vapor deposition (LPCVD) may be used in terms of minimizing damage to the wafer.

In the present invention, the process conditions for depositing the thin film layer can be selected and used by a person skilled in the art, but it is preferably performed at 1200 to 1300° C. for 6.5 to 7 hours. When depositing a thin film at a lower temperature and less time than the above conditions, Epi. There is a risk of the thin film layer peeling off during the deposition process (generally about 1000° C., 10 hours).

The present invention also includes a double-side polished wafer (DSP), and a thin film layer formed on one side of the double-side polished wafer, wherein the thin film layer is SiO ₂ , a-Si (amorphous-Si), poly-Si and It relates to a sapphire substrate comprising at least one selected from the group consisting of W-Si. The sapphire substrate of the present invention is characterized in that by maximizing the high flatness characteristics of the double-sided polished wafer, the yield and productivity for post-processes such as substrate patterning and epi-growth are improved.

Hereinafter, the present invention will be described in more detail through Examples and Experimental Examples. However, the following examples and experimental examples are only for specifically illustrating the present invention, and do not limit the scope of the present invention. That is, simple modifications or changes of the present invention can be easily carried out by those skilled in the art to which the present invention pertains, and all such modifications or changes can be considered to be included in the scope of the present invention.

< Example 1>

_{A SiO 2} layer was deposited on one surface of a 4-inch DSP wafer using plasma chemical vapor deposition (PECVD). In a nitrogen atmosphere, oxygen (O ₂ ), argon, and tetraethoxyorthosilicate (TEOS) were mixed with O ₂ :Ar:TEOS = 1000: _{SiO 2} by input at 100:100 (sccm) A thin film was formed.

SiO ₂ The thin film was prepared in an isolated pattern to reduce thermal stress. FIG. 2 is an SEM image of the sapphire substrate manufactured according to Example 1. FIG.

< Experimental example One : SiO ₂ Thin film property evaluation>

3 shows the component analysis results of the sapphire substrate prepared in Example 1 above. 3(a) is an _{analysis of a portion on which SiO 2} is deposited, and FIG. 3(b) is an analysis of a portion on which _{SiO 2 is not deposited. Referring to FIG. 3, SiO 2 of the isolated pattern} It can be seen that a layer is formed.

4 shows the results of measuring the size and angle of _{each SiO 2} pattern in the sapphire substrate prepared according to Example 1 above. As a result of the measurement, the average height of each pattern (SiO ₂ The thickness of the layer) is 2.466 μm, and the average diameter is 2.801 μm. It can be seen that a _{SiO 2 pattern is formed.}

< Experimental example 2 : SiO ₂ Transmittance measurement after thin film deposition>

_{SiO 2} according to Example 1 A DSP wafer on which a thin film was deposited was manufactured. Repeat this three times each to SiO ₂ Three DSP wafers on which thin films were deposited were fabricated (#1, #2, #3). DSP wafer without SiO ₂ thin film and SiO ₂ The transmittance of each of the three DSP wafers on which the thin film was deposited was measured and shown in FIG. 5 . The transmittance was measured by irradiating light of 190 nm to 1100 nm using SHIMADZU's UV-1650PC.

Referring to Figure 5, SiO ₂ DSP wafers with no thin film deposited have a transmittance of 80% or more and transmit a spectrum ranging from 200 to 1100 nm well, but SiO ₂ It can be seen that the transmittance of the DSP wafer on which the thin film is deposited is significantly reduced.

When the substrate is transparent, there is a problem in that it is difficult to focus for forming a pattern on the sapphire substrate, but as in the present invention, a SiO ₂ thin film is deposited on one side of the DSP wafer to lower the transparency of one side of the patterned sapphire substrate It can facilitate the manufacture of (patterned sapphire substrate, PSS).

The above description is merely illustrative of the technical idea of the present invention, and various modifications and variations will be possible without departing from the essential characteristics of the present invention by those skilled in the art to which the present invention pertains. Therefore, the embodiments described in the present invention are for explaining the technical spirit of the present invention, and the technical spirit of the present invention is not limited by these embodiments. The protection scope of the present invention should be construed by the following claims, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

Claims (7)

providing a Double Side Polished Wafer (DSP Wafer); and
Including; forming a thin film layer on one surface of the double-sided polishing wafer;
The thin film layer includes _{at least one selected from the group consisting of SiO 2} , a-Si (amorphous-Si), poly-Si, and W-Si.
According to claim 1,
The thin film layer is formed to have a thickness of less than 5 μm, a method of manufacturing a sapphire substrate.
According to claim 1,
The thin film layer is formed to have an isolated pattern (isolated pattern), the manufacturing method of the sapphire substrate.
According to claim 1,
The thin film layer is formed using a chemical vapor deposition (CVD) method, a method of manufacturing a sapphire substrate.
Double Side Polished (DSP) wafers, and
A thin film layer formed on one side of the double-sided polishing wafer,
The thin film layer includes _{at least one selected from the group consisting of SiO 2} , a-Si (amorphous-Si), poly-Si, and W-Si, a sapphire substrate.
6. The method of claim 5,
The thin film layer has a thickness of less than 5 μm, a sapphire substrate.
6. The method of claim 5,
The thin film layer is an isolated pattern (isolated pattern), a sapphire substrate.

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