KR20210075291A - Display device and method of fabricating the display device - Google Patents

Abstract

The present invention relates to a display device, which comprises: a substrate including a display area including a plurality of pixel areas and a non-display area surrounding the display area; and a pixel provided in each of the pixel areas. The pixel includes: first and second electrodes extending in one direction on the substrate, and spaced apart from each other; a first insulating film provided on the first and second electrodes; a bank pattern provided on the first insulating film to correspond to each of the first and second electrodes; an intermediate layer provided on the bank pattern; a plurality of light emitting devices provided between the two intermediate layers adjacent in the other direction intersecting the one direction; a first contact electrode being in contact with one of the two adjacent intermediate layers, and connected to one of both ends of each of the light emitting devices; and a second contact electrode being in contact with the other of the two adjacent intermediate layers, and connected to the other of both ends of each of the light emitting devices. Accordingly, a manufacturing process is simplified while improving the alignment of the light emitting devices.

Description

Display device and manufacturing method thereof

The present invention relates to a display device and a method for manufacturing the same.

A light emitting diode (Light Emitting Diode) exhibits relatively good durability even in harsh environmental conditions, and has excellent performance in terms of lifespan and luminance.

In order to apply the light emitting diode to a lighting device or a display device, it is necessary to connect an electrode capable of applying power to the light emitting diode, and it is related to the purpose of use, reduction of the space occupied by the electrode, a manufacturing method, or a driving method. The arrangement relationship between the light emitting diode and the electrode has been studied in various ways.

SUMMARY OF THE INVENTION An object of the present invention is to provide a display device in which a manufacturing process is simplified while improving alignment of light emitting devices.

Another object of the present invention is to provide a method for manufacturing the above-described display device.

A display device according to an embodiment of the present invention includes: a substrate including a display area including a plurality of pixel areas and a non-display area surrounding the display area; and a pixel provided in each of the pixel areas.

In an embodiment of the present invention, the pixel may include first and second electrodes extending in one direction on the substrate and spaced apart from each other; a first insulating film provided on the first and second electrodes; a bank pattern provided on the first insulating layer to correspond to each of the first and second electrodes; an intermediate layer provided on the bank pattern; a plurality of light emitting elements provided between the two intermediate layers adjacent in the other direction intersecting the one direction; a first contact electrode in contact with one of the two adjacent intermediate layers and connected to one of both ends of each of the light emitting devices; and a second contact electrode in contact with the other intermediate layer of the two adjacent intermediate layers and connected to the other end among both ends of each of the light emitting devices.

In one embodiment of the present invention, the intermediate layer may include a conductive material.

In an embodiment of the present invention, each of the first and second electrodes may extend in the one direction and may be provided in common to adjacent pixels positioned in the same pixel column as the pixel.

In an embodiment of the present invention, the one intermediate layer may be provided only to the pixel, and the other intermediate layer may be provided in common to the pixel and the adjacent pixels.

In an embodiment of the present invention, the one intermediate layer may overlap one of the first and second electrodes when viewed in a plan view. In addition, the remaining intermediate layer may overlap the remaining electrode among the first and second electrodes when viewed in a plan view.

In an embodiment of the present invention, the pixel may further include at least one transistor and a driving voltage line provided between the substrate and the first and second electrodes.

In an embodiment of the present invention, one contact electrode of the first and second contact electrodes is electrically connected to the transistor, and the other contact electrode of the first and second contact electrodes is the driving voltage line. can be electrically connected to.

In one embodiment of the present invention, the one intermediate layer and one of the first and second electrodes may form a capacitor with the first insulating layer and a bank pattern corresponding to the one electrode interposed therebetween. can In addition, the remaining intermediate layer and the remaining electrode of the first and second electrodes may form a capacitor with the first insulating layer and a bank pattern corresponding to the remaining electrode interposed therebetween.

In an embodiment of the present invention, the pixel may further include a first sub-electrode and a second sub-electrode provided on the first insulating layer, extending along the one direction and spaced apart from each other.

In an embodiment of the present invention, the first sub-electrode may overlap the first electrode when viewed in a plan view, and the second sub-electrode may overlap the second electrode when viewed in a plan view.

In an embodiment of the present invention, the first sub-electrode may be provided between the first electrode and the bank pattern corresponding to the first electrode. Also, the second sub-electrode may be provided between the second electrode and the bank pattern corresponding to the second electrode.

In an embodiment of the present invention, the first electrode and the first sub-electrode form a capacitor with the first insulating layer interposed therebetween, and the second electrode and the second sub-electrode are interposed between the first insulating layer. A capacitor can be formed by placing it in

In one embodiment of the present invention, the one intermediate layer covers the first sub-electrode and is electrically connected to the first sub-electrode, and the other intermediate layer covers the second sub-electrode and the second It may be electrically connected to the sub-electrode.

In an embodiment of the present invention, the pixel includes: a second insulating layer provided on the intermediate layer and exposing a portion of the intermediate layer; and a third insulating layer provided on a top surface of each of the light emitting devices.

In an embodiment of the present invention, the first contact electrode and the second contact electrode may be provided on the third insulating layer. The first contact electrode and the second contact electrode may be provided on the same layer or on different layers.

The display device according to the above-described exemplary embodiment may be manufactured by providing a pixel provided in each pixel area. Here, providing the pixel may include: forming at least one transistor and a driving voltage line on a substrate; forming an interlayer insulating film on the transistor and the driving voltage line; forming first and second electrodes extending in one direction and spaced apart from each other on the interlayer insulating layer; forming a first insulating layer on the first electrode and the second electrode; forming a bank pattern corresponding to each of the first and second electrodes on the first insulating layer; forming an intermediate layer including a conductive material on the bank pattern; After inputting a plurality of light emitting devices, an alignment signal corresponding to each of the first electrode and the second electrode is applied to the light emitting device between the two intermediate layers adjacent in the other direction intersecting the one direction. sorting them; forming a second insulating film on an upper surface of each of the light emitting devices; and forming a first contact electrode and a second contact electrode on the second insulating layer.

According to an embodiment of the present invention, by separating the configuration for aligning the light emitting devices and the configuration for driving the light emitting devices, the alignment of the light emitting devices can be improved by precisely aligning the light emitting devices in a desired area.

In addition, according to an embodiment of the present invention, a display device with a simplified manufacturing process is provided by arranging the light emitting elements in each pixel using a conductive line provided in the pixel circuit unit, thereby omitting a separation process of wiring for aligning the light emitting elements. may be provided.

Also, according to an embodiment of the present invention, the above-described method of manufacturing the display device may be provided.

Effects according to the embodiments of the present invention are not limited by the contents exemplified above, and more various effects are included in the present specification.

1A is a perspective view schematically illustrating a light emitting device according to an embodiment of the present invention.
1B is a cross-sectional view of the light emitting device of FIG. 1A.
2A is a perspective view schematically illustrating a light emitting device according to another embodiment of the present invention.
2B is a cross-sectional view of the light emitting device of FIG. 2A.
3A is a perspective view schematically illustrating a light emitting device according to another embodiment of the present invention.
3B is a cross-sectional view of the light emitting device of FIG. 3A.
4A is a perspective view schematically illustrating a light emitting device according to another embodiment of the present invention.
4B is a cross-sectional view of the light emitting device of FIG. 4A.
5 is a view showing a display device according to an embodiment of the present invention, and in particular, the light emitting devices shown in FIGS. 1A, 1B, 2A, 2B, 3A, 3B, 4A, and 4B. It is a schematic plan view of a display device using any one light emitting element as a light emitting source.
6A to 6E are circuit diagrams illustrating electrical connection relationships between components included in one pixel illustrated in FIG. 5 according to various embodiments.
7 is a plan view schematically illustrating only some signal lines transmitting a predetermined signal to each of the pixels and pads connected thereto in the display device illustrated in FIG. 5 .
FIG. 8 schematically illustrates one pixel among the pixels shown in FIG. 5 , and is an enlarged plan view of a portion EA of FIG. 7 .
9A to 9C are cross-sectional views taken along line I to I' of FIG. 8 .
FIG. 10 is a cross-sectional view taken along line II to II′ of FIG. 8 .
FIG. 11 is a cross-sectional view of the first bank pattern shown in FIG. 10 implemented according to another embodiment, and corresponding to lines II to II′ of FIG. 8 .
FIG. 12 is a cross-sectional view of the display element shown in FIG. 11 , which is implemented according to another exemplary embodiment, taken along lines II to II′ of FIG. 8 .
13A to 13H are cross-sectional views sequentially illustrating a method of manufacturing one pixel illustrated in FIG. 9A .
14 is a schematic plan view of a display device according to another embodiment of the present invention, and is a plan view corresponding to a portion EA of FIG. 7 .
15 is a cross-sectional view corresponding to the line III to III' of FIG. 14 .
16 is a cross-sectional view corresponding to a line IV to IV' of FIG. 14 .

Since the present invention can have various changes and can have various forms, specific embodiments are illustrated in the drawings and described in detail in the text. However, this is not intended to limit the present invention to the specific disclosed form, it should be understood to include all modifications, equivalents and substitutes included in the spirit and scope of the present invention.

In describing each figure, like reference numerals have been used for like elements. In the accompanying drawings, the dimensions of the structures are enlarged than the actual size for clarity of the present invention. Terms such as first, second, etc. may be used to describe various elements, but the elements should not be limited by the terms. The above terms are used only for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, a first component may be referred to as a second component, and similarly, a second component may also be referred to as a first component. The singular expression includes the plural expression unless the context clearly dictates otherwise.

In the present application, terms such as “comprise” or “have” are intended to designate that a feature, number, step, operation, component, part, or combination thereof described in the specification exists, but one or more other features It is to be understood that it does not preclude the possibility of the presence or addition of numbers, steps, operations, components, parts, or combinations thereof. Also, when a part of a layer, film, region, plate, etc. is said to be "on" another part, this includes not only the case where it is "directly on" another part, but also the case where another part is in the middle. In addition, in the present specification, when a portion such as a layer, film, region, or plate is formed on another portion, the formed direction is not limited only to the upper direction, and includes those formed in the side or lower direction. . Conversely, when a part of a layer, film, region, plate, etc. is said to be “under” another part, this includes not only cases where it is “directly under” another part, but also a case where another part is in between.

Hereinafter, with reference to the accompanying drawings, preferred embodiments of the present invention and other matters necessary for those skilled in the art to easily understand the contents of the present invention will be described in detail. In the description below, expressions in the singular also include the plural, unless the context clearly includes only the singular.

1A is a perspective view schematically showing a light emitting device according to an embodiment of the present invention, FIG. 1B is a cross-sectional view of the light emitting device of FIG. 1A, and FIG. 2A is a schematic view of a light emitting device according to another embodiment of the present invention One perspective view, FIG. 2B is a cross-sectional view of the light-emitting device of FIG. 2A, FIG. 3A is a perspective view schematically illustrating a light-emitting device according to another embodiment of the present invention, and FIG. 3B is a cross-sectional view of the light-emitting device of FIG. 4A is a perspective view schematically illustrating a light emitting device according to another embodiment of the present invention, and FIG. 4B is a cross-sectional view of the light emitting device of FIG. 4A .

For convenience, after explaining FIGS. 1A, 1B, 2A, 2B, 3A, and 3B illustrating a light emitting device manufactured by an etching method, FIGS. 4A and 4A and FIG. 3B showing a light emitting device manufactured by a growth method 4b will be described. In one embodiment of the present invention, the type and/or shape of the light emitting device is limited to the embodiments shown in FIGS. 1A, 1B, 2A, 2B, 3A, 3B, 4A, and 4B it doesn't happen

First, referring to FIGS. 1A, 1B, 2A, 2B, 3A, and 3B, the light emitting device LD includes a first semiconductor layer 11, a second semiconductor layer 13, and the first and an active layer 12 interposed between the second semiconductor layers 11 and 13 . For example, the light emitting device LD may be implemented as a light emitting stack in which the first semiconductor layer 11 , the active layer 12 , and the second semiconductor layer 13 are sequentially stacked.

According to an embodiment of the present invention, the light emitting device LD may be provided in a shape extending in one direction. If the extending direction of the light emitting device LD is referred to as a longitudinal direction, the light emitting device LD may have one end and the other end along the extending direction. Any one of the first and second semiconductor layers 11 and 13 may be disposed at one end of the light emitting device LD, and the first and second semiconductor layers 11 and 11 at the other end thereof. 13), the other semiconductor layer may be disposed.

The light emitting device LD may be provided in various shapes. For example, the light emitting device LD may have a long rod-like shape in the longitudinal direction (ie, an aspect ratio greater than 1) or a bar-like shape. In one embodiment of the present invention, the length L of the light emitting device LD in the longitudinal direction may be greater than the diameter D or the width of the cross-section. The light emitting device LD may include, for example, a light emitting diode manufactured so as to have a micro-scale or nano-scale diameter (D) and/or a length (L). In an embodiment of the present invention, the size of the light emitting device LD may be changed to meet a requirement (or design condition) of an applied lighting device or a self-luminous display device.

The first semiconductor layer 11 may include, for example, at least one n-type semiconductor layer. For example, the first semiconductor layer 11 includes a semiconductor material of any one of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and is an n-type semiconductor doped with a first conductive dopant such as Si, Ge, Sn, or the like. layers may be included. However, the material constituting the first semiconductor layer 11 is not limited thereto, and in addition to this, the first semiconductor layer 11 may be formed of various materials.

The active layer 12 is disposed on the first semiconductor layer 11 and may be formed in a single or multiple quantum well structure. The position of the active layer 12 may be variously changed according to the type of the light emitting device LD. The active layer 12 may emit light having a wavelength of 400 nm to 900 nm, and a double hetero structure may be used. In an embodiment of the present invention, a cladding layer (not shown) doped with a conductive dopant may be formed on the upper and/or lower portions of the active layer 12 . For example, the clad layer may be formed of an AlGaN layer or an InAlGaN layer. According to an embodiment, a material such as AlGaN or AlInGaN may be used to form the active layer 12 , and in addition to this, various materials may constitute the active layer 12 .

When an electric field greater than a predetermined voltage is applied to both ends of the light emitting device LD, the light emitting device LD emits light while electron-hole pairs are combined in the active layer 12 . By controlling light emission of the light emitting device LD using this principle, the light emitting device LD can be used as a light source of various light emitting devices including pixels of a display device.

The second semiconductor layer 13 is disposed on the active layer 12 , and may include a semiconductor layer of a different type from that of the first semiconductor layer 11 . For example, the second semiconductor layer 13 may include at least one p-type semiconductor layer. For example, the second semiconductor layer 13 may include at least one semiconductor material of InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and may include a p-type semiconductor layer doped with a second conductive dopant such as Mg. can However, the material constituting the second semiconductor layer 13 is not limited thereto, and various materials other than this may constitute the second semiconductor layer 13 .

In one embodiment of the present invention, the first semiconductor layer 11 and the second semiconductor layer 13 may have different widths (or thicknesses) in the length L direction of the light emitting device LD. For example, the first semiconductor layer 11 may have a relatively wider width (or a thicker thickness) than the second semiconductor layer 13 along the length L direction of the light emitting device LD. Accordingly, the active layer 12 of the light emitting device LD is located closer to the upper surface of the second semiconductor layer 13 than the lower surface of the first semiconductor layer 11 as shown in FIGS. 1A to 3B. can

According to an embodiment of the present invention, the light emitting device LD is disposed on the second semiconductor layer 13 in addition to the first semiconductor layer 11 , the active layer 12 , and the second semiconductor layer 13 described above. It may further include an additional electrode 15 that is. In addition, according to an embodiment, as shown in FIGS. 3A and 3B , another additional electrode 16 disposed on one end of the first semiconductor layer 11 may be further included.

The additional electrodes 15 and 16 may be ohmic contact electrodes, but are not limited thereto and may be Schottky contact electrodes according to embodiments. The additional electrodes 15 and 16 may include metal or metal oxide, for example, chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), ITO and These oxides or alloys may be used alone or in combination, but the present invention is not limited thereto.

Materials included in each of the additional electrodes 15 and 16 may be the same or different from each other. The additional electrodes 15 , 16 may be substantially transparent or translucent. Accordingly, the light generated by the light emitting device LD may pass through the additional electrodes 15 and 16 to be emitted to the outside of the light emitting device LD. In some embodiments, the light generated by the light emitting device LD does not pass through the additional electrodes 15 and 16 and passes through a region excluding both ends of the light emitting device LD to the outside of the light emitting device LD. When emitted, the additional electrodes 15 , 16 may include an opaque metal.

In an embodiment of the present invention, the light emitting device LD may further include an insulating layer 14 . However, in some embodiments, the insulating layer 14 may be omitted or provided to cover only a portion of the first semiconductor layer 11 , the active layer 12 , and the second semiconductor layer 13 .

The insulating layer 14 may prevent an electrical short circuit that may occur when the active layer 12 comes into contact with a conductive material other than the first semiconductor layer 11 and the second semiconductor layer 13 . In addition, by forming the insulating layer 14 , surface defects of the light emitting device LD may be minimized, thereby improving lifespan and efficiency. In addition, when the plurality of light emitting devices LD are closely disposed, the insulating layer 14 may prevent an unwanted short circuit between the light emitting devices LD. As long as the active layer 12 can prevent a short circuit with an external conductive material, whether or not the insulating layer 14 is provided is not limited.

The insulating film 14 is, as shown in FIGS. 1A and 1B , the outer peripheral surface of the light emitting laminate including the first semiconductor layer 11 , the active layer 12 , the second semiconductor layer 13 , and the additional electrode 15 . It may be provided in a form that surrounds the whole. For convenience of explanation, a portion of the insulating layer 14 is removed in FIG. 1A , and the first semiconductor layer 11, the active layer 12, and the second semiconductor layer ( 13), and the additional electrode 15 may be surrounded by the insulating layer 14 .

In the above-described embodiment, the insulating film 14 has been described in a form that completely surrounds the outer peripheral surface of each of the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and the additional electrode 15, The present invention is not limited thereto.

According to an embodiment, the insulating film 14 surrounds the outer peripheral surface of each of the first semiconductor layer 11 , the active layer 12 , and the second semiconductor layer 13 as shown in FIGS. 2A and 2B , and the second semiconductor The outer circumferential surface of the additional electrode 15 disposed on the layer 13 may not be entirely surrounded, or only a portion of the outer circumferential surface of the additional electrode 15 may be surrounded and the rest of the outer circumferential surface of the additional electrode 15 may not be surrounded. However, the insulating layer 14 exposes at least both ends of the light emitting device LD, and for example, the first semiconductor layer 11 together with the additional electrode 15 disposed at one end of the second semiconductor layer 13 . ) can be exposed at one end. In addition, according to an embodiment, when the additional electrodes 15 and 16 are disposed at both ends of the light emitting device LD as shown in FIGS. 3A and 3B , the insulating layer 14 is formed by the additional electrodes 15 . , 16) each of at least one region may be exposed. Alternatively, in another embodiment, the insulating film 14 may not be provided.

According to an embodiment of the present invention, the insulating layer 14 may include a transparent insulating material. For example, the insulating layer 14 may include _{one or more insulating materials selected from the group consisting of SiO 2} , Si ₃ N ₄ , Al ₂ O ₃ and TiO ₂ , but is not limited thereto, and various materials having insulating properties. can be used.

When the insulating layer 14 is provided on the light emitting device LD, it is possible to prevent the active layer 12 from being short-circuited with the first electrode and/or the second electrode (not shown). In addition, by forming the insulating layer 14 , surface defects of the light emitting device LD may be minimized, thereby improving lifespan and efficiency. In addition, when the plurality of light emitting devices LD are closely disposed, the insulating layer 14 may prevent an unwanted short circuit between the light emitting devices LD.

The above-described light emitting device LD may be used as a light emitting source of various display devices. The light emitting device LD may be manufactured through a surface treatment process. For example, when a plurality of light emitting devices LD are mixed with a fluid solution (or solvent) and supplied to each light emitting area (eg, a light emitting area of each pixel or a light emitting area of each sub-pixel), the light emission Each of the light emitting elements LD may be surface-treated so that the elements LD may be uniformly sprayed without agglomeration in the solution.

The light emitting device including the above-described light emitting element LD may be used in various types of devices requiring a light source, including a display device. For example, when a plurality of light emitting devices LD are disposed in a light emitting area of each pixel of the display panel, the light emitting devices LD may be used as light sources of each pixel. However, the field of application of the light emitting device LD is not limited to the above-described example. For example, the light emitting device LD may be used in other types of devices that require a light source, such as a lighting device.

Next, a light emitting device LD manufactured by a growth method will be described with reference to FIGS. 4A and 4B .

In the description of the light emitting device LD manufactured by the growth method, different points from the above-described embodiment will be mainly described, and parts not specifically described in the light emitting device LD manufactured by the growth method are described above. In accordance with one embodiment, the same numbers are assigned to components similar and/or identical to those of the above-described embodiment.

4A and 4B , a light emitting device LD according to an embodiment of the present invention includes a first semiconductor layer 11 and a second semiconductor layer 13 , and the first and second semiconductor layers. It may include an active layer 12 interposed between (11, 13). According to an embodiment, the light emitting device LD includes a first semiconductor layer 11 located in the center, an active layer 12 surrounding at least one side of the first semiconductor layer 11 , and at least one side of the active layer 12 . and a light emitting pattern 10 having a core-shell structure including a second semiconductor layer 13 surrounding it, and an additional electrode 15 surrounding at least one side of the second semiconductor layer 13 . can do.

The light emitting device LD may be provided in the shape of a polygonal pyramid extending in one direction. For example, the light emitting device LD may be provided in a hexagonal pyramid shape. If the extending direction of the light emitting device LD is referred to as a length (L) direction, the light emitting device LD may have one end (or lower end) and the other end (or upper end) along the length (L) direction. have. A portion of one of the first and second semiconductor layers 11 and 13 is exposed at one end (or lower end) of the light emitting device LD, and the other end (or upper end of the light emitting device LD) is exposed. end) of the first and second semiconductor layers 11 and 13 , a portion of the remaining semiconductor layer may be exposed. For example, a portion of the first semiconductor layer 11 is exposed at one end (or lower end) of the light emitting device LD, and the second semiconductor layer 11 is exposed at the other end (or upper end) of the light emitting device LD (or upper end). 13) may be exposed. In this case, when the light emitting device LD is applied as a light source of the display device, a portion of the exposed first semiconductor layer 11 is in contact with and exposed to one of the driving electrodes driving the light emitting device LD. A portion of the second semiconductor layer 13 may be in contact with another driving electrode.

According to an embodiment, when the light emitting device LD includes the additional electrode 15 , the additional electrode surrounds at least one side of the second semiconductor layer 13 at the other end (or upper end) of the light emitting device LD. A part of (15) may be exposed. In this case, a portion of the additional electrode 15 exposed when the light emitting element LD is applied as a light source of the display device may contact the other driving electrode to be electrically connected to the one electrode.

In one embodiment of the present invention, the first semiconductor layer 11 may be located at the core of the light emitting device LD, that is, at the center (or at the center). The light emitting device LD may be provided in a shape corresponding to the shape of the first semiconductor layer 11 . For example, when the first semiconductor layer 11 has a hexagonal pyramid shape, the light emitting device LD and the light emitting pattern 10 may also have a hexagonal pyramid shape.

The active layer 12 may be provided and/or formed in a shape surrounding the outer circumferential surface of the first semiconductor layer 11 in the length L direction of the light emitting device LD. Specifically, the active layer 12 is provided in a form surrounding the remaining region except for the other end disposed on the lower side among both ends of the first semiconductor layer 11 in the length L direction of the light emitting device LD and/or can be formed.

The second semiconductor layer 13 is provided and/or formed to surround the active layer 12 in the length (L) direction of the light emitting device LD, and includes a semiconductor layer of a different type from that of the first semiconductor layer 11 . may include For example, the second semiconductor layer 13 may include at least one p-type semiconductor layer.

In an embodiment of the present invention, the light emitting device LD may include an additional electrode 15 surrounding at least one side of the second semiconductor layer 13 . The additional electrode 15 may be an ohmic contact electrode electrically connected to the second semiconductor layer 13 or a Schottky contact electrode, but is not limited thereto.

As described above, the light emitting device LD may be configured in a hexagonal pyramid shape having both ends protruding, the first semiconductor layer 11 provided in the center thereof, and surrounding the first semiconductor layer 11 . is a core-shell structure light emitting pattern including an active layer 12, a second semiconductor layer 13 surrounding the active layer 12, and an additional electrode 15 surrounding the second semiconductor layer 13 ( 10) can be implemented. The first semiconductor layer 11 is disposed at one end (or lower end) of the light emitting device LD having a hexagonal pyramid shape, and the additional electrode 15 is disposed at the other end (or upper end) of the light emitting device LD. can be

Also, according to an embodiment, the light emitting device LD may further include an insulating layer 14 provided on an outer circumferential surface of the light emitting pattern 10 having a core-shell structure. The insulating layer 14 may include a transparent insulating material.

5 is a view showing a display device according to an embodiment of the present invention, and in particular, the light emitting devices shown in FIGS. 1A, 1B, 2A, 2B, 3A, 3B, 4A, and 4B. It is a schematic plan view of a display device using any one of the light emitting elements as a light emitting source.

5 , for convenience, the structure of the display device is schematically illustrated with the display area in which an image is displayed. However, according to an embodiment, at least one driving circuit unit (eg, a scan driver and a data driver, etc.) and/or a plurality of signal wires not shown may be further disposed in the display device.

1A, 1B, 2A, 2B, 3A, 3B, 4A, 4B, and 5 , a display device according to an exemplary embodiment includes a substrate SUB and a substrate SUB. ) provided on the plurality of pixels PXL and each including at least one light emitting element LD, a driver (not shown) provided on the substrate SUB and driving the pixels PXL, and the pixels A wiring unit (not shown) connecting the PXL and the driving unit may be included.

The display device may be classified into a passive matrix type display device and an active matrix type display device according to a method of driving the light emitting element LD. For example, when the display device is implemented as an active matrix type, each of the pixels PXL includes a driving transistor that controls the amount of current supplied to the light emitting device LD, a switching transistor that transmits a data signal to the driving transistor, and the like. can do.

Recently, from the viewpoint of resolution, contrast, and operation speed, active matrix type display devices that selectively light each pixel (PXL) have become mainstream, but the present invention is not limited thereto, and a passive matrix in which lighting is performed for each pixel (PXL) group. A type display device may also use components (eg, first and second electrodes) for driving the light emitting element LD.

The substrate SUB may include a display area DA and a non-display area NDA.

In some embodiments, the display area DA may be disposed in a central area of the display device, and the non-display area NDA may be disposed at an edge area of the display device to surround the display area DA. However, the positions of the display area DA and the non-display area NDA are not limited thereto, and positions thereof may be changed.

The display area DA may be an area in which pixels PXL displaying an image are provided. The non-display area NDA may be an area in which a driver for driving the pixels PXL and a portion of a wiring connecting the pixels PXL and the driver are provided.

The display area DA may have various shapes. For example, the display area DA may be provided as a closed polygon including straight sides. Also, the display area DA may be provided in a circular shape and/or an elliptical shape including curved sides. In addition, the display area DA may be provided in various shapes, such as a semicircle including straight and curved sides, and a semi-ellipse.

The non-display area NDA may be provided on at least one side of the display area DA. In an embodiment of the present invention, the non-display area NDA may surround a circumference (or an edge) of the display area DA.

The substrate SUB may include a transparent insulating material to allow light to pass therethrough. The substrate SUB may be a rigid substrate or a flexible substrate.

One area on the substrate SUB may serve as the display area DA so that the pixels PXL are disposed, and the remaining area on the substrate SUB may serve as the non-display area NDA. For example, the substrate SUB may include a display area DA including pixel areas in which each pixel PXL is disposed, and a non-display area NDA disposed around the display area DA. have.

Each of the pixels PXL may be provided in the display area DA on the substrate SUB. In an embodiment of the present invention, the pixels PXL may be arranged in the display area DA in a stripe or pentile arrangement structure, but the present invention is not limited thereto.

Each pixel PXL may include at least one light emitting element LD driven by a corresponding scan signal and data signal. The light emitting device LD may have a size as small as a micro-scale or a nano-scale and may be connected in parallel to adjacent light emitting devices, but the present invention is not limited thereto. The light emitting element LD may constitute a light source of each pixel PXL.

Each pixel PXL includes at least one light source driven by a predetermined signal (eg, a scan signal and a data signal) and/or a predetermined power (eg, a first driving power and a second driving power) can do. For example, each pixel PXL is the light emitting device LD shown in each of the embodiments of FIGS. 1A to 4B , for example, at least one ultra-small light emitting device having a size as small as a nano-scale to a micro-scale, respectively. The device LD may be included. However, in the exemplary embodiment of the present invention, the type of the light emitting device LD that can be used as a light source of each pixel PXL is not limited thereto.

In one embodiment of the present invention, the color, type, and/or number of the pixels PXL is not particularly limited, and for example, the color of light emitted from each pixel PXL may be variously changed. .

The driver may provide a predetermined signal and a predetermined power to each pixel PXL through the wiring unit, and thus may control driving of the pixel PXL. In FIG. 5, a wiring part is omitted for convenience of description.

The driver includes a scan driver that provides a scan signal to the pixels PXL through a scan line, a light emission driver that provides a light emission control signal to the pixels PXL through an emission control line, and the pixels PXL through a data line. It may include a data driver providing a data signal to the , and a timing controller. The timing controller may control the scan driver, the light emission driver, and the data driver.

6A to 6E are circuit diagrams illustrating electrical connection relationships between components included in one pixel illustrated in FIG. 5 according to various embodiments.

For example, FIGS. 6A to 6E illustrate an electrical connection relationship between components included in a pixel PXL that can be applied to an active display device according to different embodiments. However, the types of components included in the pixel PXL to which the embodiment of the present invention can be applied are not limited thereto.

In FIGS. 6A to 6E , not only components included in each of the pixels illustrated in FIG. 5 , but also regions in which the components are provided are collectively referred to as a pixel PXL. According to an exemplary embodiment, each of the pixels PXL illustrated in FIGS. 6A to 6E may be any one of the pixels PXL included in the display device of FIG. 5 , and the pixels PXL are substantially each other. It may have the same or similar structure.

1A to 4B, 5 and 6A to 6E , one pixel (PXL, hereinafter referred to as a 'pixel') includes a light emitting unit (EMU) that generates light having a luminance corresponding to a data signal. can do. Also, the pixel PXL may optionally further include a pixel circuit 144 for driving the light emitting unit EMU.

According to an exemplary embodiment, the light emitting unit EMU is installed in parallel between the first power line PL1 to which the first driving power VDD is applied and the second power line PL2 to which the second driving power VSS is applied. It may include a plurality of connected light emitting devices LD. For example, the light emitting unit EMU may have a first electrode EL1 or a “first alignment electrode” to which the first driving power VDD is applied via the pixel circuit 144 and the first power line PL1 . ), a second electrode EL2 to which the second driving power VSS is applied via the second power line PL2 , or a “second alignment electrode”, and the first and second electrodes EL1 , It may include a plurality of light emitting elements LD connected in parallel in the same direction between the EL2 . In one embodiment of the present invention, the first electrode EL1 may be an anode electrode, and the second electrode EL2 may be a cathode electrode.

In one embodiment of the present invention, each of the light emitting elements LD included in the light emitting unit EMU receives the first driving power VDD through the first electrode EL1 (or the first power line). The second end to which the second driving power VSS is applied (or electrically connected to the second power line PL2) through the first end (electrically connected to PL1) and the second electrode EL2 may include The first driving power VDD and the second driving power VSS may have different potentials. For example, the first driving power VDD may be set as a high potential power, and the second driving power VSS may be set as a low potential power. In this case, the potential difference between the first and second driving power sources VDD and VSS may be set to be greater than or equal to the threshold voltage of the light emitting elements LD during the light emission period of the pixel PXL.

As described above, each light emitting element LD connected in parallel in the same direction (for example, forward direction) between the first electrode EL1 and the second electrode EL2 to which voltages of different potentials are respectively supplied is An effective light source can be configured. These effective light sources may be gathered to configure the light emitting unit EMU of the pixel PXL.

The light emitting elements LD of the light emitting unit EMU may emit light with a luminance corresponding to the driving current supplied through the corresponding pixel circuit 144 . For example, during each frame period, the pixel circuit 144 may supply a driving current corresponding to a grayscale value of the corresponding frame data to the light emitting unit EMU. The driving current supplied to the light emitting unit EMU may divide and flow through the light emitting devices LD connected in the same direction. Accordingly, the light emitting unit EMU may emit light having a luminance corresponding to the driving current while each light emitting element LD emits light with a luminance corresponding to the current flowing therein.

Meanwhile, in FIGS. 6A to 6E , an embodiment in which the light emitting devices LD are connected in the same direction between the first and second driving power sources VDD and VSS is illustrated, but the present invention is not limited thereto. does not According to an embodiment, the light emitting unit EMU may further include at least one ineffective light source in addition to the light emitting elements LD constituting each effective light source. For example, at least the reverse light emitting device LDr may be further connected between the first and second electrodes EL1 and EL2 of the light emitting unit EMU, as shown in FIGS. 6D and 6E . . The reverse light emitting device LDr is connected in parallel between the first and second electrodes EL1 and EL2 together with the light emitting devices LD constituting the effective light sources, and is not connected to the light emitting devices LD. It may be connected between the first and second electrodes EL1 and EL2 in opposite directions. The reverse light emitting device LDr maintains an inactive state even when a predetermined driving voltage (eg, a forward driving voltage) is applied between the first and second electrodes EL1 and EL2 , and thus the reverse direction A current does not substantially flow through the light emitting element LDr.

The pixel circuit 144 may be connected to the scan line Si and the data line Dj of the corresponding pixel PXL. For example, when the pixel PXL is disposed in the i (i is a natural number)-th row and j (j is a natural number)-th column of the display area DA, the pixel circuit 144 of the pixel PXL is the display area It may be connected to the i-th scan line Si and the j-th data line Dj of (DA). In some embodiments, the pixel circuit 144 may include first and second transistors T1 and T2 and a storage capacitor Cst as shown in FIGS. 6A and 6B . However, the structure of the pixel circuit 144 is not limited to the embodiment illustrated in FIGS. 6A and 6B .

First, referring to FIG. 6A , the pixel circuit 144 may include first and second transistors T1 and T2 and a storage capacitor Cst.

A first terminal of the second transistor T2 (switching transistor) may be connected to the data line Dj, and a second terminal may be connected to the first node N1. Here, the first terminal and the second terminal of the second transistor T2 are different terminals. For example, if the first terminal is a source electrode, the second terminal may be a drain electrode. In addition, the gate electrode of the second transistor T2 may be connected to the scan line Si.

The second transistor T2 is turned on when a scan signal of a voltage (eg, a low voltage) capable of turning on the second transistor T2 is supplied from the scan line Si to the data line ( Dj) and the first node N1 are electrically connected. In this case, the data signal of the corresponding frame is supplied to the data line Dj, and accordingly, the data signal is transmitted to the first node N1. The data signal transferred to the first node N1 is charged in the storage capacitor Cst.

A first terminal of the first transistor T1 may be connected to a first driving power source VDD, and a second terminal may be electrically connected to a first electrode EL1 of each of the light emitting elements LD. can The gate electrode of the first transistor T1 may be connected to the first node N1 . The first transistor T1 controls the amount of driving current supplied to the light emitting devices LD in response to the voltage of the first node N1 .

One electrode of the storage capacitor Cst may be connected to the first driving power VDD, and the other electrode may be connected to the first node N1 . The storage capacitor Cst charges a voltage corresponding to the data signal supplied to the first node N1 and maintains the charged voltage until the data signal of the next frame is supplied.

In each of FIGS. 6A and 6B , a second transistor T2 for transferring a data signal to the inside of the pixel PXL, a storage capacitor Cst for storing the data signal, and a driving current corresponding to the data signal are applied. The pixel circuit 144 including the first transistor T1 for supplying the light emitting devices LD is illustrated.

However, the present invention is not limited thereto, and the structure of the pixel circuit 144 may be variously changed. For example, the pixel circuit 144 adjusts the emission time of the transistor device for compensating the threshold voltage of the first transistor T1 , the transistor device for initializing the first node N1 , and/or the light emitting devices LDs. Of course, other circuit elements such as at least one transistor element, such as a transistor element for controlling, or a boosting capacitor, etc., for boosting the voltage of the first node N1 may be further included.

Also, although transistors included in the pixel circuit 144, for example, the first and second transistors T1 and T2, are all P-type transistors in FIG. 6A , the present invention is not limited thereto. That is, at least one of the first and second transistors T1 and T2 included in the pixel circuit 144 may be changed to an N-type transistor.

Next, referring to FIGS. 1A to 4B , 5 , and 6B , according to an embodiment of the present invention, the first and second transistors T1 and T2 may be implemented as N-type transistors. The pixel circuit 144 illustrated in FIG. 6B has a configuration and operation similar to that of the pixel circuit 144 of FIG. 6A except for a change in connection positions of some components due to a change in transistor type. Accordingly, a description thereof will be brief.

In an embodiment of the present invention, the pixel circuit 144 illustrated in FIG. 6B may include first and second transistors T1 and T2 formed of N-type transistors and a storage capacitor Cst. When the first and second transistors T1 and T2 are formed of N-type transistors, the light emitting unit is used to stabilize the storage capacitor Cst that charges a voltage corresponding to the data signal supplied to the first node N1. The EMU may be connected between the first driving power VDD and the pixel circuit 144 . However, the present invention is not limited thereto, and according to embodiments, the light emitting unit EMU illustrated in FIG. 6B may be connected between the pixel circuit 144 and the second driving power VSS. In one embodiment of the present invention, the configuration of the pixel circuit 144 is not limited to the embodiment shown in FIGS. 6A and 6B . For example, the pixel circuit 144 may be configured as in the embodiment illustrated in FIGS. 6C and 6D .

The pixel circuit 144 may be connected to the scan line Si and the data line Dj of the pixel PXL, as shown in FIGS. 6C and 6D . For example, when the pixel PXL is disposed in the i-th row and the j-th column of the display area DA, the pixel circuit 144 of the corresponding pixel PXL is the i-th scan line Si of the display area DA. and a j-th data line Dj.

Also, according to an embodiment, the pixel circuit 144 may be further connected to at least one other scan line. For example, the pixel PXL disposed in the i-th row of the display area DA may be further connected to the i-1th scan line Si-1 and/or the i+1th scan line Si+1. have. Also, according to an embodiment, the pixel circuit 144 may be further connected to a third power source in addition to the first and second driving power sources VDD and VSS. For example, the pixel circuit 144 may also be connected to an initialization power line to which the initialization power Vint is applied.

The pixel circuit 144 may include first to seventh transistors T1 to T7 and a storage capacitor Cst.

One electrode, for example, a source electrode, of the first transistor T1 (driving transistor) may be connected to the first driving power source VDD via the fifth transistor T5, and another electrode, for example, a drain electrode. may be connected to one end of the light emitting devices LD via the sixth transistor T6. In addition, the gate electrode of the first transistor T1 may be connected to the first node N1 . The first transistor T1 has a driving current flowing between the first driving power VDD and the second driving power VSS via the light emitting devices LD in response to the voltage of the first node N1 . control

The second transistor T2 (switching transistor) may be connected between the j-th data line Dj connected to the pixel PXL and the source electrode of the first transistor T1 . In addition, the gate electrode of the second transistor T2 may be connected to the i-th scan line Si connected to the pixel PXL. The second transistor T2 is turned on when a scan signal of a gate-on voltage (eg, a low voltage) is supplied from the i-th scan line Si to connect the j-th data line Dj to the first transistor. It can be electrically connected to the source electrode of (T1). Accordingly, when the second transistor T2 is turned on, the data signal supplied from the j-th data line Dj is transferred to the first transistor T1 .

The third transistor T3 may be connected between the drain electrode of the first transistor T1 and the first node N1 . In addition, the gate electrode of the third transistor T3 may be connected to the i-th scan line Si. The third transistor T3 is turned on when the scan signal of the gate-on voltage is supplied from the i-th scan line Si to electrically connect the drain electrode of the first transistor T1 and the first node N1. can be connected to

The fourth transistor T4 may be connected between the first node N1 and an initialization power line to which the initialization power Vint is applied. In addition, the gate electrode of the fourth transistor T4 may be connected to the previous scan line, for example, the i-1 th scan line Si-1. The fourth transistor T4 is turned on when the scan signal of the gate-on voltage is supplied to the i-1 th scan line Si-1 to apply the voltage of the initialization power Vint to the first node N1. can be passed to Here, the initialization power Vint may have a voltage equal to or less than the lowest voltage of the data signal.

The fifth transistor T5 may be connected between the first driving power source VDD and the first transistor T1 . In addition, the gate electrode of the fifth transistor T5 may be connected to a corresponding emission control line, for example, the i-th emission control line Ei. The fifth transistor T5 may be turned off when the emission control signal of the gate-off voltage is supplied to the i-th emission control line Ei, and may be turned on in other cases.

The sixth transistor T6 may be connected between the first transistor T1 and one end of the light emitting devices LD. In addition, the gate electrode of the sixth transistor T6 may be connected to the i-th emission control line Ei. The sixth transistor T6 may be turned off when the emission control signal of the gate-off voltage is supplied to the i-th emission control line Ei, and may be turned on in other cases.

The seventh transistor T7 may be connected between one end of the light emitting devices LD and a power line to which the initialization power Vint is applied, for example, an initialization power line. And, the gate electrode of the seventh transistor T7 may be connected to any one of the scan lines of the next stage, for example, the i+1th scan line Si+1. The seventh transistor T7 is turned on when the scan signal of the gate-on voltage is supplied to the i+1th scan line Si+1 to apply the voltage of the initialization power Vint to the light emitting devices LD. It can be supplied to one end of

The storage capacitor Cst may be connected between the first driving power VDD and the first node N1 . The storage capacitor Cst may store a data signal supplied to the first node N1 and a voltage corresponding to the threshold voltage of the first transistor T1 in each frame period.

In FIGS. 6C and 6D , the transistors included in the pixel circuit 144, for example, the first to seventh transistors T1 to T7 are all P-type transistors, but the present invention is not limited thereto. does not For example, at least one of the first to seventh transistors T1 to T7 may be changed to an N-type transistor.

In one embodiment of the present invention, the configuration of the pixel circuit 144 is not limited to the embodiment shown in FIGS. 6A to 6D . For example, the pixel circuit 144 may be configured as in the embodiment illustrated in FIG. 6E .

The pixel circuit 144 may be further connected to the control line CLi and the sensing line SENj as shown in FIG. 6E . For example, the pixel circuit 144 of the pixel PXL disposed in the i-th row and j-th column of the display area DA includes the i-th control line CLi and the j-th sensing line SENj of the display area DA. can be connected to The above-described pixel circuit 144 may further include a third transistor T3 in addition to the first and second transistors T1 and T2 illustrated in FIGS. 6A and 6B .

The third transistor T3 is connected between the first transistor T1 and the sensing line SENj. For example, one electrode of the third transistor T3 is connected to one terminal (eg, a source electrode) of the first transistor T1 connected to the first electrode EL1, and the third transistor T3 The other electrode of may be connected to the sensing line SENj. Meanwhile, when the sensing line SENj is omitted, the gate electrode of the third transistor T3 may be connected to the data line Dj.

In some embodiments, the gate electrode of the third transistor T3 is connected to the control line CLi. Meanwhile, when the control line CLi is omitted, the gate electrode of the third transistor T3 may be connected to the scan line Si. The third transistor T3 is turned on by a control signal of a gate-on voltage (eg, high level) supplied to the control line CLi for a predetermined sensing period, and thus the sensing line SENj and the first transistor T3 are turned on. The transistor T1 is electrically connected.

According to an embodiment, the sensing period may be a period for extracting characteristic information (eg, the threshold voltage of the first transistor T1 ) of each of the pixels PXL disposed in the display area DA. During the above-described sensing period, a predetermined reference voltage for turning on the first transistor T1 is supplied to the first node N1 through the data line Dj and the second transistor T2, or each pixel The first transistor T1 may be turned on by connecting PXL to a current source or the like. In addition, the first transistor T1 may be connected to the sensing line SENj by supplying a gate-on voltage control signal to the third transistor T3 to turn on the third transistor T3 . Accordingly, characteristic information of each pixel PXL including the threshold voltage of the first transistor T1 may be extracted through the above-described sensing line SENj. The extracted characteristic information may be used to convert image data so that characteristic deviation between the pixels PXL is compensated.

Meanwhile, although the embodiment in which all of the first to third transistors T1 to T3 are N-type transistors is described in FIG. 6E , the present invention is not limited thereto. For example, at least one of the first to third transistors T1 to T3 may be changed to a P-type transistor. Also, although FIG. 6E describes an embodiment in which the light emitting unit EMU is connected between the pixel circuit 144 and the second driving power VSS, the light emitting unit EMU is connected to the first driving power VDD and It may be connected between the pixel circuits 144 .

6A to 6E illustrate an embodiment in which all of the light emitting elements LD constituting each light emitting unit EMU are connected in parallel, but the present invention is not limited thereto. According to an embodiment, the light emitting unit EMU may be configured to include at least one serial stage including a plurality of light emitting devices LD connected in parallel to each other. That is, the light emitting unit EMU may be configured in a series/parallel mixed structure.

The structure of the pixel PXL applicable to the present invention is not limited to the embodiments illustrated in FIGS. 6A to 6E , and the pixel may have various structures. Also, in another embodiment of the present invention, each pixel PXL may be configured inside a passive light emitting display device or the like. In this case, the pixel circuit 144 is omitted, and both ends of the light emitting devices LD included in the light emitting unit EMU have scan lines Si-1, Si, and Si+1, respectively, and data lines Dj. ), the first power line PL1 to which the first driving power VDD is applied, the second power line PL2 to which the second driving power VSS is applied, and/or a predetermined control line may be directly connected. .

7 is a plan view schematically illustrating only some signal lines transmitting a predetermined signal to each of the pixels and pads connected thereto in the display device illustrated in FIG. 5 .

For convenience of illustration, only signal lines for aligning the light emitting devices LD in each of the pixels PXL are illustrated in FIG. 7 .

1A to 5 and 7 , the display device may include a substrate SUB including a display area DA and a non-display area NDA. Here, since the substrate SUB corresponds to the same configuration as the substrate SUB described with reference to FIG. 5 , a detailed description thereof will be omitted.

In the display area DA, first to fourth electrodes EL1 to EL4 and first to fourth connection lines CL1 to CL4 for applying an alignment signal (or alignment voltage) to each pixel PXL are provided. This can be placed

Each of the first to fourth electrodes EL1 to EL4 may have a bar shape extending in one direction, for example, the second direction DR2 in the display area DA. However, the present invention is not limited thereto, and according to embodiments, each of the first to fourth electrodes EL1 to EL4 may be electrically insulated from adjacent electrodes in various directions within a range (or limit). It may have an extended shape.

The first to fourth connecting wires CL1 to CL4 may have a bar shape extending along the first direction DR1 crossing the second direction DR2 in the display area DA, The extending direction of the first to fourth connection lines CL1 to CL4 is not limited to the above-described exemplary embodiment.

In one embodiment of the present invention, one of the first to fourth electrodes EL1 to EL4 and one of the first to fourth connecting wires CL1 to CL4 may be integrally provided. have. For example, the first electrode EL1 is provided integrally with the first connection line CL1 , the second electrode EL2 is provided integrally with the second connection line CL2 , and the third electrode EL3 is The third connection line CL3 may be provided integrally, and the fourth electrode EL4 may be provided integrally with the fourth connection line CL4 .

The first electrode EL1 and the first connection line CL1 extending in different directions and provided integrally may have a mesh shape in the display area DA. The second electrode EL2 and the second connection line CL2 extending in different directions and provided integrally may have a mesh shape in the display area DA. Also, the third electrode EL3 and the third connection line CL3 extending in different directions and provided integrally may have a mesh shape in the display area DA. Additionally, the fourth electrode EL4 and the fourth connection line CL4 extending in different directions and provided integrally may have a mesh shape in the display area DA.

The pad part PD connected to the first to fourth electrodes EL1 to EL4 and the first to fourth connection lines CL1 to CL4 may be disposed in the non-display area NDA. The pad part PD may include first to fourth pad parts PD1 to PD4.

The first pad part PD1 is electrically connected to the first connection line CL1 and the first electrode EL1 to receive a predetermined signal (or voltage), for example, a first alignment signal (or a first alignment voltage). It may be applied to the first connection line CL1 and the first electrode EL1 . The second pad part PD2 is electrically connected to the second connection line CL2 and the second electrode EL2 to receive a predetermined signal (or voltage), for example, a second alignment signal (or second alignment voltage). It may be applied to the second connection line CL2 and the second electrode EL2 . The third pad part PD3 is electrically connected to the third connection line CL3 and the third electrode EL3 to receive a predetermined signal (or voltage), for example, a third alignment signal (or third alignment voltage). It may be applied to the third connection line CL3 and the third electrode EL3 . The fourth pad part PD4 is electrically connected to the fourth connection line CL4 and the fourth electrode EL4 to receive a predetermined signal (or voltage), for example, a fourth alignment signal (or a fourth alignment voltage). It may be applied to the fourth connection line CL4 and the fourth electrode EL4 .

The above-described first to fourth alignment signals (or alignment voltages) may have different voltage levels, but the present invention is not limited thereto, and some alignment signals among the first to fourth alignment signals may have different voltage levels. The remaining alignment signals (or alignment voltages) may have different voltage levels with the same voltage level. Also, among the first to fourth alignment signals, the first and third alignment signals may have the same voltage level, and the second and fourth alignment signals may have the same voltage level.

As a corresponding alignment signal from each of the first to fourth pad parts PD1 to PD4 is applied to each of the first to fourth electrodes EL1 to EL4, the first to fourth electrodes EL1 to EL4 An electric field may be formed therebetween to align the light emitting devices LD in the pixel area PXA of each of the pixels PXL.

After the light emitting devices LD are aligned, the first to fourth pad parts PD1 to PD4 apply corresponding driving power to each of the first to fourth electrodes EL1 to EL4 to thereby apply a corresponding driving power to the pixel area PXA. It is possible to drive the light emitting devices LD aligned with the . As an example, the first pad unit PD1 applies the first driving power (refer to VDD of FIGS. 6A to 6E ) set to a high potential level to the first electrode EL1 , and the second pad unit PD2 has a low voltage level. A second driving power (refer to VSS in FIGS. 6A to 6E ) set to a potential level is applied to the second electrode EL2 , and the third pad unit PD3 applies the first driving power VDD to the third electrode ( EL3), and the fourth pad part PD4 may apply the second driving power VSS to the fourth electrode EL4.

FIG. 8 is an enlarged plan view of part EA of FIG. 7 schematically illustrating one pixel among the pixels shown in FIG. 5 , and FIGS. 9A to 9C are cross-sectional views taken along line I to I' of FIG. 8 , and FIG. 10 is a cross-sectional view taken along the line II to II' of FIG. 8, and FIG. 11 is a cross-sectional view corresponding to the line II to II' of FIG. 8 as an implementation of the first bank pattern shown in FIG. 10 according to another embodiment, 12 is a cross-sectional view of the display element shown in FIG. 11 , which is implemented according to another embodiment, and is a cross-sectional view taken along line II to II′ of FIG. 8 .

The pixel shown in FIG. 8 may be any one of the pixels shown in each of FIGS. 6A to 6E .

In FIG. 8 , the transistors connected to the light emitting devices LD and the signal lines connected to the transistors are omitted for convenience.

8 to 12, each electrode is shown as a single electrode layer and each insulating layer is shown as only a single insulating layer. However, the structure of one pixel PXL is simplified, but the present invention is not limited thereto. no.

Additionally, in one embodiment of the present invention, "formed and/or provided on the same layer" means formed in the same process, and "formed and/or provided on a different layer" means formed in different processes. can mean

In addition, in an embodiment of the present invention, the term “connection” between two components may mean that both an electrical connection and a physical connection are used inclusively.

1A to 12 , a display device according to an exemplary embodiment may include a substrate SUB, a wiring unit, and a plurality of pixels PXL.

The substrate SUB may include a transparent insulating material to allow light to pass therethrough. The substrate SUB may be a rigid substrate or a flexible substrate.

The rigid substrate may be, for example, one of a glass substrate, a quartz substrate, a glass ceramic substrate, and a crystalline glass substrate.

The flexible substrate may be one of a film substrate and a plastic substrate including a polymer organic material. For example, the flexible substrate may include polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyethersulfone, polyacrylate, and polyetherimide. ), polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, triacetate cellulose ( It may include at least one of triacetate cellulose) and cellulose acetate propionate.

The material applied to the substrate SUB may preferably have resistance (or heat resistance) to a high processing temperature during a manufacturing process of the display device.

The substrate SUB may include a display area DA including at least one pixel area PXA in which the pixel PXL is disposed, and a non-display area NDA disposed around the display area DA. .

The pixel area PXA in which each pixel PXL is disposed (or provided) may include a light emitting area from which light is emitted and a peripheral area surrounding the periphery of the light emitting area. In one embodiment of the present invention, the peripheral region may include a non-emission region from which light is not emitted.

The wiring unit may include a plurality of signal lines that transmit a signal (or voltage) to each pixel PXL. The signal lines are, for example, a scan line that transmits a scan signal to each pixel PXL (for example, refer to 'Si' in FIG. 6A ), and a data line that transmits a data signal to each pixel PXL (one For example, refer to 'Dj' of FIG. 6A ), a light emission control line that transmits a light emission control signal to each pixel PXL (for example, refer to 'Ei' of FIG. 6C ), and the like. However, the present invention is not limited thereto, and according to embodiments, the wiring unit may further include signal lines for transmitting other signals in addition to the above-described signal lines.

Each pixel PXL is provided on the substrate SUB and includes a pixel circuit part PCL including a pixel circuit (refer to '144' in FIGS. 6A to 6E ) and a display element part including a plurality of light emitting devices LD. (DPL) may be included. The light emitting devices LD may be located in the light emitting area provided in the pixel area PXA of each pixel PXL.

For convenience, the pixel circuit unit PCL will be described first, and then the display element unit DPL will be described.

The pixel circuit unit PCL may include a buffer layer BFL, a pixel circuit 144 , and a passivation layer PSV.

The buffer layer BFL may prevent impurities from diffusing into the transistor T included in the pixel circuit 144 . The buffer layer BFL may include an inorganic insulating layer including an inorganic material. For example, the buffer layer BFL may include at least one of a metal oxide such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and AlOx. The buffer layer BFL may be provided as a single layer, or may be provided as a multilayer of at least a double layer. When the buffer layer BFL is provided as a multilayer, each layer may be formed of the same material or different materials. The buffer layer BFL may be omitted depending on the material and process conditions of the substrate SUB.

The pixel circuit 144 may include at least one transistor T and a storage capacitor Cst. Here, the transistor T may include a driving transistor Tdr for controlling driving currents of the light emitting devices LD and a switching transistor Tsw connected to the driving transistor Tdr. However, the present invention is not limited thereto, and the pixel circuit 144 may include circuit elements performing other functions in addition to the driving transistor Tdr and the switching transistor Tsw. In the following embodiments, when one of the driving transistor Tdr and the switching transistor Tsw is arbitrarily named or the driving transistor Tdr and the switching transistor Tsw are collectively named, the transistor T or the transistors ( It is called T).

Each of the driving transistor Tdr and the switching transistor Tsw may include a transistor semiconductor pattern SCL, a gate electrode GE, a first terminal SE, and a second terminal DE. The first terminal SE may be one of a source electrode and a drain electrode, and the second terminal DE may be the other electrode. For example, when the first terminal SE is a source electrode, the second terminal DE may be a drain electrode.

The transistor semiconductor pattern SCL may be provided and/or formed on the buffer layer BFL. The transistor semiconductor pattern SCL may include a first contact area contacting the first terminal SE and a second contact area contacting the second terminal DE. A region between the first contact region and the second contact region may be a channel region. The transistor semiconductor pattern SCL may be a semiconductor pattern made of polysilicon, amorphous silicon, oxide semiconductor, or the like. The channel region is a semiconductor pattern that is not doped with impurities, and may be an intrinsic semiconductor. The first contact region and the second contact region may be semiconductor patterns doped with impurities.

The gate electrode GE may be provided and/or formed on the transistor semiconductor pattern SCL with the gate insulating layer GI interposed therebetween.

The gate insulating layer GI may be an inorganic insulating layer including an inorganic material. For example, the gate insulating layer GI may include at least one of a metal oxide such as silicon nitride (SiNx), silicon oxide (SiOx), silicon oxynitride (SiON), and AlOx. However, the material of the gate insulating layer GI is not limited to the above-described embodiments. In some embodiments, the gate insulating layer GI may be formed of an organic insulating layer including an organic material. The gate insulating layer GI may be provided as a single layer, or may be provided as a multilayer of at least double layers.

Each of the first terminal SE and the second terminal DE has a first contact region and a second contact region of the transistor semiconductor pattern SCL through a contact hole penetrating the first interlayer insulating layer ILD1 and the gate insulating layer GI. area can be touched.

In the above-described embodiment, the first and second terminals SE and DE of the driving transistor Tdr and the switching transistor Tsw, respectively, have been described as separate electrodes electrically connected to the transistor semiconductor pattern SCL, The present invention is not limited thereto. In example embodiments, the first terminal SE of each of the driving transistor Tdr and the switching transistor Tsw may be one of the first and second contact regions adjacent to the channel region of the corresponding transistor semiconductor pattern SCL. The second terminal DE of each of the driving transistor Tdr and the switching transistor Tsw may be the remaining region of the first and second contact regions adjacent to the channel region of the corresponding transistor semiconductor pattern SCL. have. In this case, the second terminal DE of each of the driving transistor Tdr and the switching transistor Tsw is connected to the light emitting elements LD of the corresponding pixel PXL through separate connection means including a bridge electrode or a contact electrode. can be electrically connected to.

In one embodiment of the present invention, the transistors T included in the pixel circuit 144 may be configured as LTPS thin film transistors, but the present invention is not limited thereto. may be configured. In addition, although the case where the transistors T are thin film transistors having a top gate structure has been described as an example, the present invention is not limited thereto. In some embodiments, the transistors T may be thin film transistors having a bottom gate structure.

The driving voltage line DVL may be provided and/or formed on the first interlayer insulating layer ILD1 , but the present invention is not limited thereto. According to embodiments, any of the insulating layers included in the pixel circuit unit PCL may be provided. It may be provided on one insulating film. A second driving power (refer to 'VSS' in FIGS. 6A to 6E ) may be applied to the driving voltage line DVL. In an embodiment of the present invention, the driving voltage line DVL may be the second power line PL2 to which the second driving power VSS is applied in each of FIGS. 6A to 6E .

A second interlayer insulating layer ILD2 may be provided and/or formed on the transistors T and the driving voltage line DVL.

The second interlayer insulating layer ILD2 may cover the transistors T and the driving voltage line DVL. The second interlayer insulating layer ILD2 may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. In some embodiments, the second interlayer insulating layer ILD2 may include the same material as the first interlayer insulating layer ILD1 , but the present invention is not limited thereto. The second interlayer insulating layer ILD2 may be provided as a single layer, or may be provided as a multilayer of at least a double layer. The second interlayer insulating layer ILD2 may include a first contact hole CH1 exposing a portion of the driving transistor Tdr and a second contact hole CH2 exposing a portion of the driving voltage line DVL.

First to fourth electrodes EL1 to EL4 may be provided and/or formed on the second interlayer insulating layer ILD2 . The first to fourth electrodes EL1 to EL4 may be spaced apart from each other on the second interlayer insulating layer ILD2 .

Each of the first to fourth electrodes EL1 to EL4 may extend in the second direction DR2 , and each pixel PXL and adjacent pixels PXL positioned in the same pixel column as each pixel PXL. PXL) may be provided in common.

The first electrode EL1 and the second electrode EL2 are spaced apart from each other with a predetermined interval therebetween, the second electrode EL2 and the third electrode EL3 are spaced apart from each other with a predetermined interval therebetween, and the third electrode ( EL3 and the fourth electrode EL4 may be spaced apart from each other with a predetermined interval therebetween. In the pixel area PXA of each pixel PXL, between the first electrode EL1 and the second electrode EL2 , between the second electrode EL2 and the third electrode EL3 , and the third electrode EL3 ) and the fourth electrode EL4 may have the same distance. However, the present invention is not limited thereto, and in some embodiments, between the first electrode EL1 and the second electrode EL2, between the second electrode EL2 and the third electrode EL3, and the third electrode ( The distance between the EL3 and the fourth electrode EL4 may be different from each other. A distance between two adjacent electrodes among the first to fourth electrodes EL1 to EL4 may be smaller than the length L of each of the light emitting devices LD, but the present invention is not limited thereto.

In one embodiment of the present invention, each of the first to fourth electrodes EL1 to EL4 is an alignment electrode for aligning the light emitting elements LD in the pixel area PXA of each of the pixels PXL (or alignment wiring). In some embodiments, the first to fourth electrodes EL1 to EL4 are provided on the second interlayer insulating layer ILD2 and are connected to the transistors T and the transistors T included in the pixel circuit unit PCL. By blocking the electric field induced from the signal lines, it is possible to prevent the electric field from affecting the alignment and/or driving of the light emitting elements LD included in the display element unit DPL. In addition, according to another embodiment, each of the first to fourth electrodes EL1 to EL4 includes configurations to which a predetermined signal (or voltage) is applied among configurations included in the display element unit DPL, for example, A vertical cap coupling (eg, a parasitic capacitor c) may be formed between the intermediate layer CTL and the light emitting devices LD may be aligned in a desired region.

The above-described first to fourth electrodes EL1 to EL4 are provided on the second interlayer insulating layer ILD2 and may include the same material. For example, the first to fourth electrodes EL1 to EL4 may include molybdenum (Mo), tungsten (W), aluminum neodymium (AlNd), titanium (Ti), aluminum (Al), silver (Ag), and alloys thereof. In order to form a single film alone or a mixture thereof selected from the group consisting of or to reduce wiring resistance, it can be formed in a double film or multi-layer structure of low-resistance materials such as molybdenum (Mo), aluminum (Al) or silver (Ag) .

In the above-described embodiment, it has been described that the first to fourth electrodes EL1 to EL4 are provided on the same layer, but the present invention is not limited thereto. According to an exemplary embodiment, some of the first to fourth electrodes EL1 to EL4 and the remaining electrodes may be provided on different layers.

A passivation layer PSV may be provided and/or formed on the first to fourth electrodes EL1 to EL4 .

The passivation layer PSV may be provided in a form including an organic insulating layer, an inorganic insulating layer, or an organic insulating layer disposed on the inorganic insulating layer. Here, the inorganic insulating layer may include at least one of a metal oxide such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), and AlOx. The organic insulating layer may include an organic insulating material capable of transmitting light. The organic insulating film is, for example, acrylic resin (polyacrylates resin), epoxy resin (epoxy resin), phenolic resin (phenolic resin), polyamides resin (polyamides resin), polyimide resin (polyimides rein), unsaturated polyester At least one of unsaturated polyesters resin, poly-phenylen ethers resin, poly-phenylene sulfides resin, and benzocyclobutene resin can do.

In an embodiment of the present invention, the passivation layer PSV includes a first contact hole CH1 corresponding to the first contact hole CH1 of the second interlayer insulating layer ILD2 and a first contact hole CH1 of the second interlayer insulating layer ILD2. A second contact hole CH2 corresponding to the second contact hole CH2 may be included. Accordingly, a portion of the second terminal DE of the driving transistor Tdr and a portion of the driving voltage line DVL may be exposed to the outside, respectively.

A display element part DPL may be provided on the passivation layer PSV.

The display element unit DPL may include first and second bank patterns BNK1 and BNK2 , an intermediate layer CTL, light emitting elements LD, and a contact electrode CNE.

The first bank pattern BNK1 changes the surface profile of the intermediate layer CTL by supporting the intermediate layer CTL so that light emitted from the light emitting devices LD travels in the image display direction of the display device. can

The first bank pattern BNK1 may be provided and/or formed between the passivation layer PSV and the intermediate layer CTL in the pixel area PXA of each pixel PXL. The first bank pattern BNK1 may include an inorganic insulating layer made of an inorganic material or an organic insulating layer made of an organic material. In some embodiments, the first bank pattern BNK1 may include a single-layered organic insulating layer and/or a single-layered inorganic insulating layer, but the present invention is not limited thereto. According to an exemplary embodiment, the first bank pattern BNK1 may be provided in the form of a multilayer in which at least one organic insulating layer and at least one inorganic insulating layer are stacked. However, the material of the first bank pattern BNK1 is not limited to the above-described embodiments, and according to embodiments, the first bank pattern BNK1 may include a conductive material.

The first bank pattern BNK1 may have a trapezoidal cross-section that becomes narrower toward the top from one surface of the passivation layer PSV, but the present invention is not limited thereto. According to an embodiment, as shown in FIG. 11 , the first bank pattern BNK1 has a semi-elliptical shape, a semi-circular shape (or a semi-spherical shape), etc., in which the width becomes narrower from the one surface of the passivation layer PSV toward the upper side. It may include a curved surface having When viewed in cross section, the shape of the first bank pattern BNK1 is not limited to the above-described embodiments and may be variously changed within a range capable of improving the efficiency of light emitted from each of the light emitting devices LD. have. The adjacent first bank patterns BNK1 may be disposed on the same plane on the passivation layer PSV and may have the same height (or thickness).

The first bank pattern BNK1 may have a bar shape extending in one direction, for example, the second direction DR2 (vertical direction) when viewed in a plan view, but the present invention is not limited thereto. It can be changed into various shapes.

A second bank pattern BNK2 may be provided in a peripheral area of the pixel area PXA in which each pixel PXL is disposed.

The second bank pattern BNK2 may surround at least one side of a peripheral area included in the pixel area PXA of each of the pixels PXL. The second bank pattern BNK2 is a structure that defines (or partitions) each of the pixels PXL and the emission areas of each of the pixels PXL adjacent thereto, and may be, for example, a pixel defining layer. The second bank pattern BNK2 is configured to include at least one light blocking material and/or a reflective material to prevent a light leakage defect in which light (or light) leaks between each pixel PXL and pixels PXL adjacent thereto. can be prevented In some embodiments, a reflective material layer may be formed on the second bank pattern BNK2 to further improve the efficiency of light emitted from each pixel PXL. The second bank pattern BNK2 may be formed on a different layer or on the same layer as the first bank pattern BNK1 according to an exemplary embodiment.

The intermediate layer CTL is provided in the pixel area PXA of each pixel PXL and may extend in one direction. For example, the intermediate layer CTL may extend in an extension direction of each of the first to fourth electrodes EL1 to EL4 , that is, in a direction parallel to the second direction DR2 . The intermediate layer CTL may be provided and/or formed on the first bank pattern BNK1 to overlap each of the first to fourth electrodes EL1 to EL4 when viewed in a plan view.

In one embodiment of the present invention, the intermediate layer (CTL, hereinafter referred to as 'first intermediate layer') overlapping the first electrode EL1 and the intermediate layer CTL overlapping the second electrode EL2, hereinafter ' between the second intermediate layer '), between the second intermediate layer (CTL) and the intermediate layer (CTL, hereinafter referred to as 'third intermediate layer') overlapping the third electrode EL3, the third intermediate layer ( CTL) and the intermediate layer (CTL, hereinafter referred to as a 'fourth intermediate layer') overlapping the fourth electrode EL4 may have the same spacing. However, the present invention is not limited thereto, and according to an embodiment, between the first intermediate layer (CTL) and the second intermediate layer (CTL), between the second intermediate layer (CTL) and the third intermediate layer (CTL), A gap may be different between the third intermediate layer CTL and the fourth intermediate layer CTL. In an embodiment of the present invention, a distance between two adjacent intermediate layers CTL may be smaller than a length L of each of the light emitting devices LD, but the present invention is not limited thereto. When viewed in a plan view, the first intermediate layer CTL, the second intermediate layer CTL, the third intermediate layer CTL, and the fourth intermediate layer CTL are arranged in the order along the first direction DR1. can

The intermediate layer CTL may be provided and/or formed on the first bank pattern BNK1 to have a surface profile corresponding to the shape of the first bank pattern BNK1 . For example, the intermediate layer CTL may include a protruding portion corresponding to the first bank pattern BNK1 and a flat portion corresponding to the passivation layer PSV.

In an embodiment of the present invention, the intermediate layer CTL may be made of a material (or material) having a constant reflectance in order to allow light emitted from each of the light emitting elements LD to travel in the image display direction of the display device. have. For example, the intermediate layer CTL may be formed of a conductive material (or material) having a constant reflectance. The conductive material (or material) may include an opaque metal advantageous for reflecting light emitted from the light emitting elements LD in an image display direction of the display device. The opaque metal may include, for example, a metal such as Ag, Mg, Al, Pt, Pd, Au, Ni, Nd, Ir, Cr, Ti, or alloys thereof. According to an embodiment, the intermediate layer (CTL) may include a transparent conductive material (or material). The transparent conductive material may include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium tin zinc oxide (ITZO), and a conductive polymer such as PEDOT. When the intermediate layer CTL includes a transparent conductive material (or material), a separate conductive layer made of an opaque metal for reflecting the light emitted from the light emitting elements LD in the image display direction of the display device is additionally may be included. However, the material of the intermediate layer CTL is not limited to the above-described materials.

In addition, each of the intermediate layers CTL may be provided and/or formed as a single layer, but the present invention is not limited thereto. According to an embodiment, the intermediate layer CTL may be provided and/or formed as a multilayer in which at least two or more materials of metals, alloys, conductive oxides, and conductive polymers are stacked. The intermediate layer CTL may be formed of at least a double layer or multiple layers in order to minimize distortion due to signal delay when a predetermined signal (or voltage) is transmitted to both ends of each of the light emitting devices LD. For example, the intermediate layer CTL may be formed of a multilayer sequentially stacked in the order of ITO/Ag/ITO.

As described above, since the intermediate layer CTL has a surface profile corresponding to the shape of the first bank pattern BNK1 disposed thereunder, light emitted from each of the light emitting devices LD is emitted from the intermediate layer CTL. ) and may further progress in the image display direction of the display device. Accordingly, the efficiency of light emitted from each of the light emitting devices LD may be further improved.

The first bank pattern BNK1 and the intermediate layer CTL are reflective members for improving light output efficiency of the light emitting devices LD by allowing the light emitted from the light emitting devices LD to travel in the image display direction of the display device. can function.

In an embodiment of the present invention, the first intermediate layer CTL is disposed to correspond to the first electrode EL1 , the second intermediate layer CTL is disposed to correspond to the second electrode EL2 , and the second intermediate layer CTL is disposed to correspond to the second electrode EL2 , The third intermediate layer CTL may be disposed to correspond to the third electrode EL3 , and the fourth intermediate layer CTL may be disposed to correspond to the fourth electrode EL4 . When viewed in a plan view, the first intermediate layer CTL, the first bank pattern BNK, and the first electrode EL1 may overlap each other. When viewed in a plan view, the second intermediate layer CTL, the first bank pattern BNK1 , and the second electrode EL2 may overlap each other. When viewed in a plan view, the third intermediate layer CTL, the first bank pattern BNK1 , and the third electrode EL3 may overlap each other. When viewed in a plan view, the fourth intermediate layer CTL, the first bank pattern BNK1 , and the fourth electrode EL4 may overlap each other.

In an embodiment of the present invention, after the intermediate layer CTL is disposed in the pixel area PXA of each pixel PXL, a predetermined alignment signal is applied to each of the first to fourth electrodes EL1 to EL4 . (or alignment voltage) may be applied. When a predetermined alignment signal is applied to each of the first to fourth electrodes EL1 to EL4 , each of the first to fourth electrodes EL1 to EL4 is an alignment electrode (or alignment wiring).

The first electrode EL1 may receive a first alignment signal (or a first alignment voltage) to function as a first alignment electrode (or a first alignment line), and the second electrode EL2 may receive a second alignment signal ( Alternatively, it may receive the second alignment voltage) to function as the second alignment electrode (or the second alignment line), and the third electrode EL3 receives the third alignment signal (or the third alignment voltage) to receive the third alignment It may function as an electrode (or a third alignment line), and the fourth electrode EL4 may receive a fourth alignment signal (or a fourth alignment voltage) to function as a fourth alignment electrode (or a fourth alignment line). have.

When a corresponding alignment signal is applied to each of the first to fourth electrodes EL1 to EL4 , the second electrode EL2 and the third electrode EL3 are between the first electrode EL1 and the second electrode EL2 . An electric field may be formed therebetween and between the third electrode EL3 and the fourth electrode EL4 , respectively. The light emitting devices LD may be aligned and/or provided in the pixel area PXA of each pixel PXL by an electric field formed between two adjacent electrodes. For example, the light emitting devices LD may be aligned and/or provided between two adjacent intermediate layers CTL along the length L direction of each of the light emitting devices LD.

In one embodiment of the present invention, the alignment applied to each of the first to fourth electrodes EL1 to EL4 in the step of aligning the light emitting elements LD to the pixel area PXA of each pixel PXL By controlling a signal (or an alignment voltage) or forming a magnetic field, it is possible to control the light emitting elements LD supplied to the pixel area PXA to be aligned to be relatively biased.

In an embodiment of the present invention, the first intermediate layer CTL may include the first protrusion PRT1 . The first protrusion PRT1 is provided integrally with the first intermediate layer CTL, and may be branched from the first intermediate layer CTL in the first direction DR1 . The first protrusion PRT1 may be an area of the first intermediate layer CTL. The fourth intermediate layer CTL may include the second protrusion PRT2 . The second protrusion PRT2 may be provided integrally with the fourth intermediate layer CTL and may be branched from the fourth intermediate layer CTL in the first direction DR1 . The second protrusion PRT2 may be an area of the fourth intermediate layer CTL.

The first protrusion PRT1 may be connected to a part of the pixel circuit unit PCL, for example, the driving transistor Tdr, through the first contact hole CH1 passing through the passivation layer PSV and the second interlayer insulating layer ILD2. can Accordingly, a predetermined signal (or voltage) applied to the driving transistor Tdr may be transferred to the first intermediate layer CTL. The second protrusion PRT2 is connected to a part of the pixel circuit unit PCL, for example, the driving voltage line DVL, through the second contact hole CH2 passing through the passivation layer PSV and the second interlayer insulating layer ILD2. can be connected Accordingly, a predetermined signal (or voltage) applied to the driving voltage line DVL may be transferred to the fourth intermediate layer CTL.

In the above-described exemplary embodiment, the fourth intermediate layer CTL is connected to the driving voltage line DVL through the second contact hole CH2 penetrating the passivation layer PSV and the second interlayer insulating layer ILD2 to be connected to the driving voltage line. Although it has been described that a predetermined signal (or voltage) applied to the DVL is transferred to the fourth intermediate layer CTL, the present invention is not limited thereto. In some embodiments, the fourth intermediate layer CTL may be connected to the fourth electrode EL4 through the second contact hole CH2 penetrating only the passivation layer PSV as shown in FIG. 9C . In this case, a predetermined signal (or voltage), for example, the second driving power VSS described with reference to FIGS. 6A to 6E may be applied to the fourth electrode EL4 . When the fourth intermediate layer CTL is directly connected to the fourth electrode EL4 , a predetermined signal (or voltage) applied to the fourth electrode EL4 may be directly transferred to the fourth intermediate layer CTL. . When the fourth intermediate layer CTL is connected to the fourth electrode EL4 through the second contact hole CH2 , the driving voltage line DVL uses a predetermined signal (or different from the second driving power VSS). voltage) can be applied.

Each of the light emitting devices LD may be a light emitting device using a material having an inorganic crystal structure, for example, having a size as small as a nano-scale to a micro-scale. For example, each of the light emitting devices LD may be a micro light emitting device manufactured by an etching method or a micro light emitting device manufactured by a growth method. However, the type, size, shape, etc. of the light emitting devices LD may be variously changed. At least two to tens of light emitting devices LD may be arranged and/or provided in the light emitting area of each pixel PXL, but the number of light emitting devices LD is not limited thereto. According to an embodiment, the number of light emitting devices LD arranged and/or provided in the light emitting area of each pixel PXL may be variously changed.

Each of the light emitting devices LD may be disposed between two intermediate layers CTL adjacent to each other in a first direction DR1 parallel to a length L direction thereof. The light emitting devices LD include the first light emitting devices LD1 , the second intermediate layer CTL and the third intermediate layer CTL disposed between the first intermediate layer CTL and the second intermediate layer CTL. It may include second light emitting devices LD2 disposed therebetween, and third light emitting devices LD3 disposed between the third intermediate layer CTL and the fourth intermediate layer CTL. In the following embodiments, when one of the first to third light emitting devices LD1 to LD3 is arbitrarily named or when the first to third light emitting devices LD1 to LD3 are collectively named, the light emitting devices are It is called (LD).

In one embodiment of the present invention, each of the light emitting devices LD may emit any one of color light and/or white light. The light emitting devices LD may be provided in the form of being sprayed into a solution and may be injected into the pixel area PXA of each pixel PXL.

In one embodiment of the present invention, the light emitting devices LD may be input to the pixel area PXA of each pixel PXL through an inkjet printing method, a slit coating method, or other various methods. For example, the light emitting devices LD may be mixed with a volatile solvent and supplied to the pixel area PXA of each pixel PXL through an inkjet printing method or a slit coating method. At this time, when an alignment signal (or alignment voltage) corresponding to each of the first to fourth electrodes EL1 to EL4 positioned in the pixel area PXA of each pixel PXL is applied, the first to fourth electrodes An electric field may be formed between two adjacent electrodes in the fields EL1 to EL4.

After the light emitting elements LD are aligned, the solvent is evaporated or removed by other methods so that the light emitting elements LD are finally formed in the light emitting area included in the pixel area PXA of each pixel PXL. may be arranged and/or provided

The above-described light emitting devices LD may be provided and/or formed on the first insulating layer INS1 in the pixel area PXA of each pixel PXL.

The first insulating layer INS1 is formed and/or provided under each of the light emitting devices LD arranged and/or provided between the two intermediate layers CTL in the pixel area PXA of each pixel PXL. can be The first insulating layer INS1 fills a space between each of the light emitting devices LD and the passivation layer PSV to stably support the light emitting devices LD, and from the passivation layer PSV to the light emitting devices LD. departure can be prevented.

Also, the first insulating layer INS1 may expose one area of the intermediate layer CTL and cover the remaining area except for the one area. For example, the first insulating layer INS1 may include one region of the first intermediate layer CTL, one region of the second intermediate layer CTL, one region of the third intermediate layer CTL, and the fourth intermediate layer CTL. ) of the remaining area of the first intermediate layer (CTL), the remaining area of the second intermediate layer (CTL), the remaining area of the third intermediate layer (CTL), and the fourth intermediate layer (CTL). Each of the remaining areas may be covered.

The first insulating layer INS1 may include an inorganic insulating layer made of an inorganic material or an organic insulating layer made of an organic material. In one embodiment of the present invention, the first insulating layer INS1 may be formed of an inorganic insulating layer advantageous for protecting the light emitting devices LD from the pixel circuit unit PCL of each pixel PXL. This is not limited thereto. In some embodiments, the first insulating layer INS1 may be formed of an organic insulating layer advantageous for planarizing the supporting surfaces of the light emitting devices LD.

A second insulating layer INS2 may be provided and/or formed on each of the light emitting devices LD. The second insulating layer INS2 is provided and/or formed on the light emitting devices LD, respectively, to cover a portion of the upper surface of each of the light emitting devices LD, and both ends of each of the light emitting devices LD to the outside. can be exposed The second insulating layer INS2 may be formed as an independent insulating pattern in the pixel area PXA of each pixel PXL, but the present invention is not limited thereto.

The second insulating layer INS2 may be formed of a single layer or a multilayer, and may include an inorganic insulating layer including at least one inorganic material or an organic insulating layer including at least one organic material. The second insulating layer INS2 may further fix each of the light emitting devices LD aligned in the light emitting area EMA of each pixel PXL. In an embodiment of the present invention, the second insulating layer INS2 may include an inorganic insulating layer advantageous for protecting the active layer 12 of each of the light emitting devices LD from external oxygen and moisture. However, the present invention is not limited thereto. The second insulating layer INS2 may include an organic insulating layer including an organic material according to design conditions of a display device to which the light emitting elements LD are applied.

In one embodiment of the present invention, the second insulating layer INS2 is formed on the light emitting devices LD after alignment of the light emitting devices LD in the pixel area PXA of each pixel PXL is completed. , it is possible to prevent the light emitting devices LD from being separated from the aligned positions. When a gap (or space) exists between the first insulating layer INS1 and the light emitting devices LD before the formation of the second insulating layer INS2 , the gap is a process of forming the second insulating layer INS2 . may be filled with the second insulating layer INS2 . Accordingly, the second insulating layer INS2 may constitute an organic insulating layer advantageous for filling a gap between the first insulating layer INS1 and the light emitting devices LD.

In one embodiment of the present invention, the second insulating layer INS2 may be formed on each of the light emitting devices LD so that the active layer 12 of each of the light emitting devices LD does not come into contact with an external conductive material. have. The second insulating layer INS2 may cover only a portion of the surface of each of the light emitting devices LD and may expose both ends of each of the light emitting devices LD to the outside.

A contact electrode CNE may be provided and/or formed on the second insulating layer INS2 .

The contact electrode CNE may be formed of various transparent conductive materials. For example, the contact electrode CNE may include at least one of various transparent conductive materials including ITO, IZO, and ITZO, and may be substantially transparent or translucent to satisfy a predetermined light transmittance. However, the material of the contact electrode CNE is not limited to the above-described embodiments, and according to embodiments, the contact electrode CNE may be formed of various opaque conductive materials.

The contact electrode CNE is on the first contact electrode CNE1 provided on the first intermediate layer CTL, the second contact electrode CNE2 provided on the second intermediate layer CTL, and the third intermediate layer CTL It may include a third contact electrode CNE3 provided on , and a fourth contact electrode CNE4 provided on the fourth intermediate layer CTL.

The first contact electrode CNE1 may be directly disposed on an exposed region of the first intermediate layer CTL to be connected to the first intermediate layer CTL. In addition, the first contact electrode CNE1 may be disposed on one end of both ends of each of the first light emitting devices LD1 to be connected to the one end. Accordingly, a predetermined signal (or voltage) applied to the first intermediate layer CTL may be transmitted to one of both ends of each of the first light emitting devices LD1 through the first contact electrode CNE1 . have. When viewed in a plan view, the first contact electrode CNE1 may overlap one end of the first intermediate layer CTL and both ends of each of the first light emitting devices LD1 .

In the above-described embodiment, it has been described that the first contact electrode CNE1 is indirectly connected to the driving transistor Tdr of the pixel circuit unit PCL through the first intermediate layer CTL, but the present invention is not limited thereto. no. In some embodiments, the first contact electrode CNE1 may be connected to the driving transistor (CH1) through a first contact hole CH1 that sequentially passes through the passivation layer PSV and the second interlayer insulating layer ILD2, as shown in FIG. 9B . Tdr) may be directly connected. In this case, a predetermined signal (or voltage) applied to the driving transistor Tdr may be transmitted to one end of each of both ends of the first light emitting devices LD1 through the first contact electrode CNE1 .

The second contact electrode CNE2 may be directly disposed on an exposed region of the second intermediate layer CTL to be connected to the second intermediate layer CTL. Also, the second contact electrode CNE2 may be disposed on the other end of both ends of each of the first light emitting devices LD1 to be connected to the other end. Additionally, the second contact electrode CNE2 may be disposed on one end of both ends of each of the second light emitting devices LD2 and connected to the one end. When viewed in a plan view, the second contact electrode CNE2 may overlap the other end of both ends of each of the first light emitting elements LD1 and one end of both ends of each of the second light emitting elements LD2 . .

The first contact electrode CNE1 and the second contact electrode CNE2 may be spaced apart from each other. For example, the first contact electrode CNE1 and the second contact electrode CNE2 may be disposed on the second insulating layer INS2 to be spaced apart from each other with a predetermined interval therebetween.

The first contact electrode CNE1 and the second contact electrode CNE2 may be provided on the same layer, but the present invention is not limited thereto. According to an embodiment, the first contact electrode CNE1 and the second contact electrode CNE2 may be provided on different layers. For example, as shown in FIG. 12 , the first contact electrode CNE1 may be provided on the second insulating layer INS2 and covered by the auxiliary insulating layer AUINS. Also, the second contact electrode CNE2 may be provided on the auxiliary insulating layer AUINS and covered by the encapsulation layer ENC. In this case, the auxiliary insulating layer AUINS may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material.

The third contact electrode CNE3 may be directly disposed on an exposed region of the third intermediate layer CTL to be connected to the third intermediate layer CTL. Also, the third contact electrode CNE3 may be disposed on the other end of both ends of each of the second light emitting devices LD2 to be connected to the other end. Additionally, the third contact electrode CNE3 may be disposed on one end of both ends of each of the third light emitting elements LD3 to be connected to the one end. When viewed in a plan view, the third contact electrode CNE3 may overlap the other end of both ends of each of the second light emitting elements LD2 and one end of both ends of each of the third light emitting elements LD3 . .

The fourth contact electrode CNE4 may be directly disposed on an exposed region of the fourth intermediate layer CTL and may be connected to the fourth intermediate layer CTL. In addition, the fourth contact electrode CNE4 may be disposed on the other end of both ends of each of the third light emitting elements LD3 to be connected to the other end. Accordingly, the second driving power VSS applied to the fourth intermediate layer CTL may be transmitted to the other end of each of both ends of the third light emitting devices LD3 through the fourth contact electrode CNE4. . When viewed in a plan view, the fourth contact electrode CNE4 may overlap the other end of both ends of each of the fourth intermediate layer CTL and the third light emitting devices LD3 .

In the above-described embodiment, it has been described that the fourth contact electrode CNE4 is indirectly connected to the driving voltage line DVL of the pixel circuit unit PCL through the fourth intermediate layer CTL, but the present invention is not limited thereto. it is not According to an embodiment, the fourth contact electrode CNE4 is a driving voltage line through the second contact hole CH2 that sequentially passes through the passivation layer PSV and the second interlayer insulating layer ILD2 as shown in FIG. 9B . (DVL) can also be directly linked. In this case, a predetermined signal (or voltage) applied to the driving voltage line DVL may be transmitted to the other end of each of both ends of the third light emitting devices LD3 through the fourth contact electrode CNE4 .

In an embodiment of the present invention, after the light emitting devices LD are aligned in the pixel area PXA of each pixel PXL, the first to fourth contact electrodes CNE1 to CNE4 and corresponding thereto The intermediate layer CTL may function as a driving electrode for driving the light emitting devices LD.

A driving current flows from the first power line (refer to 'PL1' in FIGS. 6A to 6E ) to the driving voltage line DVL by the driving transistor Tdr of the pixel circuit unit PCL included in each pixel PXL. In this case, the driving current may be introduced into the light emitting unit EMU of each pixel PXL through the first contact hole CH1 . For example, a driving current is supplied to the first contact electrode CNE1 through the first contact hole CH1 and the first intermediate layer CTL, and the driving current is supplied to the second contact electrode CNE1 through the first light emitting devices LD1 . flow to the contact electrode CNE2. Accordingly, each of the first light emitting devices LD1 may emit light with a luminance corresponding to the distributed current.

The driving current flowing through the second contact electrode CNE2 flows to the third contact electrode CNE3 via the second light emitting devices LD2 . Accordingly, the second light emitting elements LD2 may emit light with a luminance corresponding to the distributed current.

The driving current flowing through the third contact electrode CNE3 flows to the fourth contact electrode CNE4 via the third light emitting elements LD3 . Accordingly, the third light emitting elements LD3 may emit light with a luminance corresponding to the distributed current.

In the above-described manner, the driving current of each pixel PXL may flow while sequentially passing through the first light emitting elements LD1 , the second light emitting elements LD2 , and the third light emitting elements LD3 . have. Accordingly, each pixel PXL may emit light with a luminance corresponding to the data signal supplied during each frame period.

An encapsulation layer ENC may be provided and/or formed on the first to fourth contact electrodes CNE1 to CNE4 . The encapsulation layer ENC may be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. For example, the encapsulation layer ENC may have a structure in which at least one inorganic insulating layer or at least one organic insulating layer is alternately stacked. The encapsulation layer ENC may entirely cover the display element part DPL to prevent moisture or moisture from flowing into the display element part DPL including the light emitting elements LD from the outside.

On the other hand, one component included in the display element unit DPL serves as an alignment electrode (or alignment line) for aligning the light emitting elements LD and a driving electrode for driving the light emitting elements LD. In the device, after the light emitting elements LD are aligned, a process of removing a portion of the alignment electrode (or alignment line) may be performed in order to independently (or individually) drive each of the pixels PXL. In this case, in the pixel area PXA of each pixel PXL, the second bank pattern BNK2 surrounding the area in which the light emitting devices LD are disposed (or located in the peripheral area of the pixel area PXA) ) may include a groove portion exposing a region C in which a part of the alignment electrode (or alignment line) is removed. In this case, the light emitting elements LD may be aligned in the first area A of the pixel area PXA of each pixel PXL.

According to an embodiment of the present invention, since the intermediate layer CTL, which is a driving electrode for driving the light emitting elements LD, is formed only in the pixel area PXA of each pixel PXL, the second bank pattern BNK2 ) may not include the aforementioned groove. In this case, the area occupied by the second bank pattern BNK2 in the pixel area PXA of each pixel PXL is reduced, and the light emitting devices LD are formed in the second area B of the pixel area PXA. ) can be sorted. Accordingly, in the exemplary embodiment of the present invention, the alignment area of the light emitting elements LD in the pixel area PXA of each pixel PXL may be further secured compared to a conventional display device.

According to the above-described exemplary embodiment, as the light emitting devices LD are aligned in each pixel PXL using the first to fourth electrodes EL1 to EL4 , after aligning the light emitting devices LD In order to independently (or individually) drive each of the pixels PXL, a process of removing a portion of the alignment electrode (or alignment line) may be omitted. As a result, the manufacturing process of the display device according to the above-described exemplary embodiment may be simplified.

Also, according to the above-described exemplary embodiment, an alignment signal (or alignment voltage) for aligning the light emitting elements LD is transmitted to each of the first to fourth electrodes EL1 to EL4 , so that The light emitting devices LD may be aligned in the pixel area PXA. When a corresponding alignment signal (or alignment voltage) is applied to each of the first to fourth electrodes EL1 to EL4 , an electric field is formed between two adjacent ones of the first to fourth electrodes EL1 to EL4 . can be At this time, a cap coupling, for example, a vertical cap coupling (parasitic capacitor c), is formed between each of the first to fourth electrodes EL1 to EL4 and the intermediate layer CTL disposed to correspond thereto. can be For example, a vertical cap coupling may be formed between the first electrode EL1 and the first intermediate layer CTL, and the vertical cap coupling may be formed between the second electrode EL2 and the second intermediate layer CTL. A vertical cap coupling may be formed between the third electrode EL3 and the third intermediate layer CTL, and a vertical cap coupling may be formed between the fourth electrode EL4 and the fourth intermediate layer CTL. A ring may be formed.

The capacitance is increased by the vertical cap coupling formed between each of the first to fourth electrodes EL1 to EL4 and the intermediate layer CTL disposed to correspond thereto, and this capacitance is formed between the two adjacent electrodes. may affect the electric field. For example, an electric field may be concentrated between two adjacent electrodes due to a vertical cap coupling formed between each of the first to fourth electrodes EL1 to EL4 and the intermediate layer CTL disposed to correspond thereto. . Accordingly, the light emitting devices LD are intensively aligned between two adjacent electrodes, so that the degree of alignment of the light emitting devices LD in each pixel PXL may be improved.

13A to 13H are cross-sectional views sequentially illustrating a method of manufacturing one pixel illustrated in FIG. 9A .

1A to 5 and 7 to 13A , transistors T, driving voltage lines DVL, and at least one insulating layer are formed on a substrate SUB. Here, the at least one insulating layer may include a buffer layer BFL, a gate insulating layer GI, a first interlayer insulating layer ILD1, and a second interlayer insulating layer ILD2 sequentially formed on the substrate SUB.

Subsequently, first to fourth electrodes EL1 to EL4 spaced apart from each other are formed on the second interlayer insulating layer ILD2 .

The first to fourth electrodes EL1 to EL4 may be provided in common to the pixels PXL positioned in the same pixel column in the display area DA. That is, the pixels PXL positioned in the same pixel column may be commonly connected to the first to fourth electrodes EL1 to EL4 .

Next, after forming the passivation layer PSV on the first to fourth electrodes EL1 to EL4 , the passivation layer PSV and the second interlayer insulating layer ILD2 disposed thereunder are simultaneously patterned to form a driving transistor A first contact hole CH1 exposing a portion of Tdr and a second contact hole CH2 exposing a portion of the driving voltage line DVL are formed.

1A to 5 and 7 to 13B , a first bank pattern BNK1 is formed on the passivation layer PSV. On the passivation layer PSV, the first bank pattern BNK1 may be spaced apart from the adjacent first bank pattern BNK1 by a predetermined interval. When viewed in a plan view, the first bank pattern BNK1 may have a bar shape extending in one direction, for example, the second direction DR2, but the present invention is not limited thereto. The first bank pattern BNK1 may include an inorganic insulating layer made of an inorganic material or an organic insulating layer made of an organic material.

1A to 5 and 7 to 13C , an intermediate layer CTL including a conductive material (or material) having high reflectivity is formed on the passivation layer PSV including the first bank pattern BNK1.

The intermediate layer CTL includes the first bank pattern BNK1 on the first electrode EL1 , the first bank pattern BNK1 on the second electrode EL2 , and the first bank pattern BNK1 on the third electrode EL3 . , , and the first bank pattern BNK1 on the fourth electrode EL4 may be respectively formed.

The intermediate layer CTL formed on the first bank pattern BNK1 on the first electrode EL1 may be electrically and/or physically connected to the driving transistor Tdr through the first contact hole CH1 . The intermediate layer CTL formed on the first bank pattern BNK1 on the fourth electrode EL4 may be electrically and/or physically connected to the driving voltage line DVL through the second contact hole CH2 .

The intermediate layer CTL on the first electrode EL1, the intermediate layer CTL on the second electrode EL2, and the intermediate layer CTL on the third electrode EL3 are formed in the pixel area (CTL) of each pixel PXL. It may be formed to be disposed only in PXA). For example, the intermediate layer CTL on the first electrode EL1 , the intermediate layer CTL on the second electrode EL2 , and the intermediate layer CTL on the third electrode EL3 provided in one pixel PXL is an intermediate layer CTL on the first electrode EL1 provided in each of the adjacent pixels PXL disposed in the same pixel column as the one pixel PXL, an intermediate layer CTL on the second electrode EL2, and It may be separated from the intermediate layer CTL on the third electrode EL3 .

The intermediate layer CTL on the fourth electrode EL4 connected to the driving voltage line DVL to which a predetermined signal (or voltage) is applied may be provided in common to the pixels PXL located in the same pixel column. For example, the intermediate layer CTL on the fourth electrode EL4 provided in one pixel PXL may be provided in common to adjacent pixels PXL disposed in the same pixel column as the one pixel PXL. . That is, the pixels PXL disposed in the same pixel column may be connected to the intermediate layer CTL on the fourth electrode EL. However, the present invention is not limited thereto, and according to embodiments, the intermediate layer CTL on the fourth electrode EL4 may be formed to be disposed only in the pixel area PXA of each pixel PXL.

1A to 5 and 7 to 13D , an insulating material layer INSM is formed on the passivation layer PSV including the intermediate layer CTL. The insulating material layer INSM may include an inorganic insulating layer made of an inorganic material or an organic insulating layer made of an organic material.

Subsequently, a second bank pattern BNK2 is formed in the pixel area of each pixel PXL. The second bank pattern BNK2 may be formed on the insulating material layer INSM. The second bank pattern BNK2 may be a pixel defining layer defining (or partitioning) an emission area between each pixel PXL and pixels PXL adjacent thereto.

1A to 5 and 7 to 13E , an electric field is formed between two adjacent electrodes by applying an alignment signal (or alignment voltage) corresponding to each of the first to fourth electrodes EL1 to EL4 . do.

Next, in a state in which an electric field is formed between two adjacent electrodes, a mixed solution including the light emitting devices LD is injected into the pixel area PXA of each of the pixels PXL using an inkjet printing method or the like. For example, an inkjet nozzle may be disposed on the passivation layer PSV, and a solvent mixed with the plurality of light emitting devices LD may be injected into the pixel area PXA of each of the pixels PXL through the inkjet nozzle. Here, the solvent may be any one or more of acetone, water, alcohol, and toluene, but the present invention is not limited thereto. For example, the solvent may be in the form of an ink or paste. The method of inputting the light emitting elements LD into the pixel area PXA of each of the pixels PXL is not limited to the above-described embodiment, and the method of inputting the light emitting elements LD may be variously changed. have.

After the light emitting devices LD are put into the pixel area PXA of each of the pixels PXL, the solvent may be removed.

When the light emitting devices LD are input to the pixel area PXA of each of the pixels PXL, the second electrode EL2 and the third electrode EL2 are disposed between the first electrode EL1 and the second electrode EL2. Self-alignment of the light emitting elements LD may be induced due to the electric fields respectively formed between the EL3 and the third electrode EL3 and the fourth electrode EL4 . Accordingly, the first light emitting elements LD1 are aligned between the first electrode EL1 and the second electrode EL2 , and the second light emitting elements are arranged between the second electrode EL2 and the third electrode EL3 . LD2 may be aligned, and third light emitting elements LD3 may be aligned between the third electrode EL3 and the fourth electrode EL4 .

Each of the first to third light emitting devices LD1 to LD3 may be aligned on the insulating material layer INSM between two adjacent intermediate layers CTL in the pixel area PXA of each of the pixels PXL. can For example, each of the first light emitting devices LD1 may be aligned on the insulating material layer INSM between the intermediate layer CTL on the first electrode EL1 and the intermediate layer CTL on the second electrode EL2 . can Each of the second light emitting elements LD2 may be aligned on the insulating material layer INSM between the intermediate layer CTL on the second electrode EL2 and the intermediate layer CTL on the third electrode EL3 . Each of the third light emitting elements LD3 may be aligned on the insulating material layer INSM between the intermediate layer CTL on the third electrode EL3 and the intermediate layer CTL on the fourth electrode EL4 .

1A to 5 and 7 to 13F , after aligning the light emitting devices LD in the pixel area PXA of each pixel PXL, a second light emitting device LD is disposed on each of the light emitting devices LD. An insulating layer INS2 is formed. The second insulating layer INS2 may cover at least a portion of a top surface of each of the light emitting devices LD to expose both ends of each of the light emitting devices LD except for the active layer 12 to the outside.

The first insulating layer INS1 may be formed by etching the insulating material layer INSM to expose a portion of the intermediate layer CTL through a process of forming the second insulating layer INS2 or an etching process performed before and after it. have.

1A to 5 and 7 to 13G , first to fourth contact electrodes CNE1 to CNE4 are formed on the second insulating layer INS2 .

The first contact electrode CNE1 may overlap one end of the intermediate layer CTL on the first electrode EL1 and both ends of each of the first light emitting devices LD1 . The second contact electrode CNE2 includes an intermediate layer CTL on the second electrode EL2 , the other end of both ends of each of the first light emitting elements LD1 , and both ends of each of the second light emitting elements LD2 . It may overlap one end of one of them. The third contact electrode CNE3 includes an intermediate layer CTL on the third electrode EL3 , the other end of both ends of each of the second light emitting devices LD2 , and both ends of each of the third light emitting devices LD3 . It may overlap one end of one of them. The fourth contact electrode CNE4 may overlap the other end of the intermediate layer CTL on the fourth electrode EL4 and both ends of each of the third light emitting devices LD3 .

1A to 5 and 7 to 13H , an encapsulation layer ENC covering the first to fourth contact electrodes CNE1 to CNE4 is formed. The encapsulation layer ENC may have a structure in which at least one inorganic layer and at least one organic layer are alternately stacked.

FIG. 14 schematically illustrates a display device according to another embodiment of the present invention, and is a plan view corresponding to portion EA of FIG. 7 , FIG. 15 is a cross-sectional view corresponding to line III to Ⅲ′ of FIG. 14 , and FIG. 16 . is a cross-sectional view corresponding to line IV to IV' of FIG. 14 .

14 to 16 , in order to avoid overlapping descriptions, different points from the above-described exemplary embodiment will be mainly described. Parts not specifically described in the present invention are in accordance with the above-described exemplary embodiment, and the same numbers indicate the same components and similar numbers indicate similar components.

1A to 5 , 7 , and 14 to 16 , a display device according to an exemplary embodiment may include a substrate SUB, a wiring unit, and a plurality of pixels PXL. . Each pixel PXL may include a pixel circuit unit PCL provided on the substrate SUB and a display element unit DPL provided on the pixel circuit unit PCL.

Since the pixel circuit unit PCL has the same configuration as the pixel circuit unit PCL described with reference to FIGS. 8 to 13H , a description thereof will be omitted.

The display element part DPL includes the first to fourth sub-electrodes SEL1 to SEL4 , the first bank pattern BNK1 , the intermediate layer CTL, the light emitting elements LD, and the first and second insulating layers . INS1 and INS2 ), a contact electrode CNE, and an encapsulation layer ENC.

Each of the first to fourth sub-electrodes SEL1 to SEL4 may be provided and/or formed between the passivation layer PSV and the first bank pattern BNK1 .

The first sub-electrode SEL1 is provided and/or formed on the passivation layer PSV to correspond to the first electrode EL1 , and the second sub-electrode SEL2 is provided to correspond to the second electrode EL2 and the passivation layer PSV to correspond to the second electrode EL2 . ), the third sub-electrode SEL3 is provided and/or formed on the passivation layer PSV to correspond to the third electrode EL3 , and the fourth sub-electrode SEL4 is formed on the fourth It may be provided and/or formed on the passivation layer PSV to correspond to the electrode EL4 .

When viewed in a plan view, the first electrode EL1 and the first sub-electrode SEL1 overlap each other, the second electrode EL2 and the second sub-electrode SEL2 overlap each other, and the third electrode EL3 and The third sub-electrode SEL3 may overlap each other, and the fourth electrode EL4 and the fourth sub-electrode SEL4 may overlap each other.

A first bank pattern BNK1 may be provided and/or formed on the first to fourth sub-electrodes SEL1 to SEL4, respectively.

An intermediate layer CTL may be provided and/or formed on the first bank pattern BNK1 . For example, the first bank pattern BNK1 on the first sub-electrode SEL1, the first bank pattern BNK1 on the second sub-electrode SEL2, and the first bank pattern BNK1 on the third sub-electrode SEL3 , and the intermediate layer CTL may be provided and/or formed on the first bank pattern BNK1 on the fourth sub-electrode SEL4 , respectively.

An intermediate layer CTL (hereinafter, referred to as a 'first intermediate layer') provided on the first bank pattern BNK1 on the first sub-electrode SEL1 includes the first sub-electrode SEL1 and the first bank pattern BNK1 ) can be covered. The first intermediate layer CTL may contact both side portions of the first sub-electrode SEL1 that are not covered by the first bank pattern BNK1 and are exposed to the outside. Accordingly, the first intermediate layer CTL may be electrically and/or physically connected to the first sub-electrode SEL1 .

The intermediate layer CTL (hereinafter referred to as a 'second intermediate layer') provided on the first bank pattern BNK1 on the second sub-electrode SEL2 includes the second sub-electrode SEL2 and the first bank pattern BNK1. ) can be covered. The second intermediate layer CTL may contact both side portions of the second sub-electrode SEL2 that are not covered by the first bank pattern BNK1 and are exposed to the outside. Accordingly, the second intermediate layer CTL may be electrically and/or physically connected to the second sub-electrode SEL2 .

An intermediate layer CTL (hereinafter, referred to as a 'third intermediate layer') provided on the first bank pattern BNK1 on the third sub-electrode SEL3 includes the third sub-electrode SEL3 and the first bank pattern BNK1 ) can be covered. The third intermediate layer CTL may contact both side portions of the third sub-electrode SEL3 that are not covered by the first bank pattern BNK1 and are exposed to the outside. Accordingly, the third intermediate layer CTL may be electrically and/or physically connected to the third sub-electrode SEL3 .

An intermediate layer CTL (hereinafter, referred to as a 'fourth intermediate layer') provided on the first bank pattern BNK1 on the fourth sub-electrode SEL4 includes the fourth sub-electrode SEL4 and the first bank pattern BNK1 ) can be covered. The fourth intermediate layer CTL may contact both side portions of the fourth sub-electrode SEL4 that are not covered by the first bank pattern BNK1 and are exposed to the outside. Accordingly, the fourth intermediate layer CTL may be electrically and/or physically connected to the fourth sub-electrode SEL4 .

In one embodiment of the present invention, as each of the first to fourth sub-electrodes SEL1 to SEL4 is disposed on the corresponding electrode with the passivation layer PSV interposed therebetween, the first to fourth sub-electrodes A vertical cap coupling (eg, a parasitic capacitor c) may be formed between each of SEL1 to SEL4 and the corresponding electrode. For example, as the first sub-electrode SEL1 is disposed on the first electrode EL1 with the passivation layer PSV interposed therebetween, the vertical vertical between the first sub-electrode SEL1 and the first electrode EL1 is A cap coupling may be formed. As the second sub-electrode SEL2 is disposed on the second electrode EL2 with the passivation layer PSV interposed therebetween, a vertical cap coupling is performed between the second sub-electrode SEL2 and the second electrode EL2 . can be formed. As the third sub-electrode SEL3 is disposed on the third electrode EL3 with the passivation layer PSV interposed therebetween, the vertical cap coupling is performed between the third sub-electrode SEL3 and the third electrode EL3. can be formed. As the fourth sub-electrode SEL4 is disposed on the fourth electrode EL4 with the passivation layer PSV interposed therebetween, the vertical cap coupling is performed between the fourth sub-electrode SEL4 and the fourth electrode EL4. can be formed.

As described above, capacitance may increase due to the vertical cap coupling formed between one sub-electrode and one electrode corresponding thereto. Also, as one sub-electrode and a corresponding one of the electrodes are spaced apart with only the passivation layer PSV therebetween, a capacitance generated between the one sub-electrode and the one electrode may further increase. In this case, when an alignment signal (or an alignment voltage) corresponding to each of the first to fourth electrodes EL1 to EL4 is applied, the first to fourth electrodes EL1 to EL4 are further interposed between adjacent two electrodes. A strong electric field can be formed. Accordingly, the light emitting devices LD are intensively aligned between the first to fourth electrodes EL1 to EL4 , so that the alignment of the light emitting devices LD in each pixel PXL may be improved.

Although the above has been described with reference to the preferred embodiment of the present invention, those skilled in the art or those having ordinary knowledge in the technical field will not depart from the spirit and technical scope of the present invention described in the claims to be described later. It will be understood that various modifications and variations of the present invention can be made without departing from the scope of the present invention.

Accordingly, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

SUB: Substrate PXL: Pixel
PXA: Pixel area EMA: Emission area
EMU: light emitting unit LD: light emitting element
PCL: pixel circuit part DPL: display element part
EL1 to EL4: first to fourth electrodes CTL: intermediate layer
CNE1 to CNE4: first to fourth contact electrodes

Claims (20)

a substrate including a display area including a plurality of pixel areas and a non-display area surrounding the display area; and
a pixel provided in each of the pixel areas;
The pixel is
first and second electrodes extending in one direction on the substrate and spaced apart from each other;
a first insulating film provided on the first and second electrodes;
a bank pattern provided on the first insulating layer to correspond to each of the first and second electrodes;
an intermediate layer provided on the bank pattern;
a plurality of light emitting elements provided between the two intermediate layers adjacent in the other direction intersecting the one direction;
a first contact electrode in contact with one of the two adjacent intermediate layers and connected to one of both ends of each of the light emitting devices; and
and a second contact electrode in contact with the other intermediate layer of the two adjacent intermediate layers and connected to the other end among both ends of each of the light emitting elements. According to claim 1,
and the intermediate layer includes a conductive material. 3. The method of claim 2,
each of the first and second electrodes extends in the one direction and is provided in common to adjacent pixels positioned in the same pixel column as the pixel. 4. The method of claim 3,
and the one intermediate layer is provided only to the pixel, and the other intermediate layer is provided in common to the pixel and the adjacent pixels. 3. The method of claim 2,
The one intermediate layer overlaps one of the first and second electrodes when viewed in a plan view,
The remaining intermediate layer overlaps the remaining electrodes among the first and second electrodes when viewed in a plan view. 3. The method of claim 2,
The pixel may further include at least one transistor and a driving voltage line provided between the substrate and the first and second electrodes. 7. The method of claim 6,
one of the first and second contact electrodes is electrically connected to the transistor;
and a remaining contact electrode of the first and second contact electrodes is electrically connected to the driving voltage line. 3. The method of claim 2,
the one intermediate layer and one electrode of the first and second electrodes form a capacitor with the first insulating layer and a bank pattern corresponding to the one electrode interposed therebetween;
and the remaining intermediate layer and the remaining electrode of the first and second electrodes form a capacitor with the first insulating layer and a bank pattern corresponding to the remaining electrode interposed therebetween. 3. The method of claim 2,
The pixel may further include a first sub-electrode and a second sub-electrode provided on the first insulating layer, extending along the one direction and spaced apart from each other. 10. The method of claim 9,
the first sub-electrode overlaps the first electrode in a plan view;
and the second sub-electrode overlaps the second electrode when viewed in a plan view. 11. The method of claim 10,
the first sub-electrode is provided between the first electrode and the bank pattern corresponding to the first electrode;
The second sub-electrode is provided between the second electrode and the bank pattern corresponding to the second electrode. 12. The method of claim 11,
the first electrode and the first sub-electrode form a capacitor with the first insulating layer interposed therebetween;
and the second electrode and the second sub-electrode form a capacitor with the first insulating layer interposed therebetween. 13. The method of claim 12,
the one intermediate layer covers the first sub-electrode and is electrically connected to the first sub-electrode;
and the remaining intermediate layer covers the second sub-electrode and is electrically connected to the second sub-electrode. 3. The method of claim 2,
The pixel is
a second insulating film provided on the intermediate layer and exposing a portion of the intermediate layer; and
and a third insulating layer provided on a top surface of each of the light emitting elements. 15. The method of claim 14,
The first contact electrode and the second contact electrode are provided on the third insulating layer. 16. The method of claim 15,
and the first contact electrode and the second contact electrode are provided on the same layer. 16. The method of claim 15,
and the first contact electrode and the second contact electrode are provided on different layers. providing a pixel provided in each pixel area;
The step of providing the pixel comprises:
forming at least one transistor and a driving voltage line on a substrate;
forming an interlayer insulating film on the transistor and the driving voltage line;
forming first and second electrodes extending in one direction and spaced apart from each other on the interlayer insulating layer;
forming a first insulating layer on the first electrode and the second electrode;
forming a bank pattern corresponding to each of the first and second electrodes on the first insulating layer;
forming an intermediate layer including a conductive material on the bank pattern;
After inputting a plurality of light emitting devices, an alignment signal corresponding to each of the first electrode and the second electrode is applied to the light emitting device between the two intermediate layers adjacent in the other direction intersecting the one direction. sorting them;
forming a second insulating film on an upper surface of each of the light emitting devices; and
and forming a first contact electrode and a second contact electrode on the second insulating layer. 19. The method of claim 18,
Each of the first and second electrodes extends in the one direction and is provided in common to adjacent pixels positioned in the same pixel column as the pixel. 20. The method of claim 19,
One intermediate layer of the two adjacent intermediate layers is provided only to the pixel, and the other intermediate layer is provided in common to the pixel and the adjacent pixels.

Images