KR20210073269A - Semiconductor device including power gating switches - Google Patents

Abstract

The present invention relates to a semiconductor device including power gating switches. The semiconductor device according to an embodiment of the present invention includes first power supply lines, second power supply lines, power gating switches, and taps. The first power supply lines are arranged in a first direction and extend in a second direction. The second power supply lines are arranged in the second direction and extend in the first direction. Each of the power gating switches is connected with one of the first power supply lines and at least two of the second power supply lines. The taps are connected with one of the first power supply lines or one of the second power supply lines. A power gating switch closest to a first power gating switch from among the power gating switches is a second power gating switch, a tap closest to the first power gating switch from among the taps is a first tap, and at least one of the first power gating switch and the first tap is spaced apart from the first power gating switch in a third direction.

Description

Semiconductor device comprising power gating switches

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including power gating switches.

In order to drive standard cells constituting a logic circuit of a semiconductor device, a power supply voltage supplied from the outside is generally supplied to the standard cells through a power gating switch. The voltage output from the power gating switch is also called a virtual voltage. In order to stably drive the semiconductor device, a sufficient virtual voltage must be supplied to each standard cell. In particular, in a place relatively far from the power gating switch, a voltage drop due to line resistance occurs relatively large. That is, the virtual voltage may not be sufficiently supplied to the standard cells disposed in such places, and as a result, the corresponding logic circuit may not be normally driven.

When the number of power gating switches is increased to sufficiently supply a voltage to the logic circuit, the size of the semiconductor device increases. Accordingly, there is a need for arrangement and design of power gating switches capable of improving area efficiency while supplying a sufficient virtual voltage to a logic circuit.

The present invention may provide a semiconductor device including power gating switches that reduce abnormal operation of a logic circuit due to a voltage drop and improve area efficiency.

The present invention can provide a semiconductor device having a required area efficiency and spacing between power gating switches under specified standard cell and size conditions of power gating switches.

A semiconductor device according to an embodiment of the present invention includes first power supply lines, second power supply lines, power gating switches, and taps. The first power supply lines are arranged in the first direction and extend in the second direction. The second power supply lines are arranged in the second direction and extend in the first direction. Each of the power gating switches is connected to one of the first power supply lines and to at least two of the second power supply lines. Each of the taps is connected to one of the first power supply lines or one of the second power supply lines. Among the power gating switches, a power gating switch closest to the first power gating switch is a second power gating switch, a tap closest to the first power gating switch among the taps is a first tap, and the second power gating switch and the first tap at least one of is spaced apart from the first power gating switch in a third direction different from the first and second directions. A semiconductor device according to an embodiment of the present invention includes first to fourth power gating switches and first to third taps. The second power gating switch is a power gating switch closest to the first power gating switch in the first direction, and is spaced apart from the first power gating switch to have a first interval. The third power gating switch is a power gating switch closest to the first power gating switch in a second direction perpendicular to the first direction, and is spaced apart from the first power gating switch to have a second interval smaller than the first interval. The fourth power gating switch is the closest power gating switch from the first power gating switch in a third direction different from the first and second directions, and is spaced apart from the first power gating switch to have a third interval smaller than the second interval . The first tab is disposed between the first power gating switch and the second power gating switch. The second tab is disposed between the first power gating switch and the third power gating switch. The third tap is disposed between the first power gating switch and the fourth power gating switch.

A semiconductor device according to an embodiment of the present invention includes first power supply lines, second power supply lines, power gating switches, and a logic circuit. The first power supply lines are arranged to have an interval of 3 μm to 4.5 μm in the first direction and extend in a second direction perpendicular to the first direction. The second power supply lines are arranged to have an interval of 0.4 μm to 0.8 μm in the second direction, and extend in the first direction. The power gating switches receive a first voltage from one of the first power supply lines and output a second voltage to two of the second power supply lines. The logic circuit operates based on the second voltage transferred through the second power supply lines. The power gating switches are arranged to have an interval of 36 μm to 54 μm in a first direction, 4.8 μm to 9.6 μm in a second direction, and a third direction different from the first and second directions. The components in the first direction are arranged to have an interval of 3 μm to 4.5 μm and the components in the second direction are 0.4 μm to 0.8 μm.

A semiconductor device including power gating switches according to an embodiment of the present invention can reduce a voltage drop due to line resistance and improve area efficiency by disposing the power gating switches diagonally.

In addition, the semiconductor device including the power gating switches according to an embodiment of the present invention replaces some of the diagonally arranged power gating switches with taps, thereby forming a design rule under a limited number of power gating switches. properties can be improved without violating

In addition, the semiconductor device including the power gating switches according to the embodiment of the present invention can satisfy the area efficiency required under the conditions of the specified standard cell and the size of the power gating switch and reduce the line resistance along the voltage transfer path. .

1 is a plan view illustrating a semiconductor device according to an embodiment of the present invention.
FIG. 2 is an enlarged view of area AA of FIG. 1 .
3 is an exemplary layout of the power gating cell of FIGS. 1 and 2 ;
FIG. 4 is a cross-sectional view of a partial region of the power gating cell of FIG. 3 .
FIG. 5 is a view for explaining the arrangement of power supply lines in the power gating cell of FIGS. 3 and 4 .
6 is a cross-sectional view of a partial region of a power gating cell according to an embodiment different from FIG. 4 .
FIG. 7 is a view for explaining the arrangement of power supply lines in the power gating cell of FIG. 6 .
8 is a plan view illustrating a semiconductor device according to an embodiment of the present invention.
9 and 10 are enlarged views of a region BB of FIG. 8 .
11 is an exemplary layout of the tab cell of FIGS. 8 to 10 .
12 is a cross-sectional view of a partial region of the tap cell of FIG. 11 .
13 is a cross-sectional view of a partial region of a tap cell according to an exemplary embodiment different from FIG. 12 .
14 is a plan view for explaining a semiconductor device according to an embodiment of the present invention.
15 is an exemplary block diagram of a design system of the semiconductor device illustrated in FIGS. 1 to 14 .
16 is an exemplary flowchart of a method of designing a semiconductor device by the design system of FIG. 15 .

Hereinafter, embodiments of the present invention will be described clearly and in detail to the extent that those skilled in the art can easily practice the present invention.

Hereinafter, first to fourth directions DR1 to DR4 are defined to describe a semiconductor device according to an embodiment of the present invention. The semiconductor device includes a semiconductor substrate, in which power gating cells and standard cells are formed on a plane defined by a first direction DR1 and a second direction DR2 . The third direction DR3 is defined as a thickness direction of the semiconductor device, and the first to third directions DR1 to DR3 may be orthogonal to each other. The fourth direction DR4 is perpendicular to the third direction DR3 and is different from the first and second directions DR1 and DR2 . The fourth direction DR4 will be understood as a direction in which the power gating cells are arranged.

In the following, power gating cells, standard cells, and tap cells are described. These various cells are defined by a cell library and can be arranged using a design tool. The designed and arranged cells may be implemented as semiconductor devices. For convenience of description, a power gating cell, a standard cell, and a tap cell are described, but this will be understood to mean a power gate switch, a logic circuit, and tabs formed according to a process of a semiconductor device.

1 is a plan view illustrating a semiconductor device according to an embodiment of the present invention. Referring to FIG. 1 , a semiconductor device 100 includes power gating cells PGC and standard cells STC.

The standard cells STC constitute a different logic circuit for the purpose of the semiconductor device 100 . Each of the standard cells STC may be a device for implementing a logic circuit. The standard cells STC may operate based on a voltage provided through the power gating cells PGC.

The power gating cells PGC may be power gating switches for supplying voltages to the standard cells STC. The power gating cells PGC may receive a power supply voltage from the outside. Such a power supply voltage may be expressed as real power. For example, the power gating cells PGC may receive the VDD voltage, but is not limited thereto and may receive the VSS voltage.

Although not shown, the semiconductor device 100 further includes power supply lines (hereinafter, referred to as first power supply lines) for outputting a power supply voltage to the power gating cells PGC. The power gating cells PGC may be electrically connected to the first power supply lines to receive a power voltage. For example, the power gating cells PGC may be implemented as PMOS or NMOS, and a first power supply line may be connected to one terminal of the PMOS or NMOS. The first power supply lines may be arranged in the first direction DR1 and may extend in the second direction DR2 . The power gating cells PGC may overlap some of the first power supply lines.

The power gating cells PGC may output a supply voltage to the standard cells STC based on the gate control signal. This supply voltage may be expressed as virtual power. The supply voltage is the voltage provided to the standard cells STC. For example, the power gating cells PGC may output a virtual VDD (VVDD) voltage based on the VDD voltage, but is not limited thereto and may output a virtual VSS (VVSS) voltage based on the VSS voltage. The power gating cells PGC may be implemented as PMOS or NMOS, and a gate terminal of the PMOS or NMOS may receive a gate control signal.

Although not shown, the semiconductor device 100 further includes power supply lines (hereinafter, referred to as second power supply lines) for receiving a supply voltage from the power gating cells PGC. The power gating cells PGC may be electrically connected to the second power supply lines to output a supply voltage. The power gating cells PGC may be implemented as PMOS or NMOS, and a second power supply line may be connected to the other terminal of the PMOS or NMOS. The second power supply lines may be arranged in the second direction DR2 and may extend in the first direction DR1 . In addition, the semiconductor device 100 further includes power supply lines (hereinafter, referred to as third power supply lines) connected to the second power supply lines to receive a supply voltage. The third power supply lines may be arranged in the first direction DR1 and extend in the second direction DR2 .

Furthermore, although not shown, the semiconductor device 100 may further include power supply lines for providing a ground voltage to the standard cells STC. The semiconductor device 100 includes power supply lines arranged in the second direction DR2 and extending in the first direction DR1 such that the ground voltage transmitted through the second power supply lines is provided to all of the standard cells STC. , and power supply lines arranged in the first direction DR1 and extending in the second direction DR2 .

In FIG. 1 , the above-described power supply lines are disposed on the standard cells STC and the power gating cells PGC, and have been omitted for convenience of clearly representing the arrangement of the power gating cells PGC. The specific arrangement of the power supply lines is represented in the drawings to be described later.

The power gating cells PGC are arranged in the fourth direction DR4 , that is, in a diagonal direction. In a general semiconductor device, the power gating cells PGC are arranged in the second direction DR2 , and in this case, a supply voltage is supplied in the first direction DR1 . When the power gating cells PGC are arranged so that the supply voltage is transmitted in one direction, a transmission path of the power supply line for transmitting the supply voltage to the standard cells STC may increase. Furthermore, the resistance of the power supply line extending in the first direction DR1 is greater than the resistance of the power supply line extending in the second direction DR2 . This is because the power supply line extending in the first direction DR1 has a relatively narrow width, and the power supply line extending in the second direction DR2 has a relatively wide width. In addition, as the transmission path increases, the resistance of the power supply line increases, and a voltage drop according to the increased resistance occurs. Accordingly, the influence of OCV (On Chip Variation) increases.

When the power gating cells PGC are arranged in the fourth direction DR4 , the supply voltage may be variously transmitted to the standard cells STC in the first direction DR1 or the second direction DR2 . Compared to a semiconductor device in which the power gating cells PGC are arranged in the second direction DR2 , a transmission path of the power supply line for transmitting the supply voltage may be reduced. Accordingly, abnormal driving of the standard cells STC according to the voltage drop may be reduced. When the same power gating cells PGC are included in the semiconductor device 100 , when the power gating cells PGC are arranged in a diagonal direction, a path through which a voltage is transmitted to the standard cells STC may be reduced. Accordingly, in order to improve the performance of the semiconductor device 100 , an increase in the number of power gating cells PGC is not required, and the size of the semiconductor device 100 may be reduced.

The semiconductor device 100 may be divided into a plurality of regions U1 to U4 in which the power gating cells PGC are arranged in the same pattern. 1 exemplarily shows four regions U1 to U4. Each of the first to fourth regions U1 to U4 has the same arrangement of power gating cells PGC. That is, each of the first to fourth regions U1 to U4 is defined as a minimum unit of an arrangement of the repeated power gating cells PGC. Each of the first to fourth regions U1 to U4 includes power gating cells PGC arranged in the fourth direction DR4 . A power gating cell having the closest distance to each of the power gating cells PGC exists in the fourth direction DR4 .

The arrangement of the power gating cells PGC shown in FIG. 1 will be understood as an arrangement in consideration of the operating performance of the standard cells STC and the size of the semiconductor device 100 while satisfying the design rule of the semiconductor device 100 . For example, each of the first to fourth regions U1 to U4 may include 12 power gating cells PGC arranged in the fourth direction DR4 . Each of the first to fourth regions U1 to U4 may include 24 standard cells STC in the first direction DR1 and 24 standard cells STC in the second direction DR2. have.

The power gating cells PGC may be arranged to have a first interval D1 in the first direction DR1 . The first interval D1 may be a width in the first direction DR1 of each of the first to fourth regions U1 to U4 . The power gating cells PGC may be arranged to have a second gap D2 in the second direction DR2 . The second interval D2 may be a width of each of the first to fourth regions U1 to U4 in the second direction DR2 . The power gating cells PGC may be arranged to have a third interval in the fourth direction DR4 . The third interval may be expressed by a first component D3 in the first direction DR1 and a second component D4 in the second direction DR2 . The second interval D2 may be smaller than the first interval D1 , and the third interval may be smaller than the second interval D2 .

A width of each of the power gating cells PGC in the first direction DR1 may be half that of the first component D3 . A width of each of the power gating cells PGC in the second direction DR2 may be the same as that of the second component D4 . As a result, the ratio of the area of the power gating cells PGC to the entire area of the semiconductor device 100 on a plane is 12/288 and may be 4.16%. In addition, under the corresponding ratio condition, the semiconductor device 100 in which the power gating cells are arranged in the fourth direction DR4 uses the power supply lines extending in the second direction DR2 as a voltage transmission path, so that the second direction ( With DR2), a voltage drop degree may be reduced by 8% compared to a semiconductor device in which the power gating cells PGC are arranged.

Specifically, each of the power gating cells PGC may have a width of 1.5 μm to 2.25 μm in the first direction DR1 and a width of 0.4 μm to 0.8 μm in the second direction DR2 . The first gap D1 may be 36 μm to 54 μm. The second gap D2 may be arranged to have a gap of 4.8 μm to 9.6 μm. The first component D3 of the third interval may be 3 μm to 4.5 μm, and the second component D4 of the third interval may be 0.4 μm to 0.8 μm.

FIG. 2 is an enlarged view of area AA of FIG. 1 . Referring to FIG. 2 , first and second power gating cells PGC1 and PGC2 adjacent in the fourth direction DR4 in area AA are illustrated. The standard cells STCs do not overlap the power gating cells PGC1 and PGC2 on a plane.

Among the power gating cells, the closest power gating cell to the first power gating cell PGC1 is the second power gating cell PGC2. The first power gating cell PGC1 and the second power gating cell PGC2 are spaced apart from each other by the third interval described in FIG. 1 . The third interval may be divided into a first component D3 corresponding to the first direction DR1 and a second component D4 corresponding to the second direction DR2 .

Each of the standard cells STCs may have a first reference width XR in the first direction DR1 and a second reference width YR in the second direction DR2 . The first reference width XR may be 1.5 μm to 2.25 μm. The second reference width YR may be 0.2 μm to 0.4 μm. For example, the second reference width YR may be set to 0.243 μm, 0.27 μm, or 0.216 μm. The first component D3 may be twice the first reference width XR, and the second component D4 may be twice the second reference width YR.

The first and second power gating cells PGC1 and PGC2 may be twice the size of each of the standard cells STCs. Each of the first and second power gating cells PGC1 and PGC2 may have a first width X1 in the first direction DR1 and a second width Y1 in the second direction DR2 . The first width X1 may be 1.5 μm to 2.25 μm. The second width Y1 may be 0.4 μm to 0.8 μm. The first component D3 may be twice the first width X1 , and the second component D4 may be equal to the second width Y1 .

3 is an exemplary layout of the power gating cell of FIGS. 1 and 2 ; FIG. 4 is a cross-sectional view of a partial region of the power gating cell of FIG. 3 . A partial area in FIG. 4 is a block indicated by a dotted line in FIG. 3 . The power gating cell PGC1 includes a P-type semiconductor substrate P-sub, an N-well formed in the P-type semiconductor substrate P-sub, and various diffusion regions and gate patterns. It can be implemented using

Referring to FIG. 3 , an N-well may be formed in the P-type semiconductor substrate P-sub. An N-well may be formed in at least a portion of the power gating cell PGC1 . It will be understood that the N-well region formed in FIG. 3 is exemplary, and the shape of the N-well may be different from that of FIG. 3 .

The first power supply line VL may be disposed on the power gating cell PGC1 . The first power supply line VL may extend in the second direction DR2 . The power gating cell PGC1 may be electrically connected to the first power supply line VL through a contact pattern. The power gating cell PGC1 may receive the power supply voltage VDD from the first power supply line VL.

The second power supply line VVL1 and the third power supply line VVL2 may be disposed on the power gating cell PGC1 . The second power supply line VVL1 and the third power supply line VVL2 may extend in the first direction DR1 . The power gating cell PGC1 may be electrically connected to the second power supply line VVL1 and the third power supply line VVL2 through a contact pattern. The power gating cell PGC1 may transmit the supply voltage VVDD corresponding to the power supply voltage VDD to the second power supply line VVL1 and the third power supply line VVL2 . The ground voltage supply line VSL may be disposed on the power gating cell PGC1 and may be disposed between the second power supply line VVL1 and the third power supply line VVL2 .

The fourth power supply line VVL3 may be disposed on the power gating cell PGC1 and the second and third power supply lines VVL1 and VVL2 . The fourth power supply line VVL3 may extend in the second direction DR2 . The fourth power supply line VVL3 may be electrically connected to the second power supply line VVL1 and the third power supply line VVL2 through a contact pattern. The supply voltage VVDD may be transferred from the second and third power supply lines VVL1 and VVL2 to the fourth power supply line VVL3 .

A gate line GL may be disposed on the power gating cell PGC1 to control transmission of the supply voltage VVDD according to the reception of the power supply voltage VVD. The supply voltage VVDD may be output from the power gating cell PGC1 based on the gate control signal transmitted through the gate line GL.

Referring to FIG. 4 , an N-well is formed in the P-type semiconductor substrate P-sub. A first diffusion region I1 , a second diffusion region I2 , and a third diffusion region T1 are formed in the N-well. A gate pattern G1 may be disposed on the N-well, and a channel region may be formed between the first diffusion region I1 and the second diffusion region O1 by the gate pattern G1 . .

The first diffusion region I1 , the second diffusion region O1 , and the gate pattern G1 may be used to implement a PMOS. The PMOS may be a header that outputs the supply voltage VVDD based on the gate control signal GC.

The first diffusion region I1 may be highly doped P-type. The first diffusion region I1 may receive the power supply voltage VDD. To this end, the first diffusion region I1 may be electrically connected to the first power supply line VL of FIG. 3 .

The second diffusion region O1 may be highly doped P-type. The second diffusion region O1 may output a supply voltage VVDD. To this end, the second diffusion region O2 may be electrically connected to the third power supply line VVL2 of FIG. 3 .

The gate pattern G1 may be disposed on the N-well and may be spaced apart from the N-well to have a predetermined distance through a gate insulating pattern or the like. The gate pattern G1 may receive the gate control signal GC for determining whether to output the supply voltage VVDD. To this end, the gate pattern G1 may be electrically connected to the gate line GL of FIG. 3 . A channel region may be formed between the first diffusion region I1 and the second diffusion region O1 based on the gate control signal GC, and a supply voltage VVDD may be output.

The third diffusion region T1 may be highly doped in an N+ type. The third diffusion region T1 is disposed adjacent to the first diffusion region I1 . The third diffusion region T1 may receive the power supply voltage VDD. To this end, the third diffusion region T1 may be connected to the first power supply line VL of FIG. 3 . The third diffusion region T1 may be a well-tap. The third diffusion region T1 may provide a bias, that is, a power supply voltage VDD, to the N-well in order to remove a diode characteristic generated between the N-well and the first diffusion region I1 .

FIG. 5 is a view for explaining the arrangement of power supply lines in the power gating cell of FIGS. 3 and 4 . FIG. 5 shows a unit area U1_1 corresponding to the first area U1 of FIG. 1 . Referring to FIG. 5 , various power supply lines are disposed on the power gating cells PGC and standard cells of the unit area U1_1 .

The first power supply lines (VDD lines extending in the second direction DR2 ) are arranged in the first direction DR1 . For example, the first power supply lines may be arranged at an interval of 3 μm to 4.5 μm. The first power supply lines overlap the power gating cells PGC and are disposed on the power gating cells PGC. The first power supply lines correspond to the first power supply line VL of FIG. 3 . The first power supply lines are connected to the first diffusion region I1 and the third diffusion region T1 of FIG. 4 . The first power supply lines may provide the power supply voltage VDD to the power gating cells PGC.

The second power supply lines (VVDD lines extending in the second direction DR2 ) are arranged in the first direction DR1 . For example, the second power supply lines may be arranged at an interval of 3 μm to 4.5 μm. The second power supply lines overlap the power gating cells PGC and are disposed on the power gating cells PGC. However, the present invention is not limited thereto, and the second power supply lines may be cut off on the power gating cells PGC so as not to overlap the power gating cells PGC. Alternatively, the second power supply lines may be disposed on an area where the power gating cells PGC are not disposed so as not to overlap the power gating cells PGC. The second power supply lines may be disposed adjacent to the first power supply lines. The second power supply lines correspond to the fourth power supply line VVL3 of FIG. 3 . The second power supply lines are connected to the second power supply line VVL1 and the third power supply line VVL2 of FIG. 3 . The second power supply lines may transfer the supply voltage VVDD to the standard cells.

The third power supply lines (VSS lines extending in the second direction DR2 ) are arranged in the first direction DR1 . For example, the third power supply lines may be arranged at an interval of 3 μm to 4.5 μm. The third power supply lines do not overlap the power gating cells PGC, but overlap the standard cells. The third power supply lines are disposed on an area in which the power gating cells PGC are not disposed, but are comprised of standard cells. The third power supply lines may provide the ground voltage VSS to the standard cells.

The fourth power supply lines (VVDD lines extending in the first direction DR1 ) are arranged in the second direction DR2 . For example, the fourth power supply lines may be arranged at intervals of 0.4 μm to 0.8 μm in the second direction DR2 . The fourth power supply lines correspond to the second power supply line VVL1 and the third power supply line VVL2 of FIG. 3 . The fourth power supply lines are connected to the second diffusion region O1 of FIG. 4 . The fourth power supply lines may be connected to the second power supply lines of FIG. 5 to transmit the supply voltage VVDD. The supply voltage VVDD may be transmitted to the standard cells through the second and fourth power supply lines. The supply voltage VVDD output from the power gating cell closest to the standard cell may be transmitted to the corresponding standard cell through the second and fourth power supply lines.

The fifth power supply lines (VSS lines extending in the first direction DR1 ) are arranged in the second direction DR2 . For example, the fifth power supply lines may be arranged at intervals of 0.4 μm to 0.8 μm in the second direction DR2 . The fifth power supply lines correspond to the ground voltage supply line VSL of FIG. 3 . The fifth power supply lines may be connected to the third power supply lines, and may provide a ground voltage VSS to the standard cells. The ground voltage VSS may be transmitted to the standard cells through the third and fifth power supply lines.

6 is a cross-sectional view of a partial region of a power gating cell according to an embodiment different from FIG. 4 . Unlike FIG. 4 , the power gating cell corresponding to the cross-sectional view of FIG. 6 may have a structure for receiving a ground voltage and supplying a supply voltage to the standard cells STCs.

Referring to FIG. 6 , a first diffusion region I1 , a second diffusion region I2 , and a third diffusion region T1 are formed on the P-type semiconductor substrate P-sub. A gate pattern G1 is disposed on the P-type semiconductor substrate P-sub, and a channel region is formed between the first diffusion region I1 and the second diffusion region O1 by the gate pattern G1. can

The first diffusion region I1 , the second diffusion region O1 , and the gate pattern G1 may be used to implement an NMOS. The NMOS may be a footer that outputs the supply voltage VVSS based on the gate control signal GC.

The first diffusion region I1 may be highly doped N-type. The first diffusion region I1 may output a supply voltage VVSS based on the ground voltage VSS. To this end, the first diffusion region I1 may be electrically connected to the third power supply line VVL2 of FIG. 3 . In this case, the third power supply line VL of FIG. 3 may receive the VVSS voltage.

The second diffusion region O1 may be highly doped N-type. The second diffusion region O1 may receive the ground voltage VSS. To this end, the second diffusion region O1 may be electrically connected to the first power supply line VL of FIG. 3 . In this case, the first power supply line VL of FIG. 3 may provide the VSS voltage to the power gating cell.

The gate pattern G1 may be disposed on the P-type semiconductor substrate P-sub and may be spaced apart from the P-type semiconductor substrate P-sub to have a predetermined distance through a gate insulating pattern or the like. The gate pattern G1 may receive the gate control signal GC for determining whether to output the supply voltage VVSS. A channel region may be formed between the first diffusion region I1 and the second diffusion region O1 based on the gate control signal GC, and a supply voltage VVSS may be output.

The third diffusion region T1 may be highly doped in a P+ type. The third diffusion region T1 is disposed adjacent to the second diffusion region O1 . The third diffusion region T1 may receive the ground voltage VSS. To this end, the third diffusion region T1 may be connected to the first power supply line VL of FIG. 3 . The third diffusion region T1 may be a substrate-tap. The third diffusion region T1 is biased to the P-type semiconductor substrate P-sub in order to remove a diode characteristic generated between the P-type semiconductor substrate P-sub and the first diffusion region I1. That is, the ground voltage VSS may be provided.

FIG. 7 is a view for explaining the arrangement of power supply lines in the power gating cell of FIG. 6 . 7 illustrates a unit area U1_2 corresponding to the first area U1 of FIG. 1 . Referring to FIG. 7 , various power supply lines are disposed on the power gating cells PGC and standard cells of the unit area U1_2 .

The arrangement of the first power supply lines (VSS lines extending in the second direction DR2 ) may be the same as the VDD lines extending in the second direction DR2 of FIG. 5 . The arrangement of the second power supply lines (VVSS lines extending in the second direction) may be the same as the VVDD lines extending in the second direction DR2 of FIG. 5 . The arrangement of the third power supply lines (VDD lines extending in the second direction DR2 ) may be the same as the VSS lines extending in the second direction DR2 of FIG. 5 . The arrangement of the fourth power supply lines (VVSS lines extending in the first direction DR1 ) may be the same as the VVDD lines extending in the first direction DR1 of FIG. 5 . The arrangement of the fifth power supply lines (VDD lines extending in the second direction DR2 ) may be the same as the VSS lines extending in the first direction DR1 of FIG. 5 .

5, the standard cells receive the power supply voltage VDD through the third and fifth power supply lines, and receive the supply voltage VVSS based on the ground voltage VSS through the second and fourth power supply lines. can be input.

8 is a plan view illustrating a semiconductor device according to an embodiment of the present invention. Referring to FIG. 8 , the semiconductor device 200 includes power gating cells PGC, standard cells STC, and tap cells TPC. Since the power gating cells PGC and the standard cells STC correspond to the power gating cells PGC and the standard cells STC of FIG. 1 , a detailed description thereof will be omitted.

The tap cells TPC may provide a bias to the well or the substrate so that the well or the substrate of the semiconductor device 200 has a constant voltage. For example, the tap cells TPC may provide a well-tied bias voltage so that the N-well does not have a reduced voltage in a specific region. This bias voltage may be a power supply voltage VDD. For example, the tap cells TPC may provide a substrate-tied bias voltage so that the P-type semiconductor substrate does not have an increased voltage in a specific region. This bias may be a ground voltage (VSS).

The semiconductor device 200 may be a result of replacing some of the power gating cells PGC of FIG. 1 with the tap cells TPC. When it is required that the ratio of the area of the power gating cells PGC to the entire area of the semiconductor device 200 on a plane satisfies within 3%, the ratio in FIG. 1 is 4.16%, so it may exceed 3%. . That is, when the number of power gating cells PGC exceeds the reference number, some of the power gating cells PGC may be replaced with tap cells TPC.

When the power gating cells PGC are disposed in the diagonal direction, that is, in the fourth direction DR4 , a path through which voltages are transmitted to the standard cells STC may be reduced. The number of power gating cells PGC required to secure the performance of the standard cells STC may be reduced. Furthermore, when a part of the power gating cells PGC is replaced with the tap cells TPC, the distance between the power gating cells PGC is to satisfy the number of power gating cells PGC required for the semiconductor device 200 . may not be required to adjust.

In the semiconductor device 200 , half of the power gating cells PGC of FIG. 1 may be replaced with tap cells TPC. As a result, one tap cell TPC may be disposed between the two power gating cells PGC in the first direction DR1 , the second direction DR2 , and the fourth direction DR4 . A ratio of the area of the power gating cells PGC to the entire area of the semiconductor device 200 on a plane may be reduced to 2.08%. The semiconductor device 200 includes a plurality of unit regions in which power gating cells PGC and tap cells TPC are arranged in the same pattern, and FIG. 9 shows one unit region. The unit area may include 48 standard cells STC in the first direction DR1 and 48 standard cells STC in the second direction DR2 .

A distance between the power gating cell PGC and the tap cell TPC in the first direction DR1 may be a first interval D1 and corresponds to the first interval D1 of FIG. 1 . A distance between the power gating cell PGC and the tap cell TPC in the second direction DR2 may be the second interval D2 and corresponds to the second interval D2 of FIG. 1 . A distance between the power gating cell PGC and the tap cell TPC in the fourth direction DR4 may be a third interval, and the third interval is the first component D3 and the second direction in the first direction DR1 . It may be divided into a second component (D4) of (DR2). The first component D3 and the second component D4 correspond to the first component D3 and the second component D4 of FIG. 1 .

The power gating cells PGC may be arranged to have an interval twice the first interval D1 in the first direction DR1 . For example, an interval twice as large as the first interval D1 may be 72 μm to 108 μm. The power gating cells PGC may be arranged to have an interval twice the second interval D2 in the second direction DR2 . For example, an interval twice the second interval D2 may be 9.6 μm to 19.2 μm. The power gating cells PGC may be arranged to have an interval twice the third interval in the fourth direction DR4 . For example, the interval twice the third interval may be divided into a component in the first direction DR1 of 6 μm to 9 μm and a component in the second direction DR2 of 0.8 μm to 1.6 μm.

The arrangement of the power supply lines in the semiconductor device 200 may be as shown in FIG. 5 . VDD lines and VVDD lines extending in the second direction DR2 overlap the power gating cell PGC and the tap cell TPC. VDD lines extending in the second direction DR2 may provide a VDD voltage to the tap cell TPC. However, the present invention is not limited thereto, and VVDD lines extending in the first direction DR1 may provide the VVDD voltage to the tap cell TPC.

9 and 10 are enlarged views of a region BB of FIG. 8 . 9 is an enlarged view of area BB1 corresponding to area BB of FIG. 8 . 10 is an enlarged view of area BB2 corresponding to area BB of FIG. 8 . 9 and 10 , the power gating cell PGC and the tap cell TPC adjacent in the fourth direction DR4 in the BB regions BB1 and BB2 are illustrated. The standard cells (STCs) do not overlap the power gating cell (PGC) and the tap cell (TPC) on a plane.

Each of the standard cells STCs may have a first reference width XR in the first direction DR1 and a second reference width YR in the second direction DR2 . 2 , the first reference width XR may be 1.5 μm to 2.25 μm, and the second reference width YR may be 0.2 μm to 0.4 μm.

The power gating cell (PGC) may be twice the size of each of the standard cells (STCs). 2 , the power gating cell PGC may have a first width X1 in the first direction DR1 and a second width Y1 in the second direction DR2 . The first width X1 may be 1.5 μm to 2.25 μm. The second width Y1 may be 0.4 μm to 0.8 μm.

The tap cell TPC may have the same size as each of the standard cells STCs, and may be 1/2 of the size of the power gating cell PGC. The tap cell TPC may have a third width X2 in the first direction DR1 and a fourth width Y2 in the second direction DR2 . The third width X2 may be 1.5 μm to 2.25 μm. The fourth width Y2 may be 0.2 μm to 0.4 μm. The third width X2 may be equal to the first width X1, and the fourth width Y2 may be 1/2 of the second width Y1. The power gating cell PGC and the tap cell TPC are They are spaced apart from each other by the third interval described in FIG. 8 . The third interval may be divided into a first component D3 corresponding to the first direction DR1 and a second component D4 corresponding to the second direction DR2 . For convenience of description, it is assumed that the first component D3 and the second component D4 are measured based on the lower boundary surface of the power gating cell PGC and the tap cell TPC with reference to the drawings.

Referring to FIG. 9 , the first component D3 may be twice the first reference width XR, and the second component D4 may be twice the second reference width YR. If the third interval is measured with respect to the center of each of the power gating cell PGC and the tap cell TPC, the first component D3 is twice the first reference width XR, and the second component D4 is It may be 1.5 times the second reference width YR.

Referring to FIG. 10 , the first component D3 may be twice the first reference width XR, and the second component D4 may be three times the second reference width YR. If the third interval is measured with respect to the center of each of the power gating cell PGC and the tap cell TPC, the first component D3 is twice the first reference width XR, and the second component D4 is It may be 2.5 times the second reference width YR.

11 is an exemplary layout of the tab cell of FIGS. 8 to 10 . 12 is a cross-sectional view of a partial region of the tap cell of FIG. 11 . 13 is a cross-sectional view of a partial region of a tap cell according to an exemplary embodiment different from FIG. 12 . A partial region of FIG. 12 or 13 is a block indicated by a dotted line of FIG. 11 .

Referring to FIG. 11 , an N-well may be formed in the P-type semiconductor substrate P-sub. An N-well may be formed in at least a portion of the tap cell TPC. It will be understood that the N-well region formed in FIG. 10 is exemplary, and the shape of the N-well may be different from that of FIG. 10 .

The first power supply line VL may be disposed on the tap cell TPC. The first power supply line VL may extend in the second direction DR2 . The tap cell TPC may be electrically connected to the first power supply line VL through a contact pattern. The tap cell TPC may receive the power supply voltage VDD from the first power supply line VL.

The second power supply line VVL1 may be disposed on the tap cell TPC. The second power supply line VVL1 may extend in the first direction DR1 . Unlike the drawing, the tap cell TPC may be electrically connected to the second power supply line VVL1 instead of the first power supply line VL. In this case, the tap cell TPC may receive the supply voltage VVDD from the second power supply line VVL1 . The third power supply line VVL2 may be disposed on the tap cell TPC and the second power supply lines VVL1 . The third power supply line VVL2 may extend in the second direction DR2 and may be electrically connected to the second power supply line VVL1 . The ground voltage supply line VSL may be disposed on the power gating cell PGC1 .

Referring to FIG. 12 , an N-well is formed in the P-type semiconductor substrate P-sub. A diffusion region T1 is formed in the N-well. In this case, the tap cell TPC may be a well-tap that provides a bias to the N-well. The diffusion region T1 may be highly doped N-type. The diffusion region T1 may receive the power supply voltage VDD. To this end, the diffusion region T1 may be connected to the first power supply line VL described in FIG. 10 . The tap cell TPC may provide a bias, that is, a power supply voltage VDD, to the N-well in order to remove a diode characteristic generated between the N-well and the P-type semiconductor substrate P-sub.

Referring to FIG. 13 , a diffusion region T1 is formed in the P-type semiconductor substrate P-sub. In this case, the tap cell TPC may be a substrate-tap that provides a bias to the P-type semiconductor substrate P-sub. For example, the diffusion region T1 may be provided in a region in which an N-well is not formed in FIG. 11 . The diffusion region T1 may be highly doped P-type. The diffusion region T1 may receive the ground voltage VSS. The tap cell TPC is biased, that is, a ground voltage VSS, to the P-type semiconductor substrate P-sub in order to remove a diode characteristic generated between the P-type semiconductor substrate P-sub and the adjacent N-well. ) can be provided.

14 is a plan view illustrating a semiconductor device according to an embodiment of the present invention. Referring to FIG. 14 , the semiconductor device 300 includes power gating cells PGC, standard cells STC, and tap cells TPC. The semiconductor device 300 may be a result of replacing some of the power gating cells PGC of FIG. 1 with the tap cells TPC.

In the semiconductor device 300 , 1/3 of the power gating cells PGC of FIG. 1 may be replaced with tap cells TPC. As a result, two power gating cells PGC may be disposed between the two tap cells TPC in the first direction DR1 , the second direction DR2 , and the fourth direction DR4 . A ratio of the area of the power gating cells PGC to the entire area of the semiconductor device 300 on a plane may be reduced to 2.77%.

The semiconductor device 300 includes a plurality of unit regions in which power gating cells PGC and tap cells TPC are arranged in the same pattern, and FIG. 13 illustrates a portion of one unit region. The unit area may include 72 standard cells STC in the first direction DR1 and 72 standard cells STC in the second direction DR2. It will be understood that the number of tap cells TPC of FIG. 13 is exemplary. According to the number of power gating cells PGC required in the semiconductor device 300 , various numbers of power gating cells PGC may be replaced with tap cells TPC. In FIG. 14 , the ratio of the number of tap cells TPC to the number of power gating cells PGC is 2:1, but is not limited thereto, and various ratios such as n:1 or 1:n (n>1) are used. may be provided.

The separation distance of the nearest tap cell TPC or power gating cell PGC from the power gating cell PGC in the first direction DR1 may be the first interval D1, and the first interval D1 of FIG. 1 . corresponds to The separation distance of the nearest tap cell TPC or power gating cell PGC from the power gating cell PGC in the second direction DR2 may be the second interval D2, and the second interval D2 of FIG. 1 . corresponds to The separation distance of the nearest tap cell TPC or power gating cell PGC from the power gating cell PGC in the fourth direction DR4 may be a third interval, and the third interval is the third interval in the first direction DR1 . It may be divided into a first component D3 and a second component D4 in the second direction DR2. The first component D3 and the second component D4 correspond to the first component D3 and the second component D4 of FIG. 1 or FIG. 8 .

15 is an exemplary block diagram of a design system of the semiconductor device illustrated in FIGS. 1 to 14 . Referring to FIG. 15 , the design system 1000 may include a CPU 1100 , a working memory 1200 , an input/output device 1300 , a storage device 1400 , and a system interconnector 1500 . Here, the design system 1000 may be provided as a dedicated device for arranging standard cells, power gating cells, and tap cells of the present invention, but is not limited thereto. For example, the design system 1000 may be implemented as a computer system having a design program for the placement of cells.

The CPU 1100 may execute software (application programs, operating systems, device drivers) to be executed in the design system 1000 . The CPU 1100 may execute an operating system (OS, not shown) loaded into the working memory 1200 . The CPU 1100 may execute various application programs to be driven based on an operating system (OS). For example, the CPU 1100 may execute the design tool 1210 loaded in the working memory 1200 .

An operating system (OS) or application programs may be loaded into the working memory 1200 . When the design system 1000 is booted, an OS image (not shown) stored in the storage device 1400 may be loaded into the working memory 1200 based on a booting sequence. All input/output operations of the design system 1000 may be supported by the operating system (OS). Similarly, application programs may be loaded into the working memory 1200 to be selected by a user or to provide a basic service. In particular, the design tool 1210 for the arrangement of cells of the present invention may also be loaded into the working memory 1200 from the storage device 1400 .

The working memory 1200 may be a volatile memory such as a static random access memory (SRAM) or a dynamic random access memory (DRAM), or a nonvolatile memory such as a PRAM, MRAM, ReRAM, FRAM, or NOR flash memory.

The design tool 1210 may place standard cells, power gating cells, and tap cells, and perform routing. The design tool 1210 may arrange the power gating cells based on the number of power gating cells set according to a design rule and the spacing between the power gating cells. As described above, the design tool 1210 may arrange the power gating cells in a diagonal direction.

The design tool 1210 may perform a design rule check (DRC) on the arranged power gating cells. The design tool 1210 may change some of the power gating cells to tap cells when the number of the arranged power gating cells or the spacing between the power gating cells does not satisfy a design rule.

A cell library for representing cells of a semiconductor device as a layout may be defined in the design tool 1210 . A cell suitable for a semiconductor circuit may be selected from among standard cells defined in the cell library, and a cell selected by the design tool 1210 may be disposed. In addition, routing for the arranged cells may be performed by the design tool 1210 . The above-described processes may be performed automatically or manually by the design tool 1210 .

The input/output device 1300 controls user input and output from user interface devices. For example, the input/output device 1300 may include a keyboard or a monitor to receive a netlist file or the like for designing a semiconductor device. For example, the input/output device 1300 may display a result of arrangement and routing of cells by the design tool 1210 .

The storage device 1400 is provided as a storage medium of the design system 1000 . The storage device 1400 may store application programs, an operating system image, and various data. The storage device 1400 may be provided as a memory card (MMC, eMMC, SD, MicroSD, etc.) or a hard disk drive (HDD). The storage device 1400 may include a NAND-type flash memory having a large storage capacity. Alternatively, the storage device 1400 may include a next-generation nonvolatile memory such as PRAM, MRAM, ReRAM, or FRAM, or NOR flash memory.

The system interconnector 1500 may be a system bus for providing a network inside the design system 1000 . The CPU 1100 , the working memory 1200 , the input/output device 1300 , and the storage device 1400 may be electrically connected to each other and exchange data through the system interconnector 1500 .

16 is an exemplary flowchart of a method of designing a semiconductor device by the design system of FIG. 15 . The steps of FIG. 16 may be performed by the design system 1000 of FIG. 15 . The steps of FIG. 16 may be performed using the design tool 1210 of FIG. 15 .

In operation S110 , the design system 1000 may determine the number of power gating cells PGC. The number of power gating cells PGC may be determined in consideration of a ratio of an area of the power gating cells PGC to the entire area of the semiconductor device. For example, the ratio may be about 4% or about 3%.

In operation S120 , the design system 1000 may determine an interval between the power gating cells PGC. For example, the interval may be the above-described first interval D1. For example, in order to consider a voltage drop according to line resistance, the spacing between the power gating cells PGC may be determined in consideration of the maximum distance between the standard cells and the power gating cells PGC. For example, when the power gating cells PGC also function as a well-tap or a substrate-tap, the spacing between the power gating cells PGC may be determined in consideration of the maximum distance between the tap and the standard cells. For example, it may be required that the maximum distance between the tap cell or the power gating cell (PGC) and the standard cell be within 100 μm.

In operation S130 , the design system 1000 may arrange the power gating cells PGC. The power gating cells PGC may be arranged according to the number of power gating cells PGC determined in step S110 and a distance between the power gating cells PGC determined in step S120 . In addition, the power gating cells PGC may be arranged in the fourth direction DR4 as shown in FIG. 1 .

In operation S140 , the design system 1000 may determine whether the number of power gating cells PGC is greater than the first reference number R1 . The first reference number R1 may be an upper limit of the number of power gating cells PGC required in the semiconductor device. When the number of power gating cells PGC is greater than the first reference number R1, step S145 is performed. When the number of power gating cells PGC is not greater than the first reference number R1, step S150 is performed.

In operation S145 , the design system 1000 may determine that the number of power gating cells PGC is excessive, and may replace some of the power gating cells PGC with tap cells TPC. For example, the replacement result may be the same as the arrangement of the power gating cells PGC and the tap cells TPC of FIG. 8 or 14 . Step S145 may be repeated until the number of power gating cells PGC is not greater than the first reference number R1.

In operation S150 , the design system 1000 may determine whether the number of power gating cells PGC is smaller than the second reference number R2 . The second reference number R2 may be a lower limit of the number of power gating cells PGC required in the semiconductor device. The first reference number R1 and the second reference number R2 may be the same or different. When the number of power gating cells PGC is smaller than the second reference number R2, step S155 is performed. When the number of power gating cells PGC is not smaller than the second reference number R2, the design system 1000 determines that the number of power gating cells PGC is appropriate and ends the arrangement of the power gating cells PGC. can do.

In operation S155 , the design system 1000 may determine that the number of power gating cells PGC is small, and thus may reduce an interval between the power gating cells PGC. For example, the interval may be the above-described first interval D1. As the distance between the power gating cells PGC is reduced, the maximum distance between the power gating cells PGC and the standard cell may be reduced, and abnormal operation of the standard cells due to voltage drop may be improved. After step S155, steps S130 to S155 may be repeated until the number of power gating cells PGC satisfies the reference range.

The contents described above are specific examples for carrying out the present invention. The present invention will include not only the above-described embodiments, but also simple design changes or easily changeable embodiments. In addition, the present invention will also include techniques that can be easily modified and implemented in the future using the above-described embodiments.

100, 200, 300: semiconductor device STC: standard cell
PGC: power gating cell TPC: tap cell
1000: design system of a semiconductor device

Claims (10)

first power supply lines arranged in a first direction and extending in a second direction;
second power supply lines arranged in the second direction and extending in the first direction;
power gating switches each connected to one of the first power supply lines and at least two of the second power supply lines;
each comprising tabs connected to one of the first power supply lines or one of the second power supply lines;
Among the power gating switches, a power gating switch closest to a first power gating switch is a second power gating switch, a tap closest to the first power gating switch among the taps is a first tap, and the second power gating switch and at least one of the first tabs is spaced apart from the first power gating switch in a third direction different from the first and second directions. According to claim 1,
a logic circuit operative based on a supply voltage delivered through the second power supply lines;
The power gating switches output the supply voltage to the second power supply lines based on a gate control signal and a power supply voltage received from the first power supply lines. 3. The method of claim 2,
and third power supply lines arranged in the first direction and extending in the second direction,
The logic circuit operates based on a ground voltage transmitted through the third power supply lines. 3. The method of claim 2,
Each of the power gating switches,
a first diffusion region coupled to one of the first power supply lines;
a second diffusion region coupled to one of the second power supply lines;
a gate pattern for receiving the gate control signal; and
and a third diffusion region doped with a different type from the first diffusion region and connected to one of the first power supply lines. According to claim 1,
A size of each of the power gating switches is greater than a size of each of the taps. According to claim 1,
The first tab is disposed between the first power gating switch and the second power gating switch in the third direction. According to claim 1,
a second tab closest to the first tab among the tabs is spaced apart from the first tab in the third direction;
The first tab is disposed between the first power gating switch and the second tab in the third direction. According to claim 1,
The first power gating switch is disposed between the second power gating switch and the first tab in the third direction. a first power gating switch;
a second power gating switch closest to the first power gating switch in a first direction and spaced apart from the first power gating switch to have a first interval;
A third power gating switch that is the closest power gating switch from the first power gating switch in a second direction perpendicular to the first direction, and is spaced apart from the first power gating switch to have a second interval smaller than the first interval ;
a fourth power gating switch closest to the first power gating switch in a third direction different from the first and second directions, and spaced apart from the first power gating switch to have a third interval smaller than the second interval power gating switch;
a first tab disposed between the first power gating switch and the second power gating switch;
a second tab disposed between the first power gating switch and the third power gating switch; and
and a third tab disposed between the first power gating switch and the fourth power gating switch. 10. The method of claim 9,
first power supply lines extending in the second direction and outputting a first voltage to the first to fourth power gating switches and the first to third taps;
and second power supply lines extending in the first direction and receiving a second voltage based on the first voltage from the first to fourth power gating switches.

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