KR20210065022A - Operating method of memory system including memory controller and nonvolatile memory device - Google Patents

Abstract

The present invention provides an operating method of a memory system including a memory controller and a nonvolatile memory device to efficiently back up data when sudden power-off (SPO) occurs during a program operation, and efficiently perform the program operation after power restoration. According to one embodiment of the present invention, the operating method of a memory system including a memory controller and a nonvolatile memory device comprises: a step of preprogramming multi-page data of the memory controller in memory cells of the nonvolatile memory device; a step of generating a state group code having fewer bits than the bits of the multi-page data based on the multi-page data; a step of backing up the state group code in the nonvolatile memory device if sudden power-off occurs after the memory cells are preprogrammed; a step of reading the multi-page data from the preprogrammed memory cells based on the backed-up state group code after power restoration from the sudden power-off; a step of reprogramming the multi-page data in the memory cells based on the read multi-page data; and a step of reprogramming the multi-page data in the memory cells based on the multi-page data of the memory controller if the sudden power-off does not occur after the memory cells are preprogrammed.

Description

An operating method of a memory system including a memory controller and a nonvolatile memory device

The present invention relates to a semiconductor device, and more particularly, to a method of operating a memory system for efficiently completing a program operation when a sudden power off (SPO) occurs while data is being programmed in a nonvolatile memory device. .

As an example of a nonvolatile memory device, a flash memory device includes memory cells each having different threshold voltages according to a program state. In a single level cell (SLC) mode, the memory cell may be programmed to have a threshold voltage corresponding to one of an erase state and a program state. Meanwhile, in a multi-level cell (MLC) mode, the memory cell may be programmed to have a threshold voltage corresponding to one of an erase state and a plurality of program states.

When the SPO of the nonvolatile memory device occurs, data backup of memory cells in program execution may be required. In this case, the amount of data to be backed up for the memory cells programmed in the MLC mode is larger than that of the memory cells programmed in the SLC mode, and thus the required capacity of the auxiliary power used for data backup increases.

An object of the present invention is to solve the above-described technical problem, and to provide an operating method of a memory system for efficiently backing up data when an SPO occurs during a program operation and efficiently performing a program operation again after power recovery.

According to an embodiment of the present invention, a method of operating a memory system including a memory controller and a nonvolatile memory device includes pre-programming multi-page data of the memory controller into memory cells of the non-volatile memory device; generating a state group code having fewer bits than bits of the multi-page data based on data; when a sudden power-off occurs after the memory cells are pre-programmed, converting the state group code into the nonvolatile memory Backing up the device to the device, after power recovery from the sudden power-off, reading the multi-page data from the pre-programmed memory cells based on the backed-up state group code, based on the read multi-page data reprogramming the multi-page data into the memory cells, and when the sudden power-off does not occur after the memory cells are pre-programmed, the memory cells are written to the memory cells based on the multi-page data of the memory controller. and reprogramming the multi-page data.

According to an embodiment of the present invention, a method of operating a memory system including a memory controller and a nonvolatile memory device includes pre-programming multi-page data of the memory controller into memory cells of the non-volatile memory device; generating a status group code having fewer bits than bits of the multi-page data based on data, backing up the status group code to the nonvolatile memory device, and sudden power after the status group code is backed up reading the multi-page data from the pre-programmed memory cells based on the backed-up state group code after power recovery when an off occurs, and applying the multi-page data to the memory cells based on the read multi-page data reprogramming the page data; and if the sudden power-off does not occur after the state group code is backed up, reprogramming the multi-page data in the memory cells based on the multi-page data of the memory controller including the steps of

According to an embodiment of the present invention, a method of operating a memory system including a memory controller and a nonvolatile memory device includes the steps of preprogramming multi-page data of the memory controller into first memory cells of the nonvolatile memory device; generating a status group code having fewer bits than bits of the multi-page data based on the multi-page data; when a sudden power-off occurs after the first memory cells are pre-programmed, generating the status group code backing up to the nonvolatile memory device, reading the multi-page data from the preprogrammed first memory cells based on the backed-up state group code after power recovery from the sudden power-off; pre-programming the multi-page data in second memory cells of the nonvolatile memory device based on the multi-page data, and the read multi-page data after pre-programming the multi-page data in the second memory cells reprogramming the multi-page data in the second memory cells based on and reprogramming the multi-page data in the first memory cells based on the data.

According to an embodiment of the present invention, a method of operating a memory system including a memory controller and a nonvolatile memory device includes: first preprogramming multi-page data of the memory controller into memory cells of the nonvolatile memory device; generating a first state group code having fewer bits than bits of the multi-page data based on the multi-page data; when a sudden power-off occurs after the memory cells are first pre-programmed, the first Backing up the state group code to the nonvolatile memory device and after power recovery from the sudden power-off, reading the multi-page data from the first pre-programmed memory cells based on the backed-up first state group code outputting the multi-page data, second pre-programming the multi-page data into the first pre-programmed memory cells based on the read multi-page data, and bits of the multi-page data based on the read multi-page data generating a second state group code having fewer bits; backing up the second state group code to the nonvolatile memory device when a sudden power-off occurs after the memory cells are second preprogrammed; , reading the multi-page data from the second pre-programmed memory cells based on the backed-up second state group code after power recovery from the sudden power-off, and the second pre-programmed memory cells and reprogramming the multi-page data in the second pre-programmed memory cells based on the multi-page data read from the memory cell.

When an SPO occurs during a program operation for multi-bit data, the memory system according to an embodiment of the present invention backs up an amount of data less than the amount of multi-bit data, and recovers multi-bit data based on the backed up data after power recovery can do. Accordingly, auxiliary power and memory capacity used for data backup may be reduced, and the cost of a circuit or printed circuit board (PCB) connected to the auxiliary power may be reduced.

1 is a block diagram illustrating a memory system according to an embodiment of the present invention.
FIG. 2 is a diagram illustrating an exemplary program operation of the memory system of FIG. 1 in an SPO occurrence situation.
3 is a graph illustrating a threshold voltage distribution of a nonvolatile memory device according to an embodiment of the present invention.
FIG. 4 is an exemplary block diagram of the memory controller of FIG. 1 .
FIG. 5 is an exemplary block diagram of the nonvolatile memory device of FIG. 1 .
6 is a circuit diagram exemplarily illustrating a memory block according to an embodiment of the present invention.
7 shows an example of generating a status group code according to an embodiment of the present invention.
8 is a flowchart illustrating a method of operating the memory system of FIG. 1 according to an embodiment of the present invention.
9 is a flowchart illustrating operations between a memory controller and a nonvolatile memory device when an SPO occurs according to an embodiment of the present invention.
10 is a flowchart illustrating operations between a memory controller and a nonvolatile memory device when an SPO occurs according to an embodiment of the present invention.
11 is a flowchart illustrating operations between a memory controller and a nonvolatile memory device when power is restored from an SPO according to an embodiment of the present invention.
FIG. 12 is a diagram for explaining a read operation of the nonvolatile memory device of FIG. 5 .
13 is a block diagram illustrating a page buffer according to an embodiment of the present invention.
14 is a graph illustrating examples of read voltages in a normal read mode and a recovery read mode according to an embodiment of the present invention.
15 is a table showing examples of read voltages in a normal read mode according to an embodiment of the present invention.
16 is a table showing examples of read voltages in a recovery read mode according to an embodiment of the present invention.
17A and 17B show examples of adjusting a recovery read voltage according to embodiments of the present invention.
18 is a flowchart illustrating a method of operating a memory system according to an embodiment of the present invention.
19 is a flowchart illustrating a method of operating a memory system according to an embodiment of the present invention.
20 is a flowchart illustrating a method of operating a memory system according to an embodiment of the present invention.
21 is a block diagram illustrating an example in which a memory system according to embodiments of the present invention is applied to an SSD system.
22 is a block diagram illustrating a network system to which a memory system according to an embodiment of the present invention is applied.

Hereinafter, embodiments of the present invention will be described clearly and in detail to the strength that a person of ordinary skill in the art can easily practice the present invention.

1 is a block diagram illustrating a memory system according to an embodiment of the present invention. Referring to FIG. 1 , a memory system 10 may include a memory controller 100 and a non-volatile memory (NVM) 200 . For example, the memory system 10 may be implemented as a storage device such as a solid state drive (SSD).

The memory controller 100 may control the overall operation of the nonvolatile memory device 200 . Specifically, the memory controller 100 may control the nonvolatile memory device 200 by providing a control signal CTRL, a command CMD, and/or an address ADDR to the nonvolatile memory device 200 . . In an exemplary embodiment, the memory controller 100 programs data DATA in the nonvolatile memory device 200 or data DATA from the nonvolatile memory device 200 in response to a request from an external host device. The nonvolatile memory device 200 may be controlled to read

In an exemplary embodiment, the command CMD and the address ADDR may be transmitted from the memory controller 100 to the nonvolatile memory device 200 using the same input/output channel as the data DATA. In another exemplary embodiment, the command CMD and the address ADDR are transmitted from the memory controller 100 to the nonvolatile memory device 200 using the first input/output channel, and the data DATA is transmitted through the second input/output channel. may be transmitted from the memory controller 100 to the nonvolatile memory device 200 using

The memory controller 100 may include a power sensor 110 , a program manager 120 , and a buffer memory 130 . The power detector 110 may detect a power state of the memory controller 100 . For example, the power detector 110 may detect an SPO unexpectedly generated from a voltage provided to the memory controller 100 , and detect power recovery from the SPO. When the voltage provided to the memory controller 100 is less than the reference voltage, the power detector 110 may determine that the SPO has occurred. When the voltage provided to the memory controller 100 exceeds the reference voltage, the power detector 110 may determine that the power is restored.

The program manager 120 may manage a program operation of the nonvolatile memory device 200 . The program manager 120 may provide a control signal CTRL, a command CMD, an address ADDR, and/or data DATA to the nonvolatile memory device 200 according to a predetermined schedule for a program operation. have. In an exemplary embodiment, when an SPO occurs during a program operation, the program manager 120 performs a control signal CTRL, a command CMD, an address ADDR, a control signal CTRL, a command CMD, an address ADDR, and a control signal according to a predetermined schedule so that the program operation can be normally completed. and/or the data DATA may be provided to the nonvolatile memory device 200 .

The buffer memory 130 may temporarily store data. In an exemplary embodiment, the buffer memory 130 temporarily stores data DATA to be provided to the nonvolatile memory device 200 in a program operation, or data (DATA) provided from the nonvolatile memory device 200 in a read operation. DATA) can be temporarily stored.

The nonvolatile memory device 200 may operate under the control of the memory controller 100 . In an exemplary embodiment, the nonvolatile memory device 200 may output stored data DATA under the control of the memory controller 100 or store data DATA provided from the memory controller 100 .

The nonvolatile memory device 200 may include a memory cell array 210 . The memory cell array 210 may include a plurality of memory cells. For example, the plurality of memory cells may be flash memory cells. However, the present invention is not limited thereto, and the memory cells include a resistive random access memory (RRAM) cell, a ferroelectric random access memory (FRAM) cell, a phase change random access memory (PRAM) cell, a thyristor random access memory (TRAM) cell, They may be Magnetic Random Access Memory (MRAM) cells. Hereinafter, embodiments of the present invention will be described focusing on an embodiment in which the memory cells are NAND flash memory cells.

In an exemplary embodiment, each of the plurality of memory cells included in the memory cell array 210 may store N-bit data (N is a positive integer). When N is 2 or more, the memory cell may be referred to as a multi-level cell (MLC), and N-bit data may be referred to as multi-bit data. For example, when N is 3, the memory cell may be referred to as a triple level cell (TLC). For example, when N is 4, the memory cell may be referred to as a quadruple level cell (QLC). However, hereinafter, in all cases where N is 2 or more, all N-bit data will be referred to as “multi-bit data”.

According to embodiments of the present invention, when an SPO occurs during a program operation for multi-bit data, the memory system 10 backs up an amount of data smaller than the amount of multi-bit data, and based on the backed-up data after power recovery can recover multi-bit data. Accordingly, auxiliary power and memory capacity used for data backup may be reduced. Hereinafter, embodiments of the present invention for efficiently completing a program when an SPO occurs during a program operation for multi-bit data will be described in detail.

FIG. 2 is a diagram illustrating an exemplary program operation of the memory system of FIG. 1 in an SPO occurrence situation. 3 is a graph illustrating a threshold voltage distribution of a nonvolatile memory device according to an embodiment of the present invention.

2 and 3 , when a program is started, the memory system 10 may pre-program (or coarse-program) multi-bit data into memory cells of the nonvolatile memory device 200 . . For example, when the multi-bit data is 4-bit data, as shown in FIG. 3 , the pre-programmed memory cell may have any one of 16 threshold voltage distributions (ie, states) (E, P1 to P15). It may have a threshold voltage corresponding to the distribution (ie, state) of . The 16 threshold voltage distributions may respectively correspond to 16 values that multi-bit data may have. That is, the preprogrammed memory cell may correspond to one of 16 threshold voltage distributions according to a multi-bit data value. In this case, threshold voltages of the memory cells may be changed due to capacitive coupling between adjacent memory cells, and the width of each threshold voltage distribution may be widened by the threshold voltage fluctuation. Accordingly, adjacent threshold voltage distributions may overlap.

Threshold voltage distributions of preprogrammed memory cells may be divided into a plurality of state groups. For example, as shown in FIG. 3 , threshold voltage distributions corresponding to the erase state E and the first to fifteenth program states P1 to P15 are the first state group GROUP1 and the second state group. (GROUP2). In an exemplary embodiment, each of the state groups may include different threshold voltage distributions, and the threshold voltage distributions of each of the state groups may not overlap each other. For example, the first state group GROUP1 includes an erase state E, a second program state P2, a fourth program state P4, a sixth program state P6, an eighth program state P8, threshold voltage distributions corresponding to the tenth program state P10, the twelfth program state P12, and the fourteenth program state P14, and the second state group GROUP2 includes the first program state P1; A third program state P3, a fifth program state P5, a seventh program state P7, a ninth program state P9, an eleventh program state P11, a thirteenth program state P13, and a 15 , threshold voltage distributions corresponding to the program state P15 may be included.

Each of the state groups may be indicated by state group data. For example, the first state group GROUP1 and the second state group GROUP2 may be indicated by 1-bit state group data. For example, state group data indicating the first state group GROUP1 may be indicated by “0”, and state group data indicating the second state group GROUP2 may be indicated by “1”. However, the present invention is not limited thereto, and the number of bits of the state group data may vary according to the number of state groups. For example, when the threshold voltage distributions are divided into four state groups, the state group data may be 2-bit data. In this case, the number of bits of the state group data may be smaller than the number of bits of the multi-bit data, and when the multi-bit data is N bits, the state group data may be (N-1) bits.

The pre-programmed multi-bit data may correspond to state group data representing any one of a plurality of state groups according to a data value. For example, as shown in FIG. 3 , the multi-bit data corresponding to the erase state E corresponds to state group data indicating the first state group GROUP1 and corresponding to the first program state P1. The multi-bit data may correspond to state group data representing the second state group GROUP2.

When the SPO occurs after the pre-programming is completed, the memory system 10 may back up state group data corresponding to the pre-programmed memory cell in the nonvolatile memory device 200 . For example, as shown in FIG. 3 , when multi-bit data corresponding to the first program state P1 is pre-programmed, the memory system 10 stores the nonvolatile memory device ( 200), the state group data indicating the second state group GROUP2 may be backed up.

When power is restored from the SPO, the memory system 10 may restore multi-bit data based on the backed-up state group data. For example, the memory system 10 may read multi-bit data from a preprogrammed memory cell based on the state group data. As shown in FIG. 3 , even if an overlapping region exists in threshold voltage distributions of preprogrammed memory cells, when a read operation is performed for each state group based on state group data, the overlapped region corresponds to a certain threshold voltage distribution. belonging can be distinguished. Accordingly, the reliability of the recovered multi-bit data may be improved.

The memory system 10 may reprogram (or fine-program) the multi-bit data into the memory cell based on the recovered multi-bit data. According to the reprogram operation, a program operation on multi-bit data may be completed. As shown in FIG. 3 , the width of the threshold voltage distribution of the memory cells may be narrowed by performing the reprogramming operation. Since the threshold voltage rise of the memory cell due to the reprogramming is smaller than the threshold voltage rise due to the preprogramming, the threshold voltage distribution according to the reprogramming may be less affected by the coupling. Accordingly, according to the reprogramming operation, the memory cells may have narrow threshold voltage distributions, and an overlapping area of the threshold voltage distributions may be reduced. Accordingly, when multi-bit data is read from the reprogrammed memory cell, reliability of the multi-bit data may be improved.

In an exemplary embodiment, the reprogram verification voltage for reprogramming the multi-bit data may be higher than the pre-program verification voltage for preprogramming the multi-bit data. For example, a pre-program operation is performed using a pre-program verification voltage corresponding to a threshold voltage lower than a desired threshold voltage, and during the re-program operation, the memory cell selects a desired threshold by using a re-program verification voltage higher than the pre-program verification voltage. It can be programmed with voltage.

As described with reference to FIG. 2 , the memory system 10 may back up the state group data after the SPO occurs, but the present invention is not limited thereto. For example, the memory system 10 may back up the state group data before the SPO occurs.

As described above, the memory system 10 may back up the state group data corresponding to the multi-bit data in the SPO situation, and complete the program operation on the multi-bit data based on the backed up state group data. In this case, since the number of bits of the state group data is smaller than the number of bits of the multi-bit data, the auxiliary power and memory capacity required for the backup operation may be reduced compared to the operation of directly backing up the multi-bit data.

Hereinafter, as shown in FIG. 3 , embodiments of the present invention will be described focusing on an embodiment in which multi-bit data is 4-bit data and state group data is 1-bit data, but the present invention is not limited thereto. no.

FIG. 4 is an exemplary block diagram of the memory controller of FIG. 1 . Referring to FIG. 4 , the memory controller 100 includes a power detector 110 , a program manager 120 , a buffer memory 130 , a processor 140 , an error correction code (ECC) circuit 150 , and a host interface 160 . ), a nonvolatile memory interface 170 , and a bus 180 . Hereinafter, duplicate contents among the contents described above with reference to FIG. 1 may be omitted.

The power detector 110 may detect the occurrence of the SPO by sensing the voltage supplied to the memory controller 100 , or may detect power recovery from the SPO. For example, the power detector 110 may be implemented as a voltage sensor.

The program manager 120 may manage a program operation for multi-bit data. For example, as described with reference to FIG. 2 , the program manager 120 performs a control signal CTRL, a command CMD, and/or a program operation on multi-bit data through pre-programming and re-programming. Alternatively, an address ADDR may be generated. When the SPO is detected during a program operation on multi-bit data, the program manager 120 uses a control signal CTRL, a command CMD, and/or an address to complete the program operation for multi-bit data according to a predetermined schedule. (ADDR) can be created.

In an exemplary embodiment, the program manager 120 may manage address information in which multi-bit data is to be programmed and address information in which state group data is to be backed up. The address information may be stored in the buffer memory 130 or a separate memory inside the memory controller 100 . When SPO occurs, such address information may be backed up in the nonvolatile memory device 200 together with state group data.

In an exemplary embodiment, the program manager 120 may be implemented in software or firmware such as a Flash Translation Layer (FTL). In this case, the program manager 120 may be loaded into a memory (eg, the buffer memory 130 or a separate memory) in the memory controller 100 and executed by the processor 140 . However, the present invention is not limited thereto, and the program manager 120 may be implemented as hardware.

The buffer memory 130 may temporarily store data provided from the host, generated inside the memory controller 100 , or provided from the nonvolatile memory device 200 . For example, the buffer memory 130 may temporarily store multi-bit data to be provided to the nonvolatile memory device 200 while a program is being executed. When SPO occurs during a program operation, multi-bit data stored in the buffer memory 130 may be lost. After power is restored from the SPO, multi-bit data read from the nonvolatile memory device 200 may be temporarily stored in the buffer memory 130 . For example, the buffer memory 130 may be implemented as DRAM or SRAM, but the present invention is not limited thereto.

The processor 140 may control the overall operation of the memory controller 100 . For example, the processor 140 may drive the program manager 120 . Accordingly, a program operation on multi-bit data may be performed.

The ECC circuit 150 may correct an error in data read from the nonvolatile memory device 200 . For example, when power is restored from the SPO, the ECC circuit 150 may correct an error in the multi-bit data read from the nonvolatile memory device 200 . When reprogramming is performed based on the error-corrected multi-bit data, reliability of the multi-bit data programmed in the nonvolatile memory device 200 may be improved.

The host interface 160 may provide a physical connection between the host and the memory controller 100 . For example, the host interface 160 may include an advanced technology attachment (ATA), serial ATA (SATA), external SATA (e-SATA), small computer small interface (SCSI), serial attached SCSI (SAS), peripheral component (PCI). interconnection), PCI-E (PCI express), IEEE 1394, USB (universal serial bus), SD (secure digital) card, MMC (multi-media card), eMMC (embedded multi-media card), CF (compact flash) It may include various interface methods such as a card interface and the like.

The memory interface 170 may provide a physical connection between the memory controller 100 and the nonvolatile memory device 200 . For example, a control signal CTRL, a command CMD, an address ADDR, and data DATA are transmitted/received between the memory controller 100 and the nonvolatile memory device 200 through the memory interface 170 . can be The bus 180 may be configured to provide a channel between components of the memory controller 100 .

FIG. 5 is an exemplary block diagram of the nonvolatile memory device of FIG. 1 . Referring to FIG. 5 , the nonvolatile memory device 200 may include a memory cell array 210 , a page buffer unit 220 , a control logic circuit 230 , a voltage generator 240 , and a row decoder 250 . can Although not shown in FIG. 5 , the nonvolatile memory device 200 may further include a data input/output circuit or an input/output interface. In addition, the nonvolatile memory device 200 may further include column logic, a pre-decoder, a temperature sensor, a command decoder, an address decoder, and the like.

The memory cell array 210 may include a plurality of memory blocks BLK1 to BLKz (z is a positive integer), and each of the plurality of memory blocks BLK1 to BLKz may include a plurality of memory cells. have. The memory blocks BLK1 to BLKz may be included in one memory plane, but the present invention is not limited thereto. The memory cell array 210 may be connected to the page buffer unit 220 through bit lines BL, and connect the word lines WL, the string select lines SSL, and the ground select lines GSL. It may be connected to the row decoder 250 through the

In an exemplary embodiment, the memory cell array 210 may include a 3D memory cell array, and the 3D memory cell array may include a plurality of NAND strings. Each NAND string may include memory cells respectively connected to word lines stacked vertically on the substrate. This will be explained in detail with reference to FIG. 6 . U.S. Patent Publication No. 7,679,133, U.S. Patent Publication No. 8,553,466, U.S. Patent Publication No. 8,654,587, U.S. Patent Publication No. 8,559,235, and U.S. Patent Application Publication No. 2011/0233648 are incorporated herein by reference in their entirety. are combined In an exemplary embodiment, the memory cell array 210 may include a 2D memory cell array, and the 2D memory cell array may include a plurality of NAND strings disposed along row and column directions.

The page buffer unit 220 may include a plurality of page buffers PB1 to PBn (n is an integer greater than or equal to 3), and the plurality of page buffers PB1 to PBn connect a plurality of bit lines BL. may be respectively connected to the memory cells through the The page buffer 220 may select at least one bit line from among the bit lines BL in response to the column address Y-ADDR. The page buffer 220 may operate as a write driver or a sense amplifier according to an operation mode. For example, during a program operation, the page buffer 220 may apply a bit line voltage corresponding to data to be programmed to a selected bit line. During a read operation, the page buffer 220 may sense data stored in the memory cell by sensing a current or voltage of the selected bit line. A detailed description of each of the page buffers PB1 to PBn will be described later with reference to FIG. 13 .

The control logic circuit 230 may generally control various operations in the nonvolatile memory device 200 . The control logic circuit 230 programs data into or reads data from the memory cell array 210 in response to the control signal CTRL, the command CMD, and/or the address ADDR. Alternatively, various control signals for erasing data stored in the memory cell array 210 may be output. For example, the control logic circuit 230 may output a voltage control signal CTRL_vol, a row address X-ADDR, and a column address Y-ADDR.

In an exemplary embodiment, the control logic circuit 230 may output control signals for programming multi-bit data according to the received control signal CTRL, command CMD, and/or address ADDR. For example, the control logic circuit 230 outputs control signals for pre-programming and re-programming, outputting control signals for backing up state group data, or a control signal for reading pre-programmed multi-bit data. can be printed out.

The voltage generator 240 may generate various types of voltages for performing program, read, and erase operations based on the voltage control signal CTRL_vol. For example, the voltage generator 240 may generate a program voltage, a read voltage, and a program verify voltage as the word line voltage VWL. For example, the program voltage may be generated using an incremental step pulse program (ISPP) method.

In a program operation for multi-bit data, the voltage generator 240 may generate a pre-program verification voltage for pre-programming and generate a re-program verification voltage for re-programming. In this case, the pre-program verification voltage may be smaller than the re-program verification voltage.

The row decoder 250 may select one of the plurality of word lines WL and select one of the plurality of string selection lines SSL in response to the row address X-ADDR. For example, during a program operation, the row decoder 250 may apply a program voltage and a program verify voltage to a selected word line, and during a read operation, apply a read voltage to the selected word line.

6 is a circuit diagram exemplarily illustrating a memory block according to an embodiment of the present invention. Referring to FIG. 6 , the memory block BLK may correspond to one of the memory blocks BLK1 to BLKz of FIG. 5 . The memory block BLK includes NAND strings NS11 to NS33 , and each NAND string (eg, NS11 ) includes a string select transistor SST, a plurality of memory cells MCs, and a ground select transistor connected in series. (GST) may be included.

The NAND strings NS11 , NS21 , and NS31 are positioned between the first bit line BL1 and the common source line CSL, and the NAND strings NS12 are positioned between the second bit line BL2 and the common source line CSL. , NS22 and NS32 may be positioned, and NAND strings NS13 , NS23 , and NS33 may be positioned between the third bit line BL3 and the common source line CSL. The string select transistor SST may be connected to the corresponding string select lines SSL1 to SSL3 . The memory cells MCs may be respectively connected to the corresponding word lines WL1 to WL8. The ground select transistor GST may be connected to the corresponding ground select lines GSL1 to GSL3. The string select transistor SST may be connected to the corresponding bit lines BL1 to BL3 , and the ground select transistor GST may be connected to the common source line CSL. Here, the number of NAND strings, the number of word lines, the number of bit lines, the number of ground selection lines, and the number of string selection lines may be variously changed according to embodiments.

7 shows an example of generating a status group code according to an embodiment of the present invention. Referring to FIG. 7 , multi-page data may include first to n-th multi-bit data MD1 to MDn to be programmed in n memory cells connected to one word line. For example, when the multi-bit data is 4-bit data, the multi-page data may include first to fourth page data PD1 to PD4.

The state group code may include first to n-th state group data SD1 to SDn generated based on the first to n-th multi-bit data MD1 to MDn. For example, state group data may be generated based on the number of “1” bits (or “0” bits) among bits of multi-bit data. For example, when the number of bits “1” is odd, state group data may be generated as 1, and when the number of bits “1” is even, state group data may be generated as 0. For example, when 1-bit state group data is generated based on multi-bit data, first state group data SD1 “0” is generated based on first multi-bit data MD1 '1001', The two-state group data SD2 “1” may be generated based on the second multi-bit data MD2 '1000'. Accordingly, a status group code may be generated from the multi-page data.

The bits of the generated status group code may be fewer than the bits of the multi-page data. For example, when 1-bit status group data is generated from 4-bit multi-data data, bits of the status group code may be reduced to 1/4 times that of bits of multi-page data.

Hereinafter, detailed operations of the memory system 10 of FIG. 1 will be described based on multi-page data and state group codes.

8 is a flowchart illustrating a method of operating the memory system of FIG. 1 according to an embodiment of the present invention. 1 and 8 , in step S110 , the memory system 10 may preprogram multi-page data into memory cells. In operation S120 , the memory system 10 may generate a state group code based on the multi-page data. The state group code may be generated by the memory controller 100 or generated by the nonvolatile memory device 200 . For example, the state group code may be generated through a logical operation on bits of multi-bit data.

In step S130 , the memory system 10 may determine whether an SPO has occurred. When SPO occurs, in step S140 , the memory system 10 may back up the state group code to the nonvolatile memory device 200 . In this case, the state group code may be backed up in the same memory plane as the memory plane in which the multi-page data is pre-programmed, but the present invention is not limited thereto.

In operation S150 , the memory system 10 may read multi-page data from preprogrammed memory cells based on the backed-up state group code after power recovery. The nonvolatile memory device 200 may read multi-page data in a manner different from a general read operation to perform a read operation based on the state group code. For example, the nonvolatile memory device 200 may read multi-page data using a read voltage level different from a read voltage level used in a general read operation.

In operation S160 , the memory system 10 may reprogram the multi-page data in memory cells based on the read multi-page data. In this case, the reprogrammed memory cells may be the same memory cells as the preprogrammed memory cells.

If SPO does not occur after preprogramming, in step S170 , the memory system 10 may reprogram the multipage data in the memory cells without backing up the state group code. Since the multi-page data of the buffer memory 130 may be maintained as the SPO does not occur, the memory system 10 performs multi-page data based on the multi-page data stored in the buffer memory 130 of the memory controller 100 . can be reprogrammed.

In FIG. 8, an embodiment in which a state group code is generated after multi-page data is pre-programmed has been described, but the present invention is not limited thereto. For example, the status group code may be generated during a pre-program operation or may be generated prior to a pre-program operation.

According to the embodiment of FIG. 8 , when an SPO occurs during a program operation, the memory system 10 may back up the state group code instead of the multi-page data. Even if the memory system 10 does not back up the original multi-page data, the memory system 10 may recover multi-page data from preprogrammed memory cells based on the backed-up state group code. Accordingly, since the size and capacity of the auxiliary power required for data backup may be reduced, the manufacturing cost and size of the memory system 10 may be reduced.

Hereinafter, operation methods of the memory system 10 when an SPO occurs will be described in detail with reference to FIGS. 9 to 10 .

9 is a flowchart illustrating operations between a memory controller and a nonvolatile memory device when an SPO occurs according to an embodiment of the present invention. Specifically, FIG. 9 shows an embodiment in which a state group code is generated in the nonvolatile memory device 200 .

Referring to FIG. 9 , in operation S210 , the memory controller 100 may transmit a pre-program command for multi-page data to the nonvolatile memory device 200 . The memory controller 100 may transmit multi-page data to the nonvolatile memory device 200 together with a pre-program command. For example, when the multi-page data is 4 pages, the memory controller 100 may transmit the command CMD and the address ADDR to the nonvolatile memory device 200 so that the multi-page data is pre-programmed in the QLC mode. .

In operation S220 , the nonvolatile memory device 200 may preprogram the multi-page data in response to the preprogram command. For example, the nonvolatile memory device 200 may pre-program the multi-page data in memory cells indicated by the address ADDR based on the pre-program verification voltage.

In operation S230 , the memory controller 100 may transmit a state group code generation command to the nonvolatile memory device 200 . For example, the memory controller 100 may transmit a separate command CMD for generating the status group code to the nonvolatile memory device 200 . In operation S240 , the nonvolatile memory device 200 may generate a state group code in response to a state group code generation command. The nonvolatile memory device 200 may generate a state group code based on multi-page data.

In an exemplary embodiment, the nonvolatile memory device 200 may generate state group data based on each multi-bit data of the multi-page data loaded into the page buffer unit 220 of FIG. 5 . For example, the nonvolatile memory device 200 may generate state group data through a logical operation on bits of multi-bit data. The generated state group data may be temporarily stored in the page buffer 220 .

In operation S250 , the memory controller 100 may transmit a state group code output command to the nonvolatile memory device 200 . In operation S260 , the nonvolatile memory device 200 may transmit the state group code to the memory controller 100 in response to the state group code output command. For example, the nonvolatile memory device 200 may output a state group code temporarily stored in the page buffer unit 220 . The state group code provided from the nonvolatile memory device 200 may be stored in the buffer memory 130 of the memory controller 100 . In some embodiments, step S250 may be omitted. For example, the nonvolatile memory device 200 may generate a state group code in response to a state group code generation command, and transmit the generated state group code to the memory controller 100 .

In step S270 , the memory controller 100 may detect the SPO. According to the SPO detection, in step S280 , the memory controller 100 may transmit a state group code backup command to the nonvolatile memory device 200 . The memory controller 100 may transmit the state group code to the nonvolatile memory device 200 together with the state group code backup command. For example, the memory controller 100 may transmit the command CMD and the address ADDR to the nonvolatile memory device 200 so that the state group code is programmed in the SLC mode. In this case, the memory controller 100 may transmit a separate command CMD to the nonvolatile memory device 200 to change the nonvolatile memory device 200 to the SLC mode, but the present invention is not limited thereto.

In operation S290 , the nonvolatile memory device 200 may back up the state group code in response to the state group code backup command. For example, the nonvolatile memory device 200 may program the state group code in the SLC mode in memory cells corresponding to the address ADDR. However, the present invention is not limited thereto, and the nonvolatile memory device 200 may program the state group code in the MLC mode in response to the command CMD from the memory controller 100 .

In FIG. 9 , steps S250 and S260 in which the state group code is output from the nonvolatile memory device 200 according to a command of the memory controller 100 are illustrated, but steps S250 and S260 may be omitted. In this case, the state group code may be backed up in the nonvolatile memory device 200 according to a copyback command of the memory controller 100 .

10 is a flowchart illustrating operations between a memory controller and a nonvolatile memory device when an SPO occurs according to an embodiment of the present invention. Specifically, FIG. 1 shows an embodiment in which a state group code is generated by the memory controller 100 .

Referring to FIG. 9 , in step S310 , the memory controller 100 may transmit a pre-program command for multi-page data to the nonvolatile memory device 200 . In operation S320 , the nonvolatile memory device 200 may preprogram the memory cells with multipage data in response to the preprogram command.

In operation S330 , the memory controller 100 may generate a state group code. The memory controller 100 may generate a state group code based on multi-page data. In an exemplary embodiment, the memory controller 100 may generate a state group code based on multi-page data stored in the buffer memory 130 . For example, the memory controller 100 may generate state group data through a logic operation on bits of multi-bit data. The generated state group data may be temporarily stored in the buffer memory 130 .

In step S340 , the memory controller 100 may detect the SPO. According to the SPO detection, in step S350 , the memory controller 100 may transmit a state group code backup command to the nonvolatile memory device 200 . The memory controller 100 may transmit the generated state group code together with the state group code backup command to the nonvolatile memory device 200 . For example, the memory controller 100 may transmit the command CMD and the address ADDR to the nonvolatile memory device 200 so that the state group code is programmed in the SLC mode.

In operation S360 , the nonvolatile memory device 200 may back up the state group code in response to the state group code backup command. For example, the nonvolatile memory device 200 may program the state group code in the SLC mode in memory cells corresponding to the address ADDR.

Hereinafter, operating methods of the memory system 10 when power is restored from the SPO will be described in detail with reference to FIGS. 11 to 17B .

11 is a flowchart illustrating operations between a memory controller and a nonvolatile memory device when power is restored from an SPO according to an embodiment of the present invention. Referring to FIG. 11 , in step S401 , the memory controller 100 may detect power-up. The memory controller 100 may determine that the power of the memory system 10 is restored according to the power-up detection.

In operation S402 , the memory controller 100 may transmit a state group code read command to the nonvolatile memory device 200 . The memory controller 100 may transmit a state group code read command based on address information corresponding to preprogrammed memory cells. For example, the memory controller 100 may transmit the command CMD and the address ADDR to the nonvolatile memory device 200 so that the state group code is read in the SLC mode. In this case, the memory controller 100 may transmit a separate command CMD to the nonvolatile memory device 200 to change the nonvolatile memory device 200 to the SLC mode.

In operation S403 , the nonvolatile memory device 200 may read the state group code in response to the state group code read command. For example, the nonvolatile memory device 200 may read the state group code from memory cells corresponding to the address ADDR in the SLC mode. The read state group code may be stored in the page buffer 220 of FIG. 5 .

Although not shown in FIG. 11 , when the status group code and the multi-page data are stored in different memory planes or when an error correction for the status group code is required, the read status group code is an output command of the memory controller 100 . may be transmitted to the memory controller 100 . In this case, the state group code provided to the memory controller 100 may be error-corrected by the ECC circuit 150 of FIG. 4 and transmitted to the nonvolatile memory device 200 again.

In operation S404 , the memory controller 100 may transmit a recovery read mode change command to the nonvolatile memory device 200 . For example, the memory controller 100 may transmit a recovery read mode change command through the control signal CTRL or the command CMD. In operation S405 , the nonvolatile memory device 200 may change to the recovery read mode in response to the recovery read mode change command. The nonvolatile memory device 200 may perform a read operation in the recovery read mode differently from the normal read mode. For example, the nonvolatile memory device 200 may perform a read operation in the recovery read mode using read voltages different from the read voltages in the normal read mode.

In operation S406 , the memory controller 100 may transmit a multi-page data read command to the nonvolatile memory device 200 . For example, the memory controller 100 may transmit the command CMD and the address ADDR to the nonvolatile memory device 200 so that multi-page data is read in the QLC mode.

In operation S407 , the nonvolatile memory device 200 may read preprogrammed multi-page data in response to a multi-page data read command. In the recovery read mode, the nonvolatile memory device 200 may perform a read operation based on the state group code. For example, the nonvolatile memory device 200 may read multi-bit data from each of the preprogrammed memory cells using read voltages corresponding to state group data for each of the preprogrammed memory cells. For example, the read multi-page data may be stored in the page buffer unit 220 of FIG. 5 . The read operation based on the state group code will be described in detail with reference to FIGS. 12 to 17B .

In operation S408 , the memory controller 100 may transmit a multi-page data output command to the nonvolatile memory device 200 . In operation S409 , the nonvolatile memory device 200 may output the read multi-page data in response to the multi-page data output command. For example, the nonvolatile memory device 200 may transmit multi-page data stored in the page buffer unit 220 to the memory controller 100 . In some embodiments, step S408 may be omitted. For example, the nonvolatile memory device 200 may perform a read operation in response to a multi-page data read command and transmit the read multi-page data to the memory controller 100 .

In operation S410 , the memory controller 100 may correct an error in the multi-page data. When there is no error in the multi-page data, the memory controller 100 may not perform an error correction operation. Accordingly, multi-page data may be recovered, and reliability of the recovered multi-page data may be improved. In an exemplary embodiment, the error correction operation of step S410 may be omitted.

In an exemplary embodiment, operations S406 to S410 of FIG. 11 may be performed for each page. For example, the memory controller 100 may provide a read command for each of the 4 pages to the nonvolatile memory device 200 , and provide an output command for each of the 4 pages to the nonvolatile memory device 200 . can do.

In operation S411 , the memory controller 100 may transmit a general read mode change command to the nonvolatile memory device 200 . For example, the memory controller 100 may transmit a general read mode change command through the control signal CTRL or the command CMD. In operation S412 , the nonvolatile memory device 200 may change to a normal read mode in response to a normal read mode change command. The nonvolatile memory device 200 may perform a read operation using preset read voltages regardless of the state group code in the normal read mode.

In operation S413 , the memory controller 100 may transmit a multi-page data reprogram command to the nonvolatile memory device 200 . The memory controller 100 may transmit the multi-page data recovered through step S410 to the nonvolatile memory device 200 together with a reprogram command. For example, when the multi-page data is 4 pages, the memory controller 100 may transmit the command CMD and the address ADDR to the nonvolatile memory device 200 so that the multi-page data is reprogrammed in the QLC mode. .

In operation S414 , the nonvolatile memory device 200 may reprogram the multi-page data in response to the reprogram command. For example, the nonvolatile memory device 200 may program multi-page data in memory cells indicated by the address ADDR based on the reprogram verification voltage. The address ADDR provided for reprogramming may be the same as the address ADDR provided for preprogramming.

FIG. 12 is a diagram for explaining a read operation of the nonvolatile memory device of FIG. 5 . Referring to FIG. 12 , the nonvolatile memory device 200 may include NAND strings SS1 to SSn and page buffers PB1 to PBn. The NAND strings SS1 to SSn may be respectively connected to the page buffers PB1 to PBn through the bit lines BL1 to BLn.

The NAND strings SS1 to SSn may include ground select transistors GST1 to GSTn, memory cells MC10 to MCnm, and string select transistors SST1 to SSTn. The ground select transistors GST1 to GSTn may be connected to the common source line CSL and the ground select line GSL, and the memory cells MC10 to MCnm may be connected to the word lines WL0 to WLm. The string select transistors SST1 to SSTn may be connected to the string select line SSL and the bit lines BL1 to BLn.

Among the memory cells MC10 to MCnm, the memory cells MC11 to MCn1 connected to the first word line WL1 may be in a pre-programmed state. As described with reference to FIGS. 8 to 10 , multi-page data may be pre-programmed in the memory cells MC11 to MCn1 according to a pre-program command from the memory controller 100 . For example, as shown in FIG. 7 , when the multi-page data includes the first to n-th multi-bit data MD1 to MDn, the first multi-bit data MD1 is pre-programmed in the memory cell MC11, The 2-bit data MD2 may be pre-programmed in the memory cell MC21.

The page buffers PB1 to PBn may store state group codes including first to n-th state group data SD1 to SDn. The first to nth state group data SD1 to SDn may correspond to the preprogrammed memory cells MC11 to MCn1 . The status group code may be stored in the page buffers PB1 to PBn according to a status group code read command from the memory controller 100 or a status group code transmission from the memory controller 100 . For example, the first page buffer PB1 stores the first state group data SD1 corresponding to the memory cell MC11 , and the second page buffer PB2 includes the second page buffer PB2 corresponding to the memory cell MC21 . The state group data SD2 may be stored.

In the normal read mode, during a read operation on the preprogrammed memory cells MC11 to MCn1 , normal read voltages are applied to the first word line WL1 to read multi-page data from the memory cells MC11 to MCn1 . have.

In the recovery read mode, during a read operation on the preprogrammed memory cells MC11 to MCn1 , recovery read voltages are applied to the first word line WL1 to read multi-page data from the memory cells MC11 to MCn1 . have. Levels of the recovery read voltages may be different from levels of normal read voltages. For example, in order to read multi-bit data preprogrammed in the memory cell MC11 , first recovery read voltages corresponding to the first state group data SD1 may be applied to the first word line WL1 . . In order to read the multi-bit data preprogrammed in the memory cell MC21 , second recovery read voltages corresponding to the second state group data SD2 may be applied to the first word line WL1 . When the first state group data SD1 and the second state group data SD2 are the same, the first recovery read voltages and the second recovery read voltages may be the same. When the first state group data SD1 and the second state group data SD2 are different from each other, the first recovery read voltages and the second recovery read voltages may be different from each other. That is, recovery read voltages corresponding to respective values (eg, “0” and “1”) that the state group data SD1 to SDn may have are applied to the first word line WL1 to form the memory cells MC11 . to MCn1), multi-page data may be read.

13 is a block diagram illustrating a page buffer according to an embodiment of the present invention. Referring to FIG. 13 , the page buffer 221 includes a sense latch 201, a force latch 202, an upper bit latch (eg, M-latch) 203 connected to the sensing node SO. a middle bit latch (eg, U-latch) 204 , a low-bit latch (eg, L-latch) 205 , and a cache latch 206 . Also, the page buffer 221 may further include a first transistor TR1 connected between the bit line BL and the sensing node SO.

The sense latch 201 may store data stored in a memory cell or a sensing result of a threshold voltage of the memory cell during a read operation or a program verify operation. Also, the sense latch 201 may be used to apply a program bit line voltage or a program prohibit voltage to the bit line BL during a program operation.

The force latch 202 may be utilized to improve threshold voltage distribution during a program operation. During the program operation, the value stored in the force latch 202 may be changed according to the threshold voltage of the memory cell, and the voltage applied to the bit line BL may vary according to the value stored in the force latch 202 during the program operation. have.

The upper bit latch 203 , the middle bit latch 204 , the lower bit latch 205 , and the cache latch 206 may be utilized to store externally input data during a program operation, and will be referred to as a data latch. can The number of data latches may be variously changed according to an embodiment. For example, when 4-bit data is programmed into one memory cell, 4-bit data is stored in the upper bit latch 203, the middle bit latch 204, the lower bit latch 205, and the cache latch 206, respectively. can be saved. For example, when 5-bit data is programmed into one memory cell, the page buffer 221 may further include a second intermediate bit latch, and the 5-bit data includes the upper bit latch 203 and the middle bit latch ( 204 ), a second middle bit latch, a lower bit latch 205 , and a cache latch 206 , respectively. However, the present invention is not limited thereto, and the page buffer 221 may further include two or more data latches. Until the program is complete, the high bit latch 203 , the middle bit latch 204 , the low bit latch 205 , and the cache latch 206 may hold the stored data. Also, the cache latch 206 may receive data read from the memory cell during a read operation from the sense latch 201 and output the data to the outside through the data output line DOUT.

In an exemplary embodiment, at least one of the data latches 203 to 206 may temporarily store state group data. Alternatively, the page buffer 221 may further include at least one state group data latch for temporarily storing the state group data.

The first transistor TR1 is driven by a bit line shut-off signal BLSHF that controls the connection between the bit line BL and the sensing node SO, and thus, the “bit line shut -off transistor". For example, when data is read from the memory cell, the first transistor TR1 is turned on to electrically connect the bit line BL and the sense latch 201 . In addition, when data stored in the sense latch 201 is transferred to the cache latch 206 or data stored in the cache latch 206 is transferred to the force latch 202 , the first transistor TR1 is turned off (turn-off). off) can be turned off.

14 is a graph illustrating examples of read voltages in a normal read mode and a recovery read mode according to an embodiment of the present invention. 12 and 14 , each of the preprogrammed memory cells MC11 to MCn1 may correspond to one of a plurality of threshold voltage distributions E and P1 to P15 according to a multi-bit data value. For example, when the multi-bit data '1111' is pre-programmed in the memory cell MC11, the memory cell MC11 may be in the erase state (E). Multi-bit data '1110', '1010', '1000', '1001', '0001', '0000', '0010', '0110', '0100', '1100', '1101', '0101' When one of , '0111', '0011', and '1011' is pre-programmed in the memory cell MC11, the memory cell MC11 may be in one of the first to fifteenth program states P1 to P15. . However, the present invention is not limited thereto, and multi-bit data values corresponding to the threshold voltage distributions E, P1 to P15 may be changed.

Each of the preprogrammed memory cells MC11 to MCn1 is applied to one of the threshold voltage distributions E, P2, P4, P6, P8, P10, P12, P14 of the first state group GROUP1 according to the multi-bit data value. It may correspond to one of the threshold voltage distributions P1 , P3 , P5 , P7 , P9 , P11 , P13 , and P15 of the second state group GROUP2 . For example, the memory cell MC11 in which one of multi-bit data '1111', '1010', '1001', '0000', '0110', '1100', '0101', and '0011' is pre-programmed is Corresponding to the first state group GROUP1, one of multi-bit data '1110', '1000', '0001', '0010', '0100', '1101', '0111', and '1011' is pre-programmed The memory cell MC11 may correspond to the second state group GROUP2 . For example, the first state group GROUP1 may correspond to state group data 0 , and the second state group GROUP2 may correspond to state group data 1 .

In the normal read mode, first to fifteenth normal read voltages V1n to V15n may be used to read multi-page data of the preprogrammed memory cells MC11 to MCn1 . For example, as shown in FIG. 14 , the first to fifteenth general read voltages V1n to V15n may be voltages used to read multi-page data from memory cells in which a program operation is completed through reprogramming. have. Multi-page data may be read from the preprogrammed memory cells MC11 to MCn1 by applying the first to fifteenth normal read voltages V1n to V15n to the first word line WL1 . When multi-page data is read based on the general read voltages V1n to V15n, the state of each of the preprogrammed memory cells MC11 to MCn1 may not be accurately determined, and the read multi-bit data value may be preprogrammed. The possibility of being different from the data value stored in the memory cell may increase. That is, the reliability of the read multi-bit data may be reduced. Accordingly, when reprogramming is performed based on the multi-page data read in the normal read mode, the reliability of the programmed multi-page data may be reduced.

In the recovery read mode, first to fourteenth recovery read voltages V1 to V14 may be used to read multi-page data of the preprogrammed memory cells MC11 to MCn1 . Specifically, the first recovery read voltages V1, V3, V5, V7, and V9 to read multi-page data from memory cells corresponding to the first state group GROUP1 among the preprogrammed memory cells MC11 to MCn1 . , V11 and V13 may be used, and second recovery read voltages V2 to read multi-page data from memory cells corresponding to the second state group GROUP2 among the preprogrammed memory cells MC11 to MCn1 . , V4, V6, V8, V10, V12, V14) may be used. For example, one of multi-bit data '1111', '1010', '1001', '0000', '0110', '1100', '0101', and '0011' is pre-programmed in the memory cell MC11. In this case, multi-bit data may be read from the memory cell MC11 based on the first recovery read voltages V1 , V3 , V5 , V7 , V9 , V11 , and V13 . For example, one of multi-bit data '1110', '1000', '0001', '0010', '0100', '1101', '0111', and '1011' is pre-programmed in the memory cell MC11. In this case, multi-bit data may be read from the memory cell MC11 based on the second recovery read voltages V2, V4, V6, V8, V10, V12, and V14.

Here, the first recovery read voltages V1 , V3 , V5 , V7 , V9 , V11 , and V13 corresponding to the first state group GROUP1 and the second recovery read voltages corresponding to the second state group GROUP2 are (V2, V4, V6, V8, V10, V12, V14) may be different from each other. Also, the recovery read voltages V1 to V14 used in the recovery read mode may be different from the normal read voltages V1n to V15n used in the normal read mode.

As described above, in the recovery read mode, recovery read voltages V1 to V14 different from the normal read voltages V1n to V15n may be used. In this case, the state of each of the preprogrammed memory cells MC11 to MCn1 may be determined relatively accurately, and the possibility that the read multi-bit data value and the data value stored in the preprogrammed memory cell match may increase. That is, the reliability of the read multi-bit data may be improved. Accordingly, when reprogramming is performed based on the multi-page data read in the recovery read mode, the reliability of the programmed multi-page data may be improved.

15 is a table showing examples of read voltages in a normal read mode according to an embodiment of the present invention. 12 to 15 , when multi-page data is read from the preprogrammed memory cells MC11 to MCn1 in the normal read mode, the read voltages are set to the first word line based on the normal read voltage table NRVT. WL1) can be applied. In this case, read voltages applied for each page may vary.

For example, as shown in FIG. 14 , when threshold voltage distributions and multi-bit data values correspond to each other, normal read voltages are applied to the first word line WL1 to read the first page data of the multi-page data. (V1n, V4n, V6n, V11n) may be applied. Normal read voltages V3n, V7n, V9n, and V13n may be applied to the first word line WL1 to read the second page data of the multi-page data. Normal read voltages V2n, V8n, and V14n may be applied to the first word line WL1 to read the third page data of the multi-page data. Normal read voltages V5n, V10n, V12n, and V15n may be applied to the first word line WL1 to read the fourth page data of the multi-page data. In this case, a read voltage of a low voltage level may be sequentially applied, but the order in which the read voltages are applied may be variously changed.

16 is a table showing examples of read voltages in a recovery read mode according to an embodiment of the present invention. 12 to 16 , when multi-page data is read from the preprogrammed memory cells MC11 to MCn1 in the recovery read mode, the read voltages are set to the first word line based on the recovery read voltage table RRVT. WL1) can be applied. In this case, read voltages applied for each page may vary.

For example, as shown in FIG. 14 , when threshold voltage distributions and multi-bit data values correspond to each other, the first state group is transferred to the first word line WL1 to read the first page data of the multi-page data. The recovery read voltages V1 V3, V5, and V11 corresponding to GROUP1 and the recovery read voltages V4, V6, and V10 corresponding to the second state group GROUP2 may be applied. First page data is read from memory cells corresponding to the first state group GROUP1 by the recovery read voltages V1 V3, V5, and V11, and the second page data is read by the recovery read voltages V4, V6, and V10 First page data may be read from memory cells corresponding to the state group GROUP2 . The recovery read voltages V3, V7, V9, and V13 corresponding to the first state group GROUP1 and the second state group GROUP2 are the first word line WL1 to read the second page data of the multi-page data. ) corresponding recovery read voltages V2, V6, V8, and V12 may be applied. Second page data is read from memory cells corresponding to the first state group GROUP1 by the recovery read voltages V3, V7, V9, and V13, and is applied to the recovery read voltages V2, V6, V8, and V12. Accordingly, second page data may be read from memory cells corresponding to the second state group GROUP2 . Likewise, in order to read the third page data of the multi-page data, the recovery read voltages V1, V7, and V13 corresponding to the first state group GROUP1 and the second state group (V1, V7, V13) to the first word line WL1 Recovery read voltages V2 , V8 , and V14 corresponding to GROUP2 may be applied, and recovery readout corresponding to the first state group GROUP1 may be applied to the first word line WL1 to read fourth page data. The voltages V5 , V9 , and V11 and recovery read voltages V4 , V10 , V12 , and V14 corresponding to the second state group GROUP2 may be applied. In this case, a read voltage of a low voltage level may be sequentially applied, but the order in which the read voltages are applied may be variously changed.

As such, in the recovery read mode, recovery read voltages corresponding to each of the state groups may be applied to the first word line WL1 to read one page.

In an exemplary embodiment, each of the page buffers PB1 to PBn may output only data sensed by recovery read voltages corresponding to the stored state group data to the outside. For example, first data is sensed from the memory cell MC11 by the recovery read voltages corresponding to the first state group GROUP1 , and the memory is determined by the recovery read voltages corresponding to the second state group GROUP2 . Second data may be sensed from the cell MC11 . The sensed first data and second data may be stored in the latches 201 to 205 of FIG. 13 . The page buffer PB1 may output only one of the first and second data to the outside through the cache latch 206 based on the state group data stored in at least one of the latches 201 to 205 .

In an exemplary embodiment, each of the page buffers PB1 to PBn may output data sensed by recovery read voltages corresponding to all state group data to the outside. For example, first data is sensed from the memory cell MC11 by the recovery read voltages corresponding to the first state group GROUP1 , and the memory is determined by the recovery read voltages corresponding to the second state group GROUP2 . Second data may be sensed from the cell MC11 . The sensed first data and second data may be stored in the latches 201 to 205 of FIG. 13 . The page buffer PB1 may output both the first data and the second data to the outside through the cache latch 206 . In this case, the memory controller 100 may select one of the first data and the second data provided from the nonvolatile memory device 200 based on the internal state group data.

In an exemplary embodiment, in order to read multi-page data in the recovery read mode, a command CMD and an address ADDR may be provided for each page. For example, four commands CMD may be provided to read all multi-page data of four pages. In this case, the number of recovery read voltage levels applied according to one command CMD may be greater than the number of normal read voltage levels applied according to one command CMD in the normal read mode. For example, in the recovery read mode, the recovery read voltages V1 , V3 , V5 , and V11 corresponding to the first state group GROUP1 and the second state group according to the command CMD for reading the first page data Recovery read voltages V4 , V6 , and V10 corresponding to GROUP2 may be applied. In the normal read mode, the normal read voltages V1n, V4n, V6n, and V11n may be applied according to the command CMD for reading the first page data. In this case, the number of recovery read voltage levels applied according to one command CMD may be seven, and the number of normal read voltage levels applied according to one command CMD in the normal read mode may be four.

17A and 17B show examples of adjusting a recovery read voltage according to embodiments of the present invention. Referring to FIG. 17A , the NAND string 211 may include 0th to mth memory cells MC0 to MCm. During a program operation on the memory cells MC0 to MCm, the mth memory cell MCm to the 0th memory cell MC0 may be sequentially programmed. That is, a memory cell located close to the string select transistor SST may be programmed first, and a memory cell located far from the string select transistor SST may be programmed later. For example, after the first memory cell MC1 is preprogrammed, the zeroth memory cell MC0 may be preprogrammed.

When power is restored from the SPO after the first memory cell MC1 connected to the first word line WL1 of the NAND string 211 is preprogrammed, in the recovery read mode, the first memory cell MC1 ( Multi-bit data may be read from MC1). In this case, the recovery read voltages may be adjusted according to the state of the first memory cell MC1 and the adjacent zeroth memory cell MC0 . For example, when the zeroth memory cell MC0 is in the preprogram state, the recovery read voltages applied to the first word line WL1 may be increased or decreased. Accordingly, the adjusted recovery read voltages may be applied to the first word line WL1 to read multi-bit data from the first memory cell MC1 .

Referring to FIG. 17B , during a program operation on the memory cells MC0 to MCm, the zeroth memory cell MC0 to the mth memory cell MCm may be sequentially programmed. That is, a memory cell located close to the ground select transistor GST may be programmed first, and a memory cell located far from the ground select transistor GST may be programmed later. For example, after the first memory cell MC1 is preprogrammed, the second memory cell MC2 may be preprogrammed.

When power is restored from the SPO after the first memory cell MC1 connected to the first word line WL1 of the NAND string 211 is preprogrammed, in the recovery read mode, the first memory cell MC1 ( Multi-bit data may be read from MC1). In this case, the recovery read voltages may be adjusted according to the state of the second memory cell MC2 adjacent to the first memory cell MC1 . For example, when the second memory cell MC2 is in the pre-program state, the recovery read voltages applied to the first word line WL1 may be increased or decreased. Accordingly, the adjusted recovery read voltages may be applied to the first word line WL1 to read multi-bit data from the first memory cell MC1 .

As described above, when the adjacent memory cell MC0 or MC2 is preprogrammed after the first memory cell MC1 is preprogrammed, it is applied to the word line WL0 or WL2 connected to the adjacent memory cell MC0 or MC2. The threshold voltage of the first memory cell MC1 may vary depending on the used program voltage. Accordingly, when the recovery read voltages are adjusted according to the pre-program state of the adjacent memory cell MC0 or MC2 , the change in the threshold voltage of the first memory cell MC1 may be compensated.

18 is a flowchart illustrating a method of operating a memory system according to an embodiment of the present invention. 1 and 18 , in operation S510 , the memory system 10 may pre-program multi-page data into memory cells. In operation S520 , the memory system 10 may generate a state group code based on the multi-page data.

In operation S530 , the memory system 10 may back up the state group code to the nonvolatile memory device 200 . In operation S540 , the memory system 10 may determine whether an SPO has occurred. When SPO occurs, in step S550 , the memory system 10 may read multi-page data from preprogrammed memory cells based on the backed-up state group code after power recovery. For example, the memory system 10 may read multi-page data based on the state group code as described with reference to FIGS. 11 to 17B .

In operation S560 , the memory system 10 may reprogram the multi-page data in the memory cells based on the read multi-page data. The reprogrammed memory cells may be the same memory cells as the preprogrammed memory cells.

When the SPO does not occur after preprogramming, in operation S570 , the memory system 10 may reprogram the multipage data in the memory cells. The memory system 10 may reprogram the multi-page data based on the multi-page data stored in the buffer memory 130 of the memory controller 100 .

According to the embodiment of FIG. 18 , the memory system 10 may generate and back up a state group code regardless of whether an SPO has occurred. That is, the state group code for all pre-programmed multi-page data may be backed up in the nonvolatile memory device 200 . Accordingly, since the backup operation for the state group code is not performed in a situation where the SPO occurs, the size and capacity of the auxiliary power used to back up the state group code may be further reduced compared to the embodiment of FIG. 8 .

19 is a flowchart illustrating a method of operating a memory system according to an embodiment of the present invention. 1 and 19 , in operation S610 , the memory system 10 may preprogram multi-page data into first memory cells. In operation S620 , the memory system 10 may generate a state group code based on the multi-page data.

In operation S630 , the memory system 10 may determine whether SPO has occurred. When the SPO occurs, the state group code may be backed up in the nonvolatile memory device 200 in operation S640 . In operation S650 , the memory system 10 may read multi-page data from the preprogrammed first memory cells based on the backed-up state group code after power recovery. For example, the memory system 10 may read multi-page data based on the state group code as described with reference to FIGS. 11 to 17B .

In operation S660 , the memory system 10 may preprogram the multi-page data in the second memory cells based on the read multi-page data. In this case, the first memory cells and the second memory cells may be included in different memory blocks, but the present invention is not limited thereto. In operation S670 , the memory system 10 may reprogram the multi-page data in the second memory cells based on the read multi-page data.

If SPO does not occur after preprogramming, in operation S680 , the memory system 10 may reprogram the multi-page data in the first memory cells. The memory system 10 may reprogram the multi-page data based on the multi-page data stored in the buffer memory 130 of the memory controller 100 .

According to the embodiment of FIG. 19 , the memory system 10 may program multi-page data in second memory cells different from the pre-programmed first memory cells after power recovery from the SPO. That is, in a situation in which the program operation on the first memory cells cannot be performed anymore, the memory system 10 may again perform the program operation on the second memory cells based on the recovered multi-page data.

20 is a flowchart illustrating a method of operating a memory system according to an embodiment of the present invention. 1 and 20 , in step S701 , the memory system 10 may first preprogram multi-page data into memory cells. In operation S702 , the memory system 10 may generate a first state group code based on the multi-page data.

In step S703, the memory system 10 may determine whether SPO has occurred. When the SPO occurs, in operation S704 , the memory system 10 may back up the first state group code to the nonvolatile memory device 200 . In operation S705 , the memory system 10 may read multi-page data from the first pre-programmed memory cells based on the first state group code backed up after power is restored. In operation S706 , the memory system 10 may perform a second preprogramming of the multipage data in the first preprogrammed memory cells based on the read multipage data. For example, the pre-program verify voltage for the second pre-programming may be higher than the pre-program verify voltage for the first pre-program.

When the SPO does not occur after the first pre-programming, in operation S707 , the memory system 10 may second pre-program the multi-page data into the first pre-programmed memory cells. The memory system 10 may perform a second pre-program based on multi-page data stored in the buffer memory 130 of the memory controller 100 .

In operation S708 , the memory system 10 may generate a second state group code based on the multi-page data. For example, overlapping regions of threshold voltage distributions according to the second pre-programming may be reduced than overlapping regions of threshold voltage distributions according to the first pre-programming. Accordingly, the number of state groups for classifying threshold voltage distributions according to the second pre-program may be smaller than the number of state groups for classifying threshold voltage distributions according to the first pre-program. Accordingly, the number of bits of the second state group code may be smaller than the number of bits of the first state group code.

In step S709 , the memory system 10 may determine whether an SPO has occurred. When SPO occurs, in step S710 , the memory system 10 may back up the second state group code to the nonvolatile memory device 200 . In operation S711 , the memory system 10 may read multi-page data from the second pre-programmed memory cells based on the second state group code backed up after power is restored. In operation S712 , the memory system 10 may reprogram the multi-page data into second pre-programmed memory cells based on the read multi-page data. For example, the reprogram verification voltage for re-pre-programming may be higher than the pre-program verification voltage for the second pre-programming.

When the SPO does not occur after the second preprogramming, in step S713 , the memory system 10 may reprogram the multipage data in the second preprogrammed memory cells. When SPO occurs in step S703 , the memory system 10 may perform reprogramming based on multi-page data read from the first preprogrammed memory cells. When SPO does not occur in step S703 , the memory system 10 may perform reprogramming based on the multi-page data stored in the buffer memory 130 of the memory controller 100 .

As described above, the memory system 10 may perform a plurality of pre-program operations. The memory system 10 may generate a state group code (ie, state group data) in response to each pre-program operation. In this case, the number of bits of state group data may vary according to pre-program operations, and the number of bits of state group data corresponding to a previous pre-program operation may be greater than the number of bits of state group data corresponding to subsequent pre-program operations. have.

21 is a block diagram illustrating an example in which a memory system according to embodiments of the present invention is applied to an SSD system. Referring to FIG. 21 , the SSD system 1000 may include a host 1100 and an SSD 1200 . The SSD 1200 may exchange a signal SIG with the host 1100 through a signal connector, and may receive power PWR through a power connector. The SSD 1200 may include an SSD controller 1210 , an auxiliary power supply 1220 , and memory devices 1230 , 1240 , and 1250 . The memory devices 1230 , 1240 , and 1250 may be respectively connected to the SSD controller 1210 through channels Ch1 , Ch2 , and Chn.

The SSD controller 1210 may control the memory devices 1230 , 1240 , and 1250 in response to a signal SIG received from the host 1100 . The SSD controller 1210 may be implemented using the memory controller 100 described above with reference to FIGS. 1 to 20 . For example, the SSD controller 1210 controls the memory devices 1230 , 1240 , and 1250 to back up state group data corresponding to the multi-bit data when an SPO occurs while a program for the multi-bit data is being performed. can do. The SSD controller 1210 may control the memory devices 1230 , 1240 , and 1250 to recover multi-bit data based on the backed-up state group data after power recovery. Accordingly, even if the SPO occurs during the program operation, the program operation for the multi-bit data may be normally completed.

The memory devices 1230 , 1240 , and 1250 may operate under the control of the SSD controller 1210 . Each of the memory devices 1230 , 1240 , and 1250 may be implemented using the nonvolatile memory device 200 described above with reference to FIGS. 1 to 20 . For example, each of the memory devices 1230 , 1240 , and 1250 may back up state group data under the control of the SSD controller 1210 when an SPO occurs. Each of the memory devices 1230 , 1240 , and 1250 may read preprogrammed multi-bit data based on the backed-up state group data under the control of the SSD controller 1210 after power recovery.

The auxiliary power supply 1220 may be connected to the host 1100 through a power connector. The auxiliary power supply 1220 may receive power PWR from the host 1100 and charge it. The auxiliary power supply 1220 may provide power to the SSD 1200 when power supply from the host 1100 is not smooth.

22 is a block diagram illustrating a network system to which a memory system according to an embodiment of the present invention is applied. Referring to FIG. 22 , a network system 2000 is a facility that collects various types of data and provides services, and may be referred to as a data center or a data storage center. The network system 2000 may include application servers 2100 to 2100n and storage servers 2200 to 2200m, and the application servers 2100 to 2100n and the storage servers 2200 to 2200m are computing nodes. may be referred to as The number of application servers 2100 to 2100n and the number of storage servers 2200 to 2200m may be variously selected according to an embodiment, and the number of application servers 2100 to 2100n and the number of storage servers 2200 to 2200m 2200m) may be different.

The application servers 2100 to 2100n and the storage servers 2200 to 2200m may communicate with each other through the network 2300 . The network 2300 may be implemented using Fiber Channel (FC) or Ethernet. In this case, FC is a medium used for high-speed data transmission, and an optical switch providing high performance/high availability may be used. Depending on the access method of the network 2300 , the storage servers 2200 to 2200m may be provided as file storage, block storage, or object storage.

In an exemplary embodiment, the network 2300 may be a storage-only network, such as a storage area network (SAN). For example, the SAN may be an FC-SAN that uses an FC network and is implemented according to FC Protocol (FCP). In an exemplary embodiment, the SAN may be an IP-SAN that uses a TCP/IP network and is implemented according to an iSCSI (SCSI over TCP/IP or Internet SCSI) protocol. In an exemplary embodiment, network 2300 may be a generic network, such as a TCP/IP network. For example, the network 2300 may be implemented according to protocols such as FC over Ethernet (FCoE), Network Attached Storage (NAS), and NVMe over Fabrics (NVMe-oF).

Hereinafter, the application server 2100 and the storage server 2200 will be mainly described. A description of the application server 2100 may be applied to other application servers 2100n, and a description of the storage server 2200 may also be applied to other storage servers 2200m.

The application server 2100 may include a processor 2110 and a memory 2120 . The processor 2110 may control the overall operation of the application server 2100 , and may access the memory 2120 to execute instructions and/or data loaded into the memory 2120 . According to an embodiment, the number of processors 2110 and the number of memories 2120 included in the application server 2100 may be variously selected. In an exemplary embodiment, the processor 2110 and the memory 2120 may be configured as a processor-memory pair. In an exemplary embodiment, the number of the processor 2110 and the memory 2120 may be configured differently.

The application server 2100 may further include a storage device 2150 . In this case, the number of storage devices 2150 included in the application server 2100 may be variously selected according to an embodiment. The processor 2110 may provide a command to the storage device 2150 , and the storage device 2150 may operate in response to a command received from the processor 2110 . However, the present invention is not limited thereto, and the application server 2100 may not include the storage device 2150 .

The application server 2100 may further include a switch 2130 and a network interface card (NIC) 2140 . The switch 2130 may selectively connect the processor 2110 and the storage device 2150 or the NIC 2140 and the storage device 2150 under the control of the processor 2110 . The NIC 2140 may include a wired interface, a wireless interface, a Bluetooth interface, an optical interface, and the like. In an exemplary embodiment, the processor 2110 and the NIC 2140 may be integrated into one. In an exemplary embodiment, the storage device 2150 and the NIC 2140 may be integrated into one.

The application server 2100 may store data requested to be stored by a user or a client in one of the storage servers 2200 to 2200m through the network 2300 . Also, the application server 2100 may obtain data read requested by a user or a client from one of the storage servers 2200 to 2200m through the network 2300 . For example, the application server 2100 may be implemented as a web server or a database management system (DBMS).

The application server 2100 may access the memory 2120n or the storage device 2150n included in another application server 2100n through the network 2300 , or the storage servers 2200 and 2200m through the network 2300 . ) in memory 2220, 2220m or storage devices 2250, 2250m. Accordingly, the application server 2100 may perform various operations on data stored in the application servers 2100 and 2100n and/or the storage servers 2200 and 2200m. For example, the application server 2100 may execute a command for moving or copying data between the application servers 2100 and 2100n and/or the storage servers 2200 and 2200m. In this case, the data may be moved through the network 2300 in an encrypted state for security or privacy.

The storage server 2200 may include a processor 2210 and a memory 2220 . The processor 2210 may control the overall operation of the storage server 2200 , and may access the memory 2220 to execute instructions and/or data loaded into the memory 2220 . According to an embodiment, the number of processors 2210 and the number of memories 2220 included in the storage server 2200 may be variously selected. In an exemplary embodiment, the processor 2210 and the memory 2220 may be configured as a processor-memory pair. In an exemplary embodiment, the number of the processor 2210 and the memory 2220 may be configured differently.

The processor 2210 may include a single-core processor or a multi-core processor. For example, the processor 2210 is a general-purpose processor, a central processing unit (CPU), a graphic processing unit (GPU), a digital signal processor (DSP), a microcontroller (MCU), a microprocessor, a network processor, an embedded processor, It may include a field programmable gate array (FPGA), an application-specific instruction set processor (ASIP), an application-specific integrated circuit processor (ASIC), and the like.

The storage server 2200 may further include at least one storage device 2250 . The number of storage devices 2250 included in the storage server 2200 may be variously selected according to embodiments. The storage device 2250 may include a controller (CTRL) 2251 , a NAND flash (NAND) 2252 , a DRAM 2253 , and an interface (I/F) 2254 . Hereinafter, the configuration and operation of the storage device 2250 will be described in detail. The following description of the storage device 2250 may also be applied to other storage devices 2150 , 2150n , and 2250m .

The interface 2254 may provide a physical connection between the processor 2210 and the controller 2251 and a physical connection between the NIC 2240 and the controller 2251 . For example, the interface 2254 may be implemented in a DAS (Direct Attached Storage) method for directly connecting the storage device 2250 with a dedicated cable. Also, for example, the interface 2254 may be an Advanced Technology Attachment (ATA), Serial ATA (SATA), external SATA (e-SATA), Small Computer Small Interface (SCSI), Serial Attached SCSI (SAS), Peripheral (PCI) Component Interconnection), PCIe (PCI express), NVMe (NVM express), IEEE 1394, USB (universal serial bus), SD (secure digital) card, MMC (multi-media card), eMMC (embedded multi-media card), It may be implemented in various interface methods such as a compact flash (CF) card interface.

The controller 2251 may control overall operations of the storage device 2250 . The controller 2251 may program data into the NAND flash 2252 in response to a program command, or read data from the NAND flash 2252 in response to a read command. For example, program commands and/or read commands may be from processor 2210 in storage server 2200, processor 2210m in another storage server 2200m, or processors 2110, 2110n in application servers 2100, 2100n. It may be provided through the processor 2210 or may be provided directly.

The NAND flash 2252 may include a plurality of NAND flash memory cells. However, the present invention is not limited thereto, and the storage device 2250 includes a nonvolatile memory other than the NAND flash 2252 , for example, a resistive RAM (ReRAM), a phase change RAM (PRAM), or a magnetic RAM (MRAM). ), or may include a magnetic storage medium or an optical storage medium.

A dynamic RAM (DRAM) 2253 may be used as a buffer memory. For example, the DRAM 2253 may be a Double Data Rate Synchronous DRAM (DDR SDRAM), a Low Power DDR (LPDDR) SDRAM, a Graphics DDR (GDDR) SDRAM, a Rambus DRAM (RDRAM), or a High Bandwidth Memory (HBM). However, the present invention is not limited thereto, and the storage device 2250 may use a volatile memory or a nonvolatile memory other than DRAM as the buffer memory. The DRAM 2253 may temporarily store (buffer) data to be programmed into the NAND flash 2252 or data read from the NAND flash 2252 .

The storage server 2200 may further include a switch 2230 and a NIC 2240 . The switch 2230 may selectively connect the processor 2210 and the storage device 2250 or the NIC 2240 and the storage device 2250 under the control of the processor 2210 . In an exemplary embodiment, the processor 2210 and the NIC 2240 may be integrated into one. In an exemplary embodiment, the storage device 2250 and the NIC 2240 may be integrated into one.

The storage devices 2150 , 2150n , 2250 , and 2250m may correspond to the memory system 10 described above with reference to FIGS. 1 to 20 . For example, the storage device 2250 may operate according to a program command for multi-page data from one of the processors 2110 , 2110n , 2210 , and 2210m. When operating according to a program command from one of the processors 2110 , 2110n and 2210m , the storage device 2250 receives the program command through the processor 2210 , or the storage device 2250 operates the switch 2230 . It is possible to receive program commands directly from the connected processor through . The controller 2251 may control the NAND flash 2252 to store multi-page data in the NAND flash 2252 in response to a program command. For example, when SPO occurs during a program operation for multi-page data (eg, when SPO occurs in the storage server 2200), the storage device 2250 sets a status group code corresponding to the multi-page data. may be backed up to the NAND flash 2252 . When power is restored from the SPO, the storage device 2250 may restore preprogrammed multi-page data based on the backed-up state group code. The storage device 2250 may reprogram the multi-page data based on the recovered multi-page data to complete the program operation on the multi-page data.

The above are specific embodiments for carrying out the present invention. The present invention will include not only the above-described embodiments, but also simple design changes or easily changeable embodiments. In addition, the present invention will include techniques that can be easily modified and implemented using the embodiments. Therefore, the scope of the present invention should not be limited to the above-described embodiments, but should be defined by the claims described below as well as the claims and equivalents of the present invention.

10: memory system
100: memory controller
110: power sensor
120: program manager
130: buffer memory
200: nonvolatile memory device
210: memory cell array
220: page buffer unit
230: control logic
240: voltage generator
250: raw decoder

Claims (20)

A method of operating a memory system including a memory controller and a nonvolatile memory device, the method comprising:
preprogramming multi-page data of the memory controller into memory cells of the nonvolatile memory device;
generating a status group code having fewer bits than bits of the multi-page data based on the multi-page data;
backing up the state group code to the nonvolatile memory device when a sudden power-off occurs after the memory cells are preprogrammed;
reading the multi-page data from the pre-programmed memory cells based on the backed-up state group code after power recovery from the sudden power-off;
reprogramming the multi-page data in the memory cells based on the read multi-page data; and
and reprogramming the multi-page data in the memory cells based on the multi-page data of the memory controller when the sudden power-off does not occur after the memory cells are pre-programmed. The method of claim 1,
The state group code includes state group data corresponding to each of the pre-programmed memory cells,
wherein the state group data represents one of the state groups each comprising different threshold voltage distributions. 3. The method of claim 2,
Reading the multi-page data from the pre-programmed memory cells includes:
changing the nonvolatile memory device from a normal read mode to a recovery read mode; and
and applying read voltages corresponding to each of the state groups to a word line connected to the pre-programmed memory cells in the recovery read mode. 4. The method of claim 3,
The read voltage levels applied to the word line to read the multi-page data in the recovery read mode are different from the read voltage levels applied to the word line to read the multi-page data in the normal read mode. . 4. The method of claim 3,
The read voltage levels corresponding to the first state group of the state groups are different from the read voltage levels corresponding to the second state group of the state groups. 4. The method of claim 3,
The number of read voltage levels applied to the word line according to one read command in the recovery read mode is greater than the number of read voltage levels applied to the word line according to one read command in the normal read mode. 4. The method of claim 3,
Levels of the read voltages applied to the word line are adjusted according to whether a memory cell connected to an adjacent word line of the word line is in a pre-programmed state. The method of claim 1,
The program verification voltage for the reprogramming is higher than the program verification voltage for the preprogramming. The method of claim 1,
The state group code is generated in the nonvolatile memory device according to a state group code generation command from the memory controller. The method of claim 1,
The step of backing up the status group code to the nonvolatile memory device includes programming the status group code in a single level cell (SLC) mode in which one data bit is stored in each memory cell of the nonvolatile memory device. How to. The method of claim 1,
The step of reprogramming the multi-page data includes:
recovering multi-page data by correcting errors in the multi-page data read from the pre-programmed memory cells; and
and reprogramming the recovered multi-page data into the memory cells. A method of operating a memory system including a memory controller and a nonvolatile memory device, the method comprising:
preprogramming multi-page data of the memory controller into memory cells of the nonvolatile memory device;
generating a status group code having fewer bits than bits of the multi-page data based on the multi-page data;
backing up the state group code to the nonvolatile memory device;
reading the multi-page data from the pre-programmed memory cells based on the backed-up state group code after power recovery when a sudden power-off occurs after the state group code is backed up;
reprogramming the multi-page data in the memory cells based on the read multi-page data; and
and reprogramming the multi-page data in the memory cells based on the multi-page data of the memory controller when the sudden power-off does not occur after the state group code is backed up. 13. The method of claim 12,
The state group code includes state group data corresponding to each of the pre-programmed memory cells,
wherein the state group data represents one of the state groups each comprising different threshold voltage distributions. 14. The method of claim 13,
Reading the multi-page data from the pre-programmed memory cells includes:
changing the nonvolatile memory device from a normal read mode to a recovery read mode; and
and applying read voltages corresponding to each of the state groups to a word line connected to the preprogrammed memory cells in the recovery read mode. 15. The method of claim 14,
The read voltage levels applied to the word line to read the multi-page data in the recovery read mode are different from the read voltage levels applied to the word line to read the multi-page data in the normal read mode. . 15. The method of claim 14,
The read voltage levels corresponding to the first state group of the state groups are different from the read voltage levels corresponding to the second state group of the state groups. 15. The method of claim 14,
The number of read voltage levels applied to the word line according to one read command in the recovery read mode is greater than the number of read voltage levels applied to the word line according to one read command in the normal read mode. A method of operating a memory system including a memory controller and a nonvolatile memory device, the method comprising:
pre-programming the multi-page data of the memory controller into first memory cells of the nonvolatile memory device;
generating a status group code having fewer bits than bits of the multi-page data based on the multi-page data;
backing up the state group code to the nonvolatile memory device when a sudden power-off occurs after the first memory cells are preprogrammed;
reading the multi-page data from the pre-programmed first memory cells based on the backed-up state group code after power recovery from the sudden power-off;
pre-programming the multi-page data in second memory cells of the nonvolatile memory device based on the read multi-page data;
reprogramming the multi-page data in the second memory cells based on the read multi-page data after pre-programming the multi-page data in the second memory cells; and
and reprogramming the multi-page data in the first memory cells based on the multi-page data of the memory controller when the sudden power-off does not occur after the first memory cells are pre-programmed. Way. 19. The method of claim 18,
The state group code includes state group data corresponding to each of the pre-programmed first memory cells,
wherein the state group data represents one of the state groups each comprising different threshold voltage distributions. 20. The method of claim 19,
Reading the multi-page data from the pre-programmed first memory cells may include:
changing the nonvolatile memory device from a normal read mode to a recovery read mode; and
and applying read voltages corresponding to each of the state groups to a word line connected to the first memory cells in the recovery read mode.

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