KR20210053179A - Semiconductor device and method - Google Patents

Abstract

The present invention relates to a method which comprises the following steps of: forming a gate structure on pins protruding from a semiconductor substrate; forming an isolation area surrounding the pins; depositing a spacer layer on the gate structure and the pins, wherein the spacer layer fills areas extended from the gaps between adjacent pins among the pins; performing first etching on the spacer layer, wherein after the first etching, first remaining parts of the spacer layer within the internal areas extended from the gaps between the adjacent pins among the pings have a first thickness and second remaining parts of the spacer layer which is not present within the internal areas have a second thickness less than the first thickness; and forming an epitaxial source/drain area which is disposed adjacent to the gate structure and extended on the pins, wherein parts of the epitaxial source/drain area, which are within the internal areas, are separated from the first remaining parts of the spacer layer. According to the method of the present invention, additional problems caused by a decrease in minimum feature sizes can be solved.

Description

Semiconductor device and method {SEMICONDUCTOR DEVICE AND METHOD}

This application claims priority to U.S. Provisional Application No. 62/927,864, filed October 30, 2019, entitled "Higher Inner Initial Growth Height Epitaxial Source Drain," which is incorporated herein by reference in its entirety.

Semiconductor devices are used in various electronic applications such as, for example, personal computers, cellular phones, digital cameras, and other electronic equipment. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and layers of semiconductor material on a semiconductor substrate, and patterning various material layers using lithography to form circuit components and elements on the substrate. do.

The semiconductor industry has continued to increase the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) by continually decreasing the minimum feature size, which allows more components to be integrated within a given area. However, as the minimum feature sizes decrease, additional problems arise that must be addressed.

Aspects of the present disclosure are best understood from the detailed description below when read in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, various features are not drawn to scale. Indeed, the dimensions of the various features can be arbitrarily increased or decreased for clarity of discussion.
1 illustrates an example of FinFETs in a three-dimensional diagram according to some embodiments.
2, 3, 4, 5, 6, 7, 8a, 8b, 8c, 9a, 9b, 9c, 10a, 10b, 10c, 11a, 11b , FIGS. 11C, 12, 13A, 13B, 14A, 14B, 15A, 15B, 16A, 16B, 16C, 17A, 17B, 18A and 18B show some embodiments. Are cross-sectional views of intermediate steps in the fabrication of FinFETs according to.

The disclosure below provides many different embodiments or examples for implementing different features of the invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following detailed description, the formation of the first feature on or on the second feature may include an embodiment in which the first feature and the second feature are formed by direct contact, and also the first An embodiment may be included in which additional features may be formed between the first feature and the second feature so that the feature and the second feature may not be in direct contact. Further, the present disclosure may repeat reference numbers and/or letters in different examples. This repetition is for the purpose of brevity and clarity, and such repetition itself does not describe the relationship between the various embodiments and/or configurations disclosed.

In addition, spatially relative terms such as "below", "below", "lower", "above", "top", etc. may be used as one for the other element(s) or feature(s) illustrated in the figures. It may be used herein for ease of description to describe the relationship of elements or features. Spatially relative terms are intended to encompass different orientations of the device in use or in operation in addition to the orientation shown in the figures. The device may be oriented in other ways (rotated to 90 degrees or other orientations), or the spatially relative descriptors used herein may be interpreted similarly accordingly.

Various embodiments provide processes for forming source/drain regions having a reduced volume and reduced cross-sectional area. The source/drain regions may be formed by depositing a spacer material over the fins and filling regions between adjacent fins with a spacer material. The etching process is performed to etch the spacer material such that the remaining portions of the spacer material between adjacent fins are higher than the remaining portions of the spacer material outside the adjacent fins. This may allow epitaxial source/drain regions to grow laterally between the fins from the lowest point higher than the lowest point of lateral growth on the outer sidewalls of the fins. Using the techniques described herein, adjacent source/drain regions that merge at higher distances above the substrate can be formed, which reduces the cross-sectional area of the merged source/drain regions. Semiconductor devices manufactured according to embodiments of the present application and including source/drain regions may experience reduced gate-drain capacitance (Cgd), reduced RC delay, faster on/off switching, and increased device speed. have.

1 illustrates an example of FinFETs in a three-dimensional diagram according to some embodiments. The FinFET includes fins 52 on a substrate 50 (eg, a semiconductor substrate). Isolation regions 56 are disposed on the substrate 50 and a fin 52 protrudes from between them over adjacent isolation regions 56. Although the isolation regions 56 have been described/exemplified as being separated from the substrate 50, the term “substrate” as used herein may be used to refer to a semiconductor substrate including isolation regions or only a semiconductor substrate. Additionally, while pin 52 is illustrated as single continuous materials, such as substrate 50, pin 52 and/or substrate 50 may comprise a single material or multiple materials. In this context, the fin 52 refers to a portion extending between neighboring isolation regions 56.

The gate dielectric layer 92 is along the sidewalls and over the top surface of the fin 52 and the gate electrode 94 is over the gate dielectric layer 92. Source/drain regions 82 are disposed on both sides of the fin 52 with respect to the gate dielectric layer 92 and the gate electrode 94. 1 further illustrates reference cross-sectional views used in later drawings. Sections A-A are along the longitudinal axis of the gate electrode 94, for example, in a direction perpendicular to the current flow direction between the source/drain regions 82 of the FinFET. Sections B-B are perpendicular to section A-A and are along the longitudinal axis of the fin 52, for example in the direction of current flow between the source/drain regions 82 of the FinFET. Sections C-C are parallel to sections A-A and extend through the source/drain regions 92 of the FinFET. Subsequent figures refer to these reference cross-sections for clarity.

Some embodiments discussed herein are discussed in the context of FinFETs formed using a gate-last process. In other embodiments, a gate-first process may be used. Further, some embodiments contemplate aspects used in planar devices such as planar FETs.

2-18B are cross-sectional views of intermediate steps in manufacturing FinFETs in accordance with some embodiments. 2 to 7 illustrate the reference cross-section A-A' illustrated in FIG. 1 excluding multiple fins/FinFETs. 8A, 9A, 10A, 11A, 13A, 14A, 15A, 16A, 17A, and 18A are illustrated along the reference cross-section A-A illustrated in FIG. 1. 8B, 9B, 10B, 11B, 13B, 14B, 15B, 16B, 16C, 17B, and 18B are illustrated along the similar cross section B-B illustrated in FIG. 1. 8C, 9C, 10C, 11C, and 12 are illustrated along the reference cross-section C-C illustrated in FIG. 1.

In Fig. 2, a substrate 50 is provided. The substrate 50 may be a bulk semiconductor, semiconductor-on-insulator (SOI) substrate, which may or may not be doped (eg, with a p-type or n-type dopant). The substrate 50 may be a wafer such as a silicon wafer. Generally, the SOI substrate is a layer of semiconductor material formed on an insulator layer. The insulator layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulator layer is provided on a substrate, which is generally a silicon or glass substrate. Other substrates such as multilayer or gradient substrates may also be used. In some embodiments, the semiconductor material of substrate 50 is silicon; germanium; Compound semiconductors including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; Alloy semiconductors including silicon-germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide and/or gallium indium arsenide phosphide; Or combinations thereof.

The substrate 50 has a region 50N and a region 50P. Region 50N may be for forming NMOS transistors, for example n-type devices such as n-type FinFETs. Region 50P may be for forming PMOS transistors, for example p-type devices such as p-type FinFETs. Region 50N can be physically separated from region 50P (as illustrated by divider 51), and any number of device features (e.g., between region 50N and region 50P) For example, other active devices, doped regions, isolation structures, etc.) may be disposed.

In FIG. 3, fins 52 are formed on the substrate 50. The pins 52 are semiconductor strips. In some embodiments, fins 52 may be formed in substrate 50 by etching trenches in substrate 50. Etching may be any acceptable etching process such as reactive ion etch (RIE), neutral beam etch (NBE), or the like, or a combination thereof. Etching can be anisotropic. In some embodiments, the fins 52 may be formed such that adjacent fins 52 are separated by a distance W2 of about 10 nm to about 40 nm. In some embodiments, the fins 52 may be formed to have a width W2 of about 5 nm to about 30 nm. In some embodiments, the fins 52 may be formed to have a pitch W3 of about 15 nm to about 50 nm.

Pins 52 can be patterned by any suitable method. For example, the fins 52 may be patterned using one or more photolithographic processes including double patterning or multiple patterning processes. In general, a double patterning or multiple patterning process combines a photolithography and self-alignment process, allowing patterns with smaller pitches to be created than can be achieved using, for example, a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over the substrate and patterned using a photolithography process. The spacers are formed with the patterned sacrificial layer using a self-aligning process. The sacrificial layer is then removed and the remaining spacers can then be used to pattern the fins. In some embodiments, a mask (or other layer) may remain on the fins 52.

In FIG. 4, an insulating material 54 is formed over the substrate 50 and between neighboring fins 52. The insulating material 54 may be an oxide such as silicon oxide, nitride, or a combination thereof, and high density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) ( For example, it may be formed by CVD-based material deposition in a remote plasma system, and post curing to convert to other materials such as oxides), or a combination thereof. Other insulating materials formed by any acceptable process may be used. In the illustrated embodiment, the insulating material 54 is a silicon oxide formed by an FCVD process. Once the insulating material is formed, an annealing process can be performed. In some embodiments, insulating material 54 is formed such that excess insulating material 54 covers fins 52. The insulating material 54 is illustrated as a single layer, but some embodiments may use multiple layers. For example, in some embodiments, a liner (not shown) may first be formed along the surfaces of the substrate 50 and the fins 52. Thereafter, fill materials such as those discussed above can be formed over the liner.

In FIG. 5, a removal process is applied to the insulating material 54 to remove excess insulating material 54 on the fins 52. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch back process, combinations thereof, and the like may be used. The planarization process exposes the fins 52 so that the top surfaces of the fins 52 and the insulating material 54 are horizontal after the planarization process is completed. In embodiments in which the mask remains on the fins 52, the planarization process exposes or masks the mask or mask so that each of the top surfaces of the fins 52 and the insulating material 54 are horizontal after the planarization process is complete. Can be removed.

In FIG. 6, insulating material 54 is recessed to form shallow trench isolation (STI) regions 56. The insulating material 54 is recessed so that the upper portions of the fins 52 of the region 50N and the region 50P protrude from between the neighboring STI regions 56. Further, the top surfaces of the STI regions 56 may have a flat surface, a convex surface, a concave surface (such as dishing), or a combination thereof as illustrated. The top surfaces of the STI regions 56 may be formed flat, convex, and/or concave by suitable etching. The STI regions 56 are an acceptable etching process, such as selective to the material of the insulating material 54 (e.g., etch the material of the insulating material 54 at a faster rate than the material of the fins 52). It can be recessed using. For example, oxide removal using dilute hydrofluoric (dHF) acid can be used.

The process described in connection with FIGS. 2-6 is merely an example of how the fins 52 can be formed. In some embodiments, fins may be formed by an epitaxial growth process. For example, a dielectric layer can be formed over the top surface of the substrate 50, and trenches can be etched through the dielectric layer to expose the underlying substrate 50. Homoepitaxial structures can be grown epitaxially in trenches, and the dielectric layer can be recessed such that the homoepitaxial structure protrudes from the dielectric layer to form fins. Additionally, in some embodiments, heteroepitaxial structures may be used for fins 52. For example, the fins 52 of FIG. 5 may be recessed, and a material different from the fins 52 may be epitaxially grown over the recessed fins 52. In these embodiments, the fins 52 comprise a recessed material as well as an epitaxially grown material disposed over the recessed material. In still further embodiments, a dielectric layer may be formed over the top surface of the substrate 50 and trenches may be etched through the dielectric layer. Thereafter, the heteroepitaxial structures can be grown epitaxially in the trenches using a different material than the substrate 50, and the dielectric layer is such that the heteroepitaxial structures protrude from the dielectric layer to form fins 52. Can be recessed. In some embodiments in which homoepitaxial or heteroepitaxial structures are epitaxially grown, the epitaxially grown materials may be doped in situ during growth, which may preclude previous and subsequent implants, but Situ and implant doping can be used together.

Further, it may be advantageous to epitaxially grow a material of the region 50N (eg, an NMOS region) that is different from the material of the region 50P (eg, a PMOS region). In various embodiments, the upper portions of the fins 52 are silicon germanium (Si _x Ge _1-x , where x can be 0 to 1), silicon carbide, pure or substantially pure germanium, a group III-V compound. It may be formed of a semiconductor, a group II-VI compound semiconductor, or the like. For example, materials available to form III-V compound semiconductors include indium arsenide, aluminum arsenide, gallium arsenide, indium phosphide, gallium nitride, indium gallium arsenide, indium aluminum arsenide, gallium antimonide, Aluminum antimonide, aluminum phosphide, gallium phosphide, and the like, but are not limited thereto.

Additionally in FIG. 6, suitable wells (not shown) may be formed in the fins 52 and/or the substrate 50. In some embodiments, a P well may be formed in the region 50N, and an N well may be formed in the region 50P. In some embodiments, a P well or an N well is formed in both the region 50N and the region 50P.

In embodiments with different well types, different implantation steps for region 50N and region 50P may be accomplished using photoresist or other masks (not shown). For example, a photoresist may be formed over the fins 52 and the STI region 56 in the region 50N. The photoresist is patterned to expose a region 50P of the substrate 50, such as a PMOS region. Photoresist can be formed by using a spin-on technique and patterned using acceptable photolithography techniques. When the photoresist is patterned, an n-type impurity is implanted into the region 50P, and the photoresist may serve as a mask that substantially prevents the n-type impurity from being implanted into the region 50N such as the NMOS region. The n-type impurities may be phosphorus, arsenic, antimony, etc. implanted into the region at a concentration of ^{10 18} cm ^-3 or less, such as ^{from about 10 16} cm ^-3 to about 10 ¹⁸ cm ^-3. After implantation the photoresist is removed, for example by an acceptable ashing process.

After implantation of the region 50P, a photoresist is formed over the fins 52 and the STI regions 56 of the region 50P. The photoresist is patterned to expose a region 50P of the substrate 50, such as an NMOS region. Photoresist can be formed by using a spin-on technique and patterned using acceptable photolithography techniques. When the photoresist is patterned, p-type impurities are implanted into the region 50N, and the photoresist may serve as a mask that substantially prevents P-type impurities from being implanted into the region 50P such as the PMOS region. The p-type impurities may be boron, boron fluoride, indium, etc. implanted into the region at a concentration of ^{10 18} cm ^-3 or less, such as ^{from about 10 16} cm ^-3 to about 10 ¹⁸ cm ^-3. After implantation, the photoresist can be removed, for example by an acceptable ashing process.

After implantation of the region 50N and region 50P, annealing may be performed to repair the implantation damage and activate the implanted p-type and/or n-type impurities. In some embodiments, the grown materials of the epitaxial fins may be doped in situ during growth, which may preclude implantation, but in situ and implant doping may be used together.

In FIG. 7, a dummy dielectric layer 60 is formed on the fins 52. The dummy dielectric layer 60 may be, for example, silicon oxide, silicon nitride, a combination thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. The dummy gate layer 62 is formed over the dummy dielectric layer 60, and the mask layer 64 is formed over the dummy gate layer 62. The dummy gate layer 62 is deposited over the dummy dielectric layer 60 and may then be planarized by, for example, CMP. The mask layer 64 may be formed on the dummy gate layer 62. The dummy gate layer 62 may be a conductive or non-conductive material, amorphous silicon, polycrystalline-silicon (polysilicon), polycrystalline silicon-germanium (poly-SiGe), metallic nitrides, metallic silicides, metallic oxides, and It can be selected from the group containing metals. The dummy gate layer 62 may be deposited by physical vapor deposition (PVD), CVD, sputter deposition, or other techniques known and used in the art to deposit a selected material. The dummy gate layer 62 may be made of other materials with high etch selectivity from etching of the isolation regions. The mask layer 64 may include, for example, silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 62 and a single mask layer 64 are formed over region 50N and region 50P. Note that the dummy dielectric layer 60 is shown covering only the fins 52 for purposes of illustration only. In some embodiments, dummy dielectric layer 60 may be deposited to cover STI region 56 such that dummy dielectric layer 60 extends between dummy gate layer 62 and STI regions 56.

8A-18B illustrate various additional steps in the manufacture of embodiment devices. 8A to 18B illustrate features of the region 50N or region 50P. For example, the structures illustrated in FIGS. 8A to 18B may be applicable to both the region 50N and the region 50P. The differences (if any) in the structures of region 50N and region 50P are described in the text appended to the respective figures. 8A, 9A, 10A, 11A, 13A, 14A, 15A, 16A, 17A, and 18A are illustrated along the reference cross-section A-A illustrated in FIG. 1. 8B, 9B, 10B, 11B, 13B, 14B, 15B, 16B, 17B, and 18B are illustrated along the reference cross-section B-B illustrated in FIG. 1. 8C, 9C, 10C, 11C, and 12 are illustrated along the reference cross-section C-C illustrated in FIG. 1. For clarity, some dimensions or ratios of the features shown in FIGS. 8C-12 may differ from those shown in other figures.

In FIGS. 8A, 8B and 8C, the mask layer 64 (see FIG. 7) may be patterned using acceptable photolithography and etching techniques to form the masks 74. The pattern of the masks 74 may then be transferred to the dummy gate layer 62. In some embodiments (not shown), the pattern of masks 74 may also be transferred to dummy dielectric layer 60 by an acceptable etching technique to form dummy gates 72. The dummy gates 72 cover respective channel regions 58 of the fins 52. The pattern of the masks 74 may be used to physically separate each of the dummy gates 72 from adjacent dummy gates. The dummy gates 72 may also have a length direction substantially perpendicular to the length direction of each of the epitaxial fins 52.

Also in FIGS. 8A-8C, a first spacer material 78 is formed on the exposed surfaces of dummy gates 72, masks 74 and/or fins 52. The first spacer material 78 is used to form the first spacers 80 (see FIGS. 10B-10C ). In some embodiments, the first spacer material 78 may be a material such as oxide, nitride, silicon oxynitride, silicon oxycarbide, silicon oxycarbide, or a combination thereof. In some embodiments, the first spacer material 78 may be formed using a process such as thermal oxidation, CVD, PE-CVD, ALD, PVD, sputtering, or the like. In FIG. 8B, the first spacer material 78 is shown extending vertically over dummy gate 72 and mask 74 and laterally over fins 52. In some embodiments, the first spacer material 78 may include multiple layers of one or more materials. In some embodiments, the first spacer layer 78 may be formed to have a thickness of about 2 nm to about 6 nm.

After the formation of the first spacer material 78, implantation of lightly doped source/drain (LDD) regions (not explicitly illustrated) may be performed. In embodiments with different device types, similar to the implants discussed above in FIG. 6, a mask, such as a photoresist, may be formed over region 50N, exposing region 50P, and in region 50P. Impurities of an appropriate type (eg, p-type) may be implanted into the exposed fins 52. The mask can then be removed. Subsequently, while exposing the region 50N, a mask such as a photoresist may be formed on the region 50P, and impurities of an appropriate type (eg, N. -Type) can be injected. The mask can then be removed. The n-type impurities may be any of the n-type impurities previously discussed, and the p-type impurities may be any of the previously discussed p-type impurities. The lightly doped source/drain regions may have a concentration of impurities of ^{about 1015 cm -3} to about 1019 cm ^-3. Annealing can be used to repair implant damage and activate implanted impurities.

9A, 9B, and 9C, a second spacer material 79 is formed on the first spacer material 78. The second spacer material 79 is used to form the second spacers 86 (see Figs. 10A-10C). In some embodiments, the second spacer material 79 may be a material such as oxide, nitride, silicon oxynitride, silicon oxycarbide, silicon oxycarbide, or a combination thereof. The second spacer material 79 may be conformally deposited using a process such as CVD, PE-CVD, ALD, PVD, sputtering, or the like. In some embodiments, the second spacer material 79 may include multiple layers of one or more materials.

In some embodiments, the second spacer material 79 includes fins (eg, the “inner” regions) between adjacent fins 52 at least partially filled with the second spacer material 79. 52. The inner regions can be completely filled with the second spacer material 79 as shown in Fig. 9C. As such, the second spacer material 79 is formed of the first spacer material on the adjacent fins 52. It may be deposited with a thickness T1 equal to about half of the separation distance W1' between 78 or greater than half of the separation distance W1'. In other embodiments, the second spacer material 79 ) May be deposited to a thickness T1 on the fins 52 that is less than half of the separation distance W1'. In some embodiments, the second spacer layer 79 has a deposition thickness of about 3 nm to about 20 nm. It may be formed to have (T1) In some cases, the second spacer material 79 filling the inner regions may have a seam.

The upper surface of the second spacer material 79 between the pins 52 may be flat, convex, or concave, which is the separation distance W1 ′ of the deposited second spacer material 79 and/or the film thickness You can rely on (T1). For example, a larger fin separation distance W1 or a smaller deposition thickness T1 may reduce the height H1 of the second spacer material 79 in the fins 52. The height H1 may be greater than the film formation thickness T1. The height H1 of the second spacer material 79 between the fins 52 may be greater, substantially the same, or less than the height H0 of the fins 52 protruding over the STI regions 56. The height H1 of the second spacer material 79 between the fins 52 may be about 3 nm to about 60 nm. By controlling the deposition thickness T1 and/or the height H1 of the second spacer material 79, the minimum inner height IO and the height difference DH of the epitaxial source/drain region 82 (see Fig. 11C) ) Can be controlled.

Returning to FIGS. 10A, 10B and 10C, recesses 84 are formed in fins 52, according to some embodiments. In FIG. 10C, the location of the channel regions 58 of the fins 52 under the dummy gate structure (e.g., the channel regions 58 that are not etched to form the recesses 84) are for reference. Is shown for. The recesses 84 may be formed using an etching process 85, which also etch the first spacer material 78 to form the first spacers 80 and the second spacer material 79. The second spacers 86 are formed by etching. The first spacers 80 and the second spacers 86 may be collectively referred to herein as “gate spacers”. The first spacers 80 and the second spacers 86, the dummy gates 72 and the masks 74 may be collectively referred to herein as “dummy gate structures”. In some embodiments, etching process 85 includes one or more etching steps, such as one or more anisotropic dry etching steps. In other embodiments, the etch process 85 includes a first etch process to etch the first spacer material 78 and the second spacer material 79 and a second etch process to form the recesses 84. do. The exemplary etching of the first spacer material 78, the second spacer material 79 and the recesses 84 shown in FIGS. 10B-10C is for illustration purposes, and the etching process 85 is in other embodiments. The first spacer material 78, the second spacer material 79, or the recesses 84 may be etched differently. For example, the surfaces of the gate spacers are shown as flat in FIG. 10C, but may be convex or concave in other embodiments.

In some embodiments, the etching process 85 may cause different regions of the gate spacers (e.g., first spacers 80 and/or second spacers 86) to be STI than other regions of the gate spacers. Different amounts of portions of the first spacer material 78 or the second spacer material 79 can be etched to extend higher over the regions 56. For example, after the etching process 85, regions of the gate spacers extending between adjacent fins 52 may have a greater height above the STI regions 56 than regions not between adjacent fins 52. have. This is shown in Figure 10c, where the "inner regions" of the gate spacers (e.g., regions between fins 52) have a height H2 adjacent to the fins 52, and the "outer regions" of the gate spacers. The region" (eg, regions that are not between the fins 52) has a height H3 adjacent to the fins 52, which is less than the height H2. In some cases, portions of the gate spacers further away from the fins 52 may have a height H3' that is smaller than the height H3. In this way, the gate spacers have a greater vertical thickness (eg, a vertical distance between the lower and upper surfaces of the gate spacers) within the inner regions than within the outer regions. In some embodiments, the height H2 above the STI regions 56 of the gate spacers in the inner regions may be from about 5 nm to about 40 nm, and above the STI regions 56 of the gate spacers in the outer regions. The height H3 (or H3') may be about 0 nm to about 30 nm. The height difference H4 between the heights H2 and H3 may be about 0 nm to about 40 nm. The height H3 may be greater than, less than, or substantially the same as the height H0' of the etched fins 52 protruding from the STI regions 56, and the height H2 is less than the height H0'. It can be large, or about the same.

The height H2 of the inner regions of the gate spacers is due to the second spacer material 79 that fills (or partially fills) the inner regions between adjacent fins 52, as shown in FIG. 9C. It may be greater than the height H3 of the outer regions of the gate spacers. The second spacer material 79 deposited in the inner regions has exposed top surfaces, and the outer sidewalls of the fins 52 have both exposed top surfaces and exposed sides. Accordingly, the etching process 85 etches the first spacer material 78 and the second spacer material 79 in the outer regions at a greater overall rate than the inner regions. This may cause the inner regions to leave more gate spacer material than the outer regions after the etching process. Additionally, confining the presence of adjacent fins 52 may reduce etchant mobility in the inner regions, further reducing the etch rate of the inner regions.

In this way, the height H2, height H3, and/or height difference H4 of the gate spacers can be controlled by controlling the geometry or topology of the structure, for example the separation distance W1' between adjacent fins 52 By controlling, it can be controlled by controlling the thickness of the first spacer material 78 or the second spacer material 79, the height H1 of the second spacer material 79 in the inner regions, and the like. Heights can also be controlled by controlling the process parameters of etching process 85. Process parameters may include, for example, process gas mixture, voltage bias, RF power, process temperature, process pressure, other parameters, or combinations thereof. In some embodiments, the shape, volume, area, size, merge height, or other features of the epitaxial source/drain regions 82 (see FIGS. 11B-11C) formed in the recesses 84 may be in this manner. By controlling the etching process 85 can be controlled.

11A, 11B, and 11C illustrate forming epitaxial source/drain regions 82 on fins 52 according to some embodiments. For clarity, some dimensions or ratios of the features shown in FIGS. 11A-11C may be different from those shown in other figures. The epitaxial source/drain regions 82 of the region 50N, e.g., the NMOS region, masks the region 50P, e.g., the PMOS region, and the source/drain regions of the pins 52 of the region 50N. Can be formed by etching them to form recesses in the fins 52. Thereafter, the epitaxial source/drain regions 82 of the region 50N are epitaxially grown in the recesses 84 from the exposed portions of the fins 52. The epitaxial source/drain regions 82 of the region 50P, e.g., the PMOS region, mask the region 50N, e.g., the NMOS region, and the source/drain regions of the pins 52 of the region 50P. Can be formed by etching them to form recesses in the fins 52. Thereafter, the epitaxial source/drain regions 82 of the region 50P are epitaxially grown in the recesses 84 from the exposed portions of the fins 52. The epitaxial source/drain regions 82 are CVD, metal-organic CVD (MOCVD), molecular beam epitaxy (MBE), liquid phase epitaxy (LPE), and vapor phase epitaxy. It can be grown epitaxially using a suitable process such as vapor phase epitaxy (VPE), selective epitaxial growth (SEG), or the like, or a combination thereof.

The epitaxial source/drain regions 82 may comprise any acceptable material such as suitable for n-type FinFETs or p-type FinFETs. For example, when the fin 52 is silicon, the epitaxial source/drain regions 82 in the region 50N are in the channel region 58 such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide, etc. Materials that apply tensile strain may be included. When the fin 52 is silicon, the epitaxial source/drain regions 82 in the region 50P are compressively deformed in the channel region 58 such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium tin, etc. It may include materials to apply.

The epitaxial source/drain regions 82 may have surfaces raised from respective surfaces of the fins 52 and may have facets. For example, the surfaces of the epitaxial source/drain regions 82 may have facets having a (111) crystal orientation, facets of different crystal orientations, or combinations of differently oriented facets. As illustrated in FIG. 11C, the epitaxial material formed on the adjacent fins 52 may extend outwardly in the lateral direction beyond the sidewalls of the fins 52 along the crystal planes, and merge in the inner regions to form a plurality of adjacent fins. A continuous epitaxial source/drain region 82 extending over the fins 52 may be formed. For example, epitaxial material grown from adjacent fins 52 may be incorporated into the inner region at a merge height MH above the STI region 56. In this way, the epitaxial source/drain regions 82 have a lower inner surface 83A extending between adjacent fins 52 in the inner regions and a lower outer surface extending from the fins 52 to the outer regions ( 83B). In some cases, surfaces 83A and 83B may be faceted to have {111} facets or other facets, for example.

In some embodiments, the lateral growth of the epitaxial material is blocked by the material of the gate spacers. For example, the lateral growth of the inner regions may be blocked below the height H2 of the gate spacers of the inner regions, and the lateral growth of the outer regions may be blocked below the height H3 of the gate spacers of the outer regions. have. In this way, the lower inner surface 83A of the epitaxial source/drain regions 82 extending to the inner regions is the minimum above the STI regions 56 that are approximately equal to the height H2 of the gate spacers of the inner regions. It may have an inner height (IH). In addition, the lower outer surface 83B of the epitaxial source/drain regions 82 extending to the outer regions is the minimum inner height above the STI regions 56 that are substantially equal to the height H3 of the gate spacers of the outer regions. It can have (OH). Due to the height difference H4 of the gate spacers described above, the height IH may be greater than the height OH. In some embodiments, the minimum inner height (IH) may be about 5 nm to about 40 nm, and the minimum outer height (OH) may be about 0 nm to about 30 nm. The height difference DH between the heights IH and OH may be about 5 nm to about 40 nm.

In some embodiments, the merge height MH of the epitaxial source/drain region 82 may be controlled by controlling the minimum inner height IH of the epitaxial source/drain region 82, which is It can be controlled by controlling the height H2 of the gate spacers. The height H2 of the gate spacers may be controlled as described above. In some embodiments, the merge height HM may be between about 5 nm and about 70 nm. The merge height MH may be controlled to be above, below, or approximately the same height than the lateral height LH of the epitaxial source/drain regions 82, which is the epitaxial that extends farthest laterally to the outer region. Specifies the height above the STI regions 56 of the portion of the source/drain regions 82. In some embodiments, the merge height LH may be between about 30 nm and about 50 nm. In some embodiments, the merge height MH may be controlled to be above, below, or approximately equal to the intermediate height of the epitaxial source/drain region 82 (e.g., the height at half the total vertical thickness). And, in some cases, it may be approximately equal to the lateral height LH.

By controlling the merge height MH, the cross-sectional area of the epitaxial source/drain regions 82 can be controlled. For example, a larger MH may correspond to a smaller cross-sectional area of the epitaxial source/drain regions 82. Additionally, the cross-sectional area of the epitaxial source/drain regions 82 can be controlled by controlling the height difference DH. For example, a larger DH may correspond to a smaller cross-sectional area of the epitaxial source/drain regions 82. By reducing the cross-sectional area of the epitaxial source/drain regions 82, the parasitic gate-drain capacitance (Cgd) of the FinFET device can be reduced, which can improve the performance of the FinFET device. For example, the RC delay of the FinFET device can be reduced, and the response speed of the FinFET device can be improved. In this way, increasing the height difference DH can reduce the parasitic capacitance Cgd. In some embodiments, the cross-sectional area of the epitaxial source/drain regions 82 having a non-zero DH may be reduced from about 0% to about 28% of the cross-sectional area of the reference epitaxial source/drain region with DH = 0. have.

In some embodiments, epitaxial source/drain region 82 may be formed of a merged epitaxial material grown on two or more fins 52. Although an exemplary multi-fin embodiment is shown in FIG. 12, epitaxial source/drain regions 82 may be formed over more or fewer fins 52 than shown. 12, the area between each pair of adjacent pins 52 is an “inner” area. The techniques described herein are the epitaxial source/drain in this and other multi-pin embodiments. It can be used to reduce the cross-sectional area of the regions 82.

The epitaxial source/drain regions 82 and/or fins 52 may be implanted with dopants to form a source/drain region, which is similar to the process discussed above to form lightly doped source/drain regions. Similarly, annealing follows. The source/drain regions may have an impurity concentration ^{of about 10 19} cm ^-3 to about 10 ²¹ cm ^-3. The n-type and/or p-type impurities for the source/drain regions may be any of the previously discussed impurities. In some embodiments, epitaxial source/drain regions 82 may be doped in situ during growth. In some embodiments, the profile of epitaxial source/drain regions 82 is an array of prisms facing the substrate 50, which may include shorter prisms sandwiched between higher prisms.

13A and 13B, a first interlayer dielectric (ILD) 88 is deposited over the structure. The first ILD 88 may be formed of a dielectric material and may be deposited by any suitable method such as CVD, plasma enhanced CVD (PECVD) or FCVD. Dielectric materials include phospho-silicate glass (PSG), boro-silicate glass (BSG), boron-doped phospho-silicate glass (BPSG), It may include undoped silicate glass (USG). Other insulating materials formed by any acceptable process may be used. In some embodiments, the contact etch stop layer (CESL) 87 includes the first ILD 88 and epitaxial source/drain regions 82, masks 74, and gate spacers. Are placed in between. The CESL 87 may include a dielectric material such as silicon nitride, silicon oxide, silicon oxynitride, or the like having an etching rate different from that of the overlying first ILD 88.

In FIGS. 14A and 14B, a planarization process such as CMP may be performed to level the top surface of the first ILD 88 with the top surfaces of the dummy gates 72 or masks 74. The planarization process may also remove portions of the first spacers 80 and the second spacers 86 along the sidewalls of the masks 74 and the masks 74 on the dummy gates 72. After the planarization process, the dummy gates 72, the first spacers 86, the second spacers 86, and the top surfaces of the first ILD 88 are of the same height. Accordingly, upper surfaces of the dummy gates 72 are exposed through the first ILD 88. In some embodiments, the masks 74 may remain, in which case the planarization process causes the top surfaces of the masks 74 and the top surface of the first ILD 88 to be flush.

In FIGS. 15A and 15B, dummy gates 72 and masks 74, if present, are removed in the etching step(s) to form recesses 90. Portions of dummy dielectric layer 60 in recesses 90 may also be removed. In some embodiments, only dummy gates 72 are removed, and dummy dielectric layer 60 remains and is exposed by recesses 90. In some embodiments, the dummy dielectric layer 60 is removed from the recesses 90 in the first region of the die (e.g., the core logic region), and the second region of the die (e.g., the input/ Output area) of the recesses 90. In some embodiments, dummy gates 72 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using reactive gas(s) that selectively etch dummy gates 72 without etching the first ILD 88 or the gate spacers. Each recess 90 exposes and/or overlies the channel region 58 of each fin 52. Each channel region 58 is disposed between adjacent pairs of epitaxial source/drain regions 82. During removal, the dummy dielectric layer 60 can be used as an etch stop layer when the dummy gates 72 are etched. Thereafter, the dummy dielectric layer 60 may be optionally removed after the dummy gates 72 are removed.

16A and 16B, gate dielectric layers 92 and gate electrodes 94 are formed for replacement gates. 16C illustrates a detailed view of the region 89 of FIG. 16B. A gate dielectric layer 92 is conformally deposited in the recesses 90, such as on the top surfaces and sidewalls of the fins 52 and on the sidewalls of the gate spacers. Gate dielectric layers 92 may also be formed on the top surface of the first ILD 88. According to some embodiments, the gate dielectric layers 92 include silicon oxide, silicon nitride, or multiple layers thereof. In some embodiments, the gate dielectric layers 92 comprise a high-k dielectric material, and in these embodiments, the gate dielectric layers 92 may have a k value greater than about 7.0, hafnium, aluminum, Metal oxides or silicates of zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. Methods of forming the gate dielectric layers 92 may include molecular beam deposition (MBD), ALD, PECVD, or the like. In embodiments where portions of the dummy dielectric layer 60 remain in the recesses 90, the gate dielectric layers 92 comprise the material of the dummy dielectric layer 60 (eg, silicon oxide).

Gate electrodes 94 are deposited on the gate dielectric layers 92, respectively, and fill the remaining portions of the recesses 90. The gate electrodes 94 may include a metal containing material such as titanium nitride, titanium oxide, tantalum nitride, tantalum carbide, cobalt, ruthenium, aluminum, tungsten, combinations thereof, or multiple layers thereof. For example, a single layer gate electrode 94 is illustrated in FIG. 16B, but the gate electrode 94 has any number of liner layers 94A, any number of work function tuning as illustrated by FIG. 16C. Layers 94B, and a fill material 102C. After filling the recesses 90, a planarization process such as CMP may be performed to remove excess portions of the gate dielectric layers 92 and material of the gate electrodes 94, the excess portions being ILD 88 ) On the top surface. Thus, the remaining portions of the material of the gate electrodes 94 and the gate dielectric layers 92 form the replacement gates of the resulting FinFETs. The gate electrodes 94 and the gate dielectric layers 92 may be collectively referred to as a “gate stack”. The gate and gate stacks may extend along sidewalls of the channel region 58 of the fins 52.

The formation of the gate dielectric layer 92 in the region 50N and the region 50P can occur simultaneously so that the gate dielectric layers 92 of each region are formed of the same materials, and the formation of the gate electrodes 94 It can occur simultaneously so that the gate electrodes 94 of each region are formed of the same materials. In some embodiments, the gate dielectric layers 92 in each region may be formed by separate processes such that the gate dielectric layers 92 may be of different materials, and/or the gate electrodes in each region. 94 may be formed by separate processes such that the gate electrodes 94 may be of different materials. Various masking steps can be used to mask and expose appropriate areas when using a separate process.

27A and 27B, the second ILD 108 is deposited over the first ILD 88. In some embodiments, the second ILD 108 is a flowable film formed by a dominant CVD method. In some embodiments, the second ILD 108 is formed of a dielectric material such as PSG, BSG, BPSG, USG, and the like, and may be deposited by any suitable method such as CVD and PECVD. In accordance with some embodiments, prior to formation of the second ILD 108, the gate stack (including the gate dielectric layer 92 and the corresponding overlying gate electrode 94) is recessed, such that FIGS. 17A and 17B. A recess is formed directly above the gate stack and between opposite portions of the second spacers 86 as illustrated in FIG. A gate mask 96 comprising one or more layers of dielectric material such as silicon nitride, silicon oxynitride, etc. is filled in the recess, and then a planarization process is performed to remove excess portions of the dielectric material extending over the first ILD 88. Remove. Subsequently formed gate contacts (see FIGS. 18A and 18B) pass through the gate mask 96 and contact the recessed upper surface of the gate electrode 94.

18A to 18D, gate contacts 110 and source/drain contacts 112 are formed through the second ILD 108 and the first ILD 88, according to some embodiments. The openings for the source/drain contacts 112 are formed through the first and second ILDs 88 and 108, and the openings for the gate contact 110 are formed through the second ILD 108 and the gate mask 96. Is formed. The openings can be formed using acceptable photolithography and etching techniques. A liner and conductive material such as a diffusion barrier layer, an adhesive layer, and the like are formed in the openings. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, and the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process such as CMP may be performed to remove excess material from the surface of the ILD 108. The remaining liner and conductive material form source/drain contacts 112 and gate contacts 110 in the openings. An annealing process may be performed to form silicide at the interface between the epitaxial source/drain regions 82 and the source/drain contacts 112. The source/drain contacts 112 are physically and electrically coupled to the epitaxial source/drain regions 82, and the gate contacts 110 are physically and electrically coupled to the gate electrodes 106. The source/drain contacts 112 and gate contacts 110 may be formed in different processes or may be formed in the same process. Although shown as being formed with the same cross-section, it should be understood that each of the source/drain contacts 112 and the gate contacts 110 may be formed with different cross-sections that can prevent shorting of the contacts.

The disclosed FinFET embodiments can also be applied to nanostructured devices such as nanostructures (eg, nanosheets, nanowires, gate-all-around, etc.) field effect transistors (NSFETs). In an NSFET embodiment, fins are formed by patterning a stack of alternating layers of channel layers and sacrificial layers. The dummy gate stacks and epitaxial source/drain regions are formed in a manner similar to that described above. After the dummy gate stacks are removed, the sacrificial layers may be partially or completely removed in the channel regions. The replacement gate structures are formed in a manner similar to that described above and will partially or completely surround the channel layers in the channel region of the NSFET devices. ILDs and contacts to the gate structures and sources/drains are formed in a similar manner to that described above. Nanostructured devices may be formed as disclosed in US Patent Application Publication No. 2016/0365414, which is incorporated herein by reference in its entirety.

The embodiments described herein can benefit. The techniques described herein describe the formation of epitaxial source/drain regions with reduced volume and reduced cross-sectional area. For example, using the techniques described herein, epitaxial material formed on adjacent fins can be merged at a higher point, which reduces the overall cross-sectional area of the merged epitaxial source/drain region. The merge height and cross-sectional area can be controlled depending on the desired application by controlling the amount of gate spacer material deposited between adjacent fins and by controlling the parameters of the etching process to form the gate spacers from the gate spacer material. By reducing the cross-sectional area of the epitaxial source/drain region, parasitic capacitances (e.g., gate-to-drain capacitance (Cgd)) can be reduced, which reduces RC delay and allows faster on/off switching and ring-oscillator. (RO, ring-oscillator) You can tolerate a boosted device speed, such as that of the device.

In accordance with some embodiments, the device includes: a first pin and a second pin extending from the substrate, the first pin including a first recess and the second pin including a second recess; An isolation region surrounding the first fin and surrounding the second fin; A gate stack over the first fin and the second fin; A spacer material over the isolation region and surrounding the first fin and the second fin, wherein the first portion of the spacer material extending from the first side of the first fin to the second fin has a first vertical thickness, The second portion of the spacer material adjacent the second side of the opposite first fin has a second vertical thickness less than the first vertical thickness; And source/drain regions in the first recess and in the second recess, the source/drain regions adjacent to the gate stack, and the source/drain regions of the spacer material and a first lower surface extending over the first portion of the spacer material. It includes a second lower surface extending over the second portion, and the lower end of the second lower surface is closer to the isolation area than the lower end of the first lower surface ―

Includes. In an embodiment, the first lower surface and the second lower surface are faceted. In an embodiment, the upper end of the first lower surface is further away from the isolation area than the upper end of the second lower surface. In an embodiment, the upper end of the first lower surface is in a range of 5 nm to 70 nm from the isolation region. In an embodiment, the difference between the first vertical thickness and the second vertical thickness is in the range of 5 nm to 40 nm. In an embodiment, the source/drain regions extend on the sidewalls of the first portion of the spacer material. In an embodiment, there are no source/drain regions in the sidewall of the second portion of the spacer material, adjacent the second side of the first fin. In an embodiment, the spacer material includes a first layer of a first dielectric material and a second layer of a second dielectric material. In an embodiment, the first portion of the spacer material protrudes over the lower surface of the first recess and the lower surface of the second recess.

In accordance with some embodiments, the structure includes: a first fin over a semiconductor substrate; A second fin on the semiconductor substrate, the second fin adjacent to the first fin; An isolation region surrounding the first fin and the second fin; Gate spacer material over the isolation region-the gate spacer material between the first side of the first fin and the first side of the second fin is the gate spacer on the second side of the first fin opposite the first side of the first fin. Extending farther above the isolation area than the material, and the first side of the first fin and the first side of the second fin face each other—; A gate structure on top surfaces of the first fin and the second fin along sidewalls of the first fin and the second fin; And source/drain regions on the first fin and the second fin adjacent to the gate structure-the source/drain regions include a downward first facet on the first surface of the first fin and a downward second facet on the second surface of the first fin. And, a first portion of the source/drain region on the first side of the first fin extends on the sidewall of the gate spacer material, and the second portion of the source/drain region on the second side of the first fin is an upper portion of the gate spacer material. Extending above the plane, and including the first portion and the second portion being the same height above the isolation area. In an embodiment, the lower end of the first facet is farther above the isolation area than the lower end of the second facet. In an embodiment, the upper end of the first facet is farther above the isolation area than the upper end of the second facet. In an embodiment, the second distance is zero. In an embodiment, the top surface of the source/drain region is flat. In an embodiment, the first and second facets have a (111) crystal orientation. In an embodiment, the structure further comprises a downward third facet on the first side of the second fin, and the third facet ends at the first facet.

In accordance with some embodiments, a method includes: forming a plurality of fins protruding from a semiconductor substrate; Forming a gate structure over the plurality of fins; Forming an isolation region surrounding the plurality of fins; Depositing a spacer layer over the gate structure and over the plurality of fins, the spacer layer filling regions extending between pairs of adjacent fins of the plurality of fins; Performing a first etch process on the spacer layer-After performing the first etch process, the first remaining portions of the spacer layer in the inner regions extending between pairs of adjacent fins of the plurality of fins have a first thickness. And the second remaining portions of the spacer layer not within the inner regions have a second thickness less than the first thickness -; And forming an epitaxial source/drain region adjacent to the gate structure and extending over the plurality of fins, wherein portions of the epitaxial source/drain regions within the inner regions are separated from the first remaining portions of the spacer layer. . In an embodiment, the method further includes performing a second etching process on the plurality of fins to form a recess in each individual fin of the plurality of fins. In an embodiment, the epitaxial source/drain region has a lower surface closer to the isolation region than the second remaining portions of the spacer layer. In an embodiment, depositing the spacer layer includes depositing a first dielectric layer, and then conformally depositing a second dielectric layer on the first dielectric layer.

The foregoing has outlined features of some embodiments to enable those skilled in the art to better understand aspects of the present disclosure. Those skilled in the art will readily use the present disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and/or achieve the same advantages of the embodiments introduced herein. Be aware that you can. Those skilled in the art may also make various changes, substitutions, and modifications in the present invention without departing from the spirit and scope of the present disclosure, and such equivalent configurations do not depart from the spirit and scope of the present disclosure. You should know.

Examples

Example 1. In the device,

A first pin and a second pin extending from the substrate, the first pin including a first recess, and the second pin including a second recess;

An isolation region surrounding the first fin and surrounding the second fin;

A gate stack over the first fin and the second fin;

A spacer material over the isolation region and surrounding the first fin and the second fin, the first portion of the spacer material extending from the first side of the first fin to the second fin having a first vertical thickness , A second portion of the spacer material adjacent a second surface of the first fin opposite the first surface has a second vertical thickness less than the first vertical thickness; And

A source/drain region in the first recess and in the second recess, wherein the source/drain region is adjacent to the gate stack, and the source/drain region is a first extending over the first portion of the spacer material. A lower surface and a second lower surface extending over the second portion of the spacer material, and a lower end of the second lower surface is closer to the isolation region than a lower end of the first lower surface ―

Including, a device.

Example 2. In Example 1,

The device, wherein the first lower surface and the second lower surface are faceted.

Example 3. In Example 1,

Wherein the upper end of the first lower surface is further away from the isolation region than the upper end of the second lower surface.

Example 4. In Example 1,

Wherein the upper end of the first lower surface is in a range of 5 nm to 70 nm from the isolation region.

Example 5. In Example 1,

Wherein the difference between the first vertical thickness and the second vertical thickness is in the range of 5 nm to 40 nm.

Example 6. In Example 1,

Wherein the source/drain regions extend on sidewalls of the first portion of the spacer material.

Example 7. In Example 6,

Wherein the source/drain regions are absent from a sidewall of the second portion of the spacer material adjacent the second side of the first fin.

Example 8. In Example 1,

Wherein the spacer material comprises a first layer of a first dielectric material and a second layer of a second dielectric material.

Example 9. In Example 1,

Wherein the first portion of the spacer material protrudes over a lower surface of the first recess and a lower surface of the second recess.

Example 10. In the structure,

A first fin on the semiconductor substrate;

A second fin on the semiconductor substrate, the second fin adjacent to the first fin;

An isolation region surrounding the first fin and the second fin;

A gate spacer material over the isolation region, wherein the gate spacer material between the first side of the first fin and the first side of the second fin is the first fin opposite the first side of the first fin Extending farther above the isolation region than the gate spacer material on a second side of the first fin and the first side of the second fin facing each other;

A gate structure on top surfaces of the first fin and the second fin along sidewalls of the first fin and the second fin; And

Source/drain regions on the first fin and the second fin adjacent to the gate structure-the source/drain regions are a downward first facet on the first surface of the first fin and the second surface of the first fin And a downward second facet of the first fin, wherein a first portion of the source/drain region on the first surface of the first fin extends on a sidewall of the gate spacer material, and the second surface of the first fin A second portion of the source/drain region extends above the top surface of the gate spacer material, and the first portion and the second portion are the same height above the isolation region-

Containing, structure.

Example 11. In Example 10,

Wherein the lower end of the first facet is farther above the isolation area than the lower end of the second facet.

Example 12. In Example 10,

Wherein the upper end of the first facet is farther above the isolation area than the upper end of the second facet.

Example 13. In Example 10,

The structure, wherein the second distance is zero.

Example 14. In Example 10,

Wherein the top surface of the source/drain region is flat.

Example 15. In Example 10,

Wherein the first facet and the second facet have a (111) crystal orientation.

Example 16. In Example 10,

And a third facet downward on the first surface of the second fin, wherein the third facet ends at the first facet.

Example 17. In the method,

Forming a plurality of fins protruding from the semiconductor substrate;

Forming a gate structure on the plurality of fins;

Forming an isolation region surrounding the plurality of fins;

Depositing a spacer layer over the gate structure and over the plurality of fins, the spacer layer filling regions extending between pairs of adjacent fins of the plurality of fins;

Performing a first etching process on the spacer layer- After performing the first etching process, the first remaining portions of the spacer layer in inner regions extending between pairs of adjacent fins of the plurality of fins are The second remaining portions of the spacer layer having a first thickness and not within the inner regions have a second thickness less than the first thickness -; And

Forming an epitaxial source/drain region adjacent to the gate structure and extending over the plurality of fins-portions of the epitaxial source/drain regions within the inner regions are from the first remaining portions of the spacer layer Separated ―

Including, the method.

Example 18. In Example 17,

And performing a second etching process on the plurality of fins to form a recess in each individual fin of the plurality of fins.

Example 19. In Example 17,

Wherein the epitaxial source/drain region has a lower surface closer to the isolation region than the second remaining portions of the spacer layer.

Example 20. In Example 17,

Wherein depositing the spacer layer comprises depositing a first dielectric layer, and then conformally depositing a second dielectric layer on the first dielectric layer.

Claims (10)

In the device,
A first pin and a second pin extending from the substrate, the first pin including a first recess, and the second pin including a second recess;
An isolation region surrounding the first fin and surrounding the second fin;
A gate stack over the first fin and the second fin;
A spacer material over the isolation region and surrounding the first fin and the second fin, the first portion of the spacer material extending from the first side of the first fin to the second fin having a first vertical thickness , A second portion of the spacer material adjacent a second surface of the first fin opposite the first surface has a second vertical thickness less than the first vertical thickness; And
A source/drain region in the first recess and in the second recess, wherein the source/drain region is adjacent to the gate stack, and the source/drain region is a first extending over the first portion of the spacer material. A lower surface and a second lower surface extending over the second portion of the spacer material, and a lower end of the second lower surface is closer to the isolation region than a lower end of the first lower surface ―
Including, a device. The method of claim 1,
The device, wherein the first lower surface and the second lower surface are faceted. The method of claim 1,
The device of claim 1, wherein an upper end of the first lower surface is further away from the isolation region than an upper end of the second lower surface. The method of claim 1,
Wherein the upper end of the first lower surface is in a range of 5 nm to 70 nm from the isolation region. The method of claim 1,
Wherein the difference between the first vertical thickness and the second vertical thickness is in the range of 5 nm to 40 nm. The method of claim 1,
Wherein the source/drain regions extend on sidewalls of the first portion of the spacer material. The method of claim 1,
Wherein the spacer material comprises a first layer of a first dielectric material and a second layer of a second dielectric material. The method of claim 1,
Wherein the first portion of the spacer material protrudes over a lower surface of the first recess and a lower surface of the second recess. In the structure,
A first fin on the semiconductor substrate;
A second fin on the semiconductor substrate, the second fin adjacent to the first fin;
An isolation region surrounding the first fin and the second fin;
A gate spacer material over the isolation region, wherein the gate spacer material between the first side of the first fin and the first side of the second fin is the first fin opposite the first side of the first fin Extending farther above the isolation region than the gate spacer material on a second side of the first fin and the first side of the second fin facing each other;
A gate structure on top surfaces of the first fin and the second fin along sidewalls of the first fin and the second fin; And
Source/drain regions on the first fin and the second fin adjacent to the gate structure-the source/drain regions are a downward first facet on the first surface of the first fin and the second surface of the first fin And a downward second facet of the first fin, wherein a first portion of the source/drain region on the first surface of the first fin extends on a sidewall of the gate spacer material, and the second surface of the first fin A second portion of the source/drain region extends above the top surface of the gate spacer material, and the first portion and the second portion are the same height above the isolation region-
Containing, structure. In the way,
Forming a plurality of fins protruding from the semiconductor substrate;
Forming a gate structure on the plurality of fins;
Forming an isolation region surrounding the plurality of fins;
Depositing a spacer layer over the gate structure and over the plurality of fins, the spacer layer filling regions extending between pairs of adjacent fins of the plurality of fins;
Performing a first etching process on the spacer layer- After performing the first etching process, the first remaining portions of the spacer layer in inner regions extending between pairs of adjacent fins of the plurality of fins are The second remaining portions of the spacer layer having a first thickness and not within the inner regions have a second thickness less than the first thickness -; And
Forming an epitaxial source/drain region adjacent to the gate structure and extending over the plurality of fins-portions of the epitaxial source/drain regions within the inner regions are from the first remaining portions of the spacer layer Separated ―
Including, the method.

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