KR20210036593A - Storage device - Google Patents

Abstract

A storage device is provided. The storage device comprises: a memory; and a memory controller that transmits a command to the memory. The memory includes: at least one memory cell array, a memory temperature sensor for measuring a temperature of the memory; and a control logic for outputting a busy signal in response to the command, receiving the temperature of the memory from the memory temperature sensor in response to the command, and determining whether to execute the command on the memory cell array according to the received temperature of the memory. Therefore, the storage device individually controls memories according to individual temperatures of the memories without intervention of the memory controller.

Description

Storage device}

The present invention relates to a storage device.

As a nonvolatile memory, the flash memory can retain the stored data even when the power is turned off. Recently, storage devices including flash memory such as eMMC (embedded multi-media card), UFS (Universal Flash Storage), SSD (Solid State Drive), and memory cards are widely used, and storage devices store large amounts of data. It is usefully used to move or move.

Meanwhile, when the temperature of the memory device of the storage device increases, the storage device operates while consuming a large amount of power, and thus the operating performance of the storage device may deteriorate. Alternatively, the memory device may be damaged, resulting in an error in data stored in the storage device, and the life of the storage device may be shortened.

Accordingly, a technology for controlling a storage device according to the temperature of the storage device is required, and various methods for this are proposed.

The technical problem to be solved by the present invention is to provide a storage device that controls each memory according to the temperature of each memory without intervention of a memory controller.

Another technical problem to be solved by the present invention is to provide a storage device control method that controls each memory according to the temperature of each memory without intervention of a memory controller.

The technical problems of the present invention are not limited to the technical problems mentioned above, and other technical problems that are not mentioned will be clearly understood by those skilled in the art from the following description.

A storage device according to some embodiments of the present invention for achieving the above technical problem includes a memory and a memory controller that transmits commands to the memory, and the memory includes at least one memory cell array and a temperature of the memory. Control that outputs a busy signal in response to a memory temperature sensor and a command, receives the temperature of the memory from the memory temperature sensor in response to the command, and determines whether to execute a command for the memory cell array according to the temperature of the received memory Includes logic.

A storage device according to some embodiments of the present invention for achieving the above technical problem is provided with a temperature of a storage device from a storage device temperature sensor and a storage device temperature sensor that measures the temperature of the storage device, and the temperature of the storage device is When the temperature is higher than the first set temperature, a memory controller generating an enable signal and first and second memories operating in a thermal throttling mode in response to an enable signal provided from the memory controller are included, and the first memory is thermal throttling. While operating in the mode, in response to a first command provided from the memory controller, a first memory temperature is provided from a first memory temperature sensor disposed therein, and whether the first command is executed according to the received first memory temperature. And, while the second memory is operating in the thermal throttling mode, in response to a second command provided from the memory controller, a second memory temperature is provided from a second memory temperature sensor disposed therein, and the received second memory is 2 It is determined whether or not to execute the second command according to the memory temperature, and when the first command is executed in the first memory and the second command is executed in the second memory are different from each other.

In a storage device including a memory including a memory temperature sensor and a storage device temperature sensor according to some embodiments of the present invention for achieving the above technical problem, the temperature of the storage device is measured from the storage device temperature sensor, If the measured temperature of the storage device is higher than or equal to the first set temperature, an enable signal is generated, while the enable signal is provided, the memory temperature sensor measures the temperature of the memory in response to a command, and the measured temperature of the memory It is determined whether to execute a command for the memory according to the result.

Details of other embodiments are included in the detailed description and drawings.

1 is a block diagram illustrating a system including a storage device according to some embodiments of the present invention.
FIG. 2 is an exemplary block diagram for describing the memory of FIG. 1
3 is a graph illustrating a thermal throttling mode of a storage device according to some embodiments of the present invention.
4 is a diagram for describing an operation of a storage device according to some embodiments of the present invention.
5 is a diagram for describing an operation of a storage device according to some embodiments of the present invention.
6 is a diagram for describing an operation of a storage device according to some embodiments of the present invention.
7 is a flowchart illustrating an operation of a storage device according to some embodiments of the present invention.
8 is a flowchart illustrating an operation of a storage device in a thermal throttling mode according to some embodiments of the present invention.
9 is a block diagram illustrating a storage device according to some other embodiments of the present invention.
10 is a diagram illustrating an operation of a storage device according to some other embodiments of the present invention.

1 is a block diagram illustrating a system including a storage device according to some embodiments of the present invention.

Referring to FIG. 1, a system including a storage device according to some embodiments of the present invention may include a host 10 and a storage device 20. The system may be a data storage medium based on a flash memory such as a memory card, a USB memory, or a solid state drive (SSD), but embodiments are not limited to these examples.

The host 10 may transmit a data operation request REQ and an address ADDR to the memory controller 200 and may exchange data DATA with the memory controller 200.

The storage device 20 may include a storage device temperature sensor 100, a memory controller 200, and a memory 300.

The storage device temperature sensor 100 may be disposed inside the storage device 20. The storage device temperature sensor 100 may measure _{the temperature T s of the storage device 20.}

The memory controller 200 may receive _{the temperature T s} of the storage device 20 from the storage device temperature sensor 100. The memory controller 200 may provide an enable signal EN to the memory 300 according to _{the temperature T s} of the storage device 20 provided from the storage device temperature sensor 100.

The memory controller 200 may control the memory 300 in response to a request from the host 10. The memory controller 200 may read the data DATA stored in the memory 300 in response to, for example, a data operation request REQ received from the host 10, and read the data DATA into the memory 300. The memory 300 may be controlled to write ). The memory controller 200 may provide an address ADDR, a command CMD, and a control signal CTRL to the memory 300 and may control program, read, and erase operations for the memory 300. In addition, data DATA for a program and read data DATA may be transmitted and received between the memory controller 200 and the memory 300.

The memory 300 may output ready and busy signals RNB. The ready and busy signals RNB may indicate the state of the memory 300. The memory controller 200 may provide a command CMD to the memory 300 when, for example, the memory 300 outputs a ready signal. The memory controller 200 may not provide the command CMD when, for example, the memory 300 outputs a busy signal.

The memory 300 may include a memory cell array 310, a memory temperature sensor 320, and a control logic 330. Hereinafter, it will be described with reference to FIG. 2.

FIG. 2 is an exemplary block diagram illustrating the memory of FIG. 1.

1 and 2, the memory 300 may include a memory cell array 310, a memory temperature sensor 320, and a control logic 330.

The memory 300 is, for example, a NAND flash memory, a vertical NAND flash memory (VNAND), a NOA flash memory, a resistive RAM (RRAM), a phase change memory ( PRAM), magnetoresistive memory (MRAM), ferroelectric memory (FRAM), spin injection magnetization inversion memory (Spin STT-RAM), and the like, but embodiments are not limited to these examples.

The memory cell array 310 may include the plurality of memory blocks, and each of the plurality of memory blocks is a plurality of memory cells connected to a plurality of word lines WL and a plurality of bit lines BL. Can include.

The memory cell array 310 may be connected to the row decoder 350 through a string selection line SSL, a plurality of word lines WL, and a ground selection line GSL. Also, the memory cell array 310 may be connected to the page buffer circuit 360 through a plurality of bit lines BL.

The memory temperature sensor 320 may be disposed inside the memory 300. The memory temperature sensor 320 may measure _{the temperature T m of the memory 300. The temperature T m} of the memory 300 measured by the memory temperature sensor 320 may be provided to the control logic 330.

The memory 300 may operate in a thermal throttling mode in response to the enable signal EN. In the thermal throttling mode, the control logic 330 may receive _{the temperature T m} of the memory 300 from the memory temperature sensor 320 in response to the command CMD. _{The control logic 330 provides the temperature T m} of the memory 300 from the memory temperature sensor 320 when the operation according to the command CMD for the memory cell array 310 is terminated in the thermal throttling mode. I can receive it. Hereinafter, it will be described with reference to FIGS. 3 to 8.

The control logic 330 may overall control the memory 300 based on a command CMD, an address ADDR, a control signal CTRL, and an enable signal EN received from the memory controller 200. . The control logic 330 may control, for example, a write operation, a read operation, and an erase operation of the memory 300. The control logic 330 may output a ready and busy signal RNB indicating a state of the memory 300.

The control logic 330 may provide a voltage control signal CTRL_vol to the voltage generator 340. The control logic 330 may generate a row address X-ADDR and a column address Y-ADDR based on the address signal ADDR. The control logic 330 may provide the row address X-ADDR to the row decoder 350 and may provide the column address Y-ADDR to the data input/output circuit 370.

The voltage generator 340 may generate an operating voltage required for the operation of the memory 300 in response to the voltage control signal CTRL_vol. The operating voltage may include, for example, a word line voltage VWL, a program voltage, a read voltage, a verification voltage, an erase voltage, and the like, but is not limited thereto.

The row decoder 350 may be connected to the memory cell array 310 through a string selection line SSL, a word line WL, and a ground selection line GSL. The row decoder 350 may select the string selection line SSL, the word line WL, and the ground selection line GSL in response to the row address X-ADDR. The row decoder 350 may apply an operating voltage provided from the voltage generator 340 to the selected and unselected string selection lines SSL, word lines WL, and ground selection lines GSL, respectively.

The page buffer circuit 360 may be connected to the memory cell array 310 through a plurality of bit lines BL. The page buffer circuit 360 may include a plurality of page buffers. The page buffer circuit 360 may temporarily store data to be written to a selected page during a write operation. The page buffer circuit 360 may temporarily store data read from a selected page during a read operation.

The data input/output circuit 370 may be connected to the page buffer circuit 360 through a data line DL. For example, during a write operation, the data input/output circuit 370 receives write data DATA from the memory controller 200 and writes write data based on a column address Y-ADDR provided from the control logic 330. DATA) may be provided to the page buffer circuit 360. The data input/output circuit 370 stores read data DATA stored in the page buffer circuit 360 based on a column address Y-ADDR provided from the control logic 330 during a read operation, for example, to the memory controller 200. ) Can be provided.

3 is a graph illustrating a thermal throttling mode of a storage device according to some embodiments of the present invention. The X-axis represents time and the Y-axis represents the temperature of the memory or storage device.

Referring to FIG. 3, a first set temperature T ₁ , a throttling temperature T _th , and a second set temperature T ₂ may be different from each other. The throttling temperature T _th may be higher than the first set temperature T ₁ and lower than the second set temperature T ₂ .

The storage device may operate in a thermal throttling mode when the temperature of the storage device _{is higher than or equal to the first set temperature T 1} (Thermal Throttling Mode ON). The storage device may perform a command operation by comparing the temperature of the memory T _m and the throttling temperature T _{th in the thermal throttling mode.} However, when the temperature of the storage device _{is higher than or equal to the second set temperature T 2} , in order to protect the storage device, the storage device may not generate a command.

Meanwhile, when the temperature of the _{storage device is lower than the first set temperature T 1} , the storage device may not operate in the thermal throttling mode (Thermal Throttling Mode OFF). This is because the storage device is low enough to perform a command operation. Therefore, while the storage device is not operating in the thermal throttling mode, the temperature of the memory may not be provided from the memory temperature sensor. Accordingly, it is possible to prevent the amount of heat generated and power consumption of the storage device. Hereinafter, it will be described with reference to FIGS. 4 to 8.

4 to 6 are diagrams for explaining the operation of the storage device according to some embodiments of the present invention. In FIGS. 4 to 6, the solid ready and busy signal (RNB) lines indicate the case where the temperature T _m of the memory 300 is lower than or equal to the throttling temperature T _th , and the dotted ready and busy signals ( The line RNB) represents a case where _{the temperature T m} of the memory 300 is higher than the throttling temperature T _th.

1 and 4, the memory 300 may receive a command CMD from the memory controller 200 through an input/output line IOx. The memory 300 may perform a command operation according to the command CMD in response to the command CMD. The memory 300 may output a low level busy signal while performing a command operation. In this drawing, it is illustrated that the memory 300 outputs the busy signal when the command CMD is provided to the memory, but the present invention is not limited thereto. For example, the memory 300 may output a busy signal when a predetermined time elapses after receiving the command CMD.

Subsequently, the memory 300 may output a high level ready signal after ending the command operation.

_{When the temperature T s} of the storage device 20 is higher than or equal to the first set temperature T ₁ and lower than the second set temperature T ₂ , the high-level enable signal EN ) Can be printed. The memory 300 may operate in a thermal throttling mode while the high-level enable signal EN is output.

In the thermal throttling mode, the memory 300 may determine whether the temperature T _m of the memory 300 is lower than or equal to the throttling temperature T _{th in response to the command CMD.} The memory 300 may perform a command operation when _{the temperature T m} of the memory 300 is lower than or equal to the throttling temperature T _th. The memory 300 may output a low level busy signal while performing a command operation. In this drawing, when the command CMD is provided to the memory 300, _{it is illustrated as determining whether the temperature T m} of the memory 300 is lower than or equal to the throttling temperature T _th , but is not limited thereto. For example, the memory 300 may determine whether the temperature T _m of the memory 300 is lower than or equal to the throttling temperature T _{th at the time when the command operation starts to be performed.}

When the command operation is finished, the memory 300 may determine whether the temperature T _m of the memory 300 is lower than or equal to the throttling temperature T _th. When it is determined that the temperature T _m of the memory 300 is lower than or equal to the throttling temperature T _{th, the memory 300 may output a ready signal. That is, the memory 300 determines whether the temperature (T m} ) of the memory 300 is lower than or equal to the throttling temperature (T _th ) at the time when the memory 300 starts the command operation and the time when the command operation ends. can do.

Next, referring to FIGS. 1 and 5, while the memory 300 performs a command operation (actual busy state), the temperature T _m of the memory 300 may increase. _{When the temperature T m} of the memory 300 is higher than the throttling temperature T _th after completing the command operation, the memory 300 may output a low level busy signal. That is, the memory 300 may be in a dummy busy state in which a busy signal is output but a command operation is not actually performed. Accordingly, the temperature of the memory 300 may decrease.

In a dummy busy state, the memory 300 may determine whether the temperature T _m of the memory 300 is lower than or equal to the throttling temperature T _{th at a predetermined period.} When it is determined that the temperature T _m of the memory 300 is lower than or equal to the throttling temperature T _th , the memory 300 may output a high level ready signal.

Meanwhile, referring to FIGS. 1 and 6, the temperature T _m of the memory 300 before receiving the command CMD may be higher than the throttling temperature T _th. In this case, the memory 300 outputs a busy signal in response to the command CMD, but may not perform an actual command operation. That is, it may be a dummy busy state.

In a dummy busy state, the memory 300 may determine whether the temperature T _m of the memory 300 is lower than or equal to the throttling temperature T _{th at a predetermined period.} When it is determined that the temperature T _m of the memory 300 is lower than or equal to the throttling temperature T _{th, the memory 300 may perform a command operation.} That is, the memory 300 may be in an actual busy state in which a busy signal is output and an actual command operation is performed.

After terminating the command operation, the memory 300 may output a low-level busy signal when _{the temperature T m} of the memory 300 is higher than the throttling temperature T _{th, as described above.}

7 is a flowchart illustrating an operation of a storage device according to some embodiments of the present invention.

Referring to FIGS. 1 and 7, the memory controller 200 according to some embodiments of the present invention may receive _{a temperature T s of the storage device 20 from the storage device temperature sensor 100 at a predetermined period.} (S210).

The memory controller 200 may determine whether the temperature T _s of the storage device 20 is higher than or equal to the first set temperature T ₁ and lower than the second set temperature T ₂ (S220 ).

Subsequently, when it is determined that the temperature T _s of the storage device 20 is higher than or equal to the first set temperature T ₁ and lower than the second set temperature T ₂ , the enable signal EN ) Can be generated (S230). The memory controller 200 may provide an enable signal EN to the memory 300.

The memory 300 may execute the thermal throttling mode in response to the enable signal EN (S240). That is, the memory 300 may execute the thermal throttling mode while the enable signal EN is provided. The thermal throttling mode may mean, for example, a mode in which the memory 300 determines whether to execute a command according to _{the temperature T m of the memory 300.}

Meanwhile, in step S220, when it is determined that the temperature T _s of the storage device 20 is higher than or equal to the first set temperature T _{1 and lower than the second set temperature T 2} , the memory controller 200 200 may determine whether the temperature T _s of the storage device 20 is higher than or equal to the second set temperature T _{2 (S250 ).}

Subsequently, when it is determined that the temperature T _s of the storage device 20 is higher than or equal to the second set temperature T ₂ , the memory controller 200 stops transmitting the command CMD to the memory 300. It can be done (S260). The second set temperature T ₂ may mean, for example, a temperature at which the storage device 20 can operate normally. The memory controller 200 transmits a command CMD when it is determined that _{the temperature T s} of the storage device 20 is higher than or equal to the second set temperature T ₂ in order to protect the storage device 20. You can stop it.

Meanwhile, in step S250, if the memory controller 200 determines that the temperature T _s of the storage device 20 is lower than the second set temperature T ₂ , the memory controller 200 returns to step S210 to determine the storage device temperature. _{The temperature T s} of the storage device 20 may be provided from the sensor 100. In this case, since the temperature T _s of the storage device 20 is lower than the first set temperature T ₁ , the storage device 20 is protected even if the thermal throttling mode is not executed. Accordingly, the memory controller 200 may perform a command operation in response to the command CMD without receiving _{the temperature T s} of the storage device 20 from the storage device temperature sensor 100. Hereinafter, the thermal throttling mode will be described with reference to FIG. 8.

8 is a flowchart illustrating an operation of a storage device in a thermal throttling mode according to some embodiments of the present invention.

1 and 8, in the thermal throttling mode, when the control logic 330 receives a command from the memory controller 200 (S310), the control logic 330 is transmitted from the memory temperature sensor 320 to the memory 300 A temperature (T _m ) of) may be provided (S320).

On the other hand, in the thermal throttling mode, if the control logic 330 does not receive the command CMD from the memory controller 200 (S320), the control logic 330 returns the temperature of the memory 300 from the memory temperature sensor 320 T _m ) may not be provided.

_{Accordingly, the storage device 20 according to some embodiments of the present invention receives the temperature T m} of the memory 300 from the memory temperature sensor 320 in response to the command CMD in the thermal throttling mode. Therefore, the power consumed by the _{memory controller 200 to receive the temperature T m} of the memory 300 from the memory temperature sensor 320 may be reduced.

The control logic 330 may determine whether the temperature T _m of the memory 300 is lower than or equal to the throttling temperature T _{th (S330 ).} The throttling temperature T _th may be set differently for each storage device, for example, and may be a preset temperature.

If the control logic 330 determines that the temperature T _m of the memory 300 is lower than or equal to the throttling temperature T _th , the control logic 330 may output a busy signal and perform a command operation according to the command CMD ( S340).

Subsequently, the control logic 330 may determine whether the command operation according to the command CMD has ended (S350).

When the control logic 330 determines that the command operation according to the command CMD has ended, the control logic 330 may receive _{the temperature T m of the memory 300 from the memory temperature sensor 320.} (S360).

Subsequently, the control logic 330 may determine whether the temperature T _m of the memory 300 is lower than or equal to the throttling temperature T _{th (S370 ).}

When it is determined that the temperature T _m of the memory 300 is lower than or equal to the throttling temperature T _th , the control logic 330 may output a ready signal (S380).

Meanwhile, in step S330, _{when it is determined that the temperature T m} of the memory 300 is higher than the throttling temperature T _th , the control logic 330 outputs a busy signal and does not perform a command operation according to the command CMD. It may not be (S332). Accordingly, the amount of heat generated or power consumption of the storage device 20 may be reduced.

Subsequently, the control logic 330 may receive _{the temperature T m} of the memory 300 from the memory temperature sensor 320 at a predetermined period. The predetermined period may be set differently for each storage device, for example, and may be a preset period.

Subsequently, the control logic 330 may determine whether the temperature T _m of the memory 300 is lower than or equal to the throttling temperature T _{th (S336).}

When it is determined that the temperature T _m of the memory 300 is lower than or equal to the throttling temperature T _th , the control logic 330 may output a busy signal and perform a command operation according to the command CMD ( S340).

On the other hand the temperature at the S336 step, the control logic 330 includes a memory 300, a temperature (T _m), the throttling temperature (T _th) when the high determination than, periodically memory 300 back to the S334 step of (T _m) Can be measured.

Meanwhile, in step S370, _{when it is determined that the temperature T m} of the memory 300 is higher than the throttling temperature T _th , the control logic 330 outputs a busy signal and does not perform a command operation according to the command CMD. It may not be (S372).

_{Subsequently, the control logic 330 may receive the temperature T m} of the memory 300 from the memory temperature sensor 320 at a predetermined period (S374).

Subsequently, the control logic 330 may determine whether the temperature T _m of the memory 300 is lower than or equal to the throttling temperature T _{th (S376 ).}

When it is determined that the temperature T _m of the memory 300 is lower than or equal to the throttling temperature T _th , the control logic 330 may output a busy signal and perform a command operation according to the command CMD ( S380).

On the other hand the temperature at the S376 step, the control logic 330 includes a memory 300, a temperature (T _m), the throttling temperature (T _th) when the high determination than, periodically memory 300 back to the S374 step of (T _m) Can be provided.

The storage device 20 according to some embodiments of the present invention may determine whether to perform a command operation according to _{the temperature T m} of the memory 300 by the control logic 330 without the intervention of the memory controller 200. have. Accordingly, since communication between the memory controller 200 and the control logic 330 is unnecessary, the amount of heat generated and power consumption of the storage device 20 may be prevented.

9 is a block diagram illustrating a storage device according to some other embodiments of the present invention. The description will focus on differences from the storage device of FIG. 1.

Referring to FIG. 9, a storage device according to some other embodiments of the present invention may include a first memory 300_1 to an nth memory 330_n and n are natural numbers. The memory controller 200 may receive the temperature Ts of the storage device 20 from the storage device temperature sensor 100. The memory controller 200 provides an enable signal EN to each of the first memory 300_1 to the nth memory 330_n according to the temperature Ts of the storage device 20 provided from the storage device temperature sensor 100 can do.

The memory controller 200 may transmit the first command CMD1 to the nth command CMDn to the first memory 300_1 to the nth memory 330_n, respectively, according to the request of the host 10.

Each of the first to nth memories 300_1 to 300_n may include a control logic 330 and a memory temperature sensor 320. The first memory 300_1 to the nth memory 300_n provide _{the temperature T m} of the memory 300 from the memory temperature sensor 320 in response to the first command CMD1 to the nth command CMDn, respectively. Can be received, and command actions can be performed.

The first to n-th memories 300_1 to 330_n may perform a command operation at different points in time, and may respectively output ready and busy signals RNB.

The storage device according to some other embodiments of the present invention does not collectively determine whether to perform a command operation on a memory according to the temperature of the storage device. Accordingly, the efficiency of the storage device may be improved or improved.

10 is a diagram for describing an operation of a storage device according to some other embodiments of the present invention at an arbitrary point in time. For convenience of description, the first memory 330_1, the second memory 330_2, and the third memory 330_n will be described below.

9 and 10, the first to third memories 330_1, 330_2, and 330_3 may operate in a thermal throttling mode by receiving an enable signal EN.

In the thermal throttling mode, the time when the first memory 330_1 executes the first command CMD1, the time when the second memory 330_2 executes the second command CMD2, and the third memory 330_3 are 3 The timing at which the command CMD3 is executed may be different from each other. The first memory 330_1 may execute the first command CMD1 at point A, the second memory 330_2 may execute the second command CMD2 at point D, and the third memory 330_3 May execute the third command CMD3 at time E.

At point B, the temperature T _m _1 of the first memory 330_1 may be lower than _{the temperature T m _2 of the second memory 330_2.} At point B, the first memory 330_1 and the second memory 330_2 output a busy signal, but the first memory 330_1 executes the first command CMD1, and the second memory 330_2 receives the second command ( CMD2) may not be performed.

In the section between B and C, the first memory 330_1 may execute the first command and may not receive _{the temperature (T m _1) of the first memory 330_1 from the first memory temperature sensor 320_1.} have. In the section between B and C, the second memory 330_2 may receive the temperature T _m _2 of the second memory 330_2 from the second memory temperature sensor 320_2 at a predetermined period, and the third memory 330_3 ) May not receive _{the temperature T m} _3 of the third memory 330_3 from the third memory temperature sensor 320_3. _{The temperature T m} _2 of the second memory 330_2 provided from the second memory temperature sensor 320_2 is higher than _{the temperature T m} _3 of the third memory 330_3 provided from the third memory temperature sensor 320_3 It can be high. That is, the first memory 330_1 may be in an actual busy state, the second memory 330_2 may be in a dummy busy state, and the third memory 330_3 may be in a ready state.

In this drawing, the first command CMD1, the second command CMD2, and the third command CMD3 are output at different times, but the present invention is not limited thereto, and some commands may be simultaneously output. have.

The embodiments of the present invention have been described above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, but may be manufactured in various different forms, and those having ordinary knowledge in the technical field to which the present invention pertains. It will be understood that the present invention can be implemented in other specific forms without changing the technical spirit or essential features of the present invention. Therefore, it should be understood that the embodiments described above are illustrative in all respects and are not limiting.

100: storage device temperature sensor 200: memory controller
300: memory 310: memory cell array
320: memory temperature sensor 330: control logic

Claims (10)

Memory; And
Including a memory controller for transmitting a command to the memory,
The memory,
At least one memory cell array,
A memory temperature sensor measuring the temperature of the memory,
Outputs a busy signal in response to the command, receives a temperature of the memory from the memory temperature sensor in response to the command, and determines whether to execute the command for the memory cell array according to the received temperature of the memory A storage device that includes control logic to perform. The method of claim 1,
The control logic,
When the temperature of the memory is lower than or equal to the throttling temperature, the command operation is performed on the memory cell array,
When the temperature of the memory is higher than the throttling temperature, the storage device does not perform the command operation on the memory cell array. The method of claim 1,
While the control logic is executing the command for the memory cell array, the memory temperature sensor does not measure the temperature of the memory,
While the control logic does not execute the command for the memory cell array, the memory temperature sensor measures the temperature of the memory. The method of claim 1,
The control logic,
When the operation according to the command for the memory cell array is terminated, the storage device receives the temperature of the memory from the memory temperature sensor. In the storage device,
A storage device temperature sensor measuring a temperature of the storage device;
A memory controller configured to receive a temperature of the storage device from the storage device temperature sensor and generate an enable signal when the temperature of the provided storage device is higher than or equal to a first set temperature; And
First and second memories operating in a thermal throttling mode in response to the enable signal provided from the memory controller,
While the first memory is operating in the thermal throttling mode, in response to a first command provided from the memory controller, the temperature of the first memory is provided from a first memory temperature sensor disposed therein, and the received Determine whether to execute the first command according to the temperature of the first memory,
While the second memory is operating in the thermal throttling mode, in response to a second command provided from the memory controller, the temperature of the second memory is provided from a second memory temperature sensor disposed therein, and the received Determine whether to execute the second command according to the temperature of the second memory,
A storage device in which a time when the first command is executed in the first memory and a time when the second command is executed in the second memory are different from each other. The method of claim 5,
When the first command is executed in the first memory, the first memory and the second memory output a busy signal,
A storage device in which the first memory executes the first command and the second memory does not execute the second command. The method of claim 6,
When the first command is executed in the first memory, the temperature of the second memory provided from the second memory temperature sensor is higher than the temperature of the first memory provided from the first memory temperature sensor . The method of claim 5,
Further comprising a third memory operating in a thermal throttling mode in response to the enable signal provided from the memory controller,
While operating in the thermal throttling mode, the third memory receives the temperature of the third memory from a third memory temperature sensor disposed therein in response to a third command provided from the memory controller. 3 Determine whether to execute the third command according to the temperature of the memory,
A storage device in which a time when the first command is executed in the first memory, a time when the second command is executed in the second memory, and a time when the third command is executed in the third memory are different from each other. The method of claim 8,
The first memory includes a first control logic,
The second memory includes a second control logic,
The third memory includes a third control logic,
While the first memory is executing the first command,
The first control logic does not receive the temperature of the first memory from the first memory temperature sensor,
The second control logic receives the temperature of the second memory from the second memory temperature sensor at a predetermined period,
The third control logic is not provided with the temperature of the third memory from the third memory temperature sensor. The method of claim 9,
A storage device in which the temperature of the second memory provided from the second memory temperature sensor is higher than the temperature of the third memory provided from the third memory temperature sensor.

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