KR20210022890A - Analog Neuron-Synapse Circuits - Google Patents

Abstract

The present invention relates to an analog neuron-synaptic circuit using a current signal to transmit information from a neuron circuit to a synapse circuit and increasing or creasing an output current according to a weighted sign bit, wherein the magnitude of a current to be added or subtracted is determined by a weight magnitude bit. By transmitting a signal from a neuron circuit to a synapse circuit as an electric current, the signal loss may be minimized and a circuit resistant to mismatch between elements can be composed.

Description

Analog Neuron-Synapse Circuits}

The present invention relates to an analog neuron-synaptic circuit, and more particularly, a current signal is used when information is transmitted from the neuron circuit to the synaptic circuit, and the output current is increased or decreased according to the weight code bit, but the magnitude of the current to be added or decreased is It relates to an analog neuron-synaptic circuit determined by weight size bits.

Recently, researches on artificial neural networks and neuromorphic computing to mimic human learning ability by imitating the computer's computational structure in the form of an artificial neural network by imitating the process of learning and computing are actively progressing. . Neuromorphic computing can be implemented using digital logic or analog circuit elements. Analog neuromorphic circuits are designed as circuits corresponding to neurons and synapses that exist in the human nervous system, respectively. Neurons are connected by synapses, and they process information by sending and receiving spike signals (action potentials) between neurons. Unlike digital systems, analog systems use current and voltage, can perform certain tasks with simpler circuits than digital systems, and offer advantages in terms of speed and power. At this time, the strength of each synapse is determined according to the importance of the information to be transmitted to the neuron. However, since the current and voltage are continuous, it is affected by the physical distribution of the device, and the inherent variability of the microchip manufacturing process can lead to significant functional differences between individual devices.

EP 3208750 (hereinafter referred to as'prior literature') relates to a multilayer neuron network composed of analog circuits. A current signal is input to the neuron circuit of the prior literature, but a voltage signal is used when information is transmitted from the neuron circuit to the synaptic circuit. Although the prior literature has the advantage of a simple circuit configuration, a problem occurs in that information transmitted from the output of one neuron to a plurality of synapses does not have the same distribution due to mismatch between devices as signals are transmitted by voltage. In addition, when the number of layers of the neural network and the number of input/output neurons are very large, voltage loss may occur due to load effects and signal routing when microprocessing large-scale synaptic circuits are integrated.

EP 3208750 (Name of invention: AN ANALOGUE ELECTRONIC DEEP NEURAL NETWORK, release date: 2017.08.22.)

An object of the present invention is to transmit a signal transmitted from a neuron circuit to a synaptic circuit as a current in order to solve the above problems.

In addition, an object of the present invention is to integrate a switch operated according to the weight code bit into a single unit and place it at the front end of the diode load of the synapse circuit.

In addition, an object of the present invention is to introduce a cascode technique in a current mirror region of a neuron circuit and a synaptic circuit.

The analog neuron-synapse circuit according to the present invention includes a neuron circuit receiving a current signal as an input current signal, and a weight code bit switch operated according to a weight code bit corresponding to an increase or decrease in the output current; A weight size bit switch including at least one switch operated according to the weight size bit; And an output transistor comprising at least one transistor connected to each of the weight size bit switches, the output transistor adding or subtracting the output current through a current mirror operation by the operation of the weight code bit switch and the weight size bit switch. Includes.

The neuron circuit according to the present invention includes a current signal generation circuit for rectifying by summing current signals received from a plurality of synaptic circuits provided at the front end into one input current signal, and transmitting to the synaptic circuit in a current mode. Includes.

The synaptic circuit according to the present invention further includes a diode load for receiving the input current signal transmitted from the neuron circuit.

The weight size bit switch according to the present invention is controlled by a weight size bit corresponding to the importance of information, and the amount of current flowing in or out of the weight size bit is determined according to the weight size bit.

The weight code bit switch according to the present invention is provided at the front end of the diode load.

A cascode circuit is provided in which transistors are stacked in a current mirror region of the neuron circuit and the synapse circuit according to the present invention.

The synaptic circuit of the present invention has an array structure, and is connected to the neuron circuit and a plurality of other neuron circuits provided at the rear end, wherein the neuron circuit transmits the input current signal to the synaptic circuit having an array structure, and , Each of the synaptic circuits transmits the output current to another neuron circuit provided at the rear end.

In the present invention, by transmitting a signal transmitted from a neuron circuit to a synaptic circuit as a current, signal loss is minimized, and a circuit that is robust against mismatch between devices can be configured.

In addition, the present invention can reduce the size of the circuit and reduce the cost by integrating a switch operated according to the weight code bit and placing it at the front end of the diode load of the synaptic circuit.

Further, according to the present invention, by introducing a cascode technique to the current mirror region of the neuron circuit and the synaptic circuit, it is possible to implement a precise and accurate weighting.

1 is a diagram for explaining a neuromorphic circuit to which a neuron-synaptic circuit proposed in the present invention is applied.
2 is an analog neuron-synaptic circuit diagram according to the present invention.
3 is another analog neuron-synaptic circuit diagram according to the present invention.
4 is an analog neuron-synaptic circuit diagram in which the cascode technique according to the present invention is introduced.
5 is another analog neuron-synaptic circuit diagram in which the cascode technique according to the present invention is introduced.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings. In describing an embodiment of the present invention, when it is determined that a detailed description of a related known technology may unnecessarily obscure the subject matter of the present invention, a detailed description thereof will be omitted.

1 is a diagram for explaining a neuromorphic circuit to which a neuron-synaptic circuit proposed in the present invention is applied. Referring to FIG. 1, the synaptic circuit has an array structure, and is connected to a neuron circuit at a front end (Layer k-1) and another neuron circuit at a rear end (Layer k). 1A is a conventional neuromorphic circuit, and a current (I) is input to the neuron circuit, but the signal transmitted from the neuron circuit to the synaptic circuit is a voltage (V). Conventional neuromorphic circuits have the advantage of simple circuit configuration, but voltage loss may occur due to load effects and signal routing as voltage signals are used. In addition, a problem occurs in that the weights in each synaptic circuit do not have the same distribution due to mismatch between devices.

1B is a neuromorphic circuit proposed in the present invention, in which a current (I) is input to a neuron circuit, and a signal transmitted from the neuron circuit to the synaptic circuit is also a current (I). Accordingly, the present invention can avoid a load effect and signal loss due to signal routing, and has an advantage of being very robust against mismatch between devices.

Hereinafter, the neuromorphic circuit proposed by the present invention will be described in detail with reference to FIGS. 2 to 3.

2 is an analog neuron-synaptic circuit diagram according to the present invention. 2, the analog neuron-synaptic circuit is composed of a neuron circuit 100 and a synapse circuit 200.

As described above with reference to FIG. 1, the neuron circuit 100 receives the current output from the synaptic circuit at the front end in a current-mode. The current-mode refers to a circuit through which a signal is transmitted as a current, and for low power operation, a transistor included in the neuron-synapse circuit of the present invention may be operated in a subthreshold region.

Referring to FIG. 2, the neuron circuit 100 includes transistors M ₀ to M ₅ . The neuron circuit 100 receives a plurality of current signals from synaptic circuits provided at the front end, and receives a plurality of input current signals (I _in1 ,I _in2 ,...,I _inN ) into one input current signal (I _in). ). The neuron circuit 100 includes a current signal generation circuit for transmitting an input current signal to the synapse circuit 200 in a current mode, and is composed of _{transistors M 0} to M _4. The NMOS transistor (M ₀ ) is converted to a voltage after rectifying by summing a plurality of input current signals (I _in1 ,I _in2 ,...,I _{inN ), and the NMOS transistor (M 1} ) is an NMOS transistor (M ₀ ) Generates a current for the voltage generated at The PMOS transistor M ₂ generates a voltage for the current generated by the NMOS transistor M ₁ , and a positive current I _p is generated by _{the PMOS transistor M 3 formed as a current mirror.} In addition, a negative current I _n is generated by the _{NMOS transistor M 0} and the NMOS transistor M _{4 forming a current mirror.} That is, the current signal generation circuit serves to induce an input current signal into a current and transfer it to the synapse circuit 200.

The synapse circuit 200 includes diode loads (M _p1 , M _n1 ), weight code bit switches (S _p , S _n , M _p0 , M _n0 ), weight size bit switches (S ₁ to S ₆ ), and output transistors (M _p2 to M _p4 , M _n2 to M _n4 ).

The diode loads M _p1 and M _n1 are devices that generate a voltage for weight implementation from _{the input current signal I in} transmitted from the neuron circuit 100.

The weight code bit switches S _p and S _n are devices for increasing or decreasing the output current output from the synapse circuit 200 according to the weight code bit w. According to the weight code bit w, either the weight code bit switch S _p or the weight code bit switch S _n is operated (turned on). Here, the weight code bit switch M _p0 is controlled at the same time as the weight code bit switch _{S p , and the weight code bit switch M n0} is controlled at the same time as the weight code bit switch S _n. A detailed description of the operation of the weight code bit switch will be described later.

Each weight size bit switch (S ₁ to S ₆ ) is assigned a weight value, and each weight size bit switch is turned on or off according to the weight size bit. The weight size bit means the importance of information, and is composed of a 3-bit signal to control _{each weight size bit switch (S 1} to S _{6 ).} Weight size bit switch (S ₁₎ is w _0, a weight magnitude bit switch (S _2), the size, the weight w ₂ of the bit ₁ is input w, weight size bit switch (S _3).

The output transistor can be composed of a PMOS output transistor group (M _p2 ~ M _p4 ) and an NMOS output transistor group (M _n2 ~ M _n4 ), and each output transistor group is connected to a respective weight size bit switch. 2, the NMOS output transistor (M _n2 ) is a weight size bit switch (S ₁ ), the NMOS output transistor (M _n3 ) is a weight size bit switch (S ₂ ), and the NMOS output transistor (M _n4 ) is It is connected to the weight size bit switch (S ₃ ), and the PMOS output transistor (M _p2 ) is the weight size bit switch (S ₄ ), the PMOS output transistor (M _p3 ) is the weight size bit switch (S ₅ ), and the PMOS output The transistor M _{p4 is} connected to the weight size bit switch S ₆ .

PMOS output transistors (M _p2 ~ M _p4 ) share the voltage generated by _{the diode load (M p1} ) to apply the weight value, and the channel width is 4:1 _{from the diode load (M p1} ) to M _p2 ~ M _p4 It has a binary weight ratio of :2:4. NMOS output transistors (M _n2 ~ M _n4 ) also share the voltage generated by _{the diode load (M n1} ) to apply the weight value, and the channel width is a binary number of 4:1:2:4 from the _{diode load (M n1 ).} Has a weight ratio.

Through this, the output transistor can generate a current signal multiplied by a binary weight of the input current signal through a current mirror operation. This can be expressed as (-1) ^w *1/4 (2 ² w ₀ +2 ¹ w ₁ +2 ⁰ w _{2 ).}

Hereinafter, a method of generating an output current signal by multiplying the input current signal by a binary weight will be described.

First, the increase or decrease of the output current signal is determined by the weight code bit of '0' or '1'. When the weight code bit (w) is '0', the weight size bit switches S _{4 to} S ₆ are operated so that the PMOS transistor adds a positive current to the output current, thereby increasing the size of the output current. On the other hand, when the weight code bit (w) is '1', the weight size bit switches S _{1 to} S ₃ are operated so that the NMOS transistor adds a negative current to the output current, thereby reducing the size of the output current. Here, the positive current and the negative current are currents flowing in or out of another neuron circuit provided at the rear end of the synaptic circuit 200. Therefore, if the output current I _out is a positive current, the output current is transmitted to another neuron circuit provided at the rear end, whereas if the output current I out is a negative current, current flows from another neuron circuit provided at the rear end.

The weight size bit for adding a positive current or a negative current to the output current I _{out is determined by the importance of the information.} Therefore, when all the weight size bit switches are turned on, the magnitude of adding or subtracting current is the largest, and when all the weight size bit switches are turned off, the magnitude of adding current or subtracting current is the smallest.

For example, when the importance of information is the highest, the weight code bit is '0' and the weight size bit is '111', and the most current is added. The importance of information gradually decreases in the order of weight bits '110', '101', '011', and '010'.. As the importance of information decreases, the amount of added current decreases.

3 is another analog neuron-synaptic circuit diagram according to the present invention. The neuron circuit of FIG. 3 is the same as the neuron circuit of FIG. 2. This is the case where the synaptic circuit is more simplified. The neuron circuit of FIG. 3 is the same as that of FIG. 2 and thus detailed description thereof will be omitted. In the case of the output transistor of the synaptic circuit of FIG. 2, a weight size bit switch is connected to each output transistor group, but FIG. 3 shows a case in which a weight size bit switch is provided as a single unit. 3 shows a weight size bit switch is integrated into a single unit in order to reduce the size of the circuit, and is disposed in front of the diode load of the synaptic circuit.

The weight coded bit switches S _p and S _n of FIG. 3 are provided at the front end of the diode loads M _p1 and M _n1 and receive current from the neuron circuit 100. A single weight size bit switch (S ₁ ~ S ₃ ) is connected to the PMOS output transistor group (M _p2 ~ M _p4 ) and the NMOS output transistor group (M _n2 ~ M _n4 ) at the same time. Therefore, the weight size bit switch (S ₁ ) is an NMOS output transistor (M _n2 ) and a PMOS output transistor (M _p2 ), and the weight size bit switch (S ₂ ) is an NMOS output transistor (M _n3 ) and a PMOS output transistor (M _p3 ). , The weight size bit switch S _{3 is} connected to the NMOS output transistor M _n4 and the PMOS output transistor M _p4 . The NMOS output transistor group and the PMOS output transistor group are connected to the same weight size bit switch, but only one transistor of the NMOS output transistor group or the PMOS output transistor group is operated due to the weight code bit switch provided at the front end of the diode load.

FIG. 4 is a circuit diagram of the analog neuron-synaptic circuit diagram shown in FIG. 2 and a cascode technique introduced, and FIG. 5 is a circuit diagram of the analog neuron-synaptic circuit diagram shown in FIG. 3.

Referring to FIGS. 4 and 5, it can be seen that the cascode circuit 300 is provided in all regions to which the current mirror is applied to the neuron circuit 100 and the synapse circuit 200. The cascode technique is a device for improving the difference between drain-source voltages and has the advantage that current is accurately copied from the current mirror.

100: neuron circuit 200: synaptic circuit
300: cascode circuit

Claims (7)

A neuron circuit receiving an input current signal in a current mode; And
A weight code bit switch operated according to a weight code bit corresponding to an increase or decrease in the output current; A weight size bit switch including at least one switch operated according to the weight size bit; And an output transistor comprising at least one transistor connected to each of the weight size bit switches, the output transistor adding or subtracting the output current through a current mirror operation by the operation of the weight code bit switch and the weight size bit switch. Analog neuron comprising a-synaptic circuit.
The method of claim 1, wherein the neuron circuit
A neuron comprising: a current signal generation circuit for rectifying and rectifying current signals received from a plurality of synaptic circuits provided in the front end into one of the input current signals, and transmitting them to the synaptic circuit in a current mode. -Synaptic circuit.
According to 1,
The synaptic circuit further comprises a diode load for receiving the input current signal transmitted from the neuron circuit, characterized in that the analog neuron-synaptic circuit.
The method of claim 1,
The weight size bit switch is controlled by a weight size bit corresponding to the importance of information, and an amount of an incoming or outgoing current is determined according to the weight size bit.
The method of claim 3,
The weight code bit switch is an analog neuron-synapse circuit, characterized in that provided at a front end of the diode load.
The method of claim 1,
An analog neuron-synaptic circuit, comprising a cascode circuit for stacking transistors in a current mirror region of the neuron circuit and the synaptic circuit.
The method of claim 2,
The synaptic circuit is composed of an array structure, which is connected to the neuron circuit and a plurality of other neuron circuits provided at the rear end, wherein the neuron circuit transmits the input current signal to the synaptic circuit consisting of an array structure, and each of the The synaptic circuit of the analog neuron-synaptic circuit, characterized in that transmitting the output current to another neuron circuit provided at the rear end.

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