KR20210016264A - Semiconductor device - Google Patents

Abstract

Provided is a semiconductor element which can improve reliability. The semiconductor element comprises: a first gate electrode crossing a substrate in a first direction; and a first gate contact and a dummy gate contact in contact with an upper surface of the gate electrode and spaced apart from each other, wherein a voltage is applied through the first gate contact and the voltage is not applied through the dummy gate contact.

Description

Semiconductor device {Semiconductor device}

The present invention relates to a semiconductor device, and more particularly, to a semiconductor device including a field effect transistor.

Due to characteristics such as miniaturization, multifunctionality, and/or low manufacturing cost, semiconductor devices are attracting attention as an important factor in the electronic industry. The semiconductor devices may be classified into a semiconductor memory device that stores logic data, a semiconductor logic device that operates and processes logic data, and a hybrid semiconductor device that includes a memory element and a logic element. As the electronics industry is highly developed, demands on the characteristics of semiconductor devices are increasingly increasing. For example, demand for high reliability, high speed and/or multifunctionality for semiconductor devices is increasing. In order to meet these required characteristics, structures in semiconductor devices are becoming more and more complex, and semiconductor devices are increasingly highly integrated.

The problem to be solved by the present invention is to provide a semiconductor device with improved performance or reliability.

According to the concept of the present invention, a semiconductor device includes: a first gate electrode crossing a substrate in a first direction; And a first gate contact and a dummy gate contact in contact with an upper surface of the gate electrode and spaced apart from each other, wherein a voltage is applied through the first gate contact and a voltage is not applied through the dummy gate contact.

A semiconductor device according to an aspect of the present invention includes a plurality of gate electrodes crossing a substrate and spaced apart from each other; At least one gate contact disposed on at least one of the gate electrodes and applied with a voltage; And at least one dummy gate contact disposed on the at least one gate electrode and spaced apart from the gate contact, wherein a voltage is not applied through the dummy gate contact.

A semiconductor device according to another aspect of the present invention includes: a substrate including a first active region and a second active region spaced apart in a first direction; Active fins protruding from the substrate and extending in a second direction crossing the first direction; First to third gate electrodes crossing the active fins in the first direction and having a line shape parallel to each other; A first gate contact disposed on the second gate electrode between the first active region and the second active region; And a first dummy gate contact overlapping or adjacent to one of the first active region or the second active region and disposed on the second gate, wherein the first and second active regions have the Two or three active fins are disposed, and a voltage is applied through the first gate contact, but the first dummy gate contact is electrically floating.

In the semiconductor device according to the present invention, the speed of the semiconductor device including the dummy gate contact is improved, so that the performance may be excellent. Alternatively, a leakage current may be reduced by the dummy gate contact, thereby improving reliability.

1 is a block diagram showing a computer system for performing semiconductor design according to embodiments of the present invention.
2 is a flowchart illustrating a method of designing and manufacturing a semiconductor device according to example embodiments.
3A, 3B, and 3C are layouts of semiconductor devices according to embodiments of the present invention, respectively.
4A, 4B and 4C are cross-sectional views of FIGS. 3A, 3B and 3C taken along lines I-I' and II-II', respectively.
5 is a layout of a semiconductor device according to example embodiments.
6 is a cross-sectional view of FIG. 5 taken along lines I-I' and III-III'.
7 is a layout of a semiconductor device according to example embodiments.
8 is a cross-sectional view of FIG. 7 taken along lines IV-IV' and V-V'.
9 is a layout of a semiconductor device according to example embodiments.
10 is a cross-sectional view of FIG. 9 taken along line VI-VI'.
11 is a layout of a semiconductor device according to example embodiments.
12A to 12C are layouts of semiconductor devices according to embodiments of the present invention.
12A to 12C may be layouts of standard cells according to embodiments of the present invention.
13A, 13B, and 13C are cross-sectional views taken along lines VII-VII', VIII-VIII', and IX-IX' of FIG. 12B according to embodiments of the present invention, respectively.
14A, 14B, and 14C are cross-sectional views taken along lines VII-VII', VIII-VIII', and IX-IX' of FIG. 12B according to embodiments of the present invention, respectively.
15A and 15B are layouts of semiconductor devices according to example embodiments.
16 is a layout of a semiconductor device according to example embodiments.
17 is a layout of a semiconductor device according to example embodiments.
18 is a layout of a semiconductor device according to example embodiments.
19 is a layout of a semiconductor device according to example embodiments.
20 is a layout of a semiconductor device according to example embodiments.

1 is a block diagram showing a computer system for performing semiconductor design according to embodiments of the present invention.

Referring to FIG. 1, the computer system may include a CPU 100, a working memory 30, an input/output device 50, and an auxiliary memory device 70. Here, the computer system may be provided as a dedicated device for layout design of the present invention. Furthermore, the computer system may be equipped with various design and verification simulation programs.

The CPU 100 may execute software (application programs, operating systems, device drivers) to be executed in the computer system. The CPU 100 may execute an operating system loaded into the working memory 30. The CPU 100 may execute various application programs to be driven based on the operating system. For example, the CPU 100 may execute the layout design tool 32, the layout, rearrangement and routing tool 34, and/or the OPC tool 36 loaded in the working memory 30.

The operating system or the application programs may be loaded in the working memory 30. When the computer system is booted, the operating system image (not shown) stored in the auxiliary memory device 70 may be loaded into the working memory 30 based on a booting sequence. Various input/output operations of the computer system may be supported by the operating system. Likewise, the application programs may be selected by a user or loaded into the working memory 30 to provide basic services.

The layout design tool 32 for layout design may be loaded from the auxiliary memory device 70 to the working memory 30. A placement and routing tool 34 for placing the designed standard cells and routing the placed standard cells may be loaded from the auxiliary storage device 70 to the working memory 30. The OPC tool 36 that performs Optical Proximity Correction (OPC) on the designed layout data may be loaded from the auxiliary memory device 70 to the working memory 30.

The layout design tool 32 may have a bias function capable of changing the shape and position of specific layout patterns differently from those defined by design rules. In addition, the layout design tool 32 may perform a design rule check (DRC) under the changed bias data condition. The working memory 30 may be a volatile memory such as a static random access memory (SRAM) or a dynamic random access memory (DRAM), or a nonvolatile memory such as PRAM, MRAM, ReRAM, FRAM, and NOR flash memory.

The input/output device 50 controls user input and output from the user interface devices. For example, the input/output device 50 may include a keyboard or a monitor to receive information from a designer. Using the input/output device 50, a designer may receive information on a semiconductor region or data paths requiring adjusted operating characteristics. Further, the processing process and processing result of the OPC tool 36 may be displayed through the input/output device 50.

The auxiliary storage device 70 is provided as a storage medium of a computer system. The auxiliary memory device 70 may store application programs, an operating system image, and various data. The auxiliary memory device 70 may be provided as a memory card (MMC, eMMC, SD, MicroSD, etc.) or a hard disk drive (HDD). The auxiliary memory device 70 may include a NAND-type flash memory having a large storage capacity. Alternatively, the auxiliary memory device 70 may include a next-generation nonvolatile memory such as PRAM, MRAM, ReRAM, FRAM, or NOR flash memory.

The system interconnector 90 may be a system bus for providing a network inside a computer system. Through the system interconnector 90, the CPU 100, the working memory 30, the input/output device 50, and the auxiliary memory device 70 may be electrically connected and exchange data with each other. However, the configuration of the system interconnector 90 is not limited to the above description, and may further include arbitration means for efficient management.

2 is a flowchart illustrating a method of designing and manufacturing a semiconductor device according to example embodiments.

Referring to FIG. 2, high level design of a semiconductor integrated circuit may be performed using the computer system described with reference to FIG. 1 (S10 ). High-level design may mean describing an integrated circuit to be designed in a language higher than a computer language. For example, you can use a higher level language such as C language. Circuits designed by high-level design can be expressed more specifically by register transfer level (RTL) coding or simulation. Furthermore, the code generated by the register transfer level coding can be converted into a netlist and synthesized into an entire semiconductor device. The synthesized schematic circuit is verified by a simulation tool, and an adjustment process may be accompanied according to the verification result.

Layout design for implementing a logically completed semiconductor junction circuit on a silicon substrate may be performed (S20). For example, layout design may be performed by referring to a schematic circuit synthesized in a high-level design or a netlist corresponding thereto.

The cell library for layout design may also include information on operation, speed, and power consumption of standard cells. Cell libraries for expressing a specific gate level circuit in a layout are defined in most layout design tools. The layout may actually be a procedure for defining the shape or size of a pattern for configuring transistors and wirings to be formed on a silicon substrate. For example, in order to actually form an inverter circuit on a silicon substrate, layout patterns such as PMOS, NMOS, N-WELL, gate electrodes, and wirings to be disposed on them can be appropriately arranged. To do this, first, it is possible to search and select a suitable one among inverters already defined in the cell library.

Various standard cells stored in a cell library may be placed (Place) and routing may be performed (S30). Specifically, standard cells may be two-dimensionally arranged. Upper wirings (routing patterns) may be arranged on the arranged standard cells. By performing routing, the deployed standard cells can be connected to each other according to the design. The placement and routing of standard cells can be performed automatically by the placement and routing tool 34.

After routing, the layout can be verified to see if there is a part that violates the design rule. The items to be verified include DRC (Design Rule Check) to verify that the layout is properly in accordance with the design rules, ERC (Electronical Rule Check) to verify that the layout is properly done without electrical disconnection, and whether the layout matches the gate level netlist. It can include LVS (Layout vs Schematic) to check.

An Optical Proximity Correction (OPC) procedure may be performed (S40). Layout patterns obtained through layout design may be implemented on a silicon substrate by using a photolithography process. In this case, the optical proximity correction may be a technique for correcting a distortion phenomenon that may occur in a photolithography process. That is, through the optical proximity correction, distortion such as refraction or process effect occurring due to the characteristics of light during exposure using the laid out pattern can be corrected. While performing optical proximity correction, the shape and position of the designed layout patterns may be slightly changed (biased).

A photomask may be manufactured based on the layout changed by optical proximity correction (S50). In general, the photomask may be manufactured in a manner depicting layout patterns using a chromium film applied on a glass substrate.

A semiconductor device may be manufactured using the generated photomask (S60). In the manufacturing process of a semiconductor device using a photomask, various types of exposure and etching processes may be repeated. Through these processes, patterns formed during layout design may be sequentially formed on a silicon substrate.

3A, 3B, and 3C are layouts of semiconductor devices according to embodiments of the present invention, respectively. 4A, 4B and 4C are cross-sectional views taken along lines I-I' and II-II' of FIGS. 3A, 3B and 3C, respectively.

3A and 4A, a semiconductor device 10a is provided on a substrate 1. The layout of FIG. 3 may correspond to a part of the standard cell layout. In this example, the semiconductor device 10a may be one transistor. The substrate 1 may be a semiconductor substrate including silicon, germanium, silicon-germanium, or a compound semiconductor substrate. For example, the substrate 1 may be a silicon substrate. The device isolation layer 3 may be disposed on the substrate 1 to define an active region AR. In the active region AR, the substrate 1 may be doped with an N-type impurity or a P-type impurity. The active region AR may be a PMOSFET region or an NMOSFET region.

The gate electrode GE may cross the active region AR. The gate electrode GE may have a line shape extending in the first direction D1. The gate electrode GE may include a conductive material. For example, the gate electrode GE may include at least one of a polysilicon doped with impurities, a metal nitride layer, a metal silicide, and a metal-containing layer. A gate insulating layer Gox may be interposed between the gate electrode GE and the substrate 1. The gate insulating layer Gox may include a silicon oxide layer and/or a high dielectric layer having a dielectric constant higher than that of the silicon oxide layer. The high dielectric film may include a metal oxide film such as an aluminum oxide film and a hafnium oxide film. The gate electrode GE may be covered with a gate capping pattern GP. The gate capping pattern GP may include at least one single layer or multiple layers of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer.

Source/drain regions 5 may be disposed in the substrate 1 at both sides of the gate electrode GE. The source/drain regions 5 may be doped with an impurity of a type opposite to that of the substrate 1. For example, when the active region AR is a PMOSFET region, the substrate 1 may be doped with an N-type impurity and the source/drain region 5 may be doped with a P-type impurity. When the active region AR is an NMOSFET region, the substrate 1 may be doped with a P-type impurity and the source/drain region 5 may be doped with an N-type impurity. Gate spacers GS may be disposed on both sidewalls of the gate electrode GE. The gate spacer GS may include at least one single layer or multiple layers of a silicon nitride layer, a silicon oxide layer, and a silicon oxynitride layer.

The gate electrode GE, the gate capping pattern GP, the gate spacer GS, the substrate 1 and the device isolation layer 3 may be covered with a first interlayer insulating layer IL1. The first interlayer insulating layer IL1 may include a single layer or multiple layers of at least one of a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, a low dielectric layer, and a porous layer.

A gate contact CB and a dummy gate contact DCB may contact the gate electrode GE by penetrating the first interlayer insulating layer IL1 and the gate capping pattern GP. The gate contact CB and the dummy gate contact DCB may be spaced apart from each other. The dummy gate contact DCB may overlap the active region AR. The gate contact CB may overlap the device isolation layer 3. The gate contact CB may be spaced apart from the active region AR. The dummy gate contact DCB may have the same size and height as the gate contact CB. The upper surface of the dummy gate contact DCB may be positioned at the same height as the upper surface of the gate contact CB. The lower surface of the dummy gate contact DCB may be positioned at the same height as the lower surface of the gate contact CB.

A second interlayer insulating layer IL2 may be disposed on the first interlayer insulating layer IL1. The second interlayer insulating layer IL2 may include at least one of a silicon nitride layer, a silicon oxide layer, a silicon oxynitride layer, a low dielectric layer, and a porous layer. A first wiring M1 and a gate via VB may be disposed in the second interlayer insulating layer IL2. The gate via VB may electrically connect the first wiring M1 and the gate contact CB. The gate via VB and the first wiring M1 are not positioned on the dummy gate contact DCB and are not electrically connected to them. A voltage may be applied to the gate electrode GE through the gate contact CB. A voltage may not be applied through the dummy gate contact DCB. The dummy gate contact DCB may be electrically floating.

Alternatively, referring to FIGS. 3B and 4B, the semiconductor device 10b according to the present example may further include a dummy gate via DVB disposed on the dummy gate contact DCB. A voltage may not be applied through the dummy gate via DVB. The dummy gate via DVB may be electrically floating.

Alternatively, referring to FIGS. 3C and 4C, the semiconductor device 10c according to the present example may further include a dummy gate via DVB and a dummy wiring DM1 disposed on the dummy gate contact DCB. A voltage may not be applied through the dummy wiring DM1. The dummy wiring DM1 may be electrically floating. Alternatively, the dummy wiring DM1 is connected to the first wiring M1 and the same voltage may be applied to each other.

The semiconductor device of FIG. 3a ~ 3c and Fig. 4a ~ 4c (10a, 10b, 10c) are planar (planar) (Fin Field Effect Transistor ) FinFET but showing the transistor is not limited to this type, MBCFET ^® (Multi-Bridge Channel Field Effect Transistor), Vertical Field Effect Transistor (VFET), or Negative Capacitance Field Effect Transistor (NCFET).

The semiconductor devices 10a, 10b, and 10c of the present invention include the dummy gate contact DCB. The characteristics of the semiconductor devices 10a, 10b, and 10c may be changed by the dummy gate contact DCB overlapping the active region AR. For example, a minute electrical/physical stress may be applied to the channel region by the dummy gate contact DCB. When the semiconductor devices 10a, 10b, and 10c are PMOSFETs, the speed of movement of holes in the channel region is improved due to such stress, and thus the speed of the device may be improved. Alternatively, when the semiconductor devices 10a, 10b, and 10c are NMOSFETs, the movement speed of electrons in the channel region may be slowed due to this stress, but instead, a threshold voltage may increase and a leakage current may decrease. As the semiconductor devices 10a, 10b, and 10c are highly integrated, the channel length under the gate electrode GE is also very narrow. Therefore, the presence of the dummy gate contact DCB may have a great influence on the characteristics of the semiconductor devices 10a, 10b, and 10c. In order to improve the performance of the device in the layout design step S20 of FIG. 2 or the step S30 of placing and routing various standard cells stored in a cell library, the dummy gate contact ( DCB) can be placed where necessary. In addition, a photomask may be manufactured with the layout thus manufactured, and semiconductor devices 10a, 10b, and 10c may be manufactured using the photomask.

5 is a layout of a semiconductor device according to example embodiments. 6 is a cross-sectional view of FIG. 5 taken along lines I-I' and III-III'.

5 and 6, the semiconductor device 10a according to the present example may include a first transistor TR1 and a second transistor TR2 disposed on a substrate 1 and spaced apart from each other. The first transistor TR1 may be the same as described with reference to FIGS. 3 and 4. The second transistor TR2 does not include a dummy gate contact DCB. Specifically, the first transistor TR1 includes a first gate electrode GE1 that crosses the first active region AR1. A first gate insulating layer Gox1 may be interposed between the first gate electrode GE1 and the substrate 1. A first gate capping pattern GP1 may be disposed on the first gate electrode GE1.

The second transistor TR2 includes a second gate electrode GE2 that crosses the second active region AR2. A second gate insulating layer Gox2 may be interposed between the second gate electrode GE2 and the substrate 1. A second gate capping pattern GP2 may be disposed on the second gate electrode GE2. The second gate electrode GE2 may include a conductive material different from that of the first gate electrode GE1. The second gate insulating layer Gox2 may include an insulating material or a high dielectric material different from the first gate insulating layer Gox1. The second gate capping pattern GP2 may include an insulating material identical to or different from the first gate capping pattern GP1.

Although not shown, a first source/drain region may be disposed in the substrate 1 on both sides of the first gate electrode GE1, and in the substrate 1 on both sides of the second gate electrode GE2. A second source/drain region may be disposed. The type or concentration of impurities doped in the first source/drain regions may be different from the type or concentration of impurities doped in the second source/drain regions.

The first transistor TR1 and the second transistor TR2 may be covered with a first interlayer insulating layer IL1. The first gate contact CB1 and the dummy gate contact DCB may respectively pass through the first interlayer insulating layer IL1 and the first gate capping pattern GP1 to contact the first gate electrode GE1. The dummy gate contact DCB may overlap the first active region AR1, and the first gate contact CB1 may be spaced apart from the first active region AR1. The second gate contact CB2 may pass through the first interlayer insulating layer IL1 and the second gate capping pattern GP2 to contact the second gate electrode GE2.

The first interlayer insulating layer IL1 is covered with a second interlayer insulating layer IL2. A first gate via VB1 and a first wiring M1 may be disposed in the second interlayer insulating layer IL2 to be electrically connected to the first gate contact CB1. A second gate via VB2 and a second wiring M2 may be disposed in the second interlayer insulating layer IL2 to be electrically connected to the second gate contact CB2. Other configurations may be the same/similar to those described with reference to FIGS. 3 and 4.

7 is a layout of a semiconductor device according to example embodiments. 8 is a cross-sectional view of FIG. 7 taken along lines IV-IV' and V-V'.

Referring to FIGS. 7 and 8, in the semiconductor device 10b according to the present example, a device isolation layer 3 is disposed on a substrate 1 to form second to fifth active regions AR2 to AR5 spaced apart from each other. It can be limited. An N-type or P-type impurity may be doped into the substrate 1 in each of the second to fifth active regions AR2 to AR5 independently. The second gate electrode GE2 may cross the second active area AR2. The second gate electrode GE2 may be included in the second transistor TR2 described with reference to FIGS. 5 and 6. Since the description of the second transistor TR2 is redundant, it will be omitted.

The third active area AR3 and the fourth active area AR4 may be spaced apart from each other in the first direction D1. The third gate electrode GE3 may cross the third active region AR3, and the fourth gate electrode GE4 may cross the fourth active region AR4. The third gate electrode GE3 and the fourth gate electrode GE4 may have an elongated line shape in the first direction D1. Both the third gate electrode GE3 and the fourth gate electrode GE4 may be positioned on one straight line. The third gate electrode GE3 and the fourth gate electrode GE4 may be spaced apart from each other by a gate separation pattern IP.

A third gate insulating layer Gox3 may be interposed between the third gate electrode GE3 and the substrate 1. A fourth gate insulating layer Gox4 may be interposed between the fourth gate electrode GE4 and the substrate 1. The third gate electrode GE3 and the fourth gate electrode GE4 may have the same material and the same structure. The third gate insulating layer Gox3 and the fourth gate insulating layer Gox4 may have the same material and structure. A third gate capping pattern GP3 may be disposed on the third gate electrode GE3 and a fourth gate capping pattern GP4 may be disposed on the fourth gate electrode GE4. The third gate capping pattern GP3 may have the same material and the same structure as the fourth gate capping pattern GP4.

The gate separation pattern IP may include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer. The gate separation pattern IP is formed between the third and fourth gate capping patterns GP3 and GP4, between the third and fourth gate electrodes GE3 and GE4, and the third and fourth gate insulating layers. It is interposed between (Gox3, Gox4) and can contact the device isolation layer 3.

The fifth active area AR5 and the sixth active area AR6 may be spaced apart from each other in the first direction D1. The impurities doped into the substrate 1 in the fifth active region AR5 may be of a different conductivity type than the impurities doped in the substrate 1 in the sixth active region AR6. The fifth gate electrode GE5 may cross the fifth active region AR5 and the sixth active region AR6. A fifth gate insulating layer Gox5 may be interposed between the fifth gate electrode GE5 and the substrate 1. A fifth gate capping pattern GP5 may be disposed on the fifth gate electrode GE5.

The second to fifth gate electrodes GE2 to GE5 and the substrate 1 may be sequentially covered with first and second interlayer insulating layers IL1 and IL2. The third interconnection M3 and the third gate via VB3 disposed in the second interlayer insulating layer IL2 are provided with a third gate contact penetrating through the first interlayer insulating layer IL1 and the third gate capping pattern GP3. CB3) may be electrically connected to the third gate electrode GE3. The fourth interconnection M4 and the fourth gate via VB4 disposed in the second interlayer insulating layer IL2 are provided with a fourth gate contact penetrating through the first interlayer insulating layer IL1 and the fifth gate capping pattern GP5. CB4) may be electrically connected to the fifth gate electrode GE5.

The first dummy gate contact DCB1 may pass through the first interlayer insulating layer IL1 and the fourth gate capping pattern GP4 to contact the fourth gate electrode GE4. The second dummy gate contact DCB2 may pass through the first interlayer insulating layer IL1 and the fifth gate capping pattern GP5 to contact the fifth gate electrode GE5. A voltage may not be applied through the first and second dummy contacts DCB1 and DCB2.

9 is a layout of a semiconductor device according to example embodiments. 10 is a cross-sectional view of FIG. 9 taken along line VI-VI'.

9 and 10, the semiconductor device 10c according to the present example includes a first standard cell ST1 and a second standard cell ST2 disposed adjacent to each other on the substrate 1 in the first direction D1. ) Can be included. The first standard cell ST1 may include a first NMOS region NR1 and a first PMOS region PR1 spaced apart from each other by the device isolation layer 3. The second standard cell ST2 may include a second NMOS region NR2 and a second PMOS region PR2 spaced apart from each other by the device isolation layer 3. The first NMOS region NR1 may be adjacent to the second NMOS region NR2. The first and second NMOS regions NR1 and NR2 may be disposed between the first PMOS region PR1 and the second PMOS region PR2. The first standard cell ST1 and the second standard cell ST2 may include a gate electrode GE crossing the regions NR1, PR1, NR2, and PR2 in common.

A first power line MP1 may be disposed adjacent to the first PMOS region PR1 of the first standard cell ST1. A second power line MP2 may be disposed between the first standard cell ST1 and the second standard cell ST2. A third power line MP3 may be disposed adjacent to the second PMOS region PR2 of the second standard cell ST2. A first voltage may be applied to the first power line MP1 and the third power line MP3. A second voltage different from the first voltage may be applied to the second power line MP2. One of the first voltage and the second voltage may be a power voltage Vdd and the other may be a ground voltage Vss.

The first wiring M1 may be disposed between the first PMOS region PR1 and the first NMOS region NR1. The first wiring M1 may be electrically connected to the gate electrode GE through a gate via VB and a gate contact CB. The dummy gate contact DCB may contact the gate electrode GE between the second PMOS region PR2 and the second NMOS region NR2. The dummy gate contact DCB may be closer to the second NMOS region NR2 than to the second PMOS region PR2. The dummy gate contact DCB may contact a boundary of the second NMOS region NR2. Alternatively, unlike FIG. 9, the dummy gate contact DCB may be closer to the second PMOS region PR2 than to the second NMOS region NR2.

11 is a layout of a semiconductor device according to example embodiments.

Referring to FIG. 11, the semiconductor device 10d according to the present example may include first to fourth standard cells ST1 to ST4 arranged in a row on a substrate 1 in a first direction D1. have. Each of the first to fourth standard cells ST1 to ST4 may include an NMOS region NR and a PMOS region PR. Arrangements of the NMOS regions NR and the PMOS regions PR of the first to fourth standard cells ST1 to ST4 may be symmetrical to each other. The first power line MP1 may be adjacent to the PMOS region PR of the first standard cell ST1. The second power wiring MP2 may be disposed between the first standard cell ST1 and the second standard cell ST2. The third power line MP3 may be disposed between the second standard cell ST2 and the third standard cell ST3. The fourth power wiring MP4 may be disposed between the third standard cell ST3 and the fourth standard cell ST4. The fifth power line MP5 may be adjacent to the PMOS region PR of the fourth standard cell ST4. A first voltage may be applied to the first, third, and fifth power lines MP1, MP3, and MP5. A second voltage may be applied to the second and fourth power lines MP2 and MP4.

The first wiring M1 may be disposed between the PMOS region PR and the NMOS region NR of the first standard cell ST1. The first wiring M1 may be electrically connected to the gate electrode GE through a gate via VB and a gate contact CB. The first dummy gate contact DCB1 may contact the gate electrode GE between the PMOS region PR and the NMOS region NR of the second standard cell ST2. The second dummy gate contact DCB2 may contact the gate electrode GE between the PMOS region PR and the NMOS region NR of the third standard cell ST3. The third dummy gate contact DCB3 may contact the gate electrode GE between the PMOS region PR and the NMOS region NR of the fourth standard cell ST4. Although three dummy gate contacts DCB1, DCB2, and DCB3 are shown in FIG. 11, only one or two of them may be disposed. In addition, at least one of the dummy gate contacts DCB1, DCB2, DCB3 is adjacent to or overlaps with at least one PMOS region PR or NMOS region NR of the first to fourth standard cells ST1 to ST4. Can be.

12A to 12C are layouts of semiconductor devices according to embodiments of the present invention. 12A to 12C may be layouts of standard cells according to embodiments of the present invention.

Referring to FIG. 12A, the semiconductor device 10h according to the present example may include first to fifth gate electrodes GE1 to GE5 disposed on a substrate 1 and spaced apart from each other. The first to fifth gate electrodes GE1 to GE5 may have a line shape extending in the first direction D1. First to third separation insulating patterns IS1 to IS3 spaced apart from each other may be disposed on the substrate 1. The first to third isolation insulating patterns IS1 to IS3 may also have a line shape extending in the first direction D1. The first isolation insulating pattern IS1 may be spaced apart from the second gate electrode GE2 with the first gate electrode GE1 interposed therebetween. The second isolation insulating pattern IS2 may be disposed between the fourth gate electrode GE4 and the fifth gate electrode GE5. The third isolation insulating pattern IS3 may be spaced apart from the second isolation insulating pattern IS2 with the fifth gate electrode GE5 interposed therebetween.

Intervals between the first to fourth gate electrodes GE1 to GE4, intervals between the first isolation insulating pattern IS1 and the first gate electrode GE1, and the second isolation insulating pattern IS2 The gap between the fourth gate electrode GE4, the gap between the second separation insulating pattern IS2 and the fifth gate electrode GE5, and the third separation insulating pattern IS3 and the fifth gate electrode GE5 ) Can all be the same.

Source/drain contacts CA may be disposed between the first to fifth gate electrodes GE1 to GE5. The source/drain contacts CA may have an elongated bar shape in the first direction D1. The first power line MP1 and the second power line MP2 may be spaced apart from each other and may be disposed to cross end portions of the first to fifth gate electrodes GE1 to GE5, respectively. First to sixth wires M1 to M6 may be disposed between the first and second power wires MP1 and MP2. Some of the source/drain contacts CA may be electrically connected to the wirings MP1, MP2, and M1 to M6 by source/drain vias VA.

The first to fifth gate electrodes GE1 to GE5 may be electrically connected to one of the first to sixth wires M1 to M6 through a gate contact CB and a gate via VB. For example, the first gate electrode GE1 and the third gate electrode GE3 may be electrically connected to the first wiring M1 through a gate contact CB and a gate via VB. The second gate electrode GE2 may be electrically connected to the third wiring M3 through a gate contact CB and a gate via VB. The fourth gate electrode GE4 may be electrically connected to the fourth wiring M4 through a gate contact CB and a gate via VB. The fifth gate electrode GE5 may be electrically connected to the second wiring M2 through a gate contact CB and a gate via VB.

In order to improve the performance/reliability of the semiconductor device 10h having the standard cell layout of FIG. 12A, the dummy gate contact DCB described with reference to FIGS. 3A to 11 may be disposed. The arrangement of the dummy gate contact DCB may be performed in the layout design step S20 of FIG. 2 or in the step S30 of placing and routing standard cells.

In order to improve the speed and performance of transistors disposed in the PMOS region PR in the semiconductor device 10h of FIG. 12A, a dummy gate contact DCB is formed in the first to fifth gate electrodes ( GE1~GE5) can be placed on top of one of them. That is, referring to FIG. 12B, for example, in the semiconductor device 10i according to the present example, dummy gate contacts are respectively formed on the second gate electrode GE2 and the fourth gate electrode GE4 in the PMOS region PR. DCB) can be deployed. The dummy gate contacts DCB may overlap the first wiring M1, but are not electrically connected to the first wiring M1.

Alternatively, the speed of the transistors disposed in the NMOS region NR in the semiconductor device 10h of FIG. 12A may be lowered, but in order to improve reliability by reducing or preventing leakage current, the dummy gate contact DCB is formed in the NMOS region NR. ) May be disposed on one of the first to fifth gate electrodes GE1 to GE5. That is, for example, referring to FIG. 12C, in the semiconductor device 10j according to the present example, the first, third, fourth, and fifth gate electrodes GE1 and 5 at the NMOS region NR or at the boundary of the NMOS region NR. Dummy gate contacts DCB may be disposed on GE3, GE4, and GE5, respectively. The dummy gate contacts DCB do not overlap the first to sixth wirings M1 to M6.

At least one of the first to sixth wires M1 to M6 may be a pin wire. The pin wiring may be a wiring that receives a signal from the outside of the standard cell. The pin wiring may be a wiring that outputs a signal to the outside of the standard cell.

A photomask may be fabricated using the standard cells of FIGS. 12A to 12C, and a semiconductor device may be formed using the photomask. Among them, a semiconductor device implemented on an actual substrate will be described in detail using the layout of the standard cell of FIG.

13A, 13B, and 13C are cross-sectional views taken along lines VII-VII', VIII-VIII', and IX-IX' of FIG. 12B according to embodiments of the present invention, respectively. The semiconductor device 10i of FIGS. 13A, 13B, and 13C may correspond to an example of a FinFET.

12B, 13A, 13B, and 13C, the substrate 1 may include a PMOS region PR and an NMOS region NR. The PMOS region PR and the NMOS region NR may be defined by the second trench TC2 formed on the substrate 1. A second trench TC2 may be positioned between the PMOS region PR and the NMOS region NR. The PMOS region PR and the NMOS region NR may be spaced apart from each other in the first direction D1 with the second trench TC2 interposed therebetween.

A plurality of active fins AF may be provided in the PMOS region PR and the NMOS region NR, respectively. The active fins AF may extend parallel to each other in the second direction D2. The active fins AF are part of the substrate 1 and may be vertically protruding portions. A first trench TC1 may be defined between the active fins AF adjacent to each other. The first trench TC1 may be shallower than the second trench TC2.

The device isolation layer 3 may fill the first and second trenches TR1 and TR2. The device isolation layer 3 may include a silicon oxide layer. Upper portions of the active fins AF may vertically protrude above the device isolation layer 3. The device isolation layer 3 may not cover the upper portions of the active fins AF. The device isolation layer 3 may cover lower sidewalls of the active fins AF. The first to fifth gate electrodes GE1 to GE5 may cross the active fins AF. A gate insulating layer Gox may be interposed between the first to fifth gate electrodes GE1 to GE5 and the active fins AF.

Each of the active fins AF positioned in the PMOS region PR may include a first upper surface TS1 and first side surfaces SW1. The first to fifth gate electrodes GE1 to GE5 cover the first upper surfaces TS1 and the first side surfaces SW1, respectively. First channel regions CH1 may be disposed above the active fins AF, respectively, overlapping with the first to fifth gate electrodes GE1 to GE5 in the PMOS region PR. First source/drain patterns SD1 may be disposed on the active fins AF at both sides of the first to fifth gate electrodes GE1 to GE5 in the PMOS region PR. The first source/drain patterns SD1 may include a semiconductor element (eg, SiGe) having a lattice constant greater than that of the semiconductor element of the substrate 1. Accordingly, the first source/drain patterns SD1 may provide a compressive stress to the first channel regions CH1. P-type impurities (for example, boron) may be doped into the first source/drain patterns SD1.

Each of the active fins AF positioned in the NMOS region NR may include a second upper surface TS2 and second side surfaces SW2. The first to fifth gate electrodes GE1 to GE5 may respectively cover the second upper surfaces TS2 and the second side surfaces SW2. Second channel regions CH2 may be disposed above the active fins AF, respectively, overlapping the first to fifth gate electrodes GE1 to GE5 in the NMOS region NR. Second source/drain patterns SD2 may be disposed on the active fins AF at both sides of the first to fifth gate electrodes GE1 to GE5 in the NMOS region NR. The second source/drain patterns SD2 may be semiconductor epitaxial patterns. For example, the second source/drain patterns SD2 may include the same semiconductor element (eg, Si) as the substrate 1. The second source/drain patterns SD2 may be doped with an N-type impurity (for example, phosphorus or arsenic).

In FIG. 13A, the first isolation insulating pattern IS1 and the second isolation insulating pattern IS2 may extend into the substrate 1 by passing through the first interlayer insulating layer IL1 and the active fin AF, respectively. . The first isolation insulating pattern IS1 and the second isolation insulating pattern IS2 may include at least one of a silicon oxide layer, a silicon nitride layer, and a silicon oxynitride layer.

In FIG. 13B, the gate contact CB may penetrate the first interlayer insulating layer IL1 and the gate capping pattern GP to contact the second gate electrode GE2. The gate contact CB may be disposed to overlap the device isolation layer 3 between the PMOS region PR and the NMOS region NR. The gate contact CB may be electrically connected to the third wiring M3 through a gate via VB. The dummy gate contact DCB may penetrate the first interlayer insulating layer IL1 and the gate capping pattern GP to make contact with the second gate electrode GE2. The dummy gate contact DCB may be positioned between the active fins AF in the PMOS region PR. Alternatively, the dummy gate contact DCB may overlap a part of the active fins AF in the PMOS region PR.

13C, the first source/drain patterns SD1 may contact each other. The second source/drain patterns SD2 may contact each other. The first source/drain patterns SD1 may be electrically connected to the second wiring M2 through a source/drain contact CA and a source/drain via VA. The second source/drain patterns SD2 may be electrically connected to the fifth wiring M5 through a source/drain contact CA and a source/drain via VA.

14A, 14B, and 14C are cross-sectional views taken along lines VII-VII', VIII-VIII', and IX-IX' of FIG. 12B according to embodiments of the present invention, respectively. The semiconductor device 10i of FIGS. 14A, 14B and 14C may correspond to an example of an MBCFET.

14A, 14B, and 14C, the semiconductor device 10i according to the present example may include one active fin AF in each of the PMOS region PR and the NMOS region NR. First channel patterns CP1 are stacked on the active fin AF in the PMOS region PR. The first channel patterns CP1 may be spaced apart from each other. In addition, second channel patterns CP2 may be stacked on the active fin AF in the NMOS region NR. The second channel patterns CP2 may be spaced apart from each other. The second gate electrode GE2 may extend between the first channel patterns CP1 and between the second channel patterns CP2. Other structures may be the same/similar to those described with reference to FIGS. 13A to 13C.

15A and 15B are layouts of semiconductor devices according to example embodiments.

15A, PMOS regions PR and NMOS regions NR may be disposed on a substrate 1 to be spaced apart from each other. A pair of adjacent PMOS regions PR and NMOS regions NR may be disposed to be symmetrical to each other. Gate electrodes GE may cross the PMOS regions PR and NMOS regions NR. Although not shown, the gate separation pattern IP described with reference to FIGS. 7 and 8 between the gate electrodes GE arranged in a line along the first direction D1 but spaced apart from each other, among the gate electrodes GE. ) May be intervened. A separation insulating pattern IS may be intermittently interposed between the gate electrodes GE. For convenience of description, wirings, source/drain contacts, and source/drain vias are omitted in FIG. 15A. Gate contacts CB may be disposed on the gate electrodes GE at required locations. A voltage may be applied to the gate electrodes GE through the gate contacts CB.

However, the gate contacts CB are disposed so as to be adjacent only to ends of the gate electrodes GE penetrating therethrough in the partial region P1, and the gate contacts CB are not disposed in the partial region P1. A dummy gate contact DCB may be disposed in the partial region P1 and to improve performance and reliability of transistors including the gate electrodes GE.

Referring to FIG. 15B, dummy gate contacts DCB may be disposed on the gate electrodes GE in the partial region P1. A voltage is not applied through the dummy gate contacts DCB. Each of the dummy gate contacts DCB may be independently disposed adjacent to the PMOS region PR or the NMOS region NR. Each of the dummy gate contacts DCB may independently contact a boundary of the PMOS region PR or the NMOS region NR. Each of the dummy gate contacts DCB may independently contact a boundary of the PMOS region PR or the NMOS region NR.

16 is a layout of a semiconductor device according to example embodiments.

Referring to FIG. 16, a semiconductor device 10m according to the present example includes a first standard cell ST1 and a second standard cell ST2 disposed adjacent to each other in the first direction D1 on the substrate 1. can do. Each of the first standard cell ST1 and the second standard cell ST2 may include a pair of PMOS regions PR and NMOS regions NR. The gate electrodes GE may cross the PMOS regions PR and the NMOS regions NR. A first power line MP1 may be disposed adjacent to the first standard cell ST1. A second power line MP2 may be disposed between the first standard cell ST1 and the second standard cell ST2. A third power line MP3 may be disposed adjacent to the second standard cell ST2. Descriptions of the first to third power wirings MP1 to MP3 may be the same as/similar to those described with reference to FIG. 9. Some of the source/drain contacts CA may be electrically connected to the first or third power wirings MP1 and MP3 through source/drain vias VA.

Gate contacts CB may be disposed on at least a portion of the gate electrodes GE, and may be electrically connected to the first wirings M1 through gate vias VB. Dummy gate contacts DCB may be disposed on at least some of the gate electrodes GE. In this example, the dummy gate contacts DCB may be located between the PMOS region PR and the NMOS region NR. The dummy gate contacts DCB may be connected to the dummy wiring DM1 through the dummy gate via DVB. The dummy wiring DM1 may be floating without being electrically connected to other wirings. Other structures may be the same/similar to those described above.

17 is a layout of a semiconductor device according to example embodiments. 17 may be a layout of one standard cell.

Referring to FIG. 17, the semiconductor device 10n according to the present example includes a substrate 1. A PMOS region PR and an NMOS region NR are disposed on the substrate 1. Separation insulating patterns IS spaced apart from each other are disposed on the substrate 1. The first to fifth gate electrodes GE1 to GE5 may be disposed between the separation insulating patterns IS to be spaced apart from each other. Source/drain contacts CA may be disposed between the first to fifth gate electrodes GE1 to GE5. A first power line MP1 may be disposed on one end of the first to fifth gate electrodes GE1 to GE5. A second power line MP2 may be disposed on other ends of the first to fifth gate electrodes GE1 to GE5. First to fourth wires M1 to M4 may be disposed between the first power wire MP1 and the second power wire MP2 to be spaced apart from each other. A dummy wiring DM1 may be disposed between the fourth wiring M4 and the second power wiring MP2.

Gate contacts CB are respectively disposed on the second to fifth gate electrodes GE2 to GE5 in the PMOS region PR. The gate contacts CB are electrically connected to the first wiring M1 through a gate via VB. The first wiring M1 may be electrically connected to a source/drain contact CA adjacent to one side of the first gate electrode GE1 by a source/drain via VA. Dummy gate contacts DCB are respectively disposed on the second to fifth gate electrodes GE2 to GE5 in the NMOS region NR. The dummy gate contacts DCB are electrically connected to the dummy wiring DM1 through the dummy gate via DVB. The dummy wiring DM1 is electrically connected to the first wiring M1 and the same electrical signal as the first wiring M1 may be applied.

18 is a layout of a semiconductor device according to example embodiments.

Referring to FIG. 18, in the semiconductor device 10o according to the present example, a PMOS region PR and an NMOS region NR may be disposed on a substrate 1. Two active fins AF may be disposed in the PMOS region PR and the NMOS region NR, respectively. Two active fins AF may also be disposed between the PMOS region PR and the NMOS region NR. Each of the active fins AF may be spaced apart from each other and may extend in a second direction D2. The first to fifth gate electrodes GE1 to GE5 cross the active fins AF and extend in the first direction D1. The intervals between the first to fifth gate electrodes GE1 to GE5 may be the same. Each of the first to fifth gate electrodes GE1 to GE5 may have a first width W1 parallel to the second direction D2.

Gate contacts CB1 to CB3 and dummy gate contacts DCB1 to DCB3 may be disposed on the second to fourth gate electrodes GE2 to GE4, respectively. Each of the gate contacts CB1 to CB3 may have a second width W2 parallel to the second direction D2. Each of the dummy gate contacts DCB1 to DCB3 may have a third width W3 parallel to the second direction D2. The second width W2 may be the same as the third width W3. The second width W2 may be larger than the first width W1. Preferably, the second width W2 may be about 3 to 5 times the first width W1. For example, the first width W1 may be about 4 nm, and the second width W2 may be about 16 nm.

Each of the active fins AF may have fourth widths W4 parallel to the first direction D1. Each of the gate contacts CB1 to CB3 may have a fifth width W5 parallel to the first direction D1. Each of the dummy gate contacts DCB1 to DCB3 may have a sixth width W6 parallel to the first direction D1. The fifth width W5 may be the same as the sixth width W6. The fifth width W5 may be larger than the fourth width W4. Preferably, the fifth width W5 may be about 1.5 to 2.5 times the fourth width W4. For example, the fourth width W4 may be about 8 nm, and the fifth width W5 may be about 16 nm.

The gate contacts CB1 to CB3 may overlap a portion of the active fins AF. The dummy gate contacts DCB1 to DCB3 may overlap a portion of the active fins AF. The first gate contact CB1 is disposed on the second gate electrode GE2 in the PMOS region PR. The second gate contact CB2 is disposed on the second gate electrode GE2 between the PMOS region PR and the NMOS region NR. The third gate contact CB3 is disposed on the fourth gate electrode GE4 adjacent to the boundary of the PMOS region PR. The second dummy gate contact DCB2 is disposed on the third gate electrode GE3 in the PMOS region PR.

When the centers of the first gate contact CB1, the second gate contact CB2, and the second dummy gate contact DCB2 are connected, a first triangle TG1 may be formed. The first triangle TG1 may be similar to a right triangle. The first triangle TG1 may have a first angle θ1 from the center of the first gate contact CB1. The first angle θ1 may be preferably 30 to 50°.

When the centers of the third gate contact CB3, the second gate contact CB2, and the second dummy gate contact DCB2 are connected to each other, a second triangle TG2 may be formed. The second triangle TG2 may be similar to an isosceles triangle or an equilateral triangle. The second triangle TG2 may have a second angle θ2 from the center of the third gate contact CB3. The second angle θ2 may be preferably 30 to 50°.

19 is a layout of a semiconductor device according to example embodiments.

Referring to FIG. 19, in the semiconductor device 10o according to the present example, a PMOS region PR and an NMOS region NR may be disposed on a substrate 1. Three active fins AF may be disposed in the PMOS region PR and the NMOS region NR, respectively. One active fin AF may also be disposed between the PMOS region PR and the NMOS region NR. The gate electrodes GE may cross the active fins AF. Gate contacts CB and dummy gate contacts DCB may be disposed on the gate electrodes GE, respectively. The dummy gate contacts DCB may be disposed between the active fins AF or may overlap at least a portion of the active fins AF. Other structures may be the same/similar to those described with reference to FIG. 18.

20 is a layout of a semiconductor device according to example embodiments.

Referring to FIG. 20, in the semiconductor device 10o according to the present example, PMOS regions PR and NMOS regions NR may be disposed on a substrate 1. Two active fins AF may be disposed in the PMOS regions PR and the NMOS regions NR, respectively. Two active fins AF may be disposed between the PMOS regions PR and the NMOS regions NR, respectively. The gate electrodes GE may cross the active fins AF. Gate contacts CB and dummy gate contacts DCB may be disposed on the gate electrodes GE, respectively. The dummy gate contacts DCB may be disposed between the active fins AF or may overlap at least a portion of the active fins AF. The width of the active fin AF parallel to the first direction D1 may be about 5 nm. Each of the dummy gate contacts DCB may be adjacent to a boundary of the NMOS region NR or the PMOS region PR. Other structures may be the same as/similar to those described with reference to FIG. 18.

As described above, the semiconductor devices of the present invention have been described. The semiconductor devices of FIGS. 3A to 20 may be combined with each other. The present invention may be implemented in other specific forms without changing the technical idea or essential features. Therefore, it is to be understood that the embodiments described above are illustrative in all respects and not limiting.

Claims (20)

A first gate electrode crossing the substrate in a first direction; And
A first gate contact and a dummy gate contact in contact with the upper surface of the gate electrode and spaced apart from each other,
A voltage is applied through the first gate contact,
A semiconductor device to which a voltage is not applied through the dummy gate contact.
The method of claim 1,
A gate via disposed on the first gate contact; And
A semiconductor device further comprising a first wiring disposed on the gate via.
The method of claim 1,
A semiconductor device further comprising a dummy gate via disposed on the dummy gate contact.
The method of claim 3,
Further comprising a dummy wiring disposed on the dummy gate via,
A semiconductor device to which a voltage is not applied through the dummy wiring.
The method of claim 1,
Further comprising a device isolation layer disposed on the substrate and defining an active region,
The dummy gate via overlaps the active region or is adjacent to the active region.
The method of claim 5,
Further comprising an active fin protruding from the substrate and having an upper surface higher than the upper surface of the device isolation layer,
The dummy gate via overlaps the active fin.
The method of claim 6,
Further comprising at least one channel pattern disposed on the active fin,
The gate electrode covers the channel pattern and is interposed between the active fin and the channel pattern.
The method of claim 1,
A second gate electrode that crosses the substrate in the first direction and is spaced apart from the first gate electrode in a second direction crossing the first direction; And
A semiconductor device further comprising a second gate contact disposed on the second gate electrode.
The method of claim 8,
A third gate electrode spaced apart from the second gate electrode in the first direction; And
A semiconductor device further comprising a gate separation pattern interposed between the second gate electrode and the third gate electrode.
The method of claim 1,
Further comprising a device isolation layer disposed on the substrate and defining a first active region and a second active region spaced apart from each other,
The first gate electrode simultaneously crosses the first active region and the second active region,
The first gate contact is disposed between the first active region and the second active region,
The dummy gate contact overlaps with or is adjacent to one of the first active region and the second active region.
A plurality of gate electrodes crossing the substrate and spaced apart from each other;
At least one gate contact disposed on at least one of the gate electrodes and applied with a voltage; And
Further comprising at least one dummy gate contact disposed on the at least one gate electrode and spaced apart from the gate contact,
A semiconductor device to which a voltage is not applied through the dummy gate contact.
The method of claim 11,
A gate via disposed on the gate contact; And
A semiconductor device further comprising a first wiring disposed on the gate via.
The method of claim 11,
A semiconductor device further comprising a dummy gate via disposed on the dummy gate contact.
The method of claim 13,
Further comprising a dummy wiring disposed on the dummy gate via,
A semiconductor device to which a voltage is not applied through the dummy wiring.
The method of claim 11,
Further comprising a device isolation layer disposed on the substrate and defining an active region,
The dummy gate contact overlaps the active region or is adjacent to the active region.
The method of claim 11,
Further comprising a device isolation layer disposed on the substrate and defining a first active region and a second active region spaced apart from each other,
The gate electrodes simultaneously cross the first active region and the second active region,
The gate contact is disposed between the first active region and the second active region,
The dummy gate contact overlaps with or is adjacent to one of the first active region and the second active region.
A substrate including a first active region and a second active region spaced apart in a first direction;
Active fins protruding from the substrate and extending in a second direction crossing the first direction;
First to third gate electrodes crossing the active fins in the first direction and having a line shape parallel to each other;
A first gate contact disposed on the second gate electrode between the first active region and the second active region; And
A first dummy gate contact overlapping or adjacent to one of the first active region or the second active region and disposed on the second gate,
Two or three active fins are disposed in the first active region and the second active region, respectively,
A semiconductor device in which a voltage is applied through the first gate contact, but the first dummy gate contact is electrically floating.
The method of claim 17,
The first dummy gate contact and the first gate contact are each independently overlapping the active fin or disposed between adjacent active fins.
The method of claim 17,
A second gate contact disposed on the first gate electrode in the first active region; And
Further comprising a second dummy gate contact disposed on the first gate electrode in the second active region,
A semiconductor device in which a voltage is applied through the second gate contact but the second dummy gate contact is electrically floating.
A first active region and a second active region disposed on the substrate;
A gate electrode crossing the first active region and the second active region;
A gate contact disposed on the gate electrode in the first active region;
A first wiring disposed on the gate contact and electrically connected to the gate contact;
A dummy gate contact disposed on the gate electrode in the second active region; And
A dummy wiring disposed on the dummy gate contact and electrically connected to the dummy gate contact,
A semiconductor device to which the dummy wiring is electrically applied with the same voltage as the first wiring.

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