KR20210009470A - printed circuit board including interlayer insulating layer different from another and method of fabricating the same - Google Patents

Abstract

According to one aspect of the present invention, a printed circuit board including interlayer insulating layers of different materials includes: an intermediate insulating layer containing a fiber reinforcement; an upper circuit pattern layer and a lower circuit pattern layer respectively disposed on the upper and lower surfaces of the intermediate insulating layer; an upper interlayer insulating layer disposed on the upper surface of the intermediate insulating layer to cover the upper circuit pattern layer and not including a fiber reinforcement; and a lower interlayer insulating layer which is disposed on the lower surface of the intermediate insulating layer to cover the lower circuit pattern layer and does not contain the fiber reinforcement agent.

Description

Printed circuit board including interlayer insulating layer different from another and method of fabricating the same

The present invention relates to a method of manufacturing a printed circuit board, and more particularly, to a printed circuit board including interlayer insulating layers of different materials and a method of manufacturing the same.

With the development of the electronics industry, high functionality and miniaturization of electronic components is accelerating. As part of this trend, there is an increasing demand for a thinner thickness of a semiconductor chip and a printed circuit board on which a semiconductor package is mounted. Accordingly, from a technology of manufacturing a printed circuit board using a conventional copper clad laminate (CCL) as a core insulating layer, recently, a technology of manufacturing a coreless printed circuit board without applying the core insulating layer has been studied. .

In addition, in recent years, as an insulating material, instead of conventional PPG or CCL, a technique of applying an epoxy mold compound has been known. Compared with the conventional PPG or CCL, the epoxy mold compound is advantageous in realizing a fine circuit pattern through a photo-litho process, and is advantageous in reducing the thickness of a printed circuit board. However, since the epoxy mold compound has insufficient ductility when used in a cured state, there may be a problem that is relatively vulnerable to cracking and breakage compared to PPG or CCL.

The technical problem to be achieved by the present invention is to provide an insulating structure of a printed circuit board and a method of manufacturing the same, which overcomes the weakness of the epoxy mold compound that is susceptible to cracks and breakage when an insulating layer containing an epoxy mold compound is used for a printed circuit board. do.

A printed circuit board including an interlayer insulating layer made of different materials according to an aspect may include an intermediate insulating layer including a fiber reinforcement; An upper circuit pattern layer and a lower circuit pattern layer respectively disposed on the upper and lower surfaces of the intermediate insulating layer; An upper interlayer insulating layer disposed on the upper surface of the intermediate insulating layer to cover the upper circuit pattern layer and not including a fiber reinforcement agent; And a lower interlayer insulating layer disposed on the lower surface of the intermediate insulating layer to cover the lower circuit pattern layer and not including a fiber reinforcement agent.

A method of manufacturing a printed circuit board including interlayer insulating layers of different materials according to one aspect is disclosed. In the manufacturing method of the printed circuit board, a carrier substrate including an insulating layer containing a fiber reinforcement agent, and first and second copper foil layers disposed on upper and lower surfaces of the insulating layer, respectively, is prepared. A first circuit pattern layer is formed on the first copper foil layer by a plating method. A first via is formed on the first circuit pattern layer by a plating method. A first interlayer insulating layer is formed on the first copper foil layer to cover the first circuit pattern layer and the first via, and does not include a fiber reinforcement agent. A second circuit pattern layer is formed on the first interlayer insulating layer by a plating method. A second interlayer insulating layer is formed on the first interlayer insulating layer so as to cover the second circuit pattern layer and includes a fiber reinforcement agent. The second interlayer insulating layer is processed to form a via hole exposing the second circuit pattern layer. A second via filling the inside of the via hole and a third circuit pattern layer disposed on the second interlayer insulating layer are formed by plating. A third via is formed on the third circuit pattern layer by a plating method. A third interlayer insulating layer is formed on the second interlayer insulating layer to cover the third circuit pattern layer and the third via, and does not include a fiber reinforcement agent. The carrier substrate is separated from the first circuit pattern layer.

A method of manufacturing a printed circuit board including interlayer insulating layers of different materials according to one aspect is disclosed. In the manufacturing method of the printed circuit board, a core substrate including a core insulating layer containing a fiber reinforcement agent, and first and second copper foil layers disposed on upper and lower surfaces of the core insulating layer, respectively, is prepared. The core substrate is processed to form a through via hole. A through via filling the through via hole and a first circuit pattern layer and a second circuit pattern layer respectively disposed on upper and lower surfaces of the insulating layer are formed by a plating method. A first via is formed on the first circuit pattern layer by a plating method. A second via is formed on the second circuit pattern layer by a plating method. A first interlayer insulating layer is formed on an upper surface of the core insulating layer to cover the first circuit pattern layer and the first via, and does not contain a fiber reinforcement agent. A second interlayer insulating layer is formed on a lower surface of the core insulating layer to cover the second circuit pattern layer and the second via, and does not include a fiber reinforcement agent.

According to an embodiment of the present invention, an insulating material including a fiber reinforcement is applied as an intermediate insulating layer of a printed circuit board, and the first and second interlayer insulating layers respectively disposed above and below the intermediate insulating layer are provided with fibers. An insulating material containing an epoxy mold compound that does not contain a reinforcing agent can be applied.

By the fiber reinforcing agent, the intermediate insulating layer having a relatively high resistance to cracks is configured to come into contact with the first and second interlayer insulating layers including upper and lower epoxy mold compounds, thereby suppressing the cracks Structural reliability can be improved. Accordingly, an epoxy mold compound having an advantage of increasing the degree of freedom of the molding process, such as enabling a patterning process by a photo-litho process and an etching process, and having relatively excellent thermal conductivity, is used as the first and second insulating layers. It has the advantage of being able to stably employ it.

1 is a schematic cross-sectional view of a printed circuit board according to an embodiment of the present invention.
2 is a flow chart schematically showing a printed circuit board according to another embodiment of the present invention.
3 to 12 are cross-sectional views schematically showing a method of manufacturing a printed circuit board according to an embodiment of the present invention.
13 to 20 are cross-sectional views schematically showing a method of manufacturing a printed circuit board according to another embodiment of the present invention.

Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. However, the present disclosure may be implemented in various different forms and is not limited to the embodiments described herein. In the drawings, in order to clearly express the constituent elements of each device, the size of the constituent elements, such as width or thickness, is slightly enlarged. Overall, it was described at the observer's point of view when explaining the drawings, and if one element is referred to as being positioned on another element, this means that the one element is positioned directly on another element or that an additional element may be interposed between them. Include.

The same reference numerals in the plurality of drawings refer to substantially the same elements. In addition, expressions in the singular should be understood as including plural expressions unless clearly defined otherwise in the context, and terms such as'include' or'have' are described features, numbers, steps, actions, components, and parts. It is to be understood that it is intended to designate the existence of a combination of these and not to preclude the possibility of the presence or addition of one or more other features or numbers, steps, actions, components, parts, or combinations thereof.

In addition, in performing the method or manufacturing method, each of the processes constituting the method may occur differently from the specified order unless a specific order is clearly stated in the context. That is, each process may occur in the same order as the specified order or may be performed substantially at the same time, and in some cases, the case of performing in the reverse order is not excluded.

Hereinafter, a structure and a manufacturing method of a printed circuit board employing an insulating layer including a fiber reinforcement agent and an insulating layer not including a fiber reinforcement agent together will be described using various embodiments.

1 is a schematic cross-sectional view of a printed circuit board according to an embodiment of the present invention. The printed circuit board 1 may be a coreless printed circuit board that does not have a core insulating board. Referring to FIG. 1, the printed circuit board 1 includes an intermediate insulating layer 15, an upper circuit pattern layer 16 and a lower circuit pattern layer 14, an upper interlayer insulating layer 17, and a lower interlayer insulating layer 13. ). At this time, the intermediate insulating layer 15 contains a fiber reinforcement, and the upper and lower interlayer insulating layers 17 and 13 do not contain a fiber reinforcement. As described above, in an embodiment of the present invention, the upper and lower interlayer insulating layers 17 and 13 may be made of a material different from that of the intermediate insulating layer 15.

Referring again to FIG. 1, an intermediate insulating layer 15 is provided. The intermediate insulating layer 15 may include a resin 15a and a fiber reinforcement 15b. The resin 150a may include, for example, epoxy. The fiber reinforcement agent 15b may include, for example, carbon fiber or glass fiber. The intermediate insulating layer 15 may further include a filler. The filler may include silica or alumina as an example. In one embodiment, the intermediate insulating layer 15 may include a prepreg. Specifically, the intermediate insulating layer 15 may be a cured prepreg layer.

The upper circuit pattern layer 16 may be disposed on the upper surface of the intermediate insulating layer 15. In a specific embodiment, the upper circuit pattern layer 16 may be disposed to protrude from the upper surface 15S1 of the intermediate insulating layer 15. The upper circuit pattern layer 16 may be, for example, a copper plating layer.

Meanwhile, the lower circuit pattern layer 14 may be disposed on the lower surface 15S2 of the intermediate insulating layer 15. In a specific embodiment, the lower circuit pattern layer 14 may be disposed in a state buried into the intermediate insulating layer 150 from the lower surface 15S2 of the intermediate insulating layer 15. In other words, the intermediate insulating layer 15 may fill the lower circuit pattern layer 14. Each of the lower circuit pattern layers 14 may be a copper plating layer as an example.

An intermediate via 15v may be disposed inside the intermediate insulating layer 15. The intermediate via 15v may connect the upper circuit pattern layer 16 and the lower circuit pattern layer 14. The intermediate via 15v may be a copper plating layer. Meanwhile, referring to FIG. 1, the side profile of the intermediate via 15v may have a shape inclined with respect to the thickness direction on the surface of the intermediate insulating layer 15, that is, the upper surface 15S1. As an example, the upper width W1 on the upper surface 15S1 of the intermediate via 15v may be larger than the lower width W2 on the lower circuit pattern layer 14. The fact that the side profile has an inclined shape is a result of reflecting characteristics of a via hole processing process for the intermediate insulating layer 15 in the manufacturing methods of FIGS. 3 to 12 to be described later.

An upper via 16v may be disposed on the upper circuit pattern layer 16. The upper via 16v may be a copper plating layer. Meanwhile, an upper interlayer insulating layer 17 disposed to cover the upper circuit pattern layer 16 and the upper via 16v may be disposed on the upper surface 15S1 of the intermediate insulating layer 15. In this case, the side profile of the upper via 16v may have a shape substantially perpendicular to the thickness direction on the surface of the upper interlayer insulating layer 17, unlike the side profile of the intermediate via 15v. As an example, the upper width W3 and the lower width W4 of the upper via 16v may be substantially the same. The side profile may be a result of reflecting a characteristic of a semi-additive process (SAP) or a modified semi-additive process (MSAP) in a manufacturing method described later with reference to FIGS. 3 to 12.

The upper interlayer insulating layer 17 may include resin. Specifically, the upper interlayer insulating layer 17 may include an epoxy mold compound. In addition, the upper interlayer insulating layer may further include a filler. The filler may include silica or alumina as an example. In an embodiment of the present invention, the upper interlayer insulating layer 17 does not include the fiber reinforcement agent. Since the upper interlayer insulating layer 17 does not include the fiber reinforcing agent, an additional patterning process for the upper interlayer insulating layer 17 by a photo-litho process and an etching process may be performed. That is, although not shown, a via hole may be formed in the upper interlayer insulating layer 17 by a photo-litho process and an etching process, and the via hole may be filled with a plating material to additionally form a conductive via. In addition, the upper interlayer insulating layer 17 can secure a relatively superior thermal conductivity than an insulating material containing a fiber reinforcement.

Further, a lower via 12v may be disposed on the lower circuit pattern layer 14. The lower via 12v may be a copper plating layer. Meanwhile, the lower interlayer insulating layer 13 may be disposed on the lower surface 15S2 of the intermediate insulating layer 15 to cover the lower circuit pattern layer 14 and the lower via 12v. In addition, the lowermost circuit pattern layer 12 may be disposed in a state covered with the lower interlayer insulating layer 13. The lowermost circuit pattern layer 12 may be connected to the lower circuit pattern layer 14 by a lower via 12v. The lowermost circuit pattern layer 12 may be, as an example, a copper plating layer. Meanwhile, unlike the side profile of the intermediate via v15, the side profile of the lower via 12v may have a shape substantially perpendicular to the thickness direction on the surface of the lower interlayer insulating layer 13. As an example, the upper width W5 and the lower width W6 of the lower via 12v may be substantially the same. The side profile may be a result of reflecting a characteristic of a semi-additive process (SAP) or a modified semi-additive process (MSAP) in a manufacturing method described later with reference to FIGS. 3 to 12.

The lower interlayer insulating layer 13 may include resin. Specifically, the lower interlayer insulating layer 13 may include an epoxy mold compound. In addition, the lower interlayer insulating layer may further include a filler. The filler may include silica or alumina as an example. In an embodiment of the present invention, the lower interlayer insulating layer 13 does not include the fiber reinforcement agent. Since the lower interlayer insulating layer 13 does not include the fiber reinforcing agent, a photo-lithography process and a patterning process of the lower interlayer insulating layer 13 by an etching process are possible, so that the degree of freedom of the forming process can be increased. In addition, it is possible to secure a relatively superior thermal conductivity than an insulating material containing a fiber reinforcement.

In some embodiments not shown, a solder resist pattern layer may be formed on one surface of the upper interlayer insulating layer 17 to selectively cover the upper via 16v. In addition, a solder resist pattern layer selectively covering the lowermost circuit pattern layer 12 may be formed on one surface of the lower interlayer insulating layer 13. The upper via 16v and the lowermost circuit pattern layer 12 exposed by the solder resist pattern layers may function as connection pads for electrical connection to other device chips, packages, or printed circuit boards.

2 is a schematic cross-sectional view of a printed circuit board 2 according to another embodiment of the present invention. The printed circuit board 2 may be a core printed circuit board having a core insulating layer. Referring to FIG. 2, the printed circuit board 2 includes an intermediate insulating layer 21, an upper circuit pattern layer 22a and a lower circuit pattern layer 22b, an upper interlayer insulating layer 23a, and a lower interlayer insulating layer 23b. ). The intermediate insulating layer 21 may be the core insulating layer. At this time, the intermediate insulating layer 21 contains a fiber reinforcement, and the upper and lower interlayer insulating layers 23a and 23b do not contain a fiber reinforcement. As described above, in an embodiment of the present invention, the upper and lower interlayer insulating layers 23a and 23b may be made of a material different from that of the intermediate insulating layer 21.

Referring again to FIG. 2, an intermediate insulating layer 21 is provided. The intermediate insulating layer 21 may include a resin 21a and a fiber reinforcement 21b. The resin 21a may include, as an example, epoxy. The fiber reinforcing agent 21b may include, for example, carbon fiber or glass fiber. The intermediate insulating layer 21 may further include a filler. The filler may include silica or alumina as an example. In an embodiment, the intermediate insulating layer 21 may include a prepreg. Specifically, the intermediate insulating layer 21 may be a cured prepreg layer.

An upper circuit pattern layer 22a may be disposed on the upper surface 21S1 of the intermediate insulating layer 21. Similarly, the lower circuit pattern layer 22b may be disposed on the lower surface 21S2 of the intermediate insulating layer 21. In a specific embodiment, the upper and lower circuit pattern layers 22a and 22b may be disposed to protrude from the upper and lower surfaces of the intermediate insulating layer 21, respectively. The upper and lower circuit pattern layers 22a and 22b may be copper plating layers as an example.

Meanwhile, an intermediate via 21c may be disposed inside the intermediate insulating layer 21. The intermediate via 21c may be, for example, a copper plating layer. The side profile of the intermediate via 21c may have a shape inclined with respect to the inner direction (ie, the thickness direction) from both surfaces of the intermediate insulating layer 21, that is, the upper surface 21S1 and the lower surface 21S2. That is, the widths W7 and W8 on the upper surface 21S1 and the lower surface 21S2 may be larger than the width W9 at a predetermined point inside the intermediate insulating layer 21.

An upper via 22c may be disposed on the upper circuit pattern layer 22a. The upper via 22c may be a copper plating layer. Meanwhile, an upper interlayer insulating layer 23a covering the upper circuit pattern layer 22a and the upper via 22c may be disposed on the upper surface 21S1 of the intermediate insulating layer 21. Likewise, a lower via 22d may be disposed on the lower circuit pattern layer 22b. The lower via 22d may be a copper plating layer. Meanwhile, a lower interlayer insulating layer 23b disposed to cover the lower circuit pattern layer 22b and the lower via 22d may be disposed on the lower surface 21S2 of the intermediate insulating layer 21. The side profiles of the upper via 22c and the lower via 22d may have a shape substantially perpendicular to the inner direction (ie, the thickness direction) on the surfaces of the upper and lower interlayer insulating layers 23a and 23b, respectively. The side profile may be a result of reflecting a characteristic of a semi-additive process (SAP) or a modified semi-additive process (MSAP) in the method for manufacturing a printed circuit board described above with reference to FIGS. 13 to 19.

The upper and lower interlayer insulating layers 23a and 23b may include resin. Specifically, the upper and lower interlayer insulating layers 23a and 23b may include an epoxy mold compound. In addition, the upper and lower interlayer insulating layers 23a and 23b may further include a filler. As an example, the filler may include silica or alumina. In an embodiment of the present invention, the upper and lower interlayer insulating layers 23a and 23b do not contain the fiber reinforcement. Since the upper and lower interlayer insulating layers 23a and 23b do not contain the fiber reinforcing agent, the patterning process of the upper and lower interlayer insulating layers 23a and 23b by a photo-litho process and an etching process is additionally possible. Process freedom can be increased. In addition, it is possible to secure a relatively superior thermal conductivity than an insulating material containing a fiber reinforcement.

Referring again to FIG. 2, the uppermost circuit pattern layer 24 may be disposed on the upper interlayer insulating layer 23a. The uppermost circuit pattern layer 24 may be, for example, a copper plating layer. The uppermost circuit pattern layer 24 may be connected to the upper circuit pattern layer 22a through the upper via 22c.

In some embodiments not shown, a solder resist pattern layer selectively covering the uppermost circuit pattern layer 24 may be disposed on the upper interlayer insulating layer 23a. In addition, a solder resist pattern layer may be disposed on the lower interlayer insulating layer 23b to selectively cover the lower via 22d. The uppermost circuit pattern layer 24 and the lower via 22d exposed by the solder resist pattern layers may function as connection pads for electrical connection to other device chips, packages, or printed circuit boards.

As described above, according to an embodiment of the present invention, the printed circuit board includes an intermediate insulating layer, and an upper interlayer insulating layer and a lower interlayer insulating layer respectively disposed on upper and lower surfaces of the intermediate insulating layer. The intermediate insulating layer having a relatively high resistance to cracks by the fiber reinforcement agent is configured to contact the upper and lower interlayer insulating layers containing an epoxy mold compound, thereby suppressing the cracks and improving the structural reliability of the printed circuit board. I can. Accordingly, an epoxy mold compound having an advantage of increasing the degree of freedom of the molding process, such as enabling a patterning process by a photo-litho process and an etching process, and having relatively excellent thermal conductivity, as the upper and lower interlayer insulating layers. It has the advantage of being able to employ it stably.

3 to 12 are cross-sectional views schematically showing a method of manufacturing a printed circuit board according to an embodiment of the present invention. This method of manufacturing a printed circuit board can be applied to the method of manufacturing the printed circuit board 1 described above with respect to FIG. 1.

Referring to FIG. 3, a carrier substrate 100 is prepared. The carrier substrate 100 includes an insulating layer 110 and first and second copper foil layers 112a and 112b disposed on upper and lower surfaces of the insulating layer 110, respectively. In this case, the insulating layer 110 may include a fiber reinforcement. The fiber reinforcement may include carbon fiber or glass fiber. Specifically, the insulating layer 110 may include a resin, a fiber reinforcement, and a filler. The filler may include silica or alumina. As an example, the insulating layer 110 may include a prepreg. The insulating layer 110 may be, for example, a copper laminated substrate CCL.

Referring to FIG. 4, a first circuit pattern layer 120 is formed on the first copper foil layer 112a by plating. The first circuit pattern layer 120 may be a copper plating layer. In this case, the first copper foil layer 112a may function as a plating seed layer. As an example, the plating method may apply a semi-additive process (SAP) or a modified semi-additive process (MSAP).

Referring to FIG. 5, the first via 125 is formed on the first circuit pattern layer 120 by a plating method. The first via 125 may be a copper plating layer. As an example, the plating method may apply a semi-additive process (SAP) or a modified semi-additive process (MSAP). The first via 125 may be formed such that the side profile has a shape substantially perpendicular to the surface of the first circuit pattern layer 120. This side profile may be caused by the characteristics of the plating process using the SAP or MSAP method. That is, the first via 125 may be formed by forming a photosensitive pattern of a hole type where the first via 125 is to be formed and filling the hole with a plating material. In this case, the side profile of the hole of the photosensitive pattern may have a shape substantially perpendicular to the first circuit pattern layer 120. After the first via 125 is formed, the hole-type photosensitive pattern may be removed.

6 and 7, a first interlayer insulating layer 130 covering the first circuit pattern layer 120 and the first via 125 is formed on the first copper foil layer 112a. In this case, the first interlayer insulating layer 130 does not contain a fiber reinforcement. In addition, the first interlayer insulating layer 130 may include an epoxy mold compound. Meanwhile, the first interlayer insulating layer 130 may further include an inorganic filler in addition to the epoxy mold compound. The inorganic filler may include silica or alumina.

Meanwhile, the process of forming the first interlayer insulating layer 130 may specifically follow the following steps. First, an incompletely cured epoxy component insulating material is prepared. Then, the insulating material is pressed onto the first copper foil layer 112a using pressure and heat. As a result, as shown in FIG. 6, the insulating material including the epoxy mold compound may be formed to cover the first circuit pattern layer 120 and the first via 125 in a cured form. Subsequently, as shown in FIG. 7, the insulating material is removed and flattened so that the top surface of the first via 125 and the top surface of the insulating material lie on the same plane. As a result, the first interlayer insulating layer 130 may be formed on the first copper foil layer 112a. As an example, the planarization process may include an etching method or a chemical mechanical polishing method.

Referring to FIG. 8, a second circuit pattern layer 140 is formed on the first interlayer insulating layer 130 by plating. In this case, a portion of the second circuit pattern layer 140 may be connected to the first via 125. As an example, the plating method may apply SAP or MSAP.

Referring to FIG. 9, a second interlayer insulating layer 150 disposed on the first interlayer insulating layer 130 to cover the second circuit pattern layer 140 is formed. At this time, the second interlayer insulating layer 150 includes a fiber reinforcement. Subsequently, the second interlayer insulating layer 150 is processed to form a via hole 10 exposing the second circuit pattern layer 140. Specifically, the fiber reinforcement agent may include carbon fiber or glass fiber. The second interlayer insulating layer 150 may include, for example, a prepreg.

In an embodiment, the method of forming the structure shown in FIG. 9 may proceed as follows. First, an insulating material 150 including a non-cured resin 150a and a fiber reinforcement 150b is prepared. In this case, a copper foil layer 151 may be additionally disposed on one surface of the insulating material 150. Subsequently, the copper foil layer 151 and the insulating material 150 are pressed onto the first interlayer insulating layer 130 using pressure and heat. As a result, by curing the insulating material 150, it can be converted into the second interlayer insulating layer 150. Subsequently, the copper foil layer 151 and the second interlayer insulating layer 150 may be processed to form a via hole 10 exposing the second circuit pattern layer 140. The processing method may be a laser processing method or a mechanical processing method. In this case, the side profile of the via hole 10 may have an inclined shape in an inward direction (ie, a thickness direction) from a surface where processing of the second interlayer insulating layer 150 starts. The side profile having such an inclined shape may be a characteristic of forming a via hole according to a laser processing method or a mechanical processing method.

Referring to FIG. 10, a second via 155 filling the inside of the via hole 10 and a third circuit pattern layer 160 disposed on the second interlayer insulating layer 150 are formed by plating. As an example, the plating method may include SAP or MSAP. During the plating method, the copper foil layer 151 may function as a plating seed layer. After the via 155 and the third circuit pattern layer 160 are formed, the copper foil layer 151 positioned between the third circuit pattern layer 160 may be removed. As a result, it is possible to prevent an electrical short from occurring between the neighboring third circuit pattern layers 160.

Referring to FIG. 11, a third via 165 is formed on the third circuit pattern layer 160 by a plating method. As an example, the plating method may include SAP or MSAP. The third via 165 may be formed such that the side profile has a shape substantially perpendicular to the surface of the third circuit pattern layer 160. This side profile may be caused by the characteristics of the plating process using the SAP or MSAP method. That is, by forming a photosensitive pattern of a hole type where the third via 165 is to be formed and filling the inside of the hole with a plating material, the third via 165 may be formed. In this case, the side profile of the hole of the photosensitive pattern may have a shape substantially perpendicular to the third circuit pattern layer 160.

Referring to FIG. 12, a third interlayer insulating layer 170 is formed on the second interlayer insulating layer 150 to cover the third circuit pattern layer 160 and the third via 165. The third interlayer insulating layer 170 does not contain a fiber reinforcement. Specifically, the third interlayer insulating layer 170 may include an epoxy mold compound. Meanwhile, the third interlayer insulating layer 170 may further include a filler in addition to the epoxy mold compound. The filler may include silica or alumina.

Meanwhile, the process of forming the third interlayer insulating layer 170 may specifically follow the following steps. First, an incompletely cured epoxy component insulating material is prepared. Subsequently, the insulating material is pressed onto the second interlayer insulating layer 150 using pressure and heat. As a result, as illustrated in FIG. 12, the insulating material including the epoxy mold compound may be formed to cover the third circuit pattern layer 160 and the third via 165 in a cured state. Subsequently, the insulating material is removed and planarized so that the upper surface of the third via 165 and the upper surface of the insulating material lie on the same plane. As a result, the third interlayer insulating layer 170 may be formed on the second interlayer insulating layer 150. As an example, the planarization process may include an etching method or a chemical mechanical polishing method.

Subsequently, the carrier substrate 100 is separated from the first circuit pattern layer 120. Specifically, the carrier substrate 100 and the first circuit pattern layer 120 can be separated by the interface between the first copper foil layer 112a and the first circuit pattern layer 120 of the carrier substrate 100. have. As a result, the printed circuit board disclosed in FIG. 12 can be manufactured.

In some embodiments not shown, a solder resist pattern layer may be formed on one surface of the third interlayer insulating layer 170 to selectively cover the third via 165. In addition, a solder resist pattern layer selectively covering the first circuit pattern layer 120 may be formed on one surface of the first interlayer insulating layer 130. The third via 165 and the first circuit pattern layer 120 exposed by the solder resist pattern layers may function as connection pads for electrical connection to other device chips, packages, or printed circuit boards.

13 to 20 are cross-sectional views schematically showing a method of manufacturing a printed circuit board according to another embodiment of the present invention. This method of manufacturing a printed circuit board can be applied to the method of manufacturing the printed circuit board 2 described above with respect to FIG. 2.

Referring to FIG. 13, a core substrate 200 is prepared. The core substrate 200 includes a core insulating layer 210 and first and second copper foil layers 212a and 212b disposed on upper and lower surfaces of the core insulating layer 210, respectively.

The core insulating layer 210 may include a resin 210a and a fiber reinforcement 210b. The fiber reinforcement agent 210b may include carbon fiber or glass fiber. The core insulating layer 210 may additionally include a filler. The filler may include silica or alumina. The core insulating layer 210 may include, for example, a prepreg. The core insulating layer 210 may be, for example, a copper laminated substrate (CCL).

Referring to FIG. 14, a through via hole 20 is formed by processing the core substrate 200. As an example, a method of processing the core substrate 200 may employ a laser processing method or a mechanical processing method.

In an embodiment, the core substrate 200 is processed in the direction of the'T1' and'T2' of FIG. 14, from the top and the bottom of the core substrate 200 to the inner direction of the core substrate 200 by laser processing. can do. Accordingly, the side profile of the formed through via hole 20 may have a shape inclined from the surface of the core substrate 200 in the inner direction (ie, the thickness direction). As an example, as shown in FIG. 14, a side profile of the via hole 20 having a mortar shape and a concave center may be formed.

Referring to FIG. 15, a through via 215 filling the through via hole 20 and a first circuit pattern layer 220a and a second circuit pattern layer 220b respectively disposed on the upper and lower surfaces of the core insulating layer 210 Is formed by a plating method. As an example, the plating method may include SAP or MSAP.

Referring to FIG. 16, a first via 225a is formed on the first circuit pattern layer 220a by a plating method. The first via 225a may include, as an example, a copper plating layer. As an example, the plating method may include SAP or MSAP. The first via 225a may be formed such that the side profile has a shape substantially perpendicular to the surface of the first circuit pattern layer 220a. This side profile may be caused by the characteristics of the plating process using the SAP or MSAP method. That is, the first via 225a may be formed by forming a photosensitive pattern of a hole type where the first via 225a is to be formed and filling the inside of the hole with a plating material. In this case, the side profile of the hole of the photosensitive pattern may have a shape substantially perpendicular to the first circuit pattern layer 220a. After forming the first via 225a, the hole-type photosensitive pattern may be removed.

Referring again to FIG. 16, a second via 225b is formed on the second circuit pattern layer 220b by a plating method. The second via 225b may include, for example, a copper plating layer. As an example, the plating method may include SAP or MSAP. The second via 225b may be formed such that the side profile has a shape substantially perpendicular to the surface of the second circuit pattern layer 220b. This side profile may be caused by the characteristics of the plating process using the SAP or MSAP method. That is, the second via 225b may be formed by forming a photosensitive pattern of a hole type where the second via 225b is to be formed and filling the inside of the hole with a plating material. In this case, the side profile of the hole of the photosensitive pattern may have a shape substantially perpendicular to the second circuit pattern layer 220b. After forming the second via 225b, the hole-type photosensitive pattern may be removed.

17 and 18, a first interlayer insulating layer 230a disposed to cover the first circuit pattern layer 220a and the first via 225a on the upper surface of the core insulating layer 210 is formed. The first interlayer insulating layer 230a may include the above-described fiber reinforcement. The process of forming the first interlayer insulating layer 230a may be specifically performed as follows.

First, referring to FIG. 17, an insulating material made of an incompletely cured epoxy component is prepared. The insulating material is pressed onto the upper surface of the core insulating layer 210 using pressure and heat. Accordingly, the insulating material is cured and disposed to cover the first circuit pattern layer 220a and the first via 225a. Subsequently, referring to FIG. 18, the insulating material is removed and planarized so that the top surface of the first via 225a and the top surface of the insulating material lie on the same plane. As a result, the first interlayer insulating layer 230a may be formed. As an example, the planarization process may include an etching method or a chemical mechanical polishing method.

Similarly, a second interlayer insulating layer 230b disposed to cover the second circuit pattern layer 220b and the second via 225b on the lower surface of the core insulating layer 210 is formed. The second interlayer insulating layer 230b may include the above-described fiber reinforcement. The process of forming the second interlayer insulating layer 230b may be specifically performed as follows.

First, referring to FIG. 17, an insulating material made of an incompletely cured epoxy component is prepared. The insulating material is pressed onto the lower surface of the core insulating layer 210 using pressure and heat. Accordingly, the insulating material is hardened and disposed to cover the second circuit pattern layer 220b and the second via 225b. Subsequently, referring to FIG. 18, the insulating material is removed and planarized so that the top surface of the second via 225b and the top surface of the insulating material lie on the same plane. As a result, a second interlayer insulating layer 230b may be formed. As an example, the planarization process may include an etching method or a chemical mechanical polishing method.

Referring to FIG. 19, a third circuit pattern layer 240 may be formed on the first interlayer insulating layer 230a by plating. As an example, the plating method may include SAP or MSAP. The third circuit pattern layer 240 may be electrically connected to the first circuit pattern layer 220a through the second via 225a.

In some embodiments not shown, a solder resist pattern layer selectively covering the third circuit pattern layer 240 may be further disposed on the first interlayer insulating layer 230a. In addition, a solder resist pattern layer may be disposed on the second interlayer insulating layer 230b to selectively cover the second via 225b. The third circuit pattern layer 240 and the second via 225b exposed by the solder resist pattern layers may function as connection pads for electrical connection to other device chips, packages, or printed circuit boards. Through the above-described process, a printed circuit board according to an embodiment of the present invention may be manufactured.

Although described above with reference to the drawings and embodiments, those skilled in the art will variously modify and change the embodiments disclosed in the present application within the scope not departing from the technical spirit of the present application described in the following claims. You will understand that you can do it.

1 2: printed circuit board,
10 20: Via hole
12: lowermost circuit pattern layer, 12v: lower via,
13: lower interlayer insulating layer, 14: lower circuit pattern layer,
15: intermediate insulating layer, 15a: resin, 15b: fiber reinforcement,
15S1: top, 15S2: bottom, 15v: middle via,
16: upper circuit pattern layer, 16v: upper via, 17: upper interlayer insulating layer,
21: intermediate insulating layer, 21a: resin, 21b: fiber reinforcement, 21c: intermediate via,
21S1: top, 21S2: bottom,
22a: upper circuit pattern layer, 22b: lower circuit pattern layer,
22c: upper via, 22d: lower via,
23a: upper interlayer insulating layer, 23b: lower interlayer insulating layer, 24: uppermost circuit pattern layer,
100: carrier substrate, 110: insulating layer, 112a 112b: first and second copper foil layers,
120: first circuit pattern layer, 125: first via, 130: first interlayer insulating layer, 140: second circuit pattern layer,
150: second interlayer insulating layer, 150a: resin, 150b: fiber reinforcement,
151: copper foil layer, 155: second via,
160: a third circuit pattern layer, 165: a third via, 170: a third interlayer insulating layer,
200: core substrate, 210: core insulating layer, 210a: resin, 210b: fiber reinforcement,
212a 212b: first and second copper foil layers, 215: through vias,
220a 220b: first and second circuit pattern layers,
225a 225b: first and second vias,
230a 230b: first and second interlayer insulating layers, 240: third circuit pattern layer.

Claims (18)

An intermediate insulating layer containing a fiber reinforcement;
An upper circuit pattern layer and a lower circuit pattern layer respectively disposed on the upper and lower surfaces of the intermediate insulating layer;
An upper interlayer insulating layer disposed on the upper surface of the intermediate insulating layer to cover the upper circuit pattern layer and not including a fiber reinforcement agent; And
Disposed to cover the lower circuit pattern layer on the lower surface of the intermediate insulating layer, and including a lower interlayer insulating layer not including a fiber reinforcing agent
A printed circuit board including interlayer insulating layers of different materials.
The method of claim 1,
The fiber reinforcement agent comprises carbon fiber or glass fiber
A printed circuit board including interlayer insulating layers of different materials.
The method of claim 1,
The intermediate insulating layer includes a prepreg,
The upper and lower interlayer insulating layers contain an epoxy mold compound.
A printed circuit board including interlayer insulating layers of different materials.
The method of claim 1,
The intermediate insulating layer has an intermediate via,
The upper interlayer insulating layer has an upper via,
The lower interlayer insulating layer has a lower via,
The side profile of the intermediate via has a shape inclined with respect to the inner direction from the surface of the intermediate insulating layer,
The side profiles of the upper and lower vias have a shape that is substantially perpendicular to the inner direction on the surfaces of the upper and lower interlayer insulating layers, respectively.
A printed circuit board including interlayer insulating layers of different materials.
(a) preparing a carrier substrate including an insulating layer containing a fiber reinforcement agent, and first and second copper foil layers disposed on upper and lower surfaces of the insulating layer, respectively;
(b) forming a first circuit pattern layer on the first copper foil layer by a plating method;
(c) forming a first via on the first circuit pattern layer by a plating method;
(d) forming a first interlayer insulating layer on the first copper foil layer to cover the first circuit pattern layer and the first via, and not including a fiber reinforcement agent;
(e) forming a second circuit pattern layer on the first interlayer insulating layer by a plating method;
(f) forming a second interlayer insulating layer on the first interlayer insulating layer to cover the second circuit pattern layer and including a fiber reinforcing agent;
(g) forming a via hole exposing the second circuit pattern layer by processing the second interlayer insulating layer;
(h) forming a second via filling the inside of the via hole by a plating method and a third circuit pattern layer disposed on the second interlayer insulating layer;
(i) forming a third via on the third circuit pattern layer by a plating method;
(j) forming a third interlayer insulating layer on the second interlayer insulating layer to cover the third circuit pattern layer and the third via, and not including a fiber reinforcement agent; And
(k) separating the carrier substrate from the first circuit pattern layer
A method of manufacturing a printed circuit board including interlayer insulating layers of different materials.
The method of claim 5,
The fiber reinforcement agent comprises carbon fiber or glass fiber
A method of manufacturing a printed circuit board including interlayer insulating layers of different materials.
The method of claim 5,
The first and third interlayer insulating layers contain an epoxy mold compound,
The second interlayer insulating layer includes a prepreg
A method of manufacturing a printed circuit board including interlayer insulating layers of different materials.
The method of claim 5,
Forming the first via in step (c) and forming the third via in step (i)
The side profiles of the first and third vias are formed to have a shape substantially perpendicular to the inner direction from the surfaces of the first circuit pattern layer and the third circuit pattern layer, respectively,
Forming the second via of step (h)
Forming a side profile of the second via to have a shape inclined inward from the surface of the second circuit pattern layer
A method of manufacturing a printed circuit board including interlayer insulating layers of different materials.
The method of claim 5,
The step of forming the first interlayer insulating layer of step (d)
(d1) preparing an insulating material of an incompletely cured epoxy component;
(d2) pressing the insulating material onto the first copper foil layer using pressure and heat; And
(d3) removing the insulating material so that the top surface of the first via and the top surface of the insulating material are on the same plane, and planarizing
A method of manufacturing a printed circuit board including interlayer insulating layers of different materials.
The method of claim 5,
Forming the via hole of step (g)
Comprising the step of processing the second interlayer insulating layer by using a laser processing method or a mechanical processing method of the second interlayer insulating layer
A method of manufacturing a printed circuit board including interlayer insulating layers of different materials.
The method of claim 5,
Forming the third interlayer insulating layer of step (j)
(j1) preparing an insulating material of an incompletely cured epoxy component;
(j2) pressing the insulating material onto the second interlayer insulating layer using pressure and heat; And
(j3) removing the insulating material so that the top surface of the third via and the top surface of the insulating material are on the same plane, and planarizing
A method of manufacturing a printed circuit board including interlayer insulating layers of different materials.
(a) preparing a core substrate including a core insulating layer containing a fiber reinforcement agent, and first and second copper foil layers disposed on upper and lower surfaces of the core insulating layer, respectively;
(b) forming a through via hole by processing the core substrate;
(c) forming a through via filling the through via hole and a first circuit pattern layer and a second circuit pattern layer respectively disposed on upper and lower surfaces of the insulating layer by a plating method;
(d) forming a first via on the first circuit pattern layer by a plating method;
(e) forming a second via on the second circuit pattern layer by a plating method;
(f) forming a first interlayer insulating layer on an upper surface of the core insulating layer to cover the first circuit pattern layer and the first via, and not including a fiber reinforcement agent; And
(g) forming a second interlayer insulating layer disposed on a lower surface of the core insulating layer to cover the second circuit pattern layer and the second via, and does not contain a fiber reinforcement agent.
A method of manufacturing a printed circuit board including interlayer insulating layers of different materials.
The method of claim 12,
The fiber reinforcement agent comprises carbon fiber or glass fiber
A method of manufacturing a printed circuit board including interlayer insulating layers of different materials.
The method of claim 12,
The first and second interlayer insulating layers contain an epoxy mold compound,
The core insulating layer includes a prepreg
A method of manufacturing a printed circuit board including interlayer insulating layers of different materials.
The method of claim 12,
The core substrate in step (a) is a copper laminated substrate
A method of manufacturing a printed circuit board including interlayer insulating layers of different materials.
The method of claim 12,
The step of forming the through via hole of step (b)
In the inner direction from the upper and lower surfaces of the core substrate, comprising the step of processing the core substrate by a laser processing method
A method of manufacturing a printed circuit board including interlayer insulating layers of different materials.
The method of claim 12,
The step of forming the first interlayer insulating layer of step (f)
(f1) preparing an insulating material of an incompletely cured epoxy component;
(f2) pressing the insulating material on the upper surface of the core insulating layer using pressure and heat; And
(f3) removing the insulating material so that the top surface of the first via and the top surface of the insulating material are on the same plane, and planarizing
A method of manufacturing a printed circuit board including interlayer insulating layers of different materials.
The method of claim 12,
The step of forming the second interlayer insulating layer of step (g)
(g1) preparing an insulating material of an incompletely cured epoxy component;
(g2) pressing the insulating material on the lower surface of the core insulating layer using pressure and heat; And
(g3) removing the insulating material so that the top surface of the second via and the top surface of the insulating material are on the same plane, and planarizing
A method of manufacturing a printed circuit board including interlayer insulating layers of different materials.

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