KR20210002994A - Display panel - Google Patents

Abstract

Embodiments of the present invention relate to a display panel, and more specifically to the display panel including: a planarization layer; an etch stop layer provided between the bank layers; and a first electrode including an inclined region. Therefore, light efficiency is improved by reflection of the first electrode having the inclined region having a high inclination angle.

Description

Display panel {DISPLAY PANEL}

Embodiments of the present invention relate to a display panel.

As the information society develops, demands for various display panels such as display devices and lighting devices are increasing in various forms. In the field of display panels, since a separate light source is not required, there is an increasing demand for an organic light emitting display panel that is advantageous in reducing weight and thickness.

However, the organic light-emitting display panel includes an organic light-emitting layer that emits light, and among the light emitted from the organic light-emitting layer, light from the organic light-emitting display panel exists because the light cannot come out of the organic light-emitting display panel and is trapped inside the organic light-emitting display panel. There is a problem in that the extraction efficiency is lowered and the luminous efficiency is lowered.

Embodiments of the present invention can provide a display panel with improved light efficiency.

Embodiments of the present invention can provide a display panel in which an etch stop layer is positioned between the planarization layer and the first bank layer, so that the angle of the inclined region of the first bank layer can be easily increased.

Embodiments of the present invention provide a display panel capable of reducing light trapped inside the display panel by reflecting light emitted from the light emitting layer by the inclined area of the first electrode formed on the inclined area of the first bank layer having a high angle. Can provide.

In one aspect, embodiments of the present invention include a substrate, a planarization layer disposed on the substrate, an etch stop layer disposed on the planarization layer, a first bank layer disposed on the etch stop layer, and an etch stop layer. A first electrode disposed on the upper and first bank layers, a second bank layer disposed on the first electrode, and a light emitting layer disposed on the first electrode, a first contact hole, and a light emitting layer upper and second bank layer A display panel including a second electrode positioned thereon may be provided.

In addition, the above-described first bank layer may include a first opening for the etch stop layer, a first slope area surrounding the first opening, and a first flat area connected to the first slope area.

In addition, the above-described first electrode may be positioned above the etch stop layer exposed through the above-described first opening and above the first inclined region of the first bank layer.

In addition, the above-described second bank layer may include a second opening for the first electrode.

In addition, the above-described emission layer may be positioned on the first electrode exposed through the second opening.

In addition, the above-described first contact hole may pass through the planarization layer, the etch stop layer, and the first bank layer.

In addition, the above-described first electrode may directly contact the planarization layer through the first contact hole.

In another aspect, embodiments of the present invention include a substrate, a planarization layer disposed on the substrate, an etch stop layer disposed on the planarization layer, a first bank layer disposed on the etch stop layer, and an etch stop layer. A first electrode disposed on the upper and first bank layers, a second bank layer disposed on the first electrode, and a light emitting layer disposed on the first electrode, a first contact hole, and a light emitting layer upper and second bank layer A display panel including a second electrode positioned above, a first emission area, and a second emission area may be provided.

In addition, the aforementioned first electrode may include a second inclined region.

In addition, the above-described first electrode may directly contact the above-described planarization layer through the above-described first contact hole.

In addition, the above-described second electrode may include a flat region positioned above the emission layer.

Further, in the above-described first emission region, light may be emitted from the emission layer through the above-described flat region of the second electrode.

In addition, in the above-described second emission region, light reflected from the above-described second inclined region may be emitted.

According to embodiments of the present invention, a display panel with improved light efficiency can be provided.

In addition, according to embodiments of the present invention, since the etch stop layer is positioned between the planarization layer and the first bank layer, it is possible to provide a display panel capable of easily increasing the angle of the inclined region of the first bank layer.

In addition, according to embodiments of the present invention, light trapped inside the display panel is reduced by reflecting light emitted from the light emitting layer by the inclined area of the first electrode formed on the inclined area of the first bank layer having a high angle. It is possible to provide a display panel capable of.

1 is a diagram illustrating an example of a schematic configuration of a display device according to embodiments of the present invention.
2 is a cross-sectional view of a display panel according to example embodiments.
3 is a cross-sectional view of a display panel according to Comparative Example 1 of the present invention.
4 is a cross-sectional view of a display panel according to Comparative Example 2 of the present invention.
5 is a diagram for explaining some steps in a method of manufacturing a display panel according to Comparative Example 1 of the present invention.
6 is a view for explaining some steps of a method of manufacturing a display panel according to Comparative Example 2 of the present invention.
7 is a diagram for explaining some steps in a method of manufacturing a display panel according to example embodiments.
8 is a view for explaining that light emitted from a display panel according to exemplary embodiments is reflected by a first electrode.
9 is a partially enlarged view of FIG. 2.
10 to 11 are cross-sectional views of display panels according to embodiments of the present invention.
12 is a partially enlarged view of FIG. 11.
13 and 14 are plan views of a display panel according to example embodiments.

Hereinafter, some embodiments of the present invention will be described in detail with reference to exemplary drawings. In adding reference numerals to elements of each drawing, the same elements may have the same numerals as possible even if they are indicated on different drawings. In addition, in describing the present invention, when it is determined that a detailed description of a related known configuration or function may obscure the subject matter of the present invention, a detailed description thereof may be omitted. When "include", "have", "consists of" and the like mentioned in the present specification are used, other parts may be added unless "only" is used. In the case of expressing the constituent elements in the singular, the case including plural may be included unless there is a specific explicit description.

In addition, in describing the constituent elements of the present invention, terms such as first, second, A, B, (a) and (b) may be used. These terms are only for distinguishing the component from other components, and the nature, order, order, or number of the component is not limited by the term.

In the description of the positional relationship of the components, when two or more components are described as being "connected", "coupled" or "connected", the two or more components are directly "connected", "coupled" or "connected" "It may be, but it should be understood that two or more components and other components may be further "interposed" to be "connected", "coupled" or "connected". Here, the other components may be included in one or more of two or more components "connected", "coupled" or "connected" to each other.

In the description of the temporal flow relationship related to the components, the operation method or the manufacturing method, for example, the temporal predecessor relationship such as "after", "after", "after", "before", etc. Alternatively, a case where a flow forward and backward relationship is described may also include a case that is not continuous unless "direct" or "direct" is used.

On the other hand, when a numerical value for a component or its corresponding information (e.g., level, etc.) is mentioned, the numerical value or its corresponding information is related to various factors (e.g., process factors, internal or external impacts, etc.) It can be interpreted as including an error range that may be caused by noise, etc.).

1 is a diagram illustrating an example of a schematic configuration of a display device 100 according to embodiments of the present invention.

Referring to FIG. 1, a display device 100 according to an exemplary embodiment of the present invention is positioned outside an active area A/A and an active area A/A in which a plurality of subpixels SP are disposed. And a display panel 110 including a non-active area N/A. In addition, a gate driving circuit 120, a data driving circuit 130, and a controller 140 for driving various signal lines disposed on the display panel 110 may be included.

In the display panel 110, a plurality of gate lines GL and a plurality of data lines DL are disposed, and a subpixel SP is disposed in a region where the gate line GL and the data line DL intersect. .

The gate driving circuit 120 is controlled by the controller 140 and sequentially outputs scan signals to a plurality of gate lines GL disposed on the display panel 110 to drive timing of the plurality of subpixels SP. Control.

The gate driving circuit 120 may include one or more gate driver integrated circuits (GDIC), and may be located only on one side of the display panel 110 or on both sides according to a driving method. May be.

Each gate driver integrated circuit (GDIC) is connected to a bonding pad of the display panel 110 by a tape automated bonding (TAB) method or a chip on glass (COG) method, or a GIP (Gate In Panel) type and may be directly disposed on the display panel 110, or may be integrated and disposed on the display panel 110 in some cases. In addition, each gate driver integrated circuit (GDIC) may be implemented in a Chip On Film (COF) method mounted on a film connected to the display panel 110.

The data driving circuit 130 receives image data from the controller 140 and converts the image data into an analog data voltage. In addition, the data voltage is output to each data line DL according to a timing when a scan signal is applied through the gate line GL so that each subpixel SP expresses brightness according to the image data.

The data driving circuit 130 may include one or more source driver integrated circuits (SDIC).

Each source driver integrated circuit (SDIC) may include a shift register, a latch circuit, a digital-to-analog converter, an output buffer, and the like.

Each source driver integrated circuit (SDIC) may be connected to a bonding pad of the display panel 110 in a tape automated bonding (TAB) method or a chip on glass (COG) method, or may be directly disposed on the display panel 110. In some cases, it may be integrated and disposed on the display panel 110. In addition, each source driver integrated circuit (SDIC) may be implemented in a chip-on-film (COF) method. In this case, each source driver integrated circuit (SDIC) is mounted on a film connected to the display panel 110 , It may be electrically connected to the display panel 110 through wires on the film.

The controller 140 supplies various control signals to the gate driving circuit 120 and the data driving circuit 130, and controls operations of the gate driving circuit 120 and the data driving circuit 130.

The controller 140 may be mounted on a printed circuit board, a flexible printed circuit, and the like, and may be electrically connected to the gate driving circuit 120 and the data driving circuit 130 through a printed circuit board, a flexible printed circuit, or the like. .

The controller 140 allows the gate driving circuit 120 to output a scan signal according to the timing implemented in each frame, and converts the image data received from the outside according to the data signal format used by the data driving circuit 130 Thus, the converted image data is output to the data driving circuit 130.

The controller 140 externally provides various timing signals including a vertical synchronization signal (VSYNC), a horizontal synchronization signal (HSYNC), an input data enable signal (DE, Data Enable), a clock signal (CLK), and the like, together with image data. Receive from (e.g. host system).

The controller 140 may generate various control signals using various timing signals received from the outside and output them to the gate driving circuit 120 and the data driving circuit 130.

For example, in order to control the gate driving circuit 120, the controller 140 includes a gate start pulse (GSP), a gate shift clock (GSC), and a gate output enable signal (GOE). It outputs various gate control signals (GCS) including Gate Output Enable).

Here, the gate start pulse GSP controls an operation start timing of one or more gate driver integrated circuits GDIC constituting the gate driving circuit 120. The gate shift clock GSC is a clock signal commonly input to one or more gate driver integrated circuits GDIC and controls shift timing of the scan signal. The gate output enable signal GOE specifies timing information of one or more gate driver integrated circuits GDIC.

In addition, in order to control the data driving circuit 130, the controller 140 includes a source start pulse (SSP), a source sampling clock (SSC), and a source output enable signal (SOE, Source). Outputs various data control signals (DCS) including output enable).

Here, the source start pulse SSP controls data sampling start timing of one or more source driver integrated circuits SDIC constituting the data driving circuit 130. The source sampling clock SSC is a clock signal that controls the sampling timing of data in each of the source driver integrated circuits SDIC. The source output enable signal SOE controls the output timing of the data driving circuit 130.

The display device 100 includes a power management integrated circuit that supplies various voltages or currents to the display panel 110, the gate driving circuit 120, the data driving circuit 130, or controls various voltages or currents to be supplied. It may contain more.

Each subpixel SP is defined by the intersection of the gate line GL and the data line DL, and a liquid crystal or a light emitting element may be disposed depending on the type of the display device 100.

2 is a diagram illustrating an example of a cross-sectional structure of a display panel 200 according to embodiments of the present invention. The display panel 200 according to embodiments of the present invention includes a substrate 210, a planarization layer 220, an etch stop layer 230, a first bank layer 240, a first electrode 250, and a second electrode. A bank layer 260, a light emitting layer 270, a second electrode 280, and a first contact hole 290 may be included.

The display panel 200 may include a substrate 210. The type of the substrate 210 is not particularly limited as long as it can form a circuit on one surface, and for example, a glass substrate or a polymer plastic substrate may be used.

A planarization layer 220 may be positioned on the substrate 210. The planarization layer 220 may planarize the substrate 210 on which the circuit is formed.

The planarization layer 220 may include, for example, an organic material. Alternatively, the planarization layer 220 may include an organic material as a main component. That the planarization layer 220 contains an organic material as a main component may mean that the ratio of the organic material to the total weight of the planarization layer 220 is 50% by weight or more.

In FIG. 2, although the planarization layer 220 is illustrated in a single-layer structure, the planarization layer 220 may be configured as a multi-layer, if necessary, as long as the substrate 210 on which the circuit is formed on one surface can be planarized.

An etch stop layer 230 may be positioned on the planarization layer 220. For example, the etch stop layer 230 may be positioned between the planarization layer 220 and the first bank layer 240.

Since the etch stop layer 230 is positioned as described above, it is possible to prevent the planarization layer 220 located under the etch stop layer 230 from being etched by an etch process for patterning the first bank layer 240. have. In addition, since the etch stop layer 230 is located under the first bank layer 240, even if the etch process is performed to form the first opening 241 in the first bank layer 240, the planarization layer 220 ) Can be etched to prevent the occurrence of thickness deviation.

The average thickness of the etch stop layer 230 at the first opening 241 may be thinner than the average thickness at the remaining portions except for the first opening 241. In performing the etch process for forming the first opening 241 of the first bank layer 240 located on the etch stop layer 230, if the etch is performed somewhat excessively within the process error range, the etch The stop layer 230 is also etched so that the portion of the etch stop layer 230 located at the opening of the first bank layer 240 is thinner than the portion of the etch stop layer 230 where the first bank layer 240 is located. Because it can.

The etch stop layer 230 may include, for example, an inorganic material. Alternatively, the etch stop layer 230 may include an inorganic material as a main component.

The etch stop layer 230 may include silicon dioxide (SiO ₂ ). Alternatively, the etch stop layer 230 may include silicon dioxide (SiO2) as a main component. The fact that the etch stop layer 230 contains an inorganic material or silicon dioxide as a main component may mean that the ratio of the inorganic material or silicon dioxide to the total weight of the etch stop layer 230 is 50% by weight or more.

In FIG. 2, although the etch-stop layer 230 is illustrated in a single-layer structure, the etch-stop layer 230 is formed by etching the planarization layer 220 by an etch process performed during the patterning process of the first bank layer 240. It can be configured in multiple layers as needed.

The first bank layer 240 may be positioned on the etch stop layer 230. The first bank layer 240 may include a first opening 241, a first inclined region 242, and a first flat region 243.

The first opening 241 may be an opening for the etch stop layer 230. Accordingly, a part of the etch stop layer 230 is not covered by the first bank layer 240 and may be exposed through the first opening 241.

The first inclined region 242 may surround the first opening 241. In addition, the first inclined region 242 may be connected to the first flat region 243. Accordingly, the first opening 241 may be positioned relatively lower than the first flat region 243. In addition, the first inclined region 242 may connect the first opening 241 to the first flat region 243 positioned relatively higher than the first opening 241.

The first bank layer 240 may include an organic material. Alternatively, the first bank layer 240 may include an organic material as a main component. The fact that the first bank layer 240 contains an organic material as a major component may mean that the ratio of the organic material to the total weight of the first bank layer 240 is 50% by weight or more.

The first bank layer 240 may have a high etch selectivity with respect to the etch stop layer 230. The etch selectivity may be, for example, an oxygen ashing (O ₂ ashing) dry etch selectivity. When the etch selectivity of the first bank layer 240 with respect to the etch stop layer 230 is the same as described above, dry etching is performed to form the first opening 241 in the first bank layer 240. 1 It is possible to prevent the planarization layer 220 located under the opening 241 from being etched, and reduce a thickness variation of the planarization layer 220 located under the first opening 241.

The first electrode may be positioned above the etch stop layer 230 and above the first bank layer 240. For example, the first electrode 250 may be positioned above the etch stop layer 230 exposed through the first opening 241 and above the first inclined region 242 of the first bank layer 240. In addition, the first electrode 250 may be formed to extend to an upper portion of the first flat region 243 of the first bank layer 240.

The first electrode 250 may include a reflective layer capable of reflecting light emitted from the light emitting layer 270. Since the first electrode 250 includes a reflective layer, light emitted from the light emitting layer 270 can be effectively extracted to the outside of the display panel 200.

The first electrode 250 may include a second flat area 251, a second inclined area 252, and a third flat area 253. The second flat region 251 may correspond to a portion of the first electrode 250 formed on the etch stop layer 230 exposed by the first opening 241. The second inclined region 252 may correspond to a portion of the first electrode 250 formed on the first inclined region 242 of the first bank layer 240. The third flat area 253 may correspond to a portion of the first electrode 250 that is formed on the first flat area 243 of the first bank layer 240.

A portion of the second inclined region 252 of the first electrode 250 may be positioned higher than the highest point of the second flat region 251 of the first electrode 250. Since the second inclined area 252 corresponds to a portion formed on the first inclined area 242 of the first bank layer 240 of the first electrode 250, the second inclined area 252 is also It may be located surrounding the region 251. Accordingly, the first electrode 250 may have a shape surrounding the second flat area 251 while a part of the second inclined area 252 is positioned higher than the highest point of the second flat area 251.

In addition, a part of the second inclined region 252 of the first electrode 250 may be positioned higher than the lowest point of the emission layer 270. Accordingly, the first electrode 250 may have a shape in which a part of the second inclined area 252 is positioned higher than the lowest point of the emission layer 270, and the second inclined area 252 surrounds the emission layer 270. . When the first electrode 250 has the above-described shape, light emitted from the emission layer 270 may be effectively reflected and extracted outside the display panel.

The second bank layer 260 may be located on the first electrode 250. The second bank layer 260 may include a second opening 261 for the first electrode 250. Accordingly, a part of the first electrode 250 is partially covered by the second bank layer 260, and the other part of the first electrode 250 passes through the second opening 261 of the second bank layer 260. It can be exposed.

In addition, the second bank layer 260 may further include a third inclined region 262 and a fourth flat region 263. The third sloped region 262 of the second bank layer 260 may correspond to a portion formed on the second sloped region 252 of the first electrode 250. The fourth flat region 263 of the second bank layer 260 may correspond to a portion formed on the first flat region 243 of the first bank layer 240.

The third inclined region 262 may surround the second opening 261. In addition, the third inclined region 262 may be connected to the fourth flat region 263. Accordingly, the second opening 261 may be positioned relatively lower than the fourth flat region 263. In addition, the third inclined region 262 may connect the second opening 261 to the fourth flat region 263 positioned relatively higher than the second opening 261.

A part of the third sloped region 262 of the second bank layer 260 may be positioned lower than the highest point of the fourth flat region 263 of the second bank layer 260. Accordingly, in the second bank layer 260, a part of the third inclined area 262 is positioned lower than the highest point of the fourth flat area 263, while the third inclined area 262 surrounds the second opening 261. Can have a shape.

The emission layer 270 may be positioned on the first electrode 250. In addition, the emission layer 270 may be positioned on the first electrode 250 exposed through the second opening 261 of the second bank layer 260.

The first contact hole 290 may pass through the planarization layer 220, the etch stop layer 230, and the first bank layer 240. In addition, the first electrode 250 may directly contact the planarization layer 220 in the first contact hole 290. In addition, the etch stop layer 230 may not be located on the planarization layer 220 in the first contact hole 290.

Referring to FIG. 2, the first electrode 250 directly contacts the planarization layer 220 exposed by the first contact hole 290, and the etch stop layer 230 forms the first contact hole 290. It may not be located on an inclined surface of the constituting planarization layer 220.

In embodiments of the present invention, in order to prevent the planarization layer 220 from being etched during the patterning process of the first bank layer 240, the etch stop layer 230 is formed of the planarization layer 220 and the first bank layer 240. Because it is located between, you can have this structure.

In the first contact hole 290, the first electrode 250 may directly contact the first bank layer 240, the etch stop layer 230, and the planarization layer 220. Referring to FIG. 2, the first electrode 250 is on the slope of the first bank layer 240 constituting the first contact hole 290, the slope of the etch stop layer 230, and the slope of the planarization layer 220. Can be located in Accordingly, the first electrode 250 may directly contact the first bank layer 240, the etch stop layer 230, and the planarization layer 220 in the first contact hole 290.

The first contact hole 290 may penetrate the first flat region 243 of the first bank layer 240. Also, the first contact hole 290 may be located in the first flat region 243.

The first contact hole 290 may be located in the third flat region 253 of the first electrode 250. Referring to FIG. 2, a first contact hole 290 is located in a third flat region 253 of the first electrode 250, and a part of the third flat region 253 of the first electrode 250 is a first contact. It may be electrically connected to a circuit such as a transistor formed on the substrate 210 through the hole 290.

The second electrode 280 may be positioned above the emission layer 270 and above the second bank layer 260. Referring to FIG. 2, the second electrode 280 may be formed above the emission layer 270 and extending to the second bank layer 260.

The second electrode 280 may include a fifth flat area 281, a fourth inclined area 282, and a sixth flat area 283.

The fifth flat region 281 may correspond to a portion of the second electrode 280 positioned above the emission layer 270 while being positioned in the second opening 261. The fourth inclined region 282 may correspond to a portion of the second electrode 280 positioned above the third inclined region 262 of the second bank layer 260. The sixth flat region 283 may correspond to a portion of the second electrode 280 positioned above the fourth flat region 263 of the second bank layer 260. Accordingly, in the second electrode 280, the fifth flat area 281 is positioned relatively lower than the sixth flat area 283, and the fifth flat area 281 and the sixth flat area 283 are the fourth inclined areas. It is connected by 282, and the fourth inclined region 282 may have a shape surrounding the fifth flat region 281.

The second electrode 280 may be, for example, a transparent electrode. When the second electrode 280 is a transparent electrode, light emitted from the light emitting layer 270 may be emitted through the second electrode 280.

3 is a cross-sectional view of a display panel 300 according to Comparative Example 1 of the present invention.

The display panel 300 according to Comparative Example 1 may include a substrate 310, a planarization layer 320, a first electrode 250, a bank layer, an emission layer 270, and a second electrode 280.

In the display panel 300 according to Comparative Example 1, unlike the embodiments of the present invention, the first electrode 250 is positioned on the planarization layer 320. Therefore, it does not have a structure of the etch stop layer 230 positioned between the planarization layer 320 and the first bank layer 240, which is a characteristic of the embodiments of the present invention.

A portion of the inclined region of the first electrode 330 of the display panel 300 according to Comparative Example 1 may be positioned higher than the emission layer 350 and surround the emission layer 350. However, the display panel 300 according to Comparative Example 1 has a problem in that it is difficult to increase the angle of the inclined region of the first electrode 330.

4 is a cross-sectional view of a display panel 400 according to Comparative Example 2 of the present invention.

The display panel 400 according to Comparative Example 2 includes a substrate 410, a planarization layer 420, a first bank layer 430, a first electrode 440, a second bank layer 450, and a light emitting layer 460. And a second electrode 470.

In the display panel 400 according to Comparative Example 2, unlike the embodiments of the present invention, the etch stop layer is not positioned between the planarization layer 420 and the first bank layer 430.

A part of the inclined region of the first electrode 440 of the display panel 400 according to Comparative Example 2 may be positioned higher than the emission layer 460 and surround the emission layer 460. However, there is a problem that the display panel 400 according to Comparative Example 2 requires one more mask than the display panel 200 according to embodiments of the present invention.

5 is a diagram for explaining some steps in a method of manufacturing the display panel 300 according to Comparative Example 1.

Referring to FIG. 5, in the method of manufacturing the display panel 300 according to Comparative Example 1, exposing the planarization layer 320 stacked on the substrate 310 using a halftone mask (H/T MSK), exposure It may include developing the formed planarization layer 320 and performing a hard bake on the planarization layer 320.

However, in the display panel 300 of Comparative Example 1, the inclination angle θ2 of the inclined region of the planarization layer 320 after hard baking is performed, after the planarization layer 320 is developed. There is a problem of being smaller than the inclination angle θ1 of the inclined region. This change in the inclination angle is presumed to be caused by reflowing of the planarization layer 320 by a hard bake process performed at a high temperature of 200°C or higher.

In addition, reflowing of the planarization area of the planarization layer 320 is performed by the hard bake process, so that the inclination angle of the inclination area of the planarization layer 320 decreases as well as the planarization area of the planarization layer 320. There is also a problem in that the thickness deviation of is increased.

Referring to FIG. 6, the method of manufacturing the display panel 400 according to Comparative Example 2 may include patterning the planarization layer 420 and patterning the first bank layer 430.

Before patterning the first bank layer 430 including the inclined region, a hard bake process for the planarization layer 420 is performed in the patterning step of the planarization layer 420, so that reflowing of the planarization layer 420 ), the inclination angle of the inclined region of the first bank layer 430 is not affected. In addition, even if the patterning step of the first bank layer 430 includes a hard bake process of the first bank layer 430 including the inclined area, not only the inclined area of the planarization layer 420 but also the planarization layer 420 are planarized. Unlike Comparative Example 1 in which reflowing is performed even in the region, only the first bank layer 430 located on the cured planarization layer 420 undergoes reflowing, so Comparative Example 2 is compared. As compared with Example 1, the degree of reflowing is suppressed, so that the first bank layer 430 having a higher inclination angle than Comparative Example 1 may be formed.

However, since the display panel 400 according to Comparative Example 2 performs the patterning process twice, an additional mask is required than Comparative Example 1, which requires one halftone mask process, resulting in a high manufacturing cost.

7 is a diagram illustrating some steps in a method of manufacturing the display panel 200 according to exemplary embodiments.

Referring to FIG. 7, in a method of manufacturing a display panel 200 according to embodiments of the present invention, a planarization layer 220, an etch stop layer 230, and a first bank layer 240 are formed on a substrate 210. It may include a step, photoresist patterning step, dry etching step, Ÿ‡ etching step, dry etching step, and photoresist strip step.

In the method of manufacturing the display panel 200 according to the embodiments of the present invention, unlike Comparative Example 1, after patterning the photoresist layer, the first bank layer 240 is etched to form the first inclined region 242. Therefore, it is possible to solve the problem that the inclination angle of the first inclined region 242 is lowered during the hard baking process.

In the method of manufacturing the display panel 200 according to the exemplary embodiments, the planarization layer 220 and the first bank layer 240 are hard-baked before the photoresist layer patterning process. Accordingly, since the shape of the planarization layer 220 and the first bank layer 240 is a simple shape that does not have an inclined region during the hard bake process, a problem in which thickness variation due to reflowing increases can be solved.

The upper limit of the thickness variation of the planarization layer 220 may be, for example, 2000 Å or less, 1000 Å or less, 500 Å or less, or 250 Å or less. The lower limit of the thickness variation is not particularly limited because it means that the planarization layer 220 is formed uniformly as the thickness is smaller, but may be, for example, 50 Å or more, 100 Å or more, or 200 Å or more.

The variation in thickness of the planarization layer 220 is, for example, in the portion of the planarization layer 220 that contacts a portion of the etch stop layer 230 exposed by the first opening 241 of the first bank layer 240. Thus, it may mean a difference in height between the highest point and the lowest point.

In addition, in the manufacturing method of the display panel 200 according to the embodiments of the present invention, since the etch stop layer 230 is positioned between the planarization layer 220 and the first bank layer 240, patterning is different from Comparative Example 2. Since the process is only the photoresist layer patterning process, there is an advantage of reducing production cost because it can be manufactured by using a single mask.

8 is a view for explaining that light emitted from the display panel 200 is reflected by the first electrode 250 according to exemplary embodiments.

Referring to FIG. 8, light L emitted from the light emitting layer 270 does not have directivity in a specific direction and is radiated in various directions. Light reaching the second inclined area 252 of the first electrode 250 may be reflected from the second inclined area 252 and extracted to the outside of the display panel 200. Accordingly, the light efficiency of the display panel 200 according to embodiments of the present invention may be improved.

In particular, the display panel according to embodiments of the present invention solves the problem of lowering the inclination angle of the first inclined area 242 due to reflowing occurring in the manufacturing step as described above, Since the inclination angle can be increased, the light efficiency can be further improved.

9 is a partially enlarged view of FIG. 2.

, 제2 뱅크층(260)의 제3 경사영역(262)의 두께가 d, 제1 뱅크층(240)의 제1 경사영역(242)의 높이가 h로 표시되어 있다. 본 발명의 실시예들에 따른 디스플레이 패널(200)은

, d, 또는 h를 조절하여 우수한 광효율을 달성할 수 있다.Referring to FIG. 9, the angle formed by the first inclined region 242 of the first bank layer 240 is

, The thickness of the third inclined region 262 of the second bank layer 260 is denoted by d, and the height of the first inclined region 242 of the first bank layer 240 is denoted by h. Display panel 200 according to embodiments of the present invention

, d, or h can be adjusted to achieve excellent light efficiency.

의 범위의 상한은, 특별히 제한되는 것은 아니며,

가 큰 값을 가질 경우 발광층(270)에서 방출된 빛을 제1 전극(250)이 효과적으로 반사할 수 있어 디스플레이 패널의 광효율이 향상될 수 있다.

The upper limit of the range of is not particularly limited,

When the value is large, the first electrode 250 can effectively reflect the light emitted from the emission layer 270, so that the light efficiency of the display panel can be improved.

를 달성하는 것이 용이하므로, 우수한 광효율을 가질 수 있다.The display panel 200 according to the embodiments of the present invention, as described above,

Since it is easy to achieve, it can have excellent light efficiency.

The range of Θ may be, for example, 45° or more or 60° or more. The upper limit of Θ is not particularly limited, but if Θ is too large, disconnection of the first electrode 250 may occur, and thus, for example, Θ may be 80° or less.

As d is smaller, the second opening 261 can be expanded, and the light path through which the light reflected and extracted from the second inclined region 252 passes through the second bank layer 260 can be reduced. This can be improved.

The lower limit of d is not particularly limited, but, for example, the lower limit of d may be 0.1 μm or more, 0.3 μm or more, or 0.5 μm or more.

As h increases, a portion of the second inclined region 252 of the first electrode 250 that is positioned higher than the emission layer 270 increases, so that a reflection effect by the first electrode 250 may be increased. Therefore, the upper limit of h is not particularly limited, but may be, for example, 10 μm or less or 5 μm or less. In addition, the lower limit of h may be, for example, 0.7 μm or more, 1.2 μm or more, 1.4 μm or more, or 2 μm or more.

h may mean a height difference between the lowest point and the highest point of the first inclined region 242.

및 h를 조절함으로써, 본 발명의 표시패널은 향상된 광효율을 가질 뿐만 아니라, 디스플레이 패널(200)이 시청면(204)에서 제1 발광영역 및 제2 발광영역을 포함할 수 있다.D as above,

By adjusting h and h, not only the display panel of the present invention has improved light efficiency, but the display panel 200 may include a first emission area and a second emission area on the viewing surface 204.

10 is a cross-sectional view of a display panel 200 according to example embodiments.

Referring to FIG. 10, the display panel 200 according to exemplary embodiments of the present invention includes a transistor, an auxiliary electrode, a second contact hole, a capacitor, a pad region, a buffer layer (BUF), an interlayer insulating layer (INF), and a protective layer (PAS). ) Can be included.

The transistor may be formed between the substrate 210 and the planarization layer 220. Accordingly, the planarization layer 220 may planarize the surface of the substrate 210 on which the transistor is formed.

At least a portion of the transistor may overlap the first opening 241 or the second opening 261. The display panel 200 according to the embodiments of the present invention includes a top emission type organic electric device, so that at least a part of the transistor overlaps the first opening 241 or the second opening 261. I can.

The transistor may include at least one terminal connected through the first electrode 250 and the first contact hole 290. Hereinafter, a transistor according to a specific example of the present invention will be described, but the positional relationship of each component of the transistor may follow another method known in the field of the present invention.

The transistor may include a semiconductor layer ACT, a gate insulating layer GI, a gate electrode GATE, a source electrode S, and a drain electrode D.

The semiconductor layer ACT may be formed on the buffer layer BUF.

The gate insulating layer GI is formed on the semiconductor layer ACT, and the gate electrode GATE is formed on the gate insulating layer GI, so that the gate insulating layer GI is formed between the semiconductor layer ACT and the gate electrode GATE. Can be located.

The source electrode S and the drain electrode D may contact one end of the semiconductor layer ACT, respectively, but may be disposed to be spaced apart from each other. The drain electrode D may be connected to the first electrode 250 by the first contact hole 290.

The auxiliary electrode may be formed between the substrate 210 and the planarization layer 220. Accordingly, the planarization layer 220 may planarize the surface of the substrate 210 on which the auxiliary electrode is formed.

The second contact hole may pass through the planarization layer 220, the etch stop layer 230, the first bank layer 240 and the second bank layer 260. Accordingly, the auxiliary electrode may be exposed through the second contact hole.

The second electrode 280 and the auxiliary electrode may be connected through the second contact hole. Since the auxiliary electrode is exposed through the above-described second contact hole, the second electrode 280 positioned on the second bank layer 260 may be connected to the auxiliary electrode.

The auxiliary electrode may be disposed on the interlayer insulating layer INF. In addition, the second contact hole penetrates the passivation layer (PAS), the planarization layer 220, the etch stop layer 230, the first bank layer 240 and the second bank layer 260 to expose the auxiliary electrode AE. can do. The second electrode 280 may be connected to the auxiliary electrode AE through a second contact hole.

For example, when the display panel 200 according to the embodiments of the present invention is a large-area display panel 200, a voltage drop occurs due to the resistance of the second electrode 280, Differences in luminance may occur. However, the auxiliary electrode connected to the second electrode 280 may prevent the above-described voltage drop from occurring.

Meanwhile, although FIG. 10 illustrates a configuration in which one auxiliary electrode is disposed in one subpixel, embodiments of the present invention are not limited thereto. For example, one auxiliary electrode may be disposed per multiple subpixels.

The capacitor may be positioned between the substrate 210 and the planarization layer 220. Accordingly, the planarization layer 220 may planarize the surface of the substrate 210 on which the capacitor is formed.

At least a portion of the capacitor may overlap the first opening 241 or the second opening 261. In the display panel 200 according to the embodiments of the present invention, at least a part of the capacitor may overlap the first opening 241 or the second opening 261 including a top emission type organic electric device. I can.

The capacitor may be located on the buffer layer BUF. The first capacitor electrode C1 may be positioned on the buffer layer BUF. Alternatively, the first capacitor electrode C1 may be disposed on the same layer as the gate electrode GATE.

The second capacitor electrode C2 may be positioned on the interlayer insulating layer INF. Alternatively, the second capacitor electrode C2 may be disposed on the same layer as the source electrode S and the drain electrode D.

The pad area PA may be disposed in a non-active area of the display panel 200. A plurality of pad electrodes P1 and P2 may be disposed in the pad area.

For example, the first pad electrode P1 may be disposed on the plurality of insulating layers BUF and GI disposed in the pad area. An interlayer insulating layer INF exposing a part of the upper surface of the first pad electrode P1 may be disposed on the first pad electrode P1. In addition, a second pad electrode P2 in contact with the first pad electrode P1 may be disposed on the first pad electrode P1 and the interlayer insulating layer INF.

Although not shown in FIG. 10, the second pad electrode P2 may be electrically connected to various circuit films.

11 is a cross-sectional view of a display panel 500 according to example embodiments.

Referring to FIG. 11, the display panel 500 includes a substrate 510, a planarization layer 520, an etch stop layer 530, a first bank layer 540, a first electrode 550, and a second bank layer ( 560, light emitting layer 570, second electrode 580, first contact hole 590, transistor, auxiliary electrode, second contact hole, capacitor, pad region, buffer layer (BUF), interlayer insulating layer (INF) and protection It may include a layer (PAS).

The emission layer 570 may be formed to extend over the third inclined region 562. When the light emitting layer 570 is formed by extending to the upper portion of the third inclined region 562 of the second bank layer 560, it is easy to form the light emitting layer 570 over the entire area of the second opening 561 , There is an advantage that the aperture ratio of the subpixel can be maximized.

In addition, the emission layer 570 may be formed by extending to the upper portion of the fourth flat region 563 of the second bank layer 560. When the light emitting layer 570 is formed to extend to the top of the fourth flat region 563, for example, in the process of forming the light emitting layer 570, a mask process using a fine metal mask can be omitted. , There is an advantage in that the process is simpler and it is easy to manufacture the large display panel 500.

The thickness of a portion of the emission layer 570 formed to extend to the upper portion of the second inclined region 552 may be thinner than that of another portion of the emission layer 570 formed in the second opening 561.

11, a substrate 510, a planarization layer 520, an etch stop layer 530, a first bank layer 540, a first electrode 550, a second bank layer 560, and a second electrode ( 580), the first contact hole 590, the transistor, the auxiliary electrode, the second contact hole, the capacitor, the pad region, the buffer layer (BUF), the interlayer insulating layer (INF), and the protective layer (PAS) are described above. Since it is the same as described in the embodiments, it will be omitted.

12 is a partially enlarged view of FIG. 11. Referring to FIG. 12, the thickness of a portion of the emission layer 570 formed extending to the upper portion of the third inclined region 562 is t2, and the emission layer 570 formed in the second opening 561 of the second bank layer 560 The thickness of the other part of is denoted as t1. In the display panel 500 according to the exemplary embodiments illustrated in FIG. 12, t2 may be thinner than t1. This difference in thickness is presumed to occur as a result of forming the light emitting layer 570 on the second bank layer 560 where the inclined region exists by a deposition process or the like.

The display panels 200 and 500 according to embodiments of the present invention include the above-described substrates 210 and 510, planarization layers 220 and 520, etch stop layers 230 and 530, and a first bank layer 240, 540, first electrodes 250 and 550, second bank layers 260 and 560, emission layers 270 and 570, first contact holes 590, second electrodes 280 and 580, first emission region 201 and a second emission region 202 may be included.

The first emission region may be a region in which light passing through the fifth flat region 281 of the second electrodes 280 and 580 from the emission layers 270 and 570 is emitted. Since the light emitting layers 270 and 570 and the first electrodes 250 and 550 are sequentially positioned under the fifth flat region 281 of the second electrodes 280 and 580, light emitted from the light emitting layers 270 and 570 It may be discharged through the fifth flat region 281.

In the second emission region, light reflected from the second inclined region 252 may be emitted. As described above, some of the light emitted from the emission layers 270 and 570 may be reflected on a part of the second inclined region 252 of the first electrodes 250 and 550 positioned higher than the emission layers 270 and 570, and The generated light may be extracted outside the display panels 200 and 500.

Light emitted from the first light emitting area and light emitted from the second light emitting area have different optical paths. The light emitted from the second emission region is reflected from the second sloped region 252 of the first electrodes 250 and 550 through the second bank layers 260 and 560, unlike the light emitted from the first emission region. It is extracted to the outside. Accordingly, a color coordinate of light emitted from the first emission region and a color coordinate of light emitted from the second emission region may be different from each other.

13 is a plan view as viewed from the viewing surface 204 of the display panels 200 and 500 according to exemplary embodiments.

The first emission area may form a main emission area of the subpixel on the viewing surface 204. The main light-emitting area of the subpixel may mean a light-emitting area occupying a relatively large area among areas in which light is emitted from the subpixel when the subpixel in which light is emitted from the viewing surface 204 is observed. The first emission area may correspond to the main emission area of the subpixel within one subpixel of the viewing surface 204. The first emission area refers to a plurality of spaced apart emission areas observed in the entire active area of the display panel, but the main emission area of the subpixel may refer to a part of the first emission area included in one subpixel area. .

The second emission area may form an auxiliary emission area of the subpixel on the viewing surface 204. The auxiliary light-emitting area of the sub-pixel may mean a light-emitting area occupying a relatively small area among areas in which light is emitted from the sub-pixel when the sub-pixel in which light is emitted from the viewing surface 204 is observed. The second emission area may substantially correspond to an auxiliary emission area of the subpixel within one subpixel of the viewing surface 204. The second emission area refers to a plurality of spaced apart emission areas observed in the entire active area of the display panel, but the auxiliary emission area of the subpixel may refer to a part of the second emission area included in one subpixel area. .

On the viewing surface 204, the auxiliary light emitting area of the subpixel may be located around the main light emitting area of the subpixel. Light emitted from the light emitting layer 270 exposed through the second opening 261 located in the center of the subpixel in the main light emitting area is emitted through the fifth flat area 281 of the second electrode 280. The light may be emitted and reflected from the second inclined region 252 surrounding the fifth flat region 281 in the auxiliary emission region.

In the main emission area, light emitted from the emission layer 270 exposed through the second opening 261 is emitted, and in the auxiliary emission area, light reflected from the second inclined area 252 of the first electrode 250 is emitted. Accordingly, the positions of the main emission region and the sub emission region may be determined according to the position of the second opening 261 and the position of the second inclined region 252. Since the second inclined region 252 surrounds the second opening 261, the main emission region may be located at the center of the subpixel and the auxiliary emission region may be located around the main emission region.

The shape of the main emission area may correspond to the shape of the second opening 261 in the viewing surface 204.

For example, when the second opening 261 has an octagonal shape, the shape of the main light emitting region may also have an octagonal shape.

The shape of the auxiliary light-emitting area may correspond to the shape of the main light-emitting area of the subpixel on the viewing surface 204 or may have a shape in which a portion of the frame is cut off.

Referring to FIG. 13, in one subpixel, an auxiliary light emitting area may have a continuous shape, or a subpixel may have a shape in which the auxiliary light emitting area is cut off.

14 is a plan view of a display panel according to example embodiments. 14 is a diagram illustrating layers positioned above the second bank layers 260 and 560 in the display panel according to the exemplary embodiments shown in FIG. 2 omitted.

Referring to FIG. 14, it can be seen that the third inclined region 262 surrounds and is positioned around the second opening 261 of the second bank layer 260. Some of the light emitted from the emission layer 270 is not reflected from the second inclined area 252 and is emitted through the second opening 261, thereby forming a main emission area. Another part of the light emitted from the emission layer is reflected and emitted from the second inclined area 252 located under the third inclined area 262. Accordingly, a part of the second light emitting area from which light reflected from the second inclined area 252 is emitted may not be located above the second opening 261. In addition, a portion of the second light-emitting area from which light reflected from the second inclined area 252 is emitted may be positioned above the third inclined area 262 or above the fourth flat area 263.

The above description is merely illustrative of the technical idea of the present invention, and those of ordinary skill in the art to which the present invention pertains will be able to make various modifications and variations without departing from the essential characteristics of the present invention. In addition, since the embodiments disclosed in the present invention are not intended to limit the technical idea of the present invention, but are intended to describe the technical idea, the scope of the technical idea of the present invention is not limited by these embodiments. The scope of protection of the present invention should be interpreted by the claims below, and all technical ideas within the scope equivalent thereto should be construed as being included in the scope of the present invention.

100: display device
110: display panel
120: gate driving circuit
130: data driving circuit
140: controller
200, 500: display panel
201: first emission area
202: second light emitting region
203: subpixel
204: viewing surface
210, 510: substrate
211, 511: transistor
212, 512: auxiliary electrode
213, 513: capacitor
220, 520: planarization layer
230, 530: etch stop layer
240, 540: first bank layer
241: first opening
242: first inclined region
243: first flat area
250, 550: first electrode
251: second flat area
252: second inclined region
253: third flat area
260, 560: second bank layer
261: second opening
262, 562: third slope area
263: fourth flat area
270: light-emitting layer
280: second electrode
281: fifth flat area
282: fourth inclined region
283: sixth flat area
290: first contact hole

Claims (20)

Board;
A planarization layer on the substrate;
An etch stop layer positioned on the planarization layer;
A first bank layer disposed on the etch stop layer and including a first opening for the etch stop layer, a first inclined area surrounding the first opening, and a first flat area connected to the first inclined area;
A first electrode positioned above the etch stop layer exposed through the first opening and above the first inclined region of the first bank layer;
The second bank layer disposed on the first electrode and including a second opening for the first electrode;
An emission layer positioned on the first electrode exposed through the second opening;
A first contact hole penetrating the planarization layer, the etch stop layer, and the first bank layer; And
A second electrode positioned on the emission layer and on the second bank layer; and
The display panel in which the first electrode directly contacts the planarization layer through the first contact hole.
The method of claim 1,
The etch stop layer is a display panel in which the average thickness at the first opening is thinner than the average thickness at the remaining portions except for the first opening.
The method of claim 1,
The etch stop layer is a display panel containing silicon dioxide (SiO ₂ ).
The method of claim 1,
The etch stop layer is not positioned on the planarization layer in the first contact hole.
The method of claim 4,
The first electrode directly contacts the first bank layer, the etch stop layer, and the planarization layer through the first contact hole.
The method of claim 1,
Formed between the substrate and the planarization layer,
At least a portion overlaps the first opening or the second opening,
A display panel including a transistor including at least one terminal connected to the first electrode and the first contact hole.
The method of claim 1,
An auxiliary electrode formed between the substrate and the planarization layer;
A second contact hole penetrating the planarization layer, the etch stop layer, the first bank layer, and the second bank layer,
The display panel to which the second electrode and the auxiliary electrode are connected through the second contact hole.
The method of claim 1,
A display panel including a capacitor positioned between the substrate and the planarization layer and at least partially overlapping the first opening or the second opening.
The method of claim 1,
The planarization layer has a thickness variation of 2000 Å or less.
The method of claim 1,
The first contact hole penetrates the first flat area.
The method of claim 1,
The first electrode includes a second flat region, a second slope region, and a third flat region,
A display panel in which a portion of the second inclined region is positioned higher than the highest point of the second flat region.
The method of claim 11,
A display panel in which a portion of the second inclined region is positioned higher than the lowest point of the emission layer.
The method of claim 11,
The first contact hole is a display panel located in a third flat area.
The method of claim 1,
The second bank layer includes a third inclined region and a fourth flat region,
The third inclined region connects the second opening and the fourth flat region,
A display panel in which a portion of the third inclined region is positioned lower than a maximum point of the fourth flat region.
The method of claim 11,
The emission layer is formed to extend to an upper portion of the third inclined region,
A display panel in which a thickness of a portion of the emission layer formed extending to an upper portion of the third inclined region is thinner than that of another portion of the emission layer formed in the second opening.
Board;
A planarization layer on the substrate;
An etch stop layer positioned on the planarization layer;
A first bank layer disposed on the etch stop layer and including a first opening for the etch stop layer, a first inclined area surrounding the first opening, and a first flat area connected to the first inclined area;
A first electrode positioned above the etch stop layer and above the first bank layer and including a second inclined region;
A second bank layer positioned on the first electrode and including a second opening for the first electrode;
A light-emitting layer on the first electrode;
A first contact hole penetrating the planarization layer, the etch stop layer, and the first bank layer;
A second electrode positioned above the emission layer and above the second bank layer and including a fifth flat region positioned in the second opening;
A first light-emitting area through which light passing through the fifth flat area of the second electrode is emitted from the light-emitting layer; And
And a second light-emitting area from which light reflected from the second inclined area is emitted,
The display panel in which the first electrode directly contacts the planarization layer through the first contact hole.
The method of claim 16,
A display panel in which a part of the second emission area is not positioned above the second opening.
The method of claim 16,
The first emission area forms a main emission area of a sub-pixel on the viewing surface,
The second emission area forms an auxiliary emission area of the sub-pixel on the viewing surface,
A display panel in which an auxiliary light emitting area of the subpixel is located around a main light emitting area of the subpixel on the viewing surface.
The method of claim 18,
The main light emitting area of the subpixel corresponds to the shape of the second opening in the viewing surface,
The auxiliary light emitting area of the sub-pixel corresponds to a shape of an edge of the main light emitting area of the sub-pixel on the viewing surface, or a portion of the edge is cut off.
The method of claim 16,
A display panel in which color coordinates of light emitted from the first emission area and color coordinates of light emitted from the second emission area are different from each other.

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