KR20210002170A - Display device - Google Patents

Abstract

According to an embodiment of the present invention, a display device includes: a substrate; a metal layer disposed on the substrate; a first conductive layer including a lower pattern disposed on the metal layer; an active layer disposed on the first conductive layer; a second conductive layer disposed on the active layer and including a first gate electrode; a pixel electrode disposed on the second conductive layer; and an emission layer and a common electrode disposed on the pixel electrode. According to the present invention, resistance to a predetermined signal is reduced through the metal layer while maintaining the thickness of the lower pattern below a certain level.

Description

Display device {DISPLAY DEVICE}

The present disclosure relates to a display device.

A display device is a device that displays an image, and recently, a light emitting diode display has been attracting attention as a self-luminous display device.

The light emitting display device has a self-luminous characteristic, and unlike a liquid crystal display device, since it does not require a separate light source, thickness and weight can be reduced. In addition, the light emitting display device exhibits high quality characteristics such as low power consumption, high luminance, and high reaction speed.

In general, a light emitting display device includes a plurality of pixels, and each pixel includes a plurality of transistors and a light emitting element. The plurality of transistors are connected to the signal line and can transmit driving current to the light emitting device. The transistor may include an active pattern including a channel region and a conductive region.

The light emitting device includes an anode and a cathode, and the anode is connected to a transistor of a pixel to receive a driving current.

Embodiments provide a display device with improved image quality by reducing resistance to a signal through a metal layer while maintaining the thickness of a lower pattern below a certain level.

The display device according to an exemplary embodiment includes a substrate, a metal layer disposed on the substrate, a first conductive layer including a lower pattern disposed on the metal layer, an active layer disposed on the first conductive layer, and a first conductive layer disposed on the active layer. And a second conductive layer including one gate electrode, a pixel electrode disposed on the second conductive layer, a light emitting layer disposed on the pixel electrode, and a common electrode.

The metal layer may overlap the entire surface of the substrate.

The metal layer may include an opening overlapping the active layer.

A third conductive layer disposed between the second conductive layer and the pixel electrode and including a common voltage line, a driving voltage line, and a data line may be further included.

The metal layer may include at least one of a first voltage metal layer connected to the driving voltage line and a second voltage metal layer connected to the common voltage line.

The metal layer may include a first voltage metal layer and the second voltage metal layer, and the first voltage metal layer and the second voltage metal layer may be spaced apart from each other.

The first voltage metal layer and the second voltage metal layer may include openings overlapping the active layer.

The data line includes a first data line, a second data line, and a third data line, and the metal layer includes a first sub metal layer connected to the first data line, a second sub metal layer connected to the second data line, and It may include at least one of the third sub metal layers connected to the third data line.

The metal layer includes a first sub metal layer, the second sub metal layer, and the third sub metal layer, and the first sub metal layer, the second sub metal layer, and the third sub metal layer include an opening overlapping the active layer. can do.

The first sub-metal layer, the second sub-metal layer, and the third sub-metal layer may be spaced apart from each other.

The display device according to an exemplary embodiment includes a substrate, a metal layer disposed on the substrate, a first conductive layer including a lower pattern disposed on the metal layer, an active layer disposed on the first conductive layer, and a first conductive layer disposed on the active layer. A second conductive layer including one gate electrode, a pixel electrode disposed on the second conductive layer, a light emitting layer disposed on the pixel electrode, and a common electrode, and the thickness of the metal layer is about 6,000 angstroms to about 10,000 angstroms.

According to embodiments, a display device with improved image quality may be provided by reducing resistance to signals through a metal layer while maintaining a thickness of a lower pattern below a certain level.

1 is a circuit diagram of one pixel of a display device according to an exemplary embodiment of the present invention.
2 is a plan layout diagram of a plurality of pixels of a display device according to an exemplary embodiment of the present invention.
3 is a plan layout view of a pixel electrode layer and a plurality of data lines of a display device according to an exemplary embodiment of the present invention.
FIG. 4 is a cross-sectional view of the display device illustrated in FIG. 2 taken along line IVa-IVb.
5 is a plan layout view of a plurality of pixels of a display device according to an exemplary embodiment of the present invention.
6A is a plan layout view of a plurality of pixels of a display device according to an exemplary embodiment, and FIG. 6B is a cross-sectional view of a partial area of FIG. 6A.
7 is a plan layout view of a plurality of pixels of a display device according to an exemplary embodiment of the present invention.
8 is a plan layout view of a plurality of pixels of a display device according to an exemplary embodiment of the present invention.
9 is a cross-sectional view of the display device shown in FIG. 8 taken along lines XIIIa-XIIIb.
10 is a plan layout view of a plurality of pixels of a display device according to an exemplary embodiment of the present invention.
11 is a plan layout view of a plurality of pixels of a display device according to an exemplary embodiment.
12 is a plan layout diagram of a plurality of pixels of a display device according to an exemplary embodiment of the present invention.
13 is a plan layout diagram of a plurality of pixels of a display device according to an exemplary embodiment of the present invention.
14 is a plan layout view of a plurality of pixels of a display device according to an exemplary embodiment of the present invention.
15 is a cross-sectional view of a plurality of pixels of a display device according to an exemplary embodiment of the present invention.

Hereinafter, various embodiments of the present invention will be described in detail with reference to the accompanying drawings so that those of ordinary skill in the art may easily implement the present invention. The present invention may be implemented in various different forms and is not limited to the embodiments described herein.

In order to clearly describe the present invention, parts irrelevant to the description have been omitted, and the same reference numerals are assigned to the same or similar components throughout the specification.

In addition, the size and thickness of each component shown in the drawings are arbitrarily shown for convenience of description, so the present invention is not necessarily limited to the illustrated bar. In the drawings, the thicknesses are enlarged to clearly express various layers and regions. And in the drawings, for convenience of description, the thickness of some layers and regions is exaggerated.

In addition, when a part such as a layer, film, region, plate, etc. is said to be "on" or "on" another part, this includes not only "directly over" another part, but also a case where another part is in the middle. . Conversely, when one part is "directly above" another part, it means that there is no other part in the middle. In addition, to be "on" or "on" the reference part means that it is located above or below the reference part, and does not necessarily mean that it is located "above" or "on" the direction opposite to the gravity. .

In addition, throughout the specification, when a part "includes" a certain component, it means that other components may be further included rather than excluding other components unless otherwise stated.

In addition, throughout the specification, when referred to as "on a plane", it means when the target portion is viewed from above, and when referred to as "cross-sectional view", it means when the cross-section of the target portion vertically cut is viewed from the side.

Throughout the specification, a plan view refers to a view that observes a plane parallel to two directions that intersect each other (for example, the first direction (DR1) and the second direction (DR2)). Also referred to as an image), the cross-sectional view is in a direction perpendicular to a plane parallel to the first direction DR1 and the second direction DR2 (for example, the third direction DR3). It means a view to observe the cut side. In addition, when two components overlap, unless otherwise stated, it means that the two components overlap in the third direction DR3 (eg, in a direction perpendicular to the upper surface of the substrate).

Hereinafter, one pixel of a display device according to an exemplary embodiment will be described with reference to FIG. 1. 1 is a circuit diagram of one pixel PX of a display device according to an exemplary embodiment of the present invention.

The display device according to the exemplary embodiment of the present invention includes a plurality of pixels PX, and one pixel PX includes a plurality of transistors T1, T2, T3, a capacitor Cst, and at least one light emitting device. It may include a light emitting diode (ED). In this embodiment, an example in which one pixel PX includes one light emitting diode ED will be mainly described.

The plurality of transistors T1, T2, and T3 include a first transistor T1, a second transistor T2, and a third transistor T3. The source electrode and the drain electrode, which will be described below, are used to distinguish between two electrodes positioned on both sides of the channel of each of the transistors T1, T2, and T3, and the terms may be interchanged with each other.

The gate electrode G1 of the first transistor T1 is connected to one end of the capacitor Cst, and the source electrode S1 of the first transistor T1 is connected to a driving voltage line that transfers the driving voltage ELVDD. In addition, the drain electrode D1 of the first transistor T1 is connected to the anode of the light emitting diode ED and the other end of the capacitor Cst. The first transistor T1 may receive the data voltage DAT according to the switching operation of the second transistor T2 and supply a driving current to the light emitting diode ED according to the voltage stored in the capacitor Cst.

The gate electrode G2 of the second transistor T2 is connected to the first scan line transmitting the first scan signal SC, and the source electrode S2 of the second transistor T2 is the data voltage DAT or It is connected to a data line capable of transmitting a reference voltage, and the drain electrode D2 of the second transistor T2 is connected to one end of the capacitor Cst and the gate electrode G1 of the first transistor T1. The second transistor T2 is turned on according to the first scan signal SC to transfer the reference voltage or the data voltage DAT to the gate electrode G1 of the first transistor T1 and one end of the capacitor Cst. .

The gate electrode G3 of the third transistor T3 is connected to a second scan line that transmits the second scan signal SS, and the source electrode S3 of the third transistor T3 is the other end of the capacitor Cst. , The drain electrode D1 of the first transistor T1 and the anode of the light emitting diode ED are connected, and the drain electrode D3 of the third transistor T3 is connected to an initialization voltage line transmitting the initialization voltage INIT. It is connected. The third transistor T3 is turned on according to the second scan signal SS, and transmits the initialization voltage INIT to the anode of the LED ED and the other end of the capacitor Cst to provide the voltage of the anode of the LED ED. Can be initialized.

One end of the capacitor Cst is connected to the gate electrode G1 of the first transistor T1, and the other end is connected to the source electrode S3 of the third transistor T3 and the anode of the light emitting diode ED. . The cathode of the light emitting diode ED is connected to a common voltage line transmitting a common voltage ELVSS.

The light emitting diode ED may emit light having a luminance according to a driving current generated by the first transistor T1.

An example of the operation of the circuit shown in Fig. 1, in particular, an example of the operation during one frame will be described. Here, a case where the transistors T1, T2, and T3 are N-type channel transistors is described as an example, but the present invention is not limited thereto.

When one frame starts, a high-level first scan signal SC and a high-level second scan signal SS are supplied during an initialization period to turn on the second transistor T2 and the third transistor T3. The reference voltage from the data line is supplied to the gate electrode G1 of the first transistor T1 and one end of the capacitor Cst through the turned-on second transistor T2, and through the turned-on third transistor T3. The initialization voltage INIT is supplied to the drain electrode D1 of the first transistor T1 and the anode of the light emitting diode ED. Accordingly, during the initialization period, the drain electrode D1 of the first transistor T1 and the anode of the light emitting diode ED are initialized to the initialization voltage INIT. At this time, the difference voltage between the reference voltage and the initialization voltage INIT is stored in the capacitor Cst.

Next, when the second scan signal SS reaches the low level while the high level first scan signal SC is maintained during the sensing period, the second transistor T2 maintains a turn-on state and the third transistor T3 ) Is turned off. The gate electrode G1 of the first transistor T1 and one end of the capacitor Cst maintain the reference voltage through the turned-on second transistor T2, and the first transistor through the turned-off third transistor T3. The drain electrode D1 of (T1) and the anode of the light emitting diode ED are disconnected from the initialization voltage INIT. Accordingly, the first transistor T1 is turned off when a current flows from the source electrode S1 to the drain electrode D1 and the voltage of the drain electrode D1 becomes “reference voltage-Vth”. Vth represents the threshold voltage of the first transistor T1. At this time, the voltage difference between the gate electrode G1 and the drain electrode D1 of the first transistor T1 is stored in the capacitor Cst, and sensing of the threshold voltage Vth of the first transistor T1 is completed. By generating a compensated data signal by reflecting the characteristic information sensed during the sensing period, a characteristic variation of the first transistor T1, which may vary for each pixel, can be externally compensated.

Next, when the high level first scan signal SC is supplied and the low level second scan signal SS is supplied during the data input period, the second transistor T2 is turned on and the third transistor T3 is turned on. Is off. The data voltage DAT from the data line is supplied to the gate electrode G1 of the first transistor T1 and one end of the capacitor Cst through the turned-on second transistor T2. In this case, the drain electrode D1 of the first transistor T1 and the anode of the light emitting diode ED may maintain the potential in the sensing period substantially as it is by the first transistor T1 in a turned-off state.

Next, the first transistor T1 turned on by the data voltage DAT transmitted to the gate electrode G1 in the emission period generates a driving current according to the data voltage DAT, and the light emitting diode ( ED) can emit light.

Hereinafter, a detailed structure of a display device according to an exemplary embodiment will be described with reference to FIGS. 2 to 4 along with FIG. 1. 2 is a plan layout view of a plurality of pixels PX1, PX2, and PX3 of a display device according to an exemplary embodiment, and FIG. 3 is a pixel electrode layer and a plurality of data of a display device according to an exemplary embodiment of the present invention. A plan layout view of a line, and FIG. 4 is a cross-sectional view of the display device of FIG. 2 taken along line IVa-IVb.

Here, each of the plurality of pixels PX1, PX2, PX3 refers to a portion or region in which a plurality of transistors T1, T2, T3 and a capacitor Cst are formed among the components included in the one pixel PX described above. I can.

The display device according to an exemplary embodiment may include a substrate 110. The substrate 110 may include an insulating material such as glass or plastic, and may have flexibility.

A metal layer 111 may be positioned on the substrate 110. The metal layer 111 according to an embodiment may overlap the entire surface of the substrate 110.

The metal layer 111 is copper (Cu), aluminum (Al), magnesium (Mg), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), It may contain at least one of metals such as iridium (Ir), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), tantalum (Ta), and alloys thereof, or may contain a material similar to a metal. have. The metal layer 111 may include a single layer or multiple layers.

The thickness of the metal layer 111 may be about 6,000 angstroms to about 10,000 angstroms. The metal layer 111 may have a fairly thick thickness. As the thickness of the metal layer 111 increases, the performance of the transistor included in the pixel may be improved, thereby increasing the image quality. Even when the thickness of the metal layer 111 is increased, a step due to the metal layer 111 does not occur, so that other conductive layers may be easily formed and reliability may be improved.

An insulating layer 112 may be positioned on the metal layer 111. The insulating layer 112 may include an inorganic insulating material, an organic insulating material, or both an inorganic insulating material and an organic insulating material. Formation of capacitance between the metal layer 111 and another conductive layer may be controlled through the insulating layer 112.

Next, first conductive layers 115 and 170a including the lower pattern 115 and the horizontal common voltage line 170a may be positioned on the insulating layer 112. Each lower pattern 115 may be positioned in each of the pixels PX1, PX2, and PX3. The horizontal common voltage line 170a may extend substantially in the first direction DR1. The lower pattern 115 may include various conductive metals or semiconductor materials having conductive properties equivalent thereto.

A buffer layer 120, which is an insulating layer, may be positioned on the first conductive layers 115 and 170a.

An active layer including a plurality of active patterns 130a, 130b, and 130c may be positioned on the buffer layer 120. The active patterns 130a, 130b, and 130c positioned in each of the pixels PX1, PX2, and PX3 include channel regions 134a, 134b, and 134c forming channels of each of the plurality of transistors T1, T2, and T3 described above, and A conductive region connected thereto may be included. The conductive regions of each of the active patterns 130a, 130b, and 130c may include source regions 133a, 133b, 133c and drain regions 135a, 135b, and 135c of each of the transistors T1, T2, and T3.

The plurality of active patterns 130a, 130b, and 130c positioned in each of the pixels PX1, PX2, and PX3 may be spaced apart from each other, but are not limited thereto. For example, the active pattern 130a and the active pattern 130c may be connected to each other. 2 illustrates an example in which the active pattern 130a and the active pattern 130c are separated from each other.

The active layer may include a semiconductor material such as amorphous silicon, polycrystalline silicon, or an oxide semiconductor.

An insulating pattern 144 as a first insulating layer may be positioned on the active layer. The insulating pattern 144 overlaps the channel regions 134a, 134b, and 134c of the active patterns 130a, 130b, and 130c and may be positioned on the channel regions 134a, 134b, and 134c. The insulating pattern 144 may not substantially overlap the conductive regions of the active patterns 130a, 130b, and 130c.

Second conductive layers 151, 152, 155, 154b and 154c may be positioned on the insulating pattern 144.

The second conductive layers 151, 152, 155, 154b, and 154c include a first scan line 151 capable of transmitting the first scan signal SC described above, and a first scan line 151 capable of transmitting the second scan signal SS. A second scan line 152, a driving gate electrode 155, a second gate electrode 154b, and a third gate electrode 154c may be included. In the above-described circuit diagram, the gate electrode G1, the gate electrode G2, and the gate electrode G3 are each of the first gate electrode 154a, the second gate electrode 154b, and the driving gate electrode 155 included therein. It may correspond to the third gate electrode 154c. The driving gate electrode 155 may also be referred to as a first gate electrode.

Each of the first and second scan lines 151 and 152 may extend in the first direction DR1. A first scan line 151 and a second scan line 152 may be positioned above and below the plurality of pixels PX1, PX2, and PX3 of a group, respectively.

Each driving gate electrode 155 may be positioned corresponding to each pixel PX1, PX2, and PX3. The driving gate electrode 155 positioned in each of the pixels PX1, PX2, and PX3 may include a first gate electrode 154a protruding upward or downward and a protrusion 155a protruding downward or upward. The first gate electrode 154a crosses the active pattern 130a and overlaps the channel region 134a of the active pattern 130a.

The plurality of second gate electrodes 154b corresponding to the plurality of pixels PX1, PX2, and PX3 may be connected to each other to form a shape that extends long in the second direction DR2 as a whole, and the first scan line 151 and It is connected. The second gate electrode 154b crosses the active pattern 130b of each of the pixels PX1, PX2, and PX3 and overlaps the channel region 134b of the active pattern 130b.

The plurality of third gate electrodes 154c corresponding to the plurality of pixels PX1, PX2, and PX3 are connected to each other to form a shape that extends long in the second direction DR2 as a whole, and the second scan line 152 and It is connected. The third gate electrode 154c crosses the active pattern 130c of each of the pixels PX1, PX2, and PX3 and overlaps the channel region 134c of the active pattern 130c.

The second conductive layers 151, 152, 155, 154b and 154c may further include a conductive pattern 150a overlapping a common voltage line 170 to be described later.

A second insulating layer 160 may be positioned on the second conductive layers 151, 152, 155, 154b and 154c. The buffer layer 120 and/or the second insulating layer 160 may include a plurality of contact holes 60, 61, 62, 63a, 63b, 64, 65, 66, and 68.

Third conductive layers 171a, 171b, 171c, 172, 170, 173, 175, and 178 may be positioned on the second insulating layer 160. The third conductive layers 171a, 171b, 171c, 172, 170, 173, 175, 178 are a plurality of data lines 171a, 171b, 171c based on a group of pixels PX1, PX2, PX3. ), a driving voltage line 172, a common voltage line 170, an initialization voltage line 173, a capacitor electrode 175, and a plurality of connection members 178.

The common voltage line 170 may be electrically connected to the horizontal common voltage line 170a through the contact hole 60 of the second insulating layer 160. The conductive pattern 150a of the second conductive layer is electrically connected to the common voltage line 170 through the contact hole 60a of the second insulating layer 160 to reduce the resistance of the common voltage line 170. The conductive pattern 150a may be omitted.

The driving voltage line 172 is electrically connected to the source region 133a of the active pattern 130a through the contact hole 61 of the second insulating layer 160.

In addition, the driving voltage line 172 may be electrically connected to the metal layer 111 through the second insulating layer 160, the buffer layer 120, and the contact hole 59 penetrating the insulating layer 112. That is, while the metal layer 111 is electrically connected to the driving voltage line 172, the signal resistance caused by the driving voltage line 172 may be reduced.

In addition, since the metal layer 111 is formed on the entire surface of the substrate 110, it can be provided with a considerably thick thickness without the burden of steps. As the thickness increases, the signal resistance due to the metal layer 111 can be easily reduced. In addition, since the metal layer 111 can be formed without a separate mask, the manufacturing process is simple and the cost and time required for the process can be reduced.

The initialization voltage line 173 is electrically connected to the drain region 135c of the active pattern 130c through the contact hole 63a of the second insulating layer 160.

The plurality of data lines 171a, 171b, and 171c may be arranged adjacent to each other in the first direction DR1. Other configurations of the third conductive layer may not be positioned between the plurality of data lines 171a, 171b, and 171c. Each of the data lines 171a, 171b, and 171c is electrically connected to the source region 133b of the active pattern 130b through the contact hole 64 of the second insulating layer 160. Each of the data lines 171a, 171b, and 171c may be bent at least once as shown in FIGS. 2 and 3.

The capacitor electrode 175 may have an island shape disposed one by one in each of the pixels PX1, PX2, and PX3. The capacitor electrode 175 may be positioned between the driving voltage line 172 and the data lines 171a, 171b, and 171c in a plan view. The capacitor electrode 175 may overlap with the corresponding driving gate electrode 155 with the second insulating layer 160 therebetween to form the capacitor Cst. The driving gate electrode 155 may be referred to as a first capacitor electrode, and the capacitor electrode 175 may be referred to as a second capacitor electrode.

The capacitor electrode 175 is electrically connected to the drain region 135a of the active pattern 130a through the contact hole 62 of the second insulating layer 160 and the contact hole 63b of the second insulating layer 160 It is electrically connected to the source region 133c of the active pattern 130c through the device. Further, the capacitor electrode 175 is electrically connected to the lower pattern 115 through the contact hole 68 of the second insulating layer 160 and the buffer layer 120. For contact between the capacitor electrode 175 and the drain region 135a of the active pattern 130a, the driving gate electrode 155 includes an opening 55a overlapping the contact hole 62 and the driving gate electrode 155 It may have a shape surrounding the contact hole 62, but is not limited thereto.

The connection member 178 is electrically connected to the drain region 135b of the active pattern 130b through a contact hole 65 in each of the pixels PX1, PX2, and PX3, and the driving gate electrode ( The protrusion 155a of the 155 is electrically connected to each other, so that the drain region 135b of the active pattern 130b and the protrusion 155a of the driving gate electrode 155 may be electrically connected to each other.

In the plan view, each of the data lines 171a, 171b, and 171c, the driving voltage line 172, the common voltage line 170, and the initialization voltage line 173 extend substantially in the second direction DR2 to be extended to the first scan line 151. ) And the second scan line 152. A plurality of data lines 171a, 171b, and 171c, a driving voltage line 172, and an initialization voltage line 173 may be positioned between two adjacent common voltage lines 170.

A group of pixels PX1, PX2, and PX3 shown in FIG. 2 may be arranged in a second direction DR2 to be adjacent to each other, and are repeated in a first direction DR1 and a second direction DR2. Can be placed. A common voltage line 170 may be positioned on both left and right sides of the plurality of pixels PX1, PX2, and PX3 of a group, respectively, and a first scan line 151 and a second scan line 152 at the upper and lower sides Each of these can be located.

When a plurality of pixels PX1, PX2, and PX3 of a repeating group includes three pixels PX1, PX2, PX3, three data lines 171a, 171b, 171c between two adjacent common voltage lines 170 , One driving voltage line 172, and one initialization voltage line 173 may be positioned.

At least one of the first conductive layers 115 and 170a, the second conductive layers 151, 152, 155, 154b, 154c, and the third conductive layers 171a, 171b, 171c, 172, 170, 173, 175, 178 Silver copper (Cu), aluminum (Al), magnesium (Mg), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), iridium (Ir) , Molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), tantalum (Ta), may include at least one of metals such as alloys thereof. Each of the first conductive layer, the second conductive layer, and the third conductive layer may include a single layer or multiple layers. For example, the third conductive layer may have a multilayer structure including a lower layer including titanium and an upper layer including copper.

The first transistor T1 includes a channel region 134a, a source region 133a and a drain region 135a, and a first gate electrode 154a. Since the source region 133a of the first transistor T1 is electrically connected to the driving voltage line 172, a driving voltage may be applied.

The lower pattern 115 corresponding to the first transistor T1 overlaps the channel region 134a between the channel region 134a of the first transistor T1 and the substrate 110 so that external light is transmitted to the channel region 134a. Leakage current and characteristic degradation can be reduced by not reaching The lower pattern 115 is electrically connected to the drain region 135a of the first transistor T1 through the capacitor electrode 175.

The second transistor T2 includes a channel region 134b, a source region 133b, a drain region 135b, and a second gate electrode 154b. The source region 133b of the second transistor T2 of each of the pixels PX1, PX2, and PX3 is electrically connected to the data lines 171a, 171b, and 171c, respectively, to receive a data voltage or a reference voltage. The drain region 135b of the second transistor T2 may be electrically connected to the first gate electrode 154a through the driving gate electrode 155.

The third transistor T3 includes a channel region 134c, a source region 133c and a drain region 135c, and a third gate electrode 154c. The drain region 135c of the third transistor T3 may receive an initialization voltage from the initialization voltage line 173.

A third insulating layer 180 may be positioned on the third conductive layer. The third insulating layer 180 may have a plurality of contact holes 71a, 72a, 73a, 74a, 75a, 76a, and 77a positioned on the third conductive layer.

A fourth conductive layer may be positioned on the third insulating layer 180. The fourth conductive layer is the data lines 171a, 171b, 171c, the driving voltage lines 172 located on the third conductive layers 171a, 171b, 171c, 172, 170, 173, 175, 178, The common voltage line 170, the initialization voltage line 173, and the third conductive layers 171a, 171b, 171c, 172, 170, 173, 175, 178, etc. It may include a plurality of conductive patterns electrically connected to the conductive patterns of the corresponding third conductive layers 171a, 171b, 171c, 172, 170, 173, 175, and 178.

For example, the data lines 171a, 171b, and 171c are electrically connected to a corresponding conductive pattern positioned in the fourth conductive layer through contact holes 74a, 75a, and 76a, respectively, and the driving voltage line 172 is It is electrically connected to the corresponding conductive pattern 183a positioned in the sixth conductive layer through the contact hole 71a, and the common voltage line 170 corresponds to the corresponding conductive pattern positioned in the fourth conductive layer through the contact hole 72a. It is electrically connected to the conductive pattern, and the initialization voltage line 173 is electrically connected to a corresponding conductive pattern located in the fourth conductive layer through a contact hole 73a, and the capacitor electrode 175 is a contact hole 77a. ) May be electrically connected to the corresponding conductive pattern 183b positioned on the fourth conductive layer.

The conductive patterns of the fourth conductive layer may transmit the same voltage as the connected third conductive layer to reduce resistance. Depending on the embodiment, the fourth conductive layer may be omitted.

A fourth insulating layer 181 may be positioned on the fourth conductive layer. The fourth insulating layer 181 may include a contact hole 80 positioned on the conductive pattern 183b connected to the capacitor electrode 175 and a contact hole 81 positioned on the common voltage line 170. .

A fifth conductive layer 190a, 190b, 190c, 190d including a plurality of contact members 190a, 190b, 190c, and 190d may be positioned on the fourth insulating layer 181. Depending on the embodiment, the fifth conductive layers 190a, 190b, 190c, and 190d may be omitted.

Each of the contact members 190a, 190b, and 190c may be positioned in each of the pixels PX1, PX2, and PX3, and may be electrically connected by contacting a corresponding conductive pattern 183b through the contact hole 80. Accordingly, each of the contact members 190a, 190b, and 190c may be electrically connected to the capacitor electrode 175 electrically connected to the conductive pattern 183b, respectively.

The contact member 190d may contact the common voltage line 170 through the contact hole 81 and may be electrically connected.

The contact members 190a, 190b, 190c, and 190d may improve adhesion between the conductive pattern of the fourth conductive layer and other conductive layers, respectively, and prevent oxidation of the fourth conductive layer. Particularly, when the fourth conductive layer includes copper, oxidation of copper may be prevented. To this end, the fifth conductive layers 190a, 190b, 190c, and 190d are conductive materials capable of preventing corrosion of the fourth conductive layer, for example, capping the fourth conductive layer when the fourth conductive layer contains copper. Thus, a conductive material capable of preventing corrosion of copper may be included. For example, the fifth conductive layers 190a, 190b, 190c, and 190d may include a conductive material such as a metal oxide such as ITO or IZO.

A fifth insulating layer 182 may be positioned on the fifth conductive layers 190a, 190b, 190c, and 190d. The fifth insulating layer 182 may include a contact hole 83 positioned on each of the contact members 190a, 190b, and 190c.

The center of the contact hole 83 in plan view and cross-sectional view may not coincide with the center of the contact hole 80. The contact hole 83 and the contact hole 80 may or may not partially overlap each other in a plan view.

Both the contact hole 83 and the contact hole 80 may overlap the corresponding contact members 190a, 190b, and 190c of each pixel PX1, PX2, and PX3.

The insulating layer 112, the buffer layer 120, the first insulating layer 121 including the insulating pattern 144, the second insulating layer 160, the third insulating layer 180, the fourth insulating layer 181 And at least one of the fifth insulating layer 182 may include an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiON) and/or an organic insulating material. In particular, the fifth insulating layer 182 may include an inorganic insulating material and/or an organic insulating material such as polyimide, an acrylic polymer, or a siloxane polymer, and may have a substantially flat top surface.

Pixel electrode layers 191a, 191b, and 191c including a plurality of pixel electrodes 191a, 191b, and 191c as a sixth conductive layer may be positioned on the fifth insulating layer 182.

2 and 3, a plurality of pixels PX1, PX2, and PX3 of a group repeated in a plan view (or first transistors T1 of the plurality of pixels PX1, PX2, PX3) The plurality of pixel electrodes 191a, 191b, and 191c, which are arranged in two directions DR2 and each corresponding to the pixels PX1, PX2, and PX3, may be arranged adjacent to each other in the first direction DR1. However, the arrangement and structure of the pixels PX1, PX2, and PX3 and the pixel electrodes 191a, 191b, and 191c corresponding thereto are not limited thereto. The pixel electrodes 191a, 191b, and 191c may have different planar sizes and shapes, but are not limited thereto.

The plurality of pixel electrodes 191a, 191b, 191c are electrically connected to the contact members 190a, 190b, and 190c, which are electrically connected to the capacitor electrode 175 through the contact hole 83 of the fifth insulating layer 182, respectively. Can be connected to. Each of the pixel electrodes 191a, 191b, and 191c is electrically connected to the drain region 135a of the first transistor T1 through the contact members 190a, 190b, and 190c, the conductive pattern 183b, and the capacitor electrode 175. It is connected to receive a voltage from the first transistor T1.

For example, the pixel electrode 191a is connected to the first transistor T1 of the pixel PX1, the pixel electrode 191b is connected to the first transistor T1 of the pixel PX2, and the pixel electrode 191c may be connected to the first transistor T1 of the pixel PX3.

The pixel electrodes 191a, 191b, and 191c may include a semi-transmissive conductive material or a reflective conductive material.

A sixth insulating layer 350 may be positioned on the fifth insulating layer 182. The sixth insulating layer 350 has openings 355a, 355b, and 355c respectively positioned on the pixel electrodes 191a, 191b, and 191c.

The sixth insulating layer 350 may include an organic insulating material such as polyacrylic resin or polyimide resin.

An emission layer 370 may be positioned on the sixth insulating layer 350 and the pixel electrode layer. The emission layer 370 may include portions positioned in the openings 355a, 355b, and 355c of the sixth insulating layer 350. The light emitting layer 370 may include an organic light emitting material or an inorganic light emitting material. The emission layer 370 may include a portion positioned on the sixth insulating layer 350 as illustrated, and at least a portion of the sixth insulating layer 350 may not be covered with the emission layer 370.

The sixth insulating layer 350 and the light emitting layer 370 may include a contact hole 82 positioned on the contact member 190d.

A common electrode 270 is positioned on the emission layer 370. The common electrode 270 may be continuously formed over the plurality of pixels PX1, PX2, and PX3. The common electrode 270 may contact the contact member 190d through the contact hole 82 and are electrically connected to the common voltage line 170 to receive the common voltage.

The common electrode 270 may include a conductive transparent material.

The pixel electrodes 191a, 191b, 191c, the emission layer 370 and the common electrode 270 of each pixel PX1, PX2, PX3 together form a light emitting diode ED, and the pixel electrodes 191a, 191b, 191c, and One of the common electrodes 270 becomes a cathode and the other becomes an anode. In the above, an example in which the pixel electrodes 191a, 191b, and 191c become anodes has been described.

In a plan view, a region in which the openings 355a, 355b, and 355c of the sixth insulating layer 350 are located may define the emission regions of each of the pixels PX1, PX2, and PX3.

2 and 3, a plurality of openings 355a, 355b, respectively corresponding to a plurality of pixel electrodes 191a, 191b, and 191c connected to a group of pixels PX1, PX2, and PX3, respectively. The 355c may be arranged adjacent to each other in the first direction DR1.

Hereinafter, a display device according to an exemplary embodiment will be described with reference to FIGS. 5 to 7. 5 is a plan layout view of a plurality of pixels of a display device according to an exemplary embodiment of the present invention, FIG. 6A is a plan layout view of a plurality of pixels of a display device according to an exemplary embodiment, and FIG. 6B is 6A is a cross-sectional view of a partial area, and FIG. 7 is a plan layout view of a plurality of pixels of a display device according to an exemplary embodiment. Description of the same components as those described above will be omitted.

First, referring to FIG. 5, the metal layer 111 according to an exemplary embodiment may include openings 111-1, 111-2, and 111-3 overlapping the active layer. Specifically, the metal layer 111 includes a first opening 111-1 overlapping the first active pattern 130a, a second opening 111-2 overlapping the second active pattern 130b, and a third active A third opening 111-3 overlapping the pattern 130a may be included.

The metal layer 111 according to an embodiment may be electrically connected to the driving voltage line 172, but the active pattern 130a, through the openings 111-1, 111-2, and 111-3 included in the metal layer 111, 130b and 130c), so the transistor performance may not be affected.

Next, referring to FIGS. 6A and 6B, the metal layer 111 according to an exemplary embodiment may include a first voltage metal layer 111d and a second voltage metal layer 111s. The first voltage metal layer 111d and the second voltage metal layer 111s may be spaced apart from each other. The first voltage metal layer 111d and the second voltage metal layer 111s may have a stripe shape extending along the second direction DR2.

In plan view, the first voltage metal layer 111d may have a first width Wd, and the second voltage metal layer 111s may have a second width Ws. In this case, the first width Wd and the second width Ws may be substantially the same. However, the present invention is not limited thereto and may be changed according to the pixel width and structure.

The first voltage metal layer 111d may be connected to the driving voltage line 172 through the contact hole 11d. The first voltage metal layer 111d may receive a driving voltage. The second voltage metal layer 111s may be connected to the common voltage line 170 or the horizontal common voltage line 170a or the conductive pattern 150a through the contact hole 11s. The second voltage metal layer 111s may receive a common voltage.

The first voltage metal layer 111d may have any stacked structure for applying a driving voltage, and the second voltage metal layer 111s may have any stacked structure for applying a common voltage.

As an example, as shown in FIG. 6B, the driving voltage line 172 is a connection member 115a included in the first conductive layer through a contact hole 11d penetrating the second insulating layer 160 and the buffer layer 120. And the connection member 115a may be connected to the first voltage metal layer 111d through a contact hole penetrating the insulating layer 112. The first voltage metal layer 111d and the driving voltage line 172 may be connected through a connection member 115a positioned on the same layer as the lower pattern 115. However, the present invention is not limited thereto, and the driving voltage line 172 may be directly connected to the first voltage metal layer 111d through the contact hole 11d.

Similarly, the common voltage line 170 may be connected to the connection member 115b included in the first conductive layer through the contact hole 11s penetrating the second insulating layer 160 and the buffer layer 120, and the connection member 115b may be connected to the second voltage metal layer 111s through a contact hole penetrating through the insulating layer 112. The second voltage metal layer 111s and the common voltage line 170 may be connected through a connection member positioned on the same layer as the lower pattern 115. However, the present invention is not limited thereto, and the common voltage line 170 may be directly connected to the second voltage metal layer 111s through the contact hole 11s.

Next, referring to FIG. 7, the metal layer 111 according to an embodiment may include a first voltage metal layer 111d and a second voltage metal layer 111s. The first voltage metal layer 111d and the second voltage metal layer 111s may be spaced apart from each other. The first voltage metal layer 111d and the second voltage metal layer 111s may have a stripe shape extending along the second direction DR2.

On a plane, the first voltage metal layer 111d may have a first width Wd, and the second voltage metal layer 111s may have a second width Ws. In this case, the first width Wd and the second width Ws may be substantially the same. However, the present invention is not limited thereto and may be changed according to the pixel width and structure.

The first voltage metal layer 111d may be connected to the driving voltage line 172 through the contact hole 11d. The first voltage metal layer 111d may receive a driving voltage. The second voltage metal layer 111s may be connected to the common voltage line 170 or the horizontal common voltage line 170a or the conductive pattern 150a through the contact hole 11s. The second voltage metal layer 111s may receive a common voltage.

The metal layer 111 according to an embodiment may include openings 111-1, 111-2, and 111-3 overlapping the active layer. Specifically, the metal layer 111 includes a first opening 111-1 overlapping the first active pattern 130a, a second opening 111-2 overlapping the second active pattern 130b, and a third active A third opening 111-3 overlapping the pattern 130a may be included.

The metal layer 111 may receive a predetermined voltage. Since the metal layer 111 according to an exemplary embodiment does not overlap the active layer through the openings 111-1, 111-2 and 111-3, transistor performance may not be affected.

Hereinafter, a display device according to an exemplary embodiment will be described with reference to FIGS. 8 and 9. FIG. 8 is a plan layout view of a plurality of pixels of a display device according to an exemplary embodiment, and FIG. 9 is a cross-sectional view of the display device of FIG. 8 taken along line VIIIa-VIIIb. Descriptions of the same and similar components as the above-described components may be omitted.

The display device according to an exemplary embodiment may include a substrate 110. The substrate 110 may include an insulating material such as glass or plastic, and may have flexibility.

A metal layer 111 may be positioned on the substrate 110. The metal layer 111 according to an embodiment may overlap the entire surface of the substrate 110.

The metal layer 111 is copper (Cu), aluminum (Al), magnesium (Mg), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel (Ni), neodymium (Nd), It may contain at least one of metals such as iridium (Ir), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), tantalum (Ta), and alloys thereof, or may contain a material similar to a metal. have. The metal layer 111 may include a single layer or multiple layers.

The thickness of the metal layer 111 may be about 6,000 angstroms to about 10,000 angstroms. The metal layer 111 may have a fairly thick thickness. As the thickness of the metal layer 111 increases, the performance of the transistor included in the pixel may be improved, thereby increasing the image quality. Even when the thickness of the metal layer 111 is increased, a step due to the metal layer 111 does not occur, so that other conductive layers may be easily formed and reliability may be improved.

An insulating layer 112 may be positioned on the metal layer 111. The insulating layer 112 may include an inorganic insulating material, an organic insulating material, or both an inorganic insulating material and an organic insulating material. Formation of capacitance between the metal layer 111 and another conductive layer may be controlled through the insulating layer 112.

Next, a first conductive layer 115 including a plurality of lower patterns 115 may be positioned on the insulating layer 112. The lower pattern 115 is also referred to as a conductive pattern. The first conductive layer may include various conductive metals or semiconductor materials having conductive properties equivalent thereto.

A buffer layer 120 is positioned on the first conductive layer 115 and the insulating layer 112.

Active layers 130a, 130b, and 130c including a plurality of active patterns 130a, 130b, and 130c are positioned on the buffer layer 120. That is, the lower pattern 115 may be positioned between the substrate 110 and the active layers 130a, 130b, and 130c. The active patterns 130a, 130b, and 130c positioned in each of the pixels PX1, PX2, and PX3 include channel regions 134a, 134b, and 134c forming channels of each of the plurality of transistors T1, T2, and T3 described above, and A conductive region connected thereto may be included. The conductive regions of each of the active patterns 130a, 130b, and 130c may include source regions 133a, 133b, 133c and drain regions 135a, 135b, and 135c of each of the transistors T1, T2, and T3.

In each of the pixels PX1, PX2, and PX3, the active pattern 130a and the active pattern 130c may be connected to each other or spaced apart from each other. 8 illustrates an example in which the active pattern 130a and the active pattern 130c are connected to each other. In this case, the drain region 135a of the active pattern 130a may be the source region 133c of the active pattern 130c.

The active layers 130a, 130b, and 130c may include a semiconductor material such as amorphous silicon, polycrystalline silicon, or an oxide semiconductor.

An insulating pattern 144 as a first insulating layer may be positioned on the active layers 130a, 130b, and 130c. The insulating pattern 144 overlaps the channel regions 134a, 134b, and 134c of the active patterns 130a, 130b, and 130c and may be positioned on the channel regions 134a, 134b, and 134c. The insulating pattern 144 may not substantially overlap the conductive regions of the active patterns 130a, 130b, and 130c.

Second conductive layers 151, 152, 153, 172b, 155, 154b, and 154c may be positioned on the insulating pattern 144. The second conductive layers 151, 152, 153, 172b, 155, 154b, 154c transmit the first scan line 151 and the second scan signal SS that can transmit the first scan signal SC described above. A second scan line 152 that can transfer, a horizontal initialization voltage line 153 that can transfer an initialization voltage INIT, a horizontal driving voltage line 172b that can transfer a driving voltage ELVDD, a driving gate electrode 155, A second gate electrode 154b and a third gate electrode 154c may be included. In the above-described circuit diagram, the gate electrode G1, the gate electrode G2, and the gate electrode G3 are each of the first gate electrode 154a, the second gate electrode 154b, and the driving gate electrode 155 included therein. It may correspond to the third gate electrode 154c.

The first and second scan lines 151 and 152, the horizontal initialization voltage line 153, and the horizontal driving voltage line 172b may each extend in the first direction DR1.

In a plan view, the driving gate electrode 155 may be positioned between the first scan line 151 and the second scan line 152.

The second gate electrode 154b is spaced apart from the first scan line 151 and may generally extend in the second direction DR2. Alternatively, the second gate electrode 154b may be directly connected to the first scan line 151.

The third gate electrode 154c is spaced apart from the second scan line 152 and may generally extend in the second direction DR2. Alternatively, the third gate electrode 154c may be directly connected to the second scan line 152.

The driving gate electrode 155 positioned in each of the pixels PX1, PX2, and PX3 includes a protruding portion 155a protruding upward and a first gate electrode 154a protruding downward and extending substantially in the second direction DR2. Can include.

The first gate electrode 154a crosses the active pattern 130a and overlaps the channel region 134a of the active pattern 130a. The second gate electrode 154b crosses the active pattern 130b and overlaps the channel region 134b of the active pattern 130b. The third gate electrode 154c crosses the active pattern 130c and overlaps the channel region 134c of the active pattern 130c.

The horizontal driving voltage line 172b may be connected to the first metal layer 111 through the contact hole 59.

A second insulating layer 160 may be positioned on the second conductive layers 151, 152, 153, 172b, 155, 154b, 154c. The buffer layer 120 and/or the second insulating layer 160 may include a plurality of contact holes 24, 26, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69.

Third conductive layers 171a, 171b, 171c, 172a, 172b, 172d, 170, 173, 175, 174, 176, 177, 178 may be positioned on the second insulating layer 160. The third conductive layers 171a, 171b, 171c, 172a, 172b, 172d, 170, 173, 175, 174, 176, 177, 178 include a plurality of data lines 171a, 171b, 171c, and a plurality of driving voltage lines ( 172a, 172c, 172d), a common voltage line 170, an initialization voltage line 173, a capacitor electrode 175, and a plurality of connection members 174, 176, 177, and 178.

In the plan view, each of the data lines 171a, 171b, and 171c, the driving voltage lines 172a, 172c, 172d, the common voltage line 170, and the initialization voltage line 173 extend substantially in the second direction DR2 to be the first It may cross the scan line 151 and the second scan line 152.

A group of pixels PX1, PX2, and PX3 shown in FIG. 8 may be arranged in a first direction DR1 to be adjacent to each other, and are repeated in a first direction DR1 and a second direction DR2. Can be placed. A common voltage line 170 may be positioned on both left and right sides of the plurality of pixels PX1, PX2, and PX3 of a group, respectively. When a plurality of pixels PX1, PX2, and PX3 of a repeating group includes three pixels PX1, PX2, PX3, three data lines 171a, 171b, 171c between two adjacent common voltage lines 170 , Three driving voltage lines 172a, 172c, 172d, and at least one initialization voltage line 173 may be positioned.

Each of the data lines 171a, 171b, and 171c has a contact hole 64 of the second insulating layer 160 (two contact holes 64 are shown in each pixel PX1, PX2, PX3 in FIG. 8). It is electrically connected to the source region 133b of the active pattern 130b through the active pattern 130b.

Each of the driving voltage lines 172a, 172c, and 172d may be positioned corresponding to each of the pixels PX1, PX2, and PX3.

The driving voltage lines 172a, 172c, 172d are the contact holes 61 of the second insulating layer 160 (in FIG. 8, two contact holes 61 are shown in the pixels PX1 and PX2, respectively, and the pixel PX3 is It is electrically connected to the source region 133a of the active pattern 130a through one contact hole 61 (shown). Further, the driving voltage lines 172a, 172c, and 172d are electrically connected to the horizontal driving voltage line 172b through the contact hole 60 of the second insulating layer 160. Therefore, the horizontal driving voltage line 172b can transmit the driving voltage together with the driving voltage lines 172a, 172c, 172d, and the driving voltage is meshed in all directions in the first direction DR1 and the second direction DR2 throughout the display device. It can be delivered in (mesh) form.

The initialization voltage line 173 is electrically connected to the horizontal initialization voltage line 153 through the contact hole 69 of the second insulating layer 160. Therefore, the horizontal initialization voltage line 153 can transmit the initialization voltage together with the initialization voltage line 173, and even if the initialization voltage line 173 is formed one for each of the three pixels PX1, PX2, PX3, the horizontal initialization voltage line 153 The initialization voltage can be delivered to all three pixels PX1, PX2, and PX3.

One capacitor electrode 175 may be located in each pixel PX1, PX2, and PX3. The capacitor electrode 175 may overlap with the corresponding driving gate electrode 155 with the second insulating layer 160 therebetween to form the capacitor Cst.

The capacitor electrode 175 may include a protrusion 175a extending downward. The protrusion 175a is the active pattern 130a through the contact hole 62 of the second insulating layer 160 (two contact holes 62 are shown in each of the pixels PX1, PX2, and PX3 in FIG. 8). It is electrically connected to the drain region 135a (or the source region 133c of the active pattern 130c) of. Further, the capacitor electrode 175 is electrically connected to the lower pattern 115 through the contact hole 68 of the second insulating layer 160 and the buffer layer 120.

The connection member 174 is electrically connected to the second scan line 152 and the third gate electrode 154c through the contact hole 24 of the second insulating layer 160, so that the second scan line 152 and the The third gate electrodes 154c may be electrically connected to each other.

The connection member 176 is electrically connected to the first scan line 151 and the second gate electrode 154b through the contact hole 26 of the second insulating layer 160, and The second gate electrodes 154b may be electrically connected to each other.

The connecting member 177 is a contact hole 63 of the second insulating layer 160 in each pixel PX1, PX2, PX3 (two contact holes 63 in each pixel PX1, PX2, PX3 in FIG. 8) Is electrically connected to the drain region 135c of the active pattern 130c, and is electrically connected to the horizontal initialization voltage line 153 through the contact hole 67 of the second insulating layer 160, The drain region 135c of the pattern 130c may be electrically connected to the horizontal initialization voltage line 153.

The horizontal initialization voltage line 153 extends in the first direction DR1 across the three pixels PX1, PX2, PX3, but is located between two adjacent common voltage lines 170 and may not cross the two common voltage lines 170. have. The horizontal initialization voltage line 153 crosses the three adjacent data lines 171a, 171b, and 171c and may extend only to the initialization voltage line 173.

The connection member 178 is a contact hole 65 of the second insulating layer 160 in each of the pixels PX1, PX2, and PX3 (two contact holes 65 in each pixel PX1, PX2, PX3 in FIG. 8). Is electrically connected to the drain region 135b of the active pattern 130b, and is electrically connected to the protrusion 155a of the driving gate electrode 155 through the contact hole 66 of the second insulating layer 160 The drain region 135b of the active pattern 130b and the protrusion 155a of the driving gate electrode 155 may be electrically connected to each other.

The first conductive layer 115, the second conductive layer 151, 152, 153, 172b, 155, 154b, 154c, and the third conductive layer 171a, 171b, 171c, 172a, 172b, 172d, 170, 173, 175 , 174, 176, 177, 178) at least one of copper (Cu), aluminum (Al), magnesium (Mg), silver (Ag), gold (Au), platinum (Pt), palladium (Pd), nickel ( Ni), neodymium (Nd), iridium (Ir), molybdenum (Mo), tungsten (W), titanium (Ti), chromium (Cr), tantalum (Ta), may contain at least one of metals such as alloys thereof have. Each of the first conductive layer, the second conductive layer, and the third conductive layer may include a single layer or multiple layers. For example, the third conductive layer may have a multilayer structure including a lower layer including titanium and an upper layer including copper.

The first transistor T1 includes a channel region 134a, a source region 133a and a drain region 135a, and a first gate electrode 154a. Since the source region 133a of the first transistor T1 is electrically connected to the driving voltage lines 172a, 172c, and 172d, a driving voltage may be applied.

The lower pattern 115 corresponding to the first transistor T1 overlaps the channel region 134a between the channel region 134a of the first transistor T1 and the substrate 110 so that external light is transmitted to the channel region 134a. Leakage current and characteristic degradation can be reduced by not reaching The lower pattern 115 is electrically connected to the drain region 135a of the first transistor T1 through the capacitor electrode 175.

The horizontal driving voltage line 172b is electrically connected to the metal layer 111 through a contact hole 59 penetrating through the buffer layer 120 and the insulating layer 112. That is, while the metal layer 111 is electrically connected to the driving voltage line 172b, resistance by the driving voltage line 172b may be reduced.

In addition, since the metal layer 111 is formed on the entire surface of the substrate 110, it can be provided with a considerably thick thickness without the burden of steps. As the thickness increases, the signal resistance due to the metal layer 111 can be easily reduced. In addition, since the metal layer 111 can be formed without a separate mask, the manufacturing process is simple and the cost and time required for the process can be reduced.

The second transistor T2 includes a channel region 134b, a source region 133b, a drain region 135b, and a second gate electrode 154b. The source region 133b of the second transistor T2 is electrically connected to the data lines 171a, 171b, and 171c to receive a data voltage or a reference voltage. The drain region 135b of the second transistor T2 may be electrically connected to the first gate electrode 154a through the driving gate electrode 155.

The third transistor T3 includes a channel region 134c, a source region 133c and a drain region 135c, and a third gate electrode 154c. The drain region 135c of the third transistor T3 may receive an initialization voltage from the horizontal initialization voltage line 153.

A third insulating layer 181 may be positioned on the second insulating layer 160 and the third conductive layer 171a, 171b, 171c, 172a, 172b, 172d, 170, 173, 175, 174, 176, 177, 178. I can. The third insulating layer 181 may include a contact hole 83a positioned on the capacitor electrode 175 and a contact hole 81 positioned on the common voltage line 170.

Fourth conductive layers 190a, 190b, 190c, and 190d including a plurality of contact members 190a, 190b, 190c, and 190d may be positioned on the third insulating layer 181. The fourth conductive layers 190a, 190b, 190c, and 190d may be omitted according to exemplary embodiments.

Each of the contact members 190a, 190b, and 190c is positioned in each of the pixels PX1, PX2, and PX3, and may be electrically connected to the capacitor electrode 175 through the contact hole 83a.

The contact member 190d may contact the common voltage line 170 through the contact hole 81 and may be electrically connected.

The contact members 190a, 190b, 190c, and 190d are capacitor electrodes of the third conductive layers 171a, 171b, 171c, 172a, 172b, 172d, 170, 173, 175, 174, 176, 177, 178, which each contact The adhesion between the 175 and the common voltage line 170 and the other conductive layer may be improved, and oxidation of the third conductive layer may be prevented. In particular, when the upper layer of the third conductive layer 171a, 171b, 171c, 172a, 172b, 172d, 170, 173, 175, 174, 176, 177, 178 contains copper, oxidation of copper may be prevented. To this end, the fourth conductive layers 190a, 190b, 190c, 190d are the upper layers of the third conductive layers 171a, 171b, 171c, 172a, 172b, 172d, 170, 173, 175, 174, 176, 177, 178 The upper layer of the conductive material that can prevent corrosion of the third conductive layer (171a, 171b, 171c, 172a, 172b, 172d, 170, 173, 175, 174, 176, 177, 178) contains copper In this case, it includes a conductive material capable of preventing corrosion of copper by capping the upper layer of the third conductive layer 171a, 171b, 171c, 172a, 172b, 172d, 170, 173, 175, 174, 176, 177, 178 can do. For example, the fourth conductive layers 190a, 190b, 190c, and 190d may include a conductive material such as a metal oxide such as ITO or IZO.

A fourth insulating layer 182 may be positioned on the third insulating layer 181 and the fourth conductive layers 190a, 190b, 190c, and 190d. Referring to FIG. 9, the fourth insulating layer 182 may include a contact hole 83b positioned on each contact member 190a, 190b, and 190c and overlapping the contact hole 83a.

At least one of the insulating layer 112, the buffer layer 120, the first insulating layer including the insulating pattern 144, the second insulating layer 160, the third insulating layer 181, and the fourth insulating layer 182 May include inorganic insulating materials and/or organic insulating materials such as silicon nitride (SiNx), silicon oxide (SiOx), and silicon oxynitride (SiON). In particular, the fourth insulating layer 182 may include an inorganic insulating material and/or an organic insulating material such as polyimide, an acrylic polymer, or a siloxane polymer, and may have a substantially flat top surface.

Pixel electrode layers 191a, 191b, and 191c including a plurality of pixel electrodes 191a, 191b, and 191c as fifth conductive layers 191a, 191b, and 191c may be positioned on the fourth insulating layer 182. Each of the pixel electrodes 191a, 191b, and 191c may be positioned corresponding to each of the pixels PX1, PX2, and PX3 as shown in FIG. 8. The size and shape of the pixel electrodes 191a, 191b, and 191c positioned in the three pixels PX1, PX2, and PX3 may be different from each other, but are not limited thereto. The pixel PX2 may represent green, the pixel PX1 may represent red, and the pixel PX3 may represent blue, but the present invention is not limited thereto.

Each pixel electrode 191a, 191b, 191c contacts the corresponding contact members 190a, 190b, 190c through the contact hole 83b of the fourth insulating layer 182, and the contact members 190a, 190b, 190c Through the capacitor electrode 175 may be electrically connected. Therefore, each of the pixel electrodes 191a, 191b, and 191c may be electrically connected to the drain region 135a of the first transistor T1 to receive a voltage from the first transistor T1.

The pixel electrode layers 191a, 191b, and 191c may include a semi-transmissive conductive material or a reflective conductive material.

A fifth insulating layer 350 may be positioned on the fourth insulating layer 182. The fifth insulating layer 350 has openings 355 positioned on the pixel electrodes 191a, 191b, and 191c. The fifth insulating layer 350 may include an organic insulating material such as polyacrylic resin or polyimide resin.

An emission layer 370 is positioned on the fifth insulating layer 350 and the pixel electrode layers 191a, 191b, and 191c. The emission layer 370 may include a portion located in the opening 355 of the fifth insulating layer 350. The light emitting layer 370 may include an organic light emitting material or an inorganic light emitting material. Unlike illustrated, at least a portion of the fifth insulating layer 350 may not be covered with the light emitting layer 370.

The fifth insulating layer 350 and the light emitting layer 370 may include a contact hole 82 positioned on the contact member 190d.

A common electrode 270 is positioned on the emission layer 370. The common electrode 270 may be continuously formed over the plurality of pixels PX1, PX2, and PX3. The common electrode 270 may contact the contact member 190d through the contact hole 82 and are electrically connected to the common voltage line 170 to receive the common voltage.

The common electrode 270 may include a conductive transparent material.

The pixel electrodes 191a, 191b, 191c, the emission layer 370 and the common electrode 270 of each pixel PX1, PX2, PX3 together form a light emitting diode ED, and the pixel electrodes 191a, 191b, 191c, and One of the common electrodes 270 becomes a cathode and the other becomes an anode. In the above, an example in which the pixel electrodes 191a, 191b, and 191c become anodes has been described.

Hereinafter, a display device according to an exemplary embodiment will be described with reference to FIGS. 10 to 14. 10 is a plan layout view of a plurality of pixels of a display device according to an exemplary embodiment of the present invention, FIG. 11 is a plan layout view of a plurality of pixels of a display device according to an exemplary embodiment, and FIG. FIG. 13 is a plan layout diagram of a plurality of pixels of a display device according to an exemplary embodiment of the present invention, FIG. 13 is a plan layout view of a plurality of pixels of a display device according to an exemplary embodiment of the present invention, and FIG. 14 is an exemplary embodiment of the present invention. A plan layout diagram of a plurality of pixels of a display device according to an example. Description of the same components as the above-described components will be omitted.

First, referring to FIG. 10, the metal layer 111 according to an embodiment may include openings 111-1 and 111-2 overlapping the active layer. Specifically, the metal layer 111 includes a first opening 111-1 overlapping the first active pattern 130a and the third active pattern 130c, and a second opening 111 overlapping the second active pattern 130b. -2) may be included.

The metal layer 111 may be connected to the horizontal driving voltage line 172b through the contact hole 59 to receive a predetermined voltage. Since the metal layer 111 according to an exemplary embodiment does not overlap the active layer through the openings 111-1 and 111-2, transistor performance may not be affected.

Next, referring to FIG. 11, the metal layer 111 according to an embodiment may include a first voltage metal layer 111d and a second voltage metal layer 111s. The first voltage metal layer 111d and the second voltage metal layer 111s may be spaced apart from each other. The first voltage metal layer 111d and the second voltage metal layer 111s may have a stripe shape extending along the second direction DR2.

On a plane, the first voltage metal layer 111d may have a first width Wd, and the second voltage metal layer 111s may have a second width Ws. In this case, the first width Wd and the second width Ws may be substantially the same. However, the present invention is not limited thereto and may be changed according to the pixel width and structure.

The first voltage metal layer 111d may be connected to the horizontal driving voltage line 172b through the contact hole 11d. The first voltage metal layer 111d may receive a driving voltage. The second voltage metal layer 111s may be connected to the common voltage line 170 through the contact hole 11s. The second voltage metal layer 111s may receive a common voltage.

Next, referring to FIG. 12, the metal layer 111 according to an embodiment may include a first voltage metal layer 111d and a second voltage metal layer 111s. The first voltage metal layer 111d and the second voltage metal layer 111s may be spaced apart from each other. The first voltage metal layer 111d and the second voltage metal layer 111s may have a stripe shape extending along the second direction DR2.

The metal layer 111 according to an embodiment may include openings 111-1 and 111-2 overlapping the active layer. Specifically, the metal layer 111 includes a first opening 111-1 overlapping the first active pattern 130a and the third active pattern 130c, and a second opening 111 overlapping the second active pattern 130b. -2) may be included. According to an embodiment, the metal layer 111 may include an opening overlapping a portion of the active patterns 130a, 130b, and 130c.

The metal layer 111 may receive a predetermined voltage such as a driving voltage or a common voltage. Since the metal layer 111 according to an exemplary embodiment does not overlap the active layer through the openings 111-1 and 111-2, transistor performance may not be affected.

Next, referring to FIG. 13, the metal layer 111 according to an embodiment may include a first sub metal layer 111d1, a second sub metal layer 111d2, and a third sub metal layer 111d3. The first sub-metal layer 111d1 according to an exemplary embodiment may be connected to the first data line 171a through the contact hole 11d1, and the second sub-metal layer 111d2 is provided with the second data through the contact hole 11d2. The line 171b may be connected, and the third sub-metal layer 111d3 may be connected to the third data line 171c through the contact hole 11d3. The first sub-metal layer 111d1 may receive a first data voltage transmitted through the first data line 171a. The second sub-metal layer 111d2 may receive a second data voltage transmitted through the second data line 171b. The third metal layer 111d3 may receive a third data voltage transmitted through the third data line 171c. Although not shown in the present specification, each data line may be connected to the metal layer by a separate conductive layer positioned between the data line and the metal layer.

The first sub-metal layer 111d1, the second sub-metal layer 111d2, and the third sub-metal layer 111d3 may be spaced apart from each other. The first sub-metal layer 111d1, the second sub-metal layer 111d2, and the third sub-metal layer 111d3 may have a stripe shape extending along the second direction DR2.

In plan view, the first sub-metal layer 111d1 has a first width W1, the second sub-metal layer 111d2 has a second width W2, and the third sub-metal layer 111d3 has a third width W3. Can have In this case, the first width W1, the second width W2, and the third width W3 may be substantially the same, but are not limited thereto, and may be changed according to the width and structure of each pixel.

Next, referring to FIG. 14, the metal layer 111 according to an exemplary embodiment may include openings 111-1 and 111-2 overlapping the active layer. Specifically, the metal layer 111 includes a first opening 111-1 overlapping the first active pattern 130a and the third active pattern 130c, and a second opening 111 overlapping the second active pattern 130b. -2) may be included. The metal layer 111 according to an exemplary embodiment may include an opening overlapping a portion of the active patterns 130a, 130b, and 130c. The shapes of the openings 111-1 and 111-2 included in the metal layer 111 may be changed by the active patterns 130a, 130b and 130c.

The metal layer 111 may receive a predetermined voltage such as a data voltage. Since the metal layer 111 according to an exemplary embodiment does not overlap the active layer through the openings 111-1 and 111-2, transistor performance may not be affected.

Hereinafter, a display device according to an exemplary embodiment will be described with reference to FIG. 15. 15 is a cross-sectional view of a plurality of pixels of a display device according to an exemplary embodiment of the present invention.

A metal layer 111 and an insulating layer 112 overlapping the entire surface of the substrate 110 may be positioned on the substrate 110. Although the present specification shows an embodiment in which the metal layer 111 and the insulating layer 112 according to the embodiment of FIG. 2 are applied, the embodiment is not limited thereto, and any embodiment described above may be applied.

A first conductive layer including the lower pattern 115 may be positioned on the insulating layer 112.

The buffer layer 120 may be positioned on the first conductive layer, and the active layer 130 may be positioned thereon.

A first insulating layer 121 may be positioned on the active layer 130. The first insulating layer 121 may be the same layer as the insulating pattern 144 described above, but unlike the insulating pattern 144, the first insulating layer 121 may be formed entirely on the substrate 110 and partially removed. That is, unlike the insulating pattern 144, the first insulating layer 121 may also be positioned on the buffer layer 120. Alternatively, a structure such as the insulating pattern 144 may be positioned instead of the first insulating layer 121.

A second conductive layer including the gate electrode 154 may be positioned on the first insulating layer 121, and a second insulating layer 160 may be positioned thereon.

A third conductive layer including a capacitor electrode 175 may be positioned on the second insulating layer 160, and a third insulating layer 180 may be positioned thereon.

A pixel electrode layer including a plurality of pixel electrodes 191 may be positioned on the third insulating layer 180. The pixel electrode 191 may be electrically connected to the capacitor electrode 175 through the contact hole 89 of the third insulating layer 180.

A sixth insulating layer 350 may be positioned on the third insulating layer 180, and a light emitting layer 370 and a common electrode 270 may be sequentially positioned on the pixel electrode layer and the sixth insulating layer 350. The emission layer 370 may include a light emitting material that emits a first color light, which may be blue light.

An encapsulation layer 380 including a plurality of insulating layers 381, 382, and 383 may be positioned on the common electrode 270. The insulating layer 381 and the insulating layer 382 may include an inorganic insulating material, and the insulating layer 382 positioned between the insulating layer 381 and the insulating layer 382 may include an organic insulating material. .

A filling layer 390 containing a filler may be positioned on the encapsulation layer 380. A cover layer 400 including an insulating material and a plurality of color conversion layers 430a and 430b and a transmission layer 430c may be positioned on the filling layer 390.

The transmission layer 430c may pass incident light. That is, the transmission layer 430c may transmit the first color light, which may be blue light. The transmission layer 430c may include a polymer material that transmits the first color light. The region where the transmission layer 430c is located may correspond to a light emitting region that emits blue color, and the transmission layer 430c may pass the incident first color light as it is without including a separate semiconductor nanocrystal.

The color conversion layers 430a and 430b may include different semiconductor nanocrystals. For example, the first color light incident on the color conversion layer 430a may be converted into second color light by semiconductor nanocrystals included in the color conversion layer 430b and then emitted. The first color light incident on the color conversion layer 430b may be converted into third color light by semiconductor nanocrystals included in the color conversion layer 430b and then emitted.

The semiconductor nanocrystal may include at least one of a phosphor and a quantum dot material that converts incident first color light into second color light or third color light.

The core of the quantum dot may be selected from a group II-VI compound, a group III-V compound, a group IV-VI compound, a group IV element, a group IV compound, and combinations thereof.

Group II-VI compounds include binary compounds selected from the group consisting of CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnO, HgS, HgSe, HgTe, MgSe, MgS, and mixtures thereof; AgInS, CuInS, CdSeS, CdSeTe, CdSTe, ZnSeS, ZnSeTe, ZnSTe, HgSeS, HgSeTe, HgSTe, CdZnS, CdZnSe, CdZnTe, CdHgS, CdHgSe, the group consisting of HZnSe, MgZe, HgS and MgZe, HgS A three-element compound selected from; And HgZnTeS, CdZnSeS, CdZnSeTe, CdZnSTe, CdHgSeS, CdHgSeTe, CdHgSTe, HgZnSeS, HgZnSeTe, HgZnSTe, and a mixture thereof.

The group III-V compound is a binary compound selected from the group consisting of GaN, GaP, GaAs, GaSb, AlN, AlP, AlAs, AlSb, InN, InP, InAs, InSb, and mixtures thereof; A ternary compound selected from the group consisting of GaNP, GaNAs, GaNSb, GaPAs, GaPSb, AlNP, AlNAs, AlNSb, AlPAs, AlPSb, InGaP, InNP, InNAs, InNSb, InPAs, InPSb, GaAlNP, and mixtures thereof; And GaAlNAs, GaAlNSb, GaAlPAs, GaAlPSb, GaInNP, GaInNAs, GaInNSb, GaInPAs, GaInPSb, InAlNP, InAlNAs, InAlNSb, InAlPAs, InAlPSb, it may be selected from the group consisting of a quaternary compound selected from the group consisting of a mixture thereof.

Group IV-VI compounds include a binary compound selected from the group consisting of SnS, SnSe, SnTe, PbS, PbSe, PbTe, and mixtures thereof; A three-element compound selected from the group consisting of SnSeS, SnSeTe, SnSTe, PbSeS, PbSeTe, PbSTe, SnPbS, SnPbSe, SnPbTe, and mixtures thereof; And SnPbSSe, SnPbSeTe, SnPbSTe, and may be selected from the group consisting of a quaternary element compound selected from the group consisting of a mixture thereof. The group IV element may be selected from the group consisting of Si, Ge, and mixtures thereof. The group IV compound may be a binary compound selected from the group consisting of SiC, SiGe, and mixtures thereof.

In this case, the two-element compound, the three-element compound, or the quaternary element compound may be present in the particle at a uniform concentration, or may be present in the same particle by partially dividing the concentration distribution into different states. In addition, one quantum dot may have a core/shell structure surrounding another quantum dot. The interface between the core and the shell may have a concentration gradient that decreases toward the center of the concentration of elements present in the shell.

In some embodiments, the quantum dot may have a core-shell structure including a core including the aforementioned nanocrystal and a shell surrounding the core. The shell of the quantum dot may serve as a protective layer for maintaining semiconductor properties by preventing chemical modification of the core and/or a charging layer for imparting electrophoretic properties to the quantum dot. The shell may be a single layer or multiple layers. The interface between the core and the shell may have a concentration gradient that decreases toward the center of the concentration of elements present in the shell. Examples of the shell of the quantum dot include metal or non-metal oxides, semiconductor compounds, or a combination thereof.

For example, the oxide of the metal or non-metal is SiO ₂ , Al ₂ O ₃ , TiO ₂ , ZnO, MnO, Mn ₂ O ₃ , Mn ₃ O ₄ , CuO, FeO, Fe ₂ O ₃ , Fe ₃ O ₄ , _Two- element compounds such as CoO, Co ₃ O ₄ , and NiO, or three-element compounds such as MgAl ₂ O ₄ , CoFe ₂ O ₄ , NiFe ₂ O ₄ , and CoMn ₂ O ₄ , but the present invention is limited thereto. It is not.

In addition, the semiconductor compounds include CdS, CdSe, CdTe, ZnS, ZnSe, ZnTe, ZnSeS, ZnTeS, GaAs, GaP, GaSb, HgS, HgSe, HgTe, InAs, InP, InGaP, InSb, AlAs, AlP, AlSb, etc. However, the present invention is not limited thereto.

Quantum dots may have a full width of half maximum (FWHM) of the emission wavelength spectrum of about 45 nm or less, preferably about 40 nm or less, more preferably about 30 nm or less, and improve color purity or color reproducibility within this range. I can. In addition, since the light emitted through the quantum dots is emitted in all directions, a wide viewing angle can be improved.

In addition, the shape of the quantum dot is a type generally used in the art and is not particularly limited, but more specifically, spherical, pyramidal, multi-arm, or cubic nanoparticles, nanotubes, It can be used in the form of nanowires, nanofibers, and nanoplatelet particles.

The quantum dots can control the color of light emitted according to the particle size, and accordingly, the quantum dots can have various emission colors such as blue, red, and green.

An insulating layer 440 may be positioned on the plurality of color conversion layers 430a and 430b and the transmission layer 430c, and a plurality of color filters 450a, 450b, 450c and a light blocking member 460 may be positioned thereon. According to an embodiment, a plurality of color filters 450a, 450b, and 450c may be omitted.

The color filter 450a may represent a second color light, the color filter 450b may represent a third color light, and the color filter 450c may represent a first color light.

The light blocking member 460 may be positioned between adjacent color filters 450a, 450b, and 450c.

A substrate 210 may be positioned on the plurality of color filters 450a, 450b, and 450c and the light blocking member 460. That is, a plurality of color conversion layers 430a and 430b and a plurality of color filters 450a, 450b and 450c may be positioned between the substrate 110 and the substrate 210.

According to another embodiment of the present invention, instead of including the plurality of color conversion layers 430a and 430b and the transmission layer 430c, the emission layer 370 may include quantum dots.

Although the embodiments of the present invention have been described in detail above, the scope of the present invention is not limited thereto, and various modifications and improvements by those skilled in the art using the basic concept of the present invention defined in the following claims are also provided. It belongs to the scope of rights.

110: substrate
111: metal layer
115: lower pattern
131: active layer
191: pixel electrode
370: light-emitting layer
270: common electrode

Claims (20)

Board,
A metal layer positioned on the substrate,
A first conductive layer including a lower pattern positioned on the metal layer,
An active layer on the first conductive layer,
A second conductive layer positioned on the active layer and including a first gate electrode,
A pixel electrode positioned on the second conductive layer,
A display device including a light emitting layer and a common electrode positioned on the pixel electrode. In claim 1,
The metal layer overlaps the entire surface of the substrate. In paragraph 2,
The metal layer includes an opening overlapping the active layer. In claim 1,
The display device further includes a third conductive layer disposed between the second conductive layer and the pixel electrode and including a common voltage line, a driving voltage line, and a data line. In claim 4,
The metal layer includes at least one of a first voltage metal layer connected to the driving voltage line and a second voltage metal layer connected to the common voltage line. In clause 5,
The metal layer includes a first voltage metal layer and the second voltage metal layer,
The first voltage metal layer and the second voltage metal layer are spaced apart from each other. In paragraph 6,
The first voltage metal layer and the second voltage metal layer include openings overlapping the active layer. In claim 4,
The data line includes a first data line, a second data line, and a third data line,
The metal layer includes at least one of a first sub metal layer connected to the first data line, a second sub metal layer connected to the second data line, and a third sub metal layer connected to the third data line. In clause 8,
The metal layer includes a first sub metal layer, the second sub metal layer, and the third sub metal layer,
The first sub-metal layer, the second sub-metal layer, and the third sub-metal layer include openings overlapping the active layer. In clause 8,
The first sub metal layer, the second sub metal layer, and the third sub metal layer are spaced apart from each other. Board,
A metal layer positioned on the substrate,
A first conductive layer including a lower pattern positioned on the metal layer,
An active layer on the first conductive layer,
A second conductive layer positioned on the active layer and including a first gate electrode,
A pixel electrode positioned on the second conductive layer,
A light emitting layer and a common electrode positioned on the pixel electrode,
The thickness of the metal layer is about 6,000 angstroms to about 10,000 angstroms. In clause 11,
Further comprising an insulating layer positioned between the metal layer and the lower pattern,
The metal layer overlaps the entire surface of the substrate. In claim 12,
The metal layer includes an opening overlapping the active layer. In clause 11,
The display device further includes a third conductive layer disposed between the second conductive layer and the pixel electrode and including a common voltage line, a driving voltage line, and a data line. In clause 14,
The metal layer includes a first voltage metal layer connected to the driving voltage line and a second voltage metal layer connected to the common voltage line. In paragraph 15,
The first voltage metal layer and the second voltage metal layer are spaced apart from each other. In paragraph 15,
The first voltage metal layer and the second voltage metal layer include openings overlapping the active layer. In clause 14,
The data line includes a first data line, a second data line, and a third data line,
The metal layer includes a first sub metal layer connected to the first data line, a second sub metal layer connected to the second data line, and a third sub metal layer connected to the third data line. In paragraph 18,
The first sub-metal layer, the second sub-metal layer, and the third sub-metal layer include openings overlapping the active layer. In paragraph 18,
The first sub metal layer, the second sub metal layer, and the third sub metal layer are spaced apart from each other.

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